drivers/gpu/drm/amd/display/dc/dc_hw_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_HW_TYPES_H
  27 #define DC_HW_TYPES_H
  28
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31 #include "signal_types.h"
  32
  33 /******************************************************************************
  34  * Data types for Virtual HW Layer of DAL3.
  35  * (see DAL3 design documents for HW Layer definition)
  36  *
  37  * The intended uses are:
  38  * 1. Generation pseudocode sequences for HW programming.
  39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
  40  *
  41  * Note: do *not* add any types which are *not* used for HW programming - this
  42  * will ensure separation of Logic layer from HW layer.
  43  ******************************************************************************/
  44
  45 union large_integer {
  46         struct {
  47                 uint32_t low_part;
  48                 int32_t high_part;
  49         };
  50
  51         struct {
  52                 uint32_t low_part;
  53                 int32_t high_part;
  54         } u;
  55
  56         int64_t quad_part;
  57 };
  58
  59 #define PHYSICAL_ADDRESS_LOC union large_integer
  60
  61 enum dc_plane_addr_type {
  62         PLN_ADDR_TYPE_GRAPHICS = 0,
  63         PLN_ADDR_TYPE_GRPH_STEREO,
  64         PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
  65 };
  66
  67 struct dc_plane_address {
  68         enum dc_plane_addr_type type;
  69         union {
  70                 struct{
  71                         PHYSICAL_ADDRESS_LOC addr;
  72                         PHYSICAL_ADDRESS_LOC meta_addr;
  73                         union large_integer dcc_const_color;
  74                 } grph;
  75
  76                 /*stereo*/
  77                 struct {
  78                         PHYSICAL_ADDRESS_LOC left_addr;
  79                         PHYSICAL_ADDRESS_LOC left_meta_addr;
  80                         union large_integer left_dcc_const_color;
  81
  82                         PHYSICAL_ADDRESS_LOC right_addr;
  83                         PHYSICAL_ADDRESS_LOC right_meta_addr;
  84                         union large_integer right_dcc_const_color;
  85
  86                 } grph_stereo;
  87
  88                 /*video  progressive*/
  89                 struct {
  90                         PHYSICAL_ADDRESS_LOC luma_addr;
  91                         PHYSICAL_ADDRESS_LOC luma_meta_addr;
  92                         union large_integer luma_dcc_const_color;
  93
  94                         PHYSICAL_ADDRESS_LOC chroma_addr;
  95                         PHYSICAL_ADDRESS_LOC chroma_meta_addr;
  96                         union large_integer chroma_dcc_const_color;
  97                 } video_progressive;
  98         };
  99 };
 100
 101 struct dc_size {
 102         uint32_t width;
 103         uint32_t height;
 104 };
 105
 106 struct rect {
 107         int x;
 108         int y;
 109         uint32_t width;
 110         uint32_t height;
 111 };
 112
 113 union plane_size {
 114         /* Grph or Video will be selected
 115          * based on format above:
 116          * Use Video structure if
 117          * format >= DalPixelFormat_VideoBegin
 118          * else use Grph structure
 119          */
 120         struct {
 121                 struct rect surface_size;
 122                 /* Graphic surface pitch in pixels.
 123                  * In LINEAR_GENERAL mode, pitch
 124                  * is 32 pixel aligned.
 125                  */
 126                 uint32_t surface_pitch;
 127         } grph;
 128
 129         struct {
 130                 struct rect luma_size;
 131                 /* Graphic surface pitch in pixels.
 132                  * In LINEAR_GENERAL mode, pitch is
 133                  * 32 pixel aligned.
 134                  */
 135                 uint32_t luma_pitch;
 136
 137                 struct rect chroma_size;
 138                 /* Graphic surface pitch in pixels.
 139                  * In LINEAR_GENERAL mode, pitch is
 140                  * 32 pixel aligned.
 141                  */
 142                 uint32_t chroma_pitch;
 143         } video;
 144 };
 145
 146 struct dc_plane_dcc_param {
 147         bool enable;
 148
 149         union {
 150                 struct {
 151                         uint32_t meta_pitch;
 152                         bool independent_64b_blks;
 153                 } grph;
 154
 155                 struct {
 156                         uint32_t meta_pitch_l;
 157                         bool independent_64b_blks_l;
 158
 159                         uint32_t meta_pitch_c;
 160                         bool independent_64b_blks_c;
 161                 } video;
 162         };
 163 };
 164
 165 /*Displayable pixel format in fb*/
 166 enum surface_pixel_format {
 167         SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
 168         /*TOBE REMOVED paletta 256 colors*/
 169         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
 170                 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
 171         /*16 bpp*/
 172         SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
 173         /*16 bpp*/
 174         SURFACE_PIXEL_FORMAT_GRPH_RGB565,
 175         /*32 bpp*/
 176         SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
 177         /*32 bpp swaped*/
 178         SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
 179
 180         SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
 181         /*swaped*/
 182         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
 183         /*TOBE REMOVED swaped, XR_BIAS has no differance
 184          * for pixel layout than previous and we can
 185          * delete this after discusion*/
 186         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 187         /*64 bpp */
 188         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
 189         /*float*/
 190         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 191         /*swaped & float*/
 192         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
 193         /*grow graphics here if necessary */
 194
 195         SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 196         SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 197                 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 198         SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
 199         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
 200         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
 201         SURFACE_PIXEL_FORMAT_INVALID
 202
 203         /*grow 444 video here if necessary */
 204 };
 205
 206 /* Pixel format */
 207 enum pixel_format {
 208         /*graph*/
 209         PIXEL_FORMAT_UNINITIALIZED,
 210         PIXEL_FORMAT_INDEX8,
 211         PIXEL_FORMAT_RGB565,
 212         PIXEL_FORMAT_ARGB8888,
 213         PIXEL_FORMAT_ARGB2101010,
 214         PIXEL_FORMAT_ARGB2101010_XRBIAS,
 215         PIXEL_FORMAT_FP16,
 216         /*video*/
 217         PIXEL_FORMAT_420BPP12,
 218         PIXEL_FORMAT_420BPP15,
 219         /*end of pixel format definition*/
 220         PIXEL_FORMAT_INVALID,
 221
 222         PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
 223         PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
 224         PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
 225         PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP15,
 226         PIXEL_FORMAT_UNKNOWN
 227 };
 228
 229 enum tile_split_values {
 230         DC_DISPLAY_MICRO_TILING = 0x0,
 231         DC_THIN_MICRO_TILING = 0x1,
 232         DC_DEPTH_MICRO_TILING = 0x2,
 233         DC_ROTATED_MICRO_TILING = 0x3,
 234 };
 235
 236 /* TODO: These values come from hardware spec. We need to readdress this
 237  * if they ever change.
 238  */
 239 enum array_mode_values {
 240         DC_ARRAY_LINEAR_GENERAL = 0,
 241         DC_ARRAY_LINEAR_ALLIGNED,
 242         DC_ARRAY_1D_TILED_THIN1,
 243         DC_ARRAY_1D_TILED_THICK,
 244         DC_ARRAY_2D_TILED_THIN1,
 245         DC_ARRAY_PRT_TILED_THIN1,
 246         DC_ARRAY_PRT_2D_TILED_THIN1,
 247         DC_ARRAY_2D_TILED_THICK,
 248         DC_ARRAY_2D_TILED_X_THICK,
 249         DC_ARRAY_PRT_TILED_THICK,
 250         DC_ARRAY_PRT_2D_TILED_THICK,
 251         DC_ARRAY_PRT_3D_TILED_THIN1,
 252         DC_ARRAY_3D_TILED_THIN1,
 253         DC_ARRAY_3D_TILED_THICK,
 254         DC_ARRAY_3D_TILED_X_THICK,
 255         DC_ARRAY_PRT_3D_TILED_THICK,
 256 };
 257
 258 enum tile_mode_values {
 259         DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
 260         DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 261 };
 262
 263 enum swizzle_mode_values {
 264         DC_SW_LINEAR = 0,
 265         DC_SW_256B_S = 1,
 266         DC_SW_256_D = 2,
 267         DC_SW_256_R = 3,
 268         DC_SW_4KB_S = 5,
 269         DC_SW_4KB_D = 6,
 270         DC_SW_4KB_R = 7,
 271         DC_SW_64KB_S = 9,
 272         DC_SW_64KB_D = 10,
 273         DC_SW_64KB_R = 11,
 274         DC_SW_VAR_S = 13,
 275         DC_SW_VAR_D = 14,
 276         DC_SW_VAR_R = 15,
 277         DC_SW_64KB_S_T = 17,
 278         DC_SW_64KB_D_T = 18,
 279         DC_SW_4KB_S_X = 21,
 280         DC_SW_4KB_D_X = 22,
 281         DC_SW_4KB_R_X = 23,
 282         DC_SW_64KB_S_X = 25,
 283         DC_SW_64KB_D_X = 26,
 284         DC_SW_64KB_R_X = 27,
 285         DC_SW_VAR_S_X = 29,
 286         DC_SW_VAR_D_X = 30,
 287         DC_SW_VAR_R_X = 31,
 288         DC_SW_MAX
 289 };
 290
 291 union dc_tiling_info {
 292
 293         struct {
 294                 /* Specifies the number of memory banks for tiling
 295                  *      purposes.
 296                  * Only applies to 2D and 3D tiling modes.
 297                  *      POSSIBLE VALUES: 2,4,8,16
 298                  */
 299                 unsigned int num_banks;
 300                 /* Specifies the number of tiles in the x direction
 301                  *      to be incorporated into the same bank.
 302                  * Only applies to 2D and 3D tiling modes.
 303                  *      POSSIBLE VALUES: 1,2,4,8
 304                  */
 305                 unsigned int bank_width;
 306                 unsigned int bank_width_c;
 307                 /* Specifies the number of tiles in the y direction to
 308                  *      be incorporated into the same bank.
 309                  * Only applies to 2D and 3D tiling modes.
 310                  *      POSSIBLE VALUES: 1,2,4,8
 311                  */
 312                 unsigned int bank_height;
 313                 unsigned int bank_height_c;
 314                 /* Specifies the macro tile aspect ratio. Only applies
 315                  * to 2D and 3D tiling modes.
 316                  */
 317                 unsigned int tile_aspect;
 318                 unsigned int tile_aspect_c;
 319                 /* Specifies the number of bytes that will be stored
 320                  *      contiguously for each tile.
 321                  * If the tile data requires more storage than this
 322                  *      amount, it is split into multiple slices.
 323                  * This field must not be larger than
 324                  *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
 325                  * Only applies to 2D and 3D tiling modes.
 326                  * For color render targets, TILE_SPLIT >= 256B.
 327                  */
 328                 enum tile_split_values tile_split;
 329                 enum tile_split_values tile_split_c;
 330                 /* Specifies the addressing within a tile.
 331                  *      0x0 - DISPLAY_MICRO_TILING
 332                  *      0x1 - THIN_MICRO_TILING
 333                  *      0x2 - DEPTH_MICRO_TILING
 334                  *      0x3 - ROTATED_MICRO_TILING
 335                  */
 336                 enum tile_mode_values tile_mode;
 337                 enum tile_mode_values tile_mode_c;
 338                 /* Specifies the number of pipes and how they are
 339                  *      interleaved in the surface.
 340                  * Refer to memory addressing document for complete
 341                  *      details and constraints.
 342                  */
 343                 unsigned int pipe_config;
 344                 /* Specifies the tiling mode of the surface.
 345                  * THIN tiles use an 8x8x1 tile size.
 346                  * THICK tiles use an 8x8x4 tile size.
 347                  * 2D tiling modes rotate banks for successive Z slices
 348                  * 3D tiling modes rotate pipes and banks for Z slices
 349                  * Refer to memory addressing document for complete
 350                  *      details and constraints.
 351                  */
 352                 enum array_mode_values array_mode;
 353         } gfx8;
 354
 355         struct {
 356                 unsigned int num_pipes;
 357                 unsigned int num_banks;
 358                 unsigned int pipe_interleave;
 359                 unsigned int num_shader_engines;
 360                 unsigned int num_rb_per_se;
 361                 unsigned int max_compressed_frags;
 362                 bool shaderEnable;
 363
 364                 enum swizzle_mode_values swizzle;
 365                 bool meta_linear;
 366                 bool rb_aligned;
 367                 bool pipe_aligned;
 368         } gfx9;
 369 };
 370
 371 /* Rotation angle */
 372 enum dc_rotation_angle {
 373         ROTATION_ANGLE_0 = 0,
 374         ROTATION_ANGLE_90,
 375         ROTATION_ANGLE_180,
 376         ROTATION_ANGLE_270,
 377         ROTATION_ANGLE_COUNT
 378 };
 379
 380 enum dc_scan_direction {
 381         SCAN_DIRECTION_UNKNOWN = 0,
 382         SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
 383         SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
 384 };
 385
 386 struct dc_cursor_position {
 387         uint32_t x;
 388         uint32_t y;
 389
 390         uint32_t x_hotspot;
 391         uint32_t y_hotspot;
 392
 393         /*
 394          * This parameter indicates whether HW cursor should be enabled
 395          */
 396         bool enable;
 397
 398         /*
 399          * This parameter indicates whether cursor hot spot should be
 400          * programmed
 401          */
 402         bool hot_spot_enable;
 403 };
 404
 405 struct dc_cursor_mi_param {
 406         unsigned int pixel_clk_khz;
 407         unsigned int ref_clk_khz;
 408         unsigned int viewport_x_start;
 409         unsigned int viewport_width;
 410         struct fixed31_32 h_scale_ratio;
 411 };
 412
 413 /* IPP related types */
 414
 415 enum {
 416         INPUT_LUT_ENTRIES = 256
 417 };
 418
 419 struct dc_gamma {
 420         uint16_t red[INPUT_LUT_ENTRIES];
 421         uint16_t green[INPUT_LUT_ENTRIES];
 422         uint16_t blue[INPUT_LUT_ENTRIES];
 423 };
 424
 425 /* Used by both ipp amd opp functions*/
 426 /* TODO: to be consolidated with enum color_space */
 427
 428 /*
 429  * This enum is for programming CURSOR_MODE register field. What this register
 430  * should be programmed to depends on OS requested cursor shape flags and what
 431  * we stored in the cursor surface.
 432  */
 433 enum dc_cursor_color_format {
 434         CURSOR_MODE_MONO,
 435         CURSOR_MODE_COLOR_1BIT_AND,
 436         CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
 437         CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
 438 };
 439
 440 /*
 441  * This is all the parameters required by DAL in order to update the cursor
 442  * attributes, including the new cursor image surface address, size, hotspot
 443  * location, color format, etc.
 444  */
 445
 446 union dc_cursor_attribute_flags {
 447         struct {
 448                 uint32_t ENABLE_MAGNIFICATION:1;
 449                 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
 450                 uint32_t HORIZONTAL_MIRROR:1;
 451                 uint32_t VERTICAL_MIRROR:1;
 452                 uint32_t INVERT_PIXEL_DATA:1;
 453                 uint32_t ZERO_EXPANSION:1;
 454                 uint32_t MIN_MAX_INVERT:1;
 455                 uint32_t RESERVED:25;
 456         } bits;
 457         uint32_t value;
 458 };
 459
 460 struct dc_cursor_attributes {
 461         PHYSICAL_ADDRESS_LOC address;
 462         uint32_t pitch;
 463
 464         /* Width and height should correspond to cursor surface width x heigh */
 465         uint32_t width;
 466         uint32_t height;
 467         uint32_t x_hot;
 468         uint32_t y_hot;
 469
 470         enum dc_cursor_color_format color_format;
 471
 472         /* In case we support HW Cursor rotation in the future */
 473         enum dc_rotation_angle rotation_angle;
 474
 475         union dc_cursor_attribute_flags attribute_flags;
 476 };
 477
 478 /* OPP */
 479
 480 enum dc_color_space {
 481         COLOR_SPACE_UNKNOWN,
 482         COLOR_SPACE_SRGB,
 483         COLOR_SPACE_SRGB_LIMITED,
 484         COLOR_SPACE_YCBCR601,
 485         COLOR_SPACE_YCBCR709,
 486         COLOR_SPACE_YCBCR601_LIMITED,
 487         COLOR_SPACE_YCBCR709_LIMITED,
 488         COLOR_SPACE_2020_RGB_FULLRANGE,
 489         COLOR_SPACE_2020_RGB_LIMITEDRANGE,
 490         COLOR_SPACE_2020_YCBCR,
 491         COLOR_SPACE_ADOBERGB,
 492 };
 493
 494 enum dc_quantization_range {
 495         QUANTIZATION_RANGE_UNKNOWN,
 496         QUANTIZATION_RANGE_FULL,
 497         QUANTIZATION_RANGE_LIMITED
 498 };
 499
 500 /* XFM */
 501
 502 /* used in  struct dc_surface */
 503 struct scaling_taps {
 504         uint32_t v_taps;
 505         uint32_t h_taps;
 506         uint32_t v_taps_c;
 507         uint32_t h_taps_c;
 508 };
 509
 510 enum dc_timing_standard {
 511         TIMING_STANDARD_UNDEFINED,
 512         TIMING_STANDARD_DMT,
 513         TIMING_STANDARD_GTF,
 514         TIMING_STANDARD_CVT,
 515         TIMING_STANDARD_CVT_RB,
 516         TIMING_STANDARD_CEA770,
 517         TIMING_STANDARD_CEA861,
 518         TIMING_STANDARD_HDMI,
 519         TIMING_STANDARD_TV_NTSC,
 520         TIMING_STANDARD_TV_NTSC_J,
 521         TIMING_STANDARD_TV_PAL,
 522         TIMING_STANDARD_TV_PAL_M,
 523         TIMING_STANDARD_TV_PAL_CN,
 524         TIMING_STANDARD_TV_SECAM,
 525         TIMING_STANDARD_EXPLICIT,
 526         /*!< For explicit timings from EDID, VBIOS, etc.*/
 527         TIMING_STANDARD_USER_OVERRIDE,
 528         /*!< For mode timing override by user*/
 529         TIMING_STANDARD_MAX
 530 };
 531
 532 enum dc_timing_3d_format {
 533         TIMING_3D_FORMAT_NONE,
 534         TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
 535         TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
 536         TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
 537         /* for active DP-HDMI dongle*/
 538         TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
 539         TIMING_3D_FORMAT_HW_FRAME_PACKING,
 540         TIMING_3D_FORMAT_SW_FRAME_PACKING,
 541         TIMING_3D_FORMAT_ROW_INTERLEAVE,
 542         TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
 543         TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
 544         TIMING_3D_FORMAT_SIDE_BY_SIDE,
 545         TIMING_3D_FORMAT_TOP_AND_BOTTOM,
 546         TIMING_3D_FORMAT_SBS_SW_PACKED,
 547         /* Side-by-side, packed by application/driver into 2D frame*/
 548         TIMING_3D_FORMAT_TB_SW_PACKED,
 549         /* Top-and-bottom, packed by application/driver into 2D frame*/
 550
 551         TIMING_3D_FORMAT_MAX,
 552 };
 553
 554 enum dc_color_depth {
 555         COLOR_DEPTH_UNDEFINED,
 556         COLOR_DEPTH_666,
 557         COLOR_DEPTH_888,
 558         COLOR_DEPTH_101010,
 559         COLOR_DEPTH_121212,
 560         COLOR_DEPTH_141414,
 561         COLOR_DEPTH_161616,
 562         COLOR_DEPTH_COUNT
 563 };
 564
 565 enum dc_pixel_encoding {
 566         PIXEL_ENCODING_UNDEFINED,
 567         PIXEL_ENCODING_RGB,
 568         PIXEL_ENCODING_YCBCR422,
 569         PIXEL_ENCODING_YCBCR444,
 570         PIXEL_ENCODING_YCBCR420,
 571         PIXEL_ENCODING_COUNT
 572 };
 573
 574 enum dc_aspect_ratio {
 575         ASPECT_RATIO_NO_DATA,
 576         ASPECT_RATIO_4_3,
 577         ASPECT_RATIO_16_9,
 578         ASPECT_RATIO_64_27,
 579         ASPECT_RATIO_256_135,
 580         ASPECT_RATIO_FUTURE
 581 };
 582
 583 enum scanning_type {
 584         SCANNING_TYPE_NODATA = 0,
 585         SCANNING_TYPE_OVERSCAN,
 586         SCANNING_TYPE_UNDERSCAN,
 587         SCANNING_TYPE_FUTURE,
 588         SCANNING_TYPE_UNDEFINED
 589 };
 590
 591 struct dc_crtc_timing_flags {
 592         uint32_t INTERLACE :1;
 593         uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 594          it is positive polarity --reversed with dal1 or video bios define*/
 595         uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 596          it is positive polarity --reversed with dal1 or video bios define*/
 597
 598         uint32_t HORZ_COUNT_BY_TWO:1;
 599
 600         uint32_t EXCLUSIVE_3D :1; /* if this bit set,
 601          timing can be driven in 3D format only
 602          and there is no corresponding 2D timing*/
 603         uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
 604          (right eye = '1', left eye = '0') */
 605         uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
 606          when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
 607         uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
 608          because corresponding 2D timing also present in the list*/
 609         uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
 610          and we want to match priority of corresponding 3D timing*/
 611         uint32_t Y_ONLY :1;
 612
 613         uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 614         uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 615
 616         /* HDMI 2.0 - Support scrambling for TMDS character
 617          * rates less than or equal to 340Mcsc */
 618         uint32_t LTE_340MCSC_SCRAMBLE:1;
 619
 620 };
 621
 622 struct dc_crtc_timing {
 623
 624         uint32_t h_total;
 625         uint32_t h_border_left;
 626         uint32_t h_addressable;
 627         uint32_t h_border_right;
 628         uint32_t h_front_porch;
 629         uint32_t h_sync_width;
 630
 631         uint32_t v_total;
 632         uint32_t v_border_top;
 633         uint32_t v_addressable;
 634         uint32_t v_border_bottom;
 635         uint32_t v_front_porch;
 636         uint32_t v_sync_width;
 637
 638         uint32_t pix_clk_khz;
 639
 640         uint32_t vic;
 641         uint32_t hdmi_vic;
 642         enum dc_timing_3d_format timing_3d_format;
 643         enum dc_color_depth display_color_depth;
 644         enum dc_pixel_encoding pixel_encoding;
 645         enum dc_aspect_ratio aspect_ratio;
 646         enum scanning_type scan_type;
 647
 648         struct dc_crtc_timing_flags flags;
 649 };
 650
 651 struct _dlg_otg_param {
 652         int vstartup_start;
 653         int vupdate_offset;
 654         int vupdate_width;
 655         int vready_offset;
 656         enum signal_type signal;
 657 };
 658
 659 #endif /* DC_HW_TYPES_H */
 660