2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "fixed31_32.h"
31 #include "signal_types.h"
33 /******************************************************************************
34 * Data types for Virtual HW Layer of DAL3.
35 * (see DAL3 design documents for HW Layer definition)
37 * The intended uses are:
38 * 1. Generation pseudocode sequences for HW programming.
39 * 2. Implementation of real HW programming by HW Sequencer of DAL3.
41 * Note: do *not* add any types which are *not* used for HW programming - this
42 * will ensure separation of Logic layer from HW layer.
43 ******************************************************************************/
59 #define PHYSICAL_ADDRESS_LOC union large_integer
61 enum dc_plane_addr_type
{
62 PLN_ADDR_TYPE_GRAPHICS
= 0,
63 PLN_ADDR_TYPE_GRPH_STEREO
,
64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
,
67 struct dc_plane_address
{
68 enum dc_plane_addr_type type
;
72 PHYSICAL_ADDRESS_LOC addr
;
73 PHYSICAL_ADDRESS_LOC meta_addr
;
74 union large_integer dcc_const_color
;
79 PHYSICAL_ADDRESS_LOC left_addr
;
80 PHYSICAL_ADDRESS_LOC left_meta_addr
;
81 union large_integer left_dcc_const_color
;
83 PHYSICAL_ADDRESS_LOC right_addr
;
84 PHYSICAL_ADDRESS_LOC right_meta_addr
;
85 union large_integer right_dcc_const_color
;
91 PHYSICAL_ADDRESS_LOC luma_addr
;
92 PHYSICAL_ADDRESS_LOC luma_meta_addr
;
93 union large_integer luma_dcc_const_color
;
95 PHYSICAL_ADDRESS_LOC chroma_addr
;
96 PHYSICAL_ADDRESS_LOC chroma_meta_addr
;
97 union large_integer chroma_dcc_const_color
;
115 /* Grph or Video will be selected
116 * based on format above:
117 * Use Video structure if
118 * format >= DalPixelFormat_VideoBegin
119 * else use Grph structure
122 struct rect surface_size
;
123 /* Graphic surface pitch in pixels.
124 * In LINEAR_GENERAL mode, pitch
125 * is 32 pixel aligned.
131 struct rect luma_size
;
132 /* Graphic surface pitch in pixels.
133 * In LINEAR_GENERAL mode, pitch is
138 struct rect chroma_size
;
139 /* Graphic surface pitch in pixels.
140 * In LINEAR_GENERAL mode, pitch is
147 struct dc_plane_dcc_param
{
153 bool independent_64b_blks
;
158 bool independent_64b_blks_l
;
161 bool independent_64b_blks_c
;
166 /*Displayable pixel format in fb*/
167 enum surface_pixel_format
{
168 SURFACE_PIXEL_FORMAT_GRPH_BEGIN
= 0,
169 /*TOBE REMOVED paletta 256 colors*/
170 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS
=
171 SURFACE_PIXEL_FORMAT_GRPH_BEGIN
,
173 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555
,
175 SURFACE_PIXEL_FORMAT_GRPH_RGB565
,
177 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
,
179 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
,
181 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
,
183 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
,
184 /*TOBE REMOVED swaped, XR_BIAS has no differance
185 * for pixel layout than previous and we can
186 * delete this after discusion*/
187 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
,
189 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
,
191 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
,
193 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
,
194 /*grow graphics here if necessary */
196 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
,
197 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
=
198 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
,
199 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
,
200 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr
,
201 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
,
202 SURFACE_PIXEL_FORMAT_INVALID
204 /*grow 444 video here if necessary */
212 PIXEL_FORMAT_UNINITIALIZED
,
215 PIXEL_FORMAT_ARGB8888
,
216 PIXEL_FORMAT_ARGB2101010
,
217 PIXEL_FORMAT_ARGB2101010_XRBIAS
,
220 PIXEL_FORMAT_420BPP8
,
221 PIXEL_FORMAT_420BPP10
,
222 /*end of pixel format definition*/
223 PIXEL_FORMAT_INVALID
,
225 PIXEL_FORMAT_GRPH_BEGIN
= PIXEL_FORMAT_INDEX8
,
226 PIXEL_FORMAT_GRPH_END
= PIXEL_FORMAT_FP16
,
227 PIXEL_FORMAT_VIDEO_BEGIN
= PIXEL_FORMAT_420BPP8
,
228 PIXEL_FORMAT_VIDEO_END
= PIXEL_FORMAT_420BPP10
,
232 enum tile_split_values
{
233 DC_DISPLAY_MICRO_TILING
= 0x0,
234 DC_THIN_MICRO_TILING
= 0x1,
235 DC_DEPTH_MICRO_TILING
= 0x2,
236 DC_ROTATED_MICRO_TILING
= 0x3,
239 /* TODO: These values come from hardware spec. We need to readdress this
240 * if they ever change.
242 enum array_mode_values
{
243 DC_ARRAY_LINEAR_GENERAL
= 0,
244 DC_ARRAY_LINEAR_ALLIGNED
,
245 DC_ARRAY_1D_TILED_THIN1
,
246 DC_ARRAY_1D_TILED_THICK
,
247 DC_ARRAY_2D_TILED_THIN1
,
248 DC_ARRAY_PRT_TILED_THIN1
,
249 DC_ARRAY_PRT_2D_TILED_THIN1
,
250 DC_ARRAY_2D_TILED_THICK
,
251 DC_ARRAY_2D_TILED_X_THICK
,
252 DC_ARRAY_PRT_TILED_THICK
,
253 DC_ARRAY_PRT_2D_TILED_THICK
,
254 DC_ARRAY_PRT_3D_TILED_THIN1
,
255 DC_ARRAY_3D_TILED_THIN1
,
256 DC_ARRAY_3D_TILED_THICK
,
257 DC_ARRAY_3D_TILED_X_THICK
,
258 DC_ARRAY_PRT_3D_TILED_THICK
,
261 enum tile_mode_values
{
262 DC_ADDR_SURF_MICRO_TILING_DISPLAY
= 0x0,
263 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY
= 0x1,
266 enum swizzle_mode_values
{
294 union dc_tiling_info
{
297 /* Specifies the number of memory banks for tiling
299 * Only applies to 2D and 3D tiling modes.
300 * POSSIBLE VALUES: 2,4,8,16
302 unsigned int num_banks
;
303 /* Specifies the number of tiles in the x direction
304 * to be incorporated into the same bank.
305 * Only applies to 2D and 3D tiling modes.
306 * POSSIBLE VALUES: 1,2,4,8
308 unsigned int bank_width
;
309 unsigned int bank_width_c
;
310 /* Specifies the number of tiles in the y direction to
311 * be incorporated into the same bank.
312 * Only applies to 2D and 3D tiling modes.
313 * POSSIBLE VALUES: 1,2,4,8
315 unsigned int bank_height
;
316 unsigned int bank_height_c
;
317 /* Specifies the macro tile aspect ratio. Only applies
318 * to 2D and 3D tiling modes.
320 unsigned int tile_aspect
;
321 unsigned int tile_aspect_c
;
322 /* Specifies the number of bytes that will be stored
323 * contiguously for each tile.
324 * If the tile data requires more storage than this
325 * amount, it is split into multiple slices.
326 * This field must not be larger than
327 * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
328 * Only applies to 2D and 3D tiling modes.
329 * For color render targets, TILE_SPLIT >= 256B.
331 enum tile_split_values tile_split
;
332 enum tile_split_values tile_split_c
;
333 /* Specifies the addressing within a tile.
334 * 0x0 - DISPLAY_MICRO_TILING
335 * 0x1 - THIN_MICRO_TILING
336 * 0x2 - DEPTH_MICRO_TILING
337 * 0x3 - ROTATED_MICRO_TILING
339 enum tile_mode_values tile_mode
;
340 enum tile_mode_values tile_mode_c
;
341 /* Specifies the number of pipes and how they are
342 * interleaved in the surface.
343 * Refer to memory addressing document for complete
344 * details and constraints.
346 unsigned int pipe_config
;
347 /* Specifies the tiling mode of the surface.
348 * THIN tiles use an 8x8x1 tile size.
349 * THICK tiles use an 8x8x4 tile size.
350 * 2D tiling modes rotate banks for successive Z slices
351 * 3D tiling modes rotate pipes and banks for Z slices
352 * Refer to memory addressing document for complete
353 * details and constraints.
355 enum array_mode_values array_mode
;
359 unsigned int num_pipes
;
360 unsigned int num_banks
;
361 unsigned int pipe_interleave
;
362 unsigned int num_shader_engines
;
363 unsigned int num_rb_per_se
;
364 unsigned int max_compressed_frags
;
367 enum swizzle_mode_values swizzle
;
375 enum dc_rotation_angle
{
376 ROTATION_ANGLE_0
= 0,
383 enum dc_scan_direction
{
384 SCAN_DIRECTION_UNKNOWN
= 0,
385 SCAN_DIRECTION_HORIZONTAL
= 1, /* 0, 180 rotation */
386 SCAN_DIRECTION_VERTICAL
= 2, /* 90, 270 rotation */
389 struct dc_cursor_position
{
397 * This parameter indicates whether HW cursor should be enabled
403 struct dc_cursor_mi_param
{
404 unsigned int pixel_clk_khz
;
405 unsigned int ref_clk_khz
;
406 unsigned int viewport_x_start
;
407 unsigned int viewport_width
;
408 struct fixed31_32 h_scale_ratio
;
411 /* IPP related types */
414 GAMMA_RGB_256_ENTRIES
= 256,
415 GAMMA_RGB_FLOAT_1024_ENTRIES
= 1024,
416 GAMMA_MAX_ENTRIES
= 1024
421 GAMMA_RGB_FLOAT_1024
= 2
425 struct kref refcount
;
426 enum dc_gamma_type type
;
427 unsigned int num_entries
;
429 struct dc_gamma_entries
{
430 struct fixed31_32 red
[GAMMA_MAX_ENTRIES
];
431 struct fixed31_32 green
[GAMMA_MAX_ENTRIES
];
432 struct fixed31_32 blue
[GAMMA_MAX_ENTRIES
];
435 /* private to DC core */
436 struct dc_context
*ctx
;
439 /* Used by both ipp amd opp functions*/
440 /* TODO: to be consolidated with enum color_space */
443 * This enum is for programming CURSOR_MODE register field. What this register
444 * should be programmed to depends on OS requested cursor shape flags and what
445 * we stored in the cursor surface.
447 enum dc_cursor_color_format
{
449 CURSOR_MODE_COLOR_1BIT_AND
,
450 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA
,
451 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
455 * This is all the parameters required by DAL in order to update the cursor
456 * attributes, including the new cursor image surface address, size, hotspot
457 * location, color format, etc.
460 union dc_cursor_attribute_flags
{
462 uint32_t ENABLE_MAGNIFICATION
:1;
463 uint32_t INVERSE_TRANSPARENT_CLAMPING
:1;
464 uint32_t HORIZONTAL_MIRROR
:1;
465 uint32_t VERTICAL_MIRROR
:1;
466 uint32_t INVERT_PIXEL_DATA
:1;
467 uint32_t ZERO_EXPANSION
:1;
468 uint32_t MIN_MAX_INVERT
:1;
469 uint32_t RESERVED
:25;
474 struct dc_cursor_attributes
{
475 PHYSICAL_ADDRESS_LOC address
;
478 /* Width and height should correspond to cursor surface width x heigh */
482 enum dc_cursor_color_format color_format
;
484 /* In case we support HW Cursor rotation in the future */
485 enum dc_rotation_angle rotation_angle
;
487 union dc_cursor_attribute_flags attribute_flags
;
492 enum dc_color_space
{
495 COLOR_SPACE_SRGB_LIMITED
,
496 COLOR_SPACE_YCBCR601
,
497 COLOR_SPACE_YCBCR709
,
498 COLOR_SPACE_YCBCR601_LIMITED
,
499 COLOR_SPACE_YCBCR709_LIMITED
,
500 COLOR_SPACE_2020_RGB_FULLRANGE
,
501 COLOR_SPACE_2020_RGB_LIMITEDRANGE
,
502 COLOR_SPACE_2020_YCBCR
,
503 COLOR_SPACE_ADOBERGB
,
506 enum dc_dither_option
{
507 DITHER_OPTION_DEFAULT
,
508 DITHER_OPTION_DISABLE
,
512 DITHER_OPTION_SPATIAL6_FRAME_RANDOM
,
513 DITHER_OPTION_SPATIAL8_FRAME_RANDOM
,
514 DITHER_OPTION_SPATIAL10_FRAME_RANDOM
,
515 DITHER_OPTION_SPATIAL6
,
516 DITHER_OPTION_SPATIAL8
,
517 DITHER_OPTION_SPATIAL10
,
520 DITHER_OPTION_TRUN10
,
521 DITHER_OPTION_TRUN10_SPATIAL8
,
522 DITHER_OPTION_TRUN10_SPATIAL6
,
523 DITHER_OPTION_TRUN10_FM8
,
524 DITHER_OPTION_TRUN10_FM6
,
525 DITHER_OPTION_TRUN10_SPATIAL8_FM6
,
526 DITHER_OPTION_SPATIAL10_FM8
,
527 DITHER_OPTION_SPATIAL10_FM6
,
528 DITHER_OPTION_TRUN8_SPATIAL6
,
529 DITHER_OPTION_TRUN8_FM6
,
530 DITHER_OPTION_SPATIAL8_FM6
,
531 DITHER_OPTION_MAX
= DITHER_OPTION_SPATIAL8_FM6
,
532 DITHER_OPTION_INVALID
535 enum dc_quantization_range
{
536 QUANTIZATION_RANGE_UNKNOWN
,
537 QUANTIZATION_RANGE_FULL
,
538 QUANTIZATION_RANGE_LIMITED
543 /* used in struct dc_plane_state */
544 struct scaling_taps
{
551 enum dc_timing_standard
{
552 TIMING_STANDARD_UNDEFINED
,
556 TIMING_STANDARD_CVT_RB
,
557 TIMING_STANDARD_CEA770
,
558 TIMING_STANDARD_CEA861
,
559 TIMING_STANDARD_HDMI
,
560 TIMING_STANDARD_TV_NTSC
,
561 TIMING_STANDARD_TV_NTSC_J
,
562 TIMING_STANDARD_TV_PAL
,
563 TIMING_STANDARD_TV_PAL_M
,
564 TIMING_STANDARD_TV_PAL_CN
,
565 TIMING_STANDARD_TV_SECAM
,
566 TIMING_STANDARD_EXPLICIT
,
567 /*!< For explicit timings from EDID, VBIOS, etc.*/
568 TIMING_STANDARD_USER_OVERRIDE
,
569 /*!< For mode timing override by user*/
575 enum dc_color_depth
{
576 COLOR_DEPTH_UNDEFINED
,
586 enum dc_pixel_encoding
{
587 PIXEL_ENCODING_UNDEFINED
,
589 PIXEL_ENCODING_YCBCR422
,
590 PIXEL_ENCODING_YCBCR444
,
591 PIXEL_ENCODING_YCBCR420
,
595 enum dc_aspect_ratio
{
596 ASPECT_RATIO_NO_DATA
,
600 ASPECT_RATIO_256_135
,
605 SCANNING_TYPE_NODATA
= 0,
606 SCANNING_TYPE_OVERSCAN
,
607 SCANNING_TYPE_UNDERSCAN
,
608 SCANNING_TYPE_FUTURE
,
609 SCANNING_TYPE_UNDEFINED
612 struct dc_crtc_timing_flags
{
613 uint32_t INTERLACE
:1;
614 uint32_t HSYNC_POSITIVE_POLARITY
:1; /* when set to 1,
615 it is positive polarity --reversed with dal1 or video bios define*/
616 uint32_t VSYNC_POSITIVE_POLARITY
:1; /* when set to 1,
617 it is positive polarity --reversed with dal1 or video bios define*/
619 uint32_t HORZ_COUNT_BY_TWO
:1;
621 uint32_t EXCLUSIVE_3D
:1; /* if this bit set,
622 timing can be driven in 3D format only
623 and there is no corresponding 2D timing*/
624 uint32_t RIGHT_EYE_3D_POLARITY
:1; /* 1 - means right eye polarity
625 (right eye = '1', left eye = '0') */
626 uint32_t SUB_SAMPLE_3D
:1; /* 1 - means left/right images subsampled
627 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
628 uint32_t USE_IN_3D_VIEW_ONLY
:1; /* Do not use this timing in 2D View,
629 because corresponding 2D timing also present in the list*/
630 uint32_t STEREO_3D_PREFERENCE
:1; /* Means this is 2D timing
631 and we want to match priority of corresponding 3D timing*/
634 uint32_t YCBCR420
:1; /* TODO: shouldn't need this flag, should be a separate pixel format */
635 uint32_t DTD_COUNTER
:5; /* values 1 to 16 */
637 uint32_t FORCE_HDR
:1;
639 /* HDMI 2.0 - Support scrambling for TMDS character
640 * rates less than or equal to 340Mcsc */
641 uint32_t LTE_340MCSC_SCRAMBLE
:1;
645 enum dc_timing_3d_format
{
646 TIMING_3D_FORMAT_NONE
,
647 TIMING_3D_FORMAT_FRAME_ALTERNATE
, /* No stereosync at all*/
648 TIMING_3D_FORMAT_INBAND_FA
, /* Inband Frame Alternate (DVI/DP)*/
649 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA
, /* Inband FA to HDMI Frame Pack*/
650 /* for active DP-HDMI dongle*/
651 TIMING_3D_FORMAT_SIDEBAND_FA
, /* Sideband Frame Alternate (eDP)*/
652 TIMING_3D_FORMAT_HW_FRAME_PACKING
,
653 TIMING_3D_FORMAT_SW_FRAME_PACKING
,
654 TIMING_3D_FORMAT_ROW_INTERLEAVE
,
655 TIMING_3D_FORMAT_COLUMN_INTERLEAVE
,
656 TIMING_3D_FORMAT_PIXEL_INTERLEAVE
,
657 TIMING_3D_FORMAT_SIDE_BY_SIDE
,
658 TIMING_3D_FORMAT_TOP_AND_BOTTOM
,
659 TIMING_3D_FORMAT_SBS_SW_PACKED
,
660 /* Side-by-side, packed by application/driver into 2D frame*/
661 TIMING_3D_FORMAT_TB_SW_PACKED
,
662 /* Top-and-bottom, packed by application/driver into 2D frame*/
664 TIMING_3D_FORMAT_MAX
,
668 struct dc_crtc_timing
{
671 uint32_t h_border_left
;
672 uint32_t h_addressable
;
673 uint32_t h_border_right
;
674 uint32_t h_front_porch
;
675 uint32_t h_sync_width
;
678 uint32_t v_border_top
;
679 uint32_t v_addressable
;
680 uint32_t v_border_bottom
;
681 uint32_t v_front_porch
;
682 uint32_t v_sync_width
;
684 uint32_t pix_clk_khz
;
688 enum dc_timing_3d_format timing_3d_format
;
689 enum dc_color_depth display_color_depth
;
690 enum dc_pixel_encoding pixel_encoding
;
691 enum dc_aspect_ratio aspect_ratio
;
692 enum scanning_type scan_type
;
694 struct dc_crtc_timing_flags flags
;
697 #define MAX_TG_COLOR_VALUE 0x3FF
699 /* Maximum 10 bits color value */
705 #endif /* DC_HW_TYPES_H */