2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "fixed31_32.h"
32 /******************************************************************************
33 * Data types for Virtual HW Layer of DAL3.
34 * (see DAL3 design documents for HW Layer definition)
36 * The intended uses are:
37 * 1. Generation pseudocode sequences for HW programming.
38 * 2. Implementation of real HW programming by HW Sequencer of DAL3.
40 * Note: do *not* add any types which are *not* used for HW programming - this
41 * will ensure separation of Logic layer from HW layer.
42 ******************************************************************************/
58 #define PHYSICAL_ADDRESS_LOC union large_integer
60 enum dc_plane_addr_type
{
61 PLN_ADDR_TYPE_GRAPHICS
= 0,
62 PLN_ADDR_TYPE_GRPH_STEREO
,
63 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
,
66 struct dc_plane_address
{
67 enum dc_plane_addr_type type
;
70 PHYSICAL_ADDRESS_LOC addr
;
71 PHYSICAL_ADDRESS_LOC meta_addr
;
72 union large_integer dcc_const_color
;
77 PHYSICAL_ADDRESS_LOC left_addr
;
78 PHYSICAL_ADDRESS_LOC left_meta_addr
;
79 union large_integer left_dcc_const_color
;
81 PHYSICAL_ADDRESS_LOC right_addr
;
82 PHYSICAL_ADDRESS_LOC right_meta_addr
;
83 union large_integer right_dcc_const_color
;
89 PHYSICAL_ADDRESS_LOC luma_addr
;
90 PHYSICAL_ADDRESS_LOC luma_meta_addr
;
91 union large_integer luma_dcc_const_color
;
93 PHYSICAL_ADDRESS_LOC chroma_addr
;
94 PHYSICAL_ADDRESS_LOC chroma_meta_addr
;
95 union large_integer chroma_dcc_const_color
;
113 /* Grph or Video will be selected
114 * based on format above:
115 * Use Video structure if
116 * format >= DalPixelFormat_VideoBegin
117 * else use Grph structure
120 struct rect surface_size
;
121 /* Graphic surface pitch in pixels.
122 * In LINEAR_GENERAL mode, pitch
123 * is 32 pixel aligned.
125 uint32_t surface_pitch
;
129 struct rect luma_size
;
130 /* Graphic surface pitch in pixels.
131 * In LINEAR_GENERAL mode, pitch is
136 struct rect chroma_size
;
137 /* Graphic surface pitch in pixels.
138 * In LINEAR_GENERAL mode, pitch is
141 uint32_t chroma_pitch
;
145 struct dc_plane_dcc_param
{
151 bool independent_64b_blks
;
155 uint32_t meta_pitch_l
;
156 bool independent_64b_blks_l
;
158 uint32_t meta_pitch_c
;
159 bool independent_64b_blks_c
;
164 /*Displayable pixel format in fb*/
165 enum surface_pixel_format
{
166 SURFACE_PIXEL_FORMAT_GRPH_BEGIN
= 0,
167 /*TOBE REMOVED paletta 256 colors*/
168 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS
=
169 SURFACE_PIXEL_FORMAT_GRPH_BEGIN
,
171 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555
,
173 SURFACE_PIXEL_FORMAT_GRPH_RGB565
,
175 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
,
177 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
,
179 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
,
181 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
,
182 /*TOBE REMOVED swaped, XR_BIAS has no differance
183 * for pixel layout than previous and we can
184 * delete this after discusion*/
185 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
,
187 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
,
189 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
,
191 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
,
192 /*grow graphics here if necessary */
194 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
,
195 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
=
196 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
,
197 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
,
198 SURFACE_PIXEL_FORMAT_INVALID
200 /*grow 444 video here if necessary */
206 PIXEL_FORMAT_UNINITIALIZED
,
209 PIXEL_FORMAT_ARGB8888
,
210 PIXEL_FORMAT_ARGB2101010
,
211 PIXEL_FORMAT_ARGB2101010_XRBIAS
,
214 PIXEL_FORMAT_420BPP12
,
215 /*end of pixel format definition*/
216 PIXEL_FORMAT_INVALID
,
218 PIXEL_FORMAT_GRPH_BEGIN
= PIXEL_FORMAT_INDEX8
,
219 PIXEL_FORMAT_GRPH_END
= PIXEL_FORMAT_FP16
,
220 PIXEL_FORMAT_VIDEO_BEGIN
= PIXEL_FORMAT_420BPP12
,
221 PIXEL_FORMAT_VIDEO_END
= PIXEL_FORMAT_420BPP12
,
225 enum tile_split_values
{
226 DC_DISPLAY_MICRO_TILING
= 0x0,
227 DC_THIN_MICRO_TILING
= 0x1,
228 DC_DEPTH_MICRO_TILING
= 0x2,
229 DC_ROTATED_MICRO_TILING
= 0x3,
232 /* TODO: These values come from hardware spec. We need to readdress this
233 * if they ever change.
235 enum array_mode_values
{
236 DC_ARRAY_LINEAR_GENERAL
= 0,
237 DC_ARRAY_LINEAR_ALLIGNED
,
238 DC_ARRAY_1D_TILED_THIN1
,
239 DC_ARRAY_1D_TILED_THICK
,
240 DC_ARRAY_2D_TILED_THIN1
,
241 DC_ARRAY_PRT_TILED_THIN1
,
242 DC_ARRAY_PRT_2D_TILED_THIN1
,
243 DC_ARRAY_2D_TILED_THICK
,
244 DC_ARRAY_2D_TILED_X_THICK
,
245 DC_ARRAY_PRT_TILED_THICK
,
246 DC_ARRAY_PRT_2D_TILED_THICK
,
247 DC_ARRAY_PRT_3D_TILED_THIN1
,
248 DC_ARRAY_3D_TILED_THIN1
,
249 DC_ARRAY_3D_TILED_THICK
,
250 DC_ARRAY_3D_TILED_X_THICK
,
251 DC_ARRAY_PRT_3D_TILED_THICK
,
254 enum tile_mode_values
{
255 DC_ADDR_SURF_MICRO_TILING_DISPLAY
= 0x0,
256 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY
= 0x1,
259 union dc_tiling_info
{
262 /* Specifies the number of memory banks for tiling
264 * Only applies to 2D and 3D tiling modes.
265 * POSSIBLE VALUES: 2,4,8,16
267 unsigned int num_banks
;
268 /* Specifies the number of tiles in the x direction
269 * to be incorporated into the same bank.
270 * Only applies to 2D and 3D tiling modes.
271 * POSSIBLE VALUES: 1,2,4,8
273 unsigned int bank_width
;
274 unsigned int bank_width_c
;
275 /* Specifies the number of tiles in the y direction to
276 * be incorporated into the same bank.
277 * Only applies to 2D and 3D tiling modes.
278 * POSSIBLE VALUES: 1,2,4,8
280 unsigned int bank_height
;
281 unsigned int bank_height_c
;
282 /* Specifies the macro tile aspect ratio. Only applies
283 * to 2D and 3D tiling modes.
285 unsigned int tile_aspect
;
286 unsigned int tile_aspect_c
;
287 /* Specifies the number of bytes that will be stored
288 * contiguously for each tile.
289 * If the tile data requires more storage than this
290 * amount, it is split into multiple slices.
291 * This field must not be larger than
292 * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
293 * Only applies to 2D and 3D tiling modes.
294 * For color render targets, TILE_SPLIT >= 256B.
296 enum tile_split_values tile_split
;
297 enum tile_split_values tile_split_c
;
298 /* Specifies the addressing within a tile.
299 * 0x0 - DISPLAY_MICRO_TILING
300 * 0x1 - THIN_MICRO_TILING
301 * 0x2 - DEPTH_MICRO_TILING
302 * 0x3 - ROTATED_MICRO_TILING
304 enum tile_mode_values tile_mode
;
305 enum tile_mode_values tile_mode_c
;
306 /* Specifies the number of pipes and how they are
307 * interleaved in the surface.
308 * Refer to memory addressing document for complete
309 * details and constraints.
311 unsigned int pipe_config
;
312 /* Specifies the tiling mode of the surface.
313 * THIN tiles use an 8x8x1 tile size.
314 * THICK tiles use an 8x8x4 tile size.
315 * 2D tiling modes rotate banks for successive Z slices
316 * 3D tiling modes rotate pipes and banks for Z slices
317 * Refer to memory addressing document for complete
318 * details and constraints.
320 enum array_mode_values array_mode
;
326 enum dc_rotation_angle
{
327 ROTATION_ANGLE_0
= 0,
334 enum dc_scan_direction
{
335 SCAN_DIRECTION_UNKNOWN
= 0,
336 SCAN_DIRECTION_HORIZONTAL
= 1, /* 0, 180 rotation */
337 SCAN_DIRECTION_VERTICAL
= 2, /* 90, 270 rotation */
340 struct dc_cursor_position
{
348 * This parameter indicates whether HW cursor should be enabled
353 * This parameter indicates whether cursor hot spot should be
356 bool hot_spot_enable
;
359 struct dc_cursor_mi_param
{
360 unsigned int pixel_clk_khz
;
361 unsigned int ref_clk_khz
;
362 unsigned int viewport_x_start
;
363 unsigned int viewport_width
;
364 struct fixed31_32 h_scale_ratio
;
367 /* IPP related types */
370 INPUT_LUT_ENTRIES
= 256
374 uint16_t red
[INPUT_LUT_ENTRIES
];
375 uint16_t green
[INPUT_LUT_ENTRIES
];
376 uint16_t blue
[INPUT_LUT_ENTRIES
];
379 /* Used by both ipp amd opp functions*/
380 /* TODO: to be consolidated with enum color_space */
383 * This enum is for programming CURSOR_MODE register field. What this register
384 * should be programmed to depends on OS requested cursor shape flags and what
385 * we stored in the cursor surface.
387 enum dc_cursor_color_format
{
389 CURSOR_MODE_COLOR_1BIT_AND
,
390 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA
,
391 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
395 * This is all the parameters required by DAL in order to update the cursor
396 * attributes, including the new cursor image surface address, size, hotspot
397 * location, color format, etc.
400 union dc_cursor_attribute_flags
{
402 uint32_t ENABLE_MAGNIFICATION
:1;
403 uint32_t INVERSE_TRANSPARENT_CLAMPING
:1;
404 uint32_t HORIZONTAL_MIRROR
:1;
405 uint32_t VERTICAL_MIRROR
:1;
406 uint32_t INVERT_PIXEL_DATA
:1;
407 uint32_t ZERO_EXPANSION
:1;
408 uint32_t MIN_MAX_INVERT
:1;
409 uint32_t RESERVED
:25;
414 struct dc_cursor_attributes
{
415 PHYSICAL_ADDRESS_LOC address
;
418 /* Width and height should correspond to cursor surface width x heigh */
424 enum dc_cursor_color_format color_format
;
426 /* In case we support HW Cursor rotation in the future */
427 enum dc_rotation_angle rotation_angle
;
429 union dc_cursor_attribute_flags attribute_flags
;
434 enum dc_color_space
{
437 COLOR_SPACE_SRGB_LIMITED
,
438 COLOR_SPACE_YCBCR601
,
439 COLOR_SPACE_YCBCR709
,
440 COLOR_SPACE_YCBCR601_LIMITED
,
441 COLOR_SPACE_YCBCR709_LIMITED
,
442 COLOR_SPACE_2020_RGB_FULLRANGE
,
443 COLOR_SPACE_2020_RGB_LIMITEDRANGE
,
444 COLOR_SPACE_2020_YCBCR
,
445 COLOR_SPACE_ADOBERGB
,
448 enum dc_quantization_range
{
449 QUANTIZATION_RANGE_UNKNOWN
,
450 QUANTIZATION_RANGE_FULL
,
451 QUANTIZATION_RANGE_LIMITED
456 /* used in struct dc_surface */
457 struct scaling_taps
{
464 enum dc_timing_standard
{
465 TIMING_STANDARD_UNDEFINED
,
469 TIMING_STANDARD_CVT_RB
,
470 TIMING_STANDARD_CEA770
,
471 TIMING_STANDARD_CEA861
,
472 TIMING_STANDARD_HDMI
,
473 TIMING_STANDARD_TV_NTSC
,
474 TIMING_STANDARD_TV_NTSC_J
,
475 TIMING_STANDARD_TV_PAL
,
476 TIMING_STANDARD_TV_PAL_M
,
477 TIMING_STANDARD_TV_PAL_CN
,
478 TIMING_STANDARD_TV_SECAM
,
479 TIMING_STANDARD_EXPLICIT
,
480 /*!< For explicit timings from EDID, VBIOS, etc.*/
481 TIMING_STANDARD_USER_OVERRIDE
,
482 /*!< For mode timing override by user*/
486 enum dc_timing_3d_format
{
487 TIMING_3D_FORMAT_NONE
,
488 TIMING_3D_FORMAT_FRAME_ALTERNATE
, /* No stereosync at all*/
489 TIMING_3D_FORMAT_INBAND_FA
, /* Inband Frame Alternate (DVI/DP)*/
490 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA
, /* Inband FA to HDMI Frame Pack*/
491 /* for active DP-HDMI dongle*/
492 TIMING_3D_FORMAT_SIDEBAND_FA
, /* Sideband Frame Alternate (eDP)*/
493 TIMING_3D_FORMAT_HW_FRAME_PACKING
,
494 TIMING_3D_FORMAT_SW_FRAME_PACKING
,
495 TIMING_3D_FORMAT_ROW_INTERLEAVE
,
496 TIMING_3D_FORMAT_COLUMN_INTERLEAVE
,
497 TIMING_3D_FORMAT_PIXEL_INTERLEAVE
,
498 TIMING_3D_FORMAT_SIDE_BY_SIDE
,
499 TIMING_3D_FORMAT_TOP_AND_BOTTOM
,
500 TIMING_3D_FORMAT_SBS_SW_PACKED
,
501 /* Side-by-side, packed by application/driver into 2D frame*/
502 TIMING_3D_FORMAT_TB_SW_PACKED
,
503 /* Top-and-bottom, packed by application/driver into 2D frame*/
505 TIMING_3D_FORMAT_MAX
,
508 enum dc_color_depth
{
509 COLOR_DEPTH_UNDEFINED
,
519 enum dc_pixel_encoding
{
520 PIXEL_ENCODING_UNDEFINED
,
522 PIXEL_ENCODING_YCBCR422
,
523 PIXEL_ENCODING_YCBCR444
,
524 PIXEL_ENCODING_YCBCR420
,
528 enum dc_aspect_ratio
{
529 ASPECT_RATIO_NO_DATA
,
533 ASPECT_RATIO_256_135
,
538 SCANNING_TYPE_NODATA
= 0,
539 SCANNING_TYPE_OVERSCAN
,
540 SCANNING_TYPE_UNDERSCAN
,
541 SCANNING_TYPE_FUTURE
,
542 SCANNING_TYPE_UNDEFINED
545 struct dc_crtc_timing_flags
{
546 uint32_t INTERLACE
:1;
547 uint32_t HSYNC_POSITIVE_POLARITY
:1; /* when set to 1,
548 it is positive polarity --reversed with dal1 or video bios define*/
549 uint32_t VSYNC_POSITIVE_POLARITY
:1; /* when set to 1,
550 it is positive polarity --reversed with dal1 or video bios define*/
552 uint32_t HORZ_COUNT_BY_TWO
:1;
554 uint32_t EXCLUSIVE_3D
:1; /* if this bit set,
555 timing can be driven in 3D format only
556 and there is no corresponding 2D timing*/
557 uint32_t RIGHT_EYE_3D_POLARITY
:1; /* 1 - means right eye polarity
558 (right eye = '1', left eye = '0') */
559 uint32_t SUB_SAMPLE_3D
:1; /* 1 - means left/right images subsampled
560 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
561 uint32_t USE_IN_3D_VIEW_ONLY
:1; /* Do not use this timing in 2D View,
562 because corresponding 2D timing also present in the list*/
563 uint32_t STEREO_3D_PREFERENCE
:1; /* Means this is 2D timing
564 and we want to match priority of corresponding 3D timing*/
567 uint32_t YCBCR420
:1; /* TODO: shouldn't need this flag, should be a separate pixel format */
568 uint32_t DTD_COUNTER
:5; /* values 1 to 16 */
570 /* HDMI 2.0 - Support scrambling for TMDS character
571 * rates less than or equal to 340Mcsc */
572 uint32_t LTE_340MCSC_SCRAMBLE
:1;
576 struct dc_crtc_timing
{
579 uint32_t h_border_left
;
580 uint32_t h_addressable
;
581 uint32_t h_border_right
;
582 uint32_t h_front_porch
;
583 uint32_t h_sync_width
;
586 uint32_t v_border_top
;
587 uint32_t v_addressable
;
588 uint32_t v_border_bottom
;
589 uint32_t v_front_porch
;
590 uint32_t v_sync_width
;
592 uint32_t pix_clk_khz
;
596 enum dc_timing_3d_format timing_3d_format
;
597 enum dc_color_depth display_color_depth
;
598 enum dc_pixel_encoding pixel_encoding
;
599 enum dc_aspect_ratio aspect_ratio
;
600 enum scanning_type scan_type
;
602 struct dc_crtc_timing_flags flags
;
605 #endif /* DC_HW_TYPES_H */