drivers/gpu/drm/amd/display/dc/dc_hw_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_HW_TYPES_H
  27 #define DC_HW_TYPES_H
  28
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31
  32 /******************************************************************************
  33  * Data types for Virtual HW Layer of DAL3.
  34  * (see DAL3 design documents for HW Layer definition)
  35  *
  36  * The intended uses are:
  37  * 1. Generation pseudocode sequences for HW programming.
  38  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
  39  *
  40  * Note: do *not* add any types which are *not* used for HW programming - this
  41  * will ensure separation of Logic layer from HW layer.
  42  ******************************************************************************/
  43
  44 union large_integer {
  45         struct {
  46                 uint32_t low_part;
  47                 int32_t high_part;
  48         };
  49
  50         struct {
  51                 uint32_t low_part;
  52                 int32_t high_part;
  53         } u;
  54
  55         int64_t quad_part;
  56 };
  57
  58 #define PHYSICAL_ADDRESS_LOC union large_integer
  59
  60 enum dc_plane_addr_type {
  61         PLN_ADDR_TYPE_GRAPHICS = 0,
  62         PLN_ADDR_TYPE_GRPH_STEREO,
  63         PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
  64 };
  65
  66 struct dc_plane_address {
  67         enum dc_plane_addr_type type;
  68         union {
  69                 struct{
  70                         PHYSICAL_ADDRESS_LOC addr;
  71                         PHYSICAL_ADDRESS_LOC meta_addr;
  72                         union large_integer dcc_const_color;
  73                 } grph;
  74
  75                 /*stereo*/
  76                 struct {
  77                         PHYSICAL_ADDRESS_LOC left_addr;
  78                         PHYSICAL_ADDRESS_LOC left_meta_addr;
  79                         union large_integer left_dcc_const_color;
  80
  81                         PHYSICAL_ADDRESS_LOC right_addr;
  82                         PHYSICAL_ADDRESS_LOC right_meta_addr;
  83                         union large_integer right_dcc_const_color;
  84
  85                 } grph_stereo;
  86
  87                 /*video  progressive*/
  88                 struct {
  89                         PHYSICAL_ADDRESS_LOC luma_addr;
  90                         PHYSICAL_ADDRESS_LOC luma_meta_addr;
  91                         union large_integer luma_dcc_const_color;
  92
  93                         PHYSICAL_ADDRESS_LOC chroma_addr;
  94                         PHYSICAL_ADDRESS_LOC chroma_meta_addr;
  95                         union large_integer chroma_dcc_const_color;
  96                 } video_progressive;
  97         };
  98 };
  99
 100 struct dc_size {
 101         uint32_t width;
 102         uint32_t height;
 103 };
 104
 105 struct rect {
 106         int x;
 107         int y;
 108         uint32_t width;
 109         uint32_t height;
 110 };
 111
 112 union plane_size {
 113         /* Grph or Video will be selected
 114          * based on format above:
 115          * Use Video structure if
 116          * format >= DalPixelFormat_VideoBegin
 117          * else use Grph structure
 118          */
 119         struct {
 120                 struct rect surface_size;
 121                 /* Graphic surface pitch in pixels.
 122                  * In LINEAR_GENERAL mode, pitch
 123                  * is 32 pixel aligned.
 124                  */
 125                 uint32_t surface_pitch;
 126         } grph;
 127
 128         struct {
 129                 struct rect luma_size;
 130                 /* Graphic surface pitch in pixels.
 131                  * In LINEAR_GENERAL mode, pitch is
 132                  * 32 pixel aligned.
 133                  */
 134                 uint32_t luma_pitch;
 135
 136                 struct rect chroma_size;
 137                 /* Graphic surface pitch in pixels.
 138                  * In LINEAR_GENERAL mode, pitch is
 139                  * 32 pixel aligned.
 140                  */
 141                 uint32_t chroma_pitch;
 142         } video;
 143 };
 144
 145 struct dc_plane_dcc_param {
 146         bool enable;
 147
 148         union {
 149                 struct {
 150                         uint32_t meta_pitch;
 151                         bool independent_64b_blks;
 152                 } grph;
 153
 154                 struct {
 155                         uint32_t meta_pitch_l;
 156                         bool independent_64b_blks_l;
 157
 158                         uint32_t meta_pitch_c;
 159                         bool independent_64b_blks_c;
 160                 } video;
 161         };
 162 };
 163
 164 /*Displayable pixel format in fb*/
 165 enum surface_pixel_format {
 166         SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
 167         /*TOBE REMOVED paletta 256 colors*/
 168         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
 169                 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
 170         /*16 bpp*/
 171         SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
 172         /*16 bpp*/
 173         SURFACE_PIXEL_FORMAT_GRPH_RGB565,
 174         /*32 bpp*/
 175         SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
 176         /*32 bpp swaped*/
 177         SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
 178
 179         SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
 180         /*swaped*/
 181         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
 182         /*TOBE REMOVED swaped, XR_BIAS has no differance
 183          * for pixel layout than previous and we can
 184          * delete this after discusion*/
 185         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 186         /*64 bpp */
 187         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
 188         /*float*/
 189         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 190         /*swaped & float*/
 191         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
 192         /*grow graphics here if necessary */
 193
 194         SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 195         SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 196                 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 197         SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
 198         SURFACE_PIXEL_FORMAT_INVALID
 199
 200         /*grow 444 video here if necessary */
 201 };
 202
 203 /* Pixel format */
 204 enum pixel_format {
 205         /*graph*/
 206         PIXEL_FORMAT_UNINITIALIZED,
 207         PIXEL_FORMAT_INDEX8,
 208         PIXEL_FORMAT_RGB565,
 209         PIXEL_FORMAT_ARGB8888,
 210         PIXEL_FORMAT_ARGB2101010,
 211         PIXEL_FORMAT_ARGB2101010_XRBIAS,
 212         PIXEL_FORMAT_FP16,
 213         /*video*/
 214         PIXEL_FORMAT_420BPP12,
 215         /*end of pixel format definition*/
 216         PIXEL_FORMAT_INVALID,
 217
 218         PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
 219         PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
 220         PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12,
 221         PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP12,
 222         PIXEL_FORMAT_UNKNOWN
 223 };
 224
 225 enum tile_split_values {
 226         DC_DISPLAY_MICRO_TILING = 0x0,
 227         DC_THIN_MICRO_TILING = 0x1,
 228         DC_DEPTH_MICRO_TILING = 0x2,
 229         DC_ROTATED_MICRO_TILING = 0x3,
 230 };
 231
 232 /* TODO: These values come from hardware spec. We need to readdress this
 233  * if they ever change.
 234  */
 235 enum array_mode_values {
 236         DC_ARRAY_LINEAR_GENERAL = 0,
 237         DC_ARRAY_LINEAR_ALLIGNED,
 238         DC_ARRAY_1D_TILED_THIN1,
 239         DC_ARRAY_1D_TILED_THICK,
 240         DC_ARRAY_2D_TILED_THIN1,
 241         DC_ARRAY_PRT_TILED_THIN1,
 242         DC_ARRAY_PRT_2D_TILED_THIN1,
 243         DC_ARRAY_2D_TILED_THICK,
 244         DC_ARRAY_2D_TILED_X_THICK,
 245         DC_ARRAY_PRT_TILED_THICK,
 246         DC_ARRAY_PRT_2D_TILED_THICK,
 247         DC_ARRAY_PRT_3D_TILED_THIN1,
 248         DC_ARRAY_3D_TILED_THIN1,
 249         DC_ARRAY_3D_TILED_THICK,
 250         DC_ARRAY_3D_TILED_X_THICK,
 251         DC_ARRAY_PRT_3D_TILED_THICK,
 252 };
 253
 254 enum tile_mode_values {
 255         DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
 256         DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 257 };
 258
 259 union dc_tiling_info {
 260
 261         struct {
 262                 /* Specifies the number of memory banks for tiling
 263                  *      purposes.
 264                  * Only applies to 2D and 3D tiling modes.
 265                  *      POSSIBLE VALUES: 2,4,8,16
 266                  */
 267                 unsigned int num_banks;
 268                 /* Specifies the number of tiles in the x direction
 269                  *      to be incorporated into the same bank.
 270                  * Only applies to 2D and 3D tiling modes.
 271                  *      POSSIBLE VALUES: 1,2,4,8
 272                  */
 273                 unsigned int bank_width;
 274                 unsigned int bank_width_c;
 275                 /* Specifies the number of tiles in the y direction to
 276                  *      be incorporated into the same bank.
 277                  * Only applies to 2D and 3D tiling modes.
 278                  *      POSSIBLE VALUES: 1,2,4,8
 279                  */
 280                 unsigned int bank_height;
 281                 unsigned int bank_height_c;
 282                 /* Specifies the macro tile aspect ratio. Only applies
 283                  * to 2D and 3D tiling modes.
 284                  */
 285                 unsigned int tile_aspect;
 286                 unsigned int tile_aspect_c;
 287                 /* Specifies the number of bytes that will be stored
 288                  *      contiguously for each tile.
 289                  * If the tile data requires more storage than this
 290                  *      amount, it is split into multiple slices.
 291                  * This field must not be larger than
 292                  *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
 293                  * Only applies to 2D and 3D tiling modes.
 294                  * For color render targets, TILE_SPLIT >= 256B.
 295                  */
 296                 enum tile_split_values tile_split;
 297                 enum tile_split_values tile_split_c;
 298                 /* Specifies the addressing within a tile.
 299                  *      0x0 - DISPLAY_MICRO_TILING
 300                  *      0x1 - THIN_MICRO_TILING
 301                  *      0x2 - DEPTH_MICRO_TILING
 302                  *      0x3 - ROTATED_MICRO_TILING
 303                  */
 304                 enum tile_mode_values tile_mode;
 305                 enum tile_mode_values tile_mode_c;
 306                 /* Specifies the number of pipes and how they are
 307                  *      interleaved in the surface.
 308                  * Refer to memory addressing document for complete
 309                  *      details and constraints.
 310                  */
 311                 unsigned int pipe_config;
 312                 /* Specifies the tiling mode of the surface.
 313                  * THIN tiles use an 8x8x1 tile size.
 314                  * THICK tiles use an 8x8x4 tile size.
 315                  * 2D tiling modes rotate banks for successive Z slices
 316                  * 3D tiling modes rotate pipes and banks for Z slices
 317                  * Refer to memory addressing document for complete
 318                  *      details and constraints.
 319                  */
 320                 enum array_mode_values array_mode;
 321         } gfx8;
 322
 323 };
 324
 325 /* Rotation angle */
 326 enum dc_rotation_angle {
 327         ROTATION_ANGLE_0 = 0,
 328         ROTATION_ANGLE_90,
 329         ROTATION_ANGLE_180,
 330         ROTATION_ANGLE_270,
 331         ROTATION_ANGLE_COUNT
 332 };
 333
 334 enum dc_scan_direction {
 335         SCAN_DIRECTION_UNKNOWN = 0,
 336         SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
 337         SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
 338 };
 339
 340 struct dc_cursor_position {
 341         uint32_t x;
 342         uint32_t y;
 343
 344         uint32_t x_hotspot;
 345         uint32_t y_hotspot;
 346
 347         /*
 348          * This parameter indicates whether HW cursor should be enabled
 349          */
 350         bool enable;
 351
 352         /*
 353          * This parameter indicates whether cursor hot spot should be
 354          * programmed
 355          */
 356         bool hot_spot_enable;
 357 };
 358
 359 struct dc_cursor_mi_param {
 360         unsigned int pixel_clk_khz;
 361         unsigned int ref_clk_khz;
 362         unsigned int viewport_x_start;
 363         unsigned int viewport_width;
 364         struct fixed31_32 h_scale_ratio;
 365 };
 366
 367 /* IPP related types */
 368
 369 enum {
 370         INPUT_LUT_ENTRIES = 256
 371 };
 372
 373 struct dc_gamma {
 374         uint16_t red[INPUT_LUT_ENTRIES];
 375         uint16_t green[INPUT_LUT_ENTRIES];
 376         uint16_t blue[INPUT_LUT_ENTRIES];
 377 };
 378
 379 /* Used by both ipp amd opp functions*/
 380 /* TODO: to be consolidated with enum color_space */
 381
 382 /*
 383  * This enum is for programming CURSOR_MODE register field. What this register
 384  * should be programmed to depends on OS requested cursor shape flags and what
 385  * we stored in the cursor surface.
 386  */
 387 enum dc_cursor_color_format {
 388         CURSOR_MODE_MONO,
 389         CURSOR_MODE_COLOR_1BIT_AND,
 390         CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
 391         CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
 392 };
 393
 394 /*
 395  * This is all the parameters required by DAL in order to update the cursor
 396  * attributes, including the new cursor image surface address, size, hotspot
 397  * location, color format, etc.
 398  */
 399
 400 union dc_cursor_attribute_flags {
 401         struct {
 402                 uint32_t ENABLE_MAGNIFICATION:1;
 403                 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
 404                 uint32_t HORIZONTAL_MIRROR:1;
 405                 uint32_t VERTICAL_MIRROR:1;
 406                 uint32_t INVERT_PIXEL_DATA:1;
 407                 uint32_t ZERO_EXPANSION:1;
 408                 uint32_t MIN_MAX_INVERT:1;
 409                 uint32_t RESERVED:25;
 410         } bits;
 411         uint32_t value;
 412 };
 413
 414 struct dc_cursor_attributes {
 415         PHYSICAL_ADDRESS_LOC address;
 416         uint32_t pitch;
 417
 418         /* Width and height should correspond to cursor surface width x heigh */
 419         uint32_t width;
 420         uint32_t height;
 421         uint32_t x_hot;
 422         uint32_t y_hot;
 423
 424         enum dc_cursor_color_format color_format;
 425
 426         /* In case we support HW Cursor rotation in the future */
 427         enum dc_rotation_angle rotation_angle;
 428
 429         union dc_cursor_attribute_flags attribute_flags;
 430 };
 431
 432 /* OPP */
 433
 434 enum dc_color_space {
 435         COLOR_SPACE_UNKNOWN,
 436         COLOR_SPACE_SRGB,
 437         COLOR_SPACE_SRGB_LIMITED,
 438         COLOR_SPACE_YPBPR601,
 439         COLOR_SPACE_YPBPR709,
 440         COLOR_SPACE_YCBCR601,
 441         COLOR_SPACE_YCBCR709,
 442         COLOR_SPACE_YCBCR601_LIMITED,
 443         COLOR_SPACE_YCBCR709_LIMITED,
 444         COLOR_SPACE_2020_RGB_FULLRANGE,
 445         COLOR_SPACE_2020_RGB_LIMITEDRANGE,
 446         COLOR_SPACE_2020_YCBCR,
 447         COLOR_SPACE_ADOBERGB,
 448 };
 449
 450 enum dc_quantization_range {
 451         QUANTIZATION_RANGE_UNKNOWN,
 452         QUANTIZATION_RANGE_FULL,
 453         QUANTIZATION_RANGE_LIMITED
 454 };
 455
 456 /* XFM */
 457
 458 /* used in  struct dc_surface */
 459 struct scaling_taps {
 460         uint32_t v_taps;
 461         uint32_t h_taps;
 462         uint32_t v_taps_c;
 463         uint32_t h_taps_c;
 464 };
 465
 466 enum dc_timing_standard {
 467         TIMING_STANDARD_UNDEFINED,
 468         TIMING_STANDARD_DMT,
 469         TIMING_STANDARD_GTF,
 470         TIMING_STANDARD_CVT,
 471         TIMING_STANDARD_CVT_RB,
 472         TIMING_STANDARD_CEA770,
 473         TIMING_STANDARD_CEA861,
 474         TIMING_STANDARD_HDMI,
 475         TIMING_STANDARD_TV_NTSC,
 476         TIMING_STANDARD_TV_NTSC_J,
 477         TIMING_STANDARD_TV_PAL,
 478         TIMING_STANDARD_TV_PAL_M,
 479         TIMING_STANDARD_TV_PAL_CN,
 480         TIMING_STANDARD_TV_SECAM,
 481         TIMING_STANDARD_EXPLICIT,
 482         /*!< For explicit timings from EDID, VBIOS, etc.*/
 483         TIMING_STANDARD_USER_OVERRIDE,
 484         /*!< For mode timing override by user*/
 485         TIMING_STANDARD_MAX
 486 };
 487
 488 enum dc_timing_3d_format {
 489         TIMING_3D_FORMAT_NONE,
 490         TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
 491         TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
 492         TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
 493         /* for active DP-HDMI dongle*/
 494         TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
 495         TIMING_3D_FORMAT_HW_FRAME_PACKING,
 496         TIMING_3D_FORMAT_SW_FRAME_PACKING,
 497         TIMING_3D_FORMAT_ROW_INTERLEAVE,
 498         TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
 499         TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
 500         TIMING_3D_FORMAT_SIDE_BY_SIDE,
 501         TIMING_3D_FORMAT_TOP_AND_BOTTOM,
 502         TIMING_3D_FORMAT_SBS_SW_PACKED,
 503         /* Side-by-side, packed by application/driver into 2D frame*/
 504         TIMING_3D_FORMAT_TB_SW_PACKED,
 505         /* Top-and-bottom, packed by application/driver into 2D frame*/
 506
 507         TIMING_3D_FORMAT_MAX,
 508 };
 509
 510 enum dc_color_depth {
 511         COLOR_DEPTH_UNDEFINED,
 512         COLOR_DEPTH_666,
 513         COLOR_DEPTH_888,
 514         COLOR_DEPTH_101010,
 515         COLOR_DEPTH_121212,
 516         COLOR_DEPTH_141414,
 517         COLOR_DEPTH_161616,
 518         COLOR_DEPTH_COUNT
 519 };
 520
 521 enum dc_pixel_encoding {
 522         PIXEL_ENCODING_UNDEFINED,
 523         PIXEL_ENCODING_RGB,
 524         PIXEL_ENCODING_YCBCR422,
 525         PIXEL_ENCODING_YCBCR444,
 526         PIXEL_ENCODING_YCBCR420,
 527         PIXEL_ENCODING_COUNT
 528 };
 529
 530 enum dc_aspect_ratio {
 531         ASPECT_RATIO_NO_DATA,
 532         ASPECT_RATIO_4_3,
 533         ASPECT_RATIO_16_9,
 534         ASPECT_RATIO_64_27,
 535         ASPECT_RATIO_256_135,
 536         ASPECT_RATIO_FUTURE
 537 };
 538
 539 enum scanning_type {
 540         SCANNING_TYPE_NODATA = 0,
 541         SCANNING_TYPE_OVERSCAN,
 542         SCANNING_TYPE_UNDERSCAN,
 543         SCANNING_TYPE_FUTURE,
 544         SCANNING_TYPE_UNDEFINED
 545 };
 546
 547 struct dc_crtc_timing_flags {
 548         uint32_t INTERLACE :1;
 549         uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 550          it is positive polarity --reversed with dal1 or video bios define*/
 551         uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 552          it is positive polarity --reversed with dal1 or video bios define*/
 553
 554         uint32_t HORZ_COUNT_BY_TWO:1;
 555
 556         uint32_t EXCLUSIVE_3D :1; /* if this bit set,
 557          timing can be driven in 3D format only
 558          and there is no corresponding 2D timing*/
 559         uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
 560          (right eye = '1', left eye = '0') */
 561         uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
 562          when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
 563         uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
 564          because corresponding 2D timing also present in the list*/
 565         uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
 566          and we want to match priority of corresponding 3D timing*/
 567         uint32_t Y_ONLY :1;
 568
 569         uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 570         uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 571
 572         /* HDMI 2.0 - Support scrambling for TMDS character
 573          * rates less than or equal to 340Mcsc */
 574         uint32_t LTE_340MCSC_SCRAMBLE:1;
 575
 576 };
 577
 578 struct dc_crtc_timing {
 579
 580         uint32_t h_total;
 581         uint32_t h_border_left;
 582         uint32_t h_addressable;
 583         uint32_t h_border_right;
 584         uint32_t h_front_porch;
 585         uint32_t h_sync_width;
 586
 587         uint32_t v_total;
 588         uint32_t v_border_top;
 589         uint32_t v_addressable;
 590         uint32_t v_border_bottom;
 591         uint32_t v_front_porch;
 592         uint32_t v_sync_width;
 593
 594         uint32_t pix_clk_khz;
 595
 596         uint32_t vic;
 597         uint32_t hdmi_vic;
 598         enum dc_timing_3d_format timing_3d_format;
 599         enum dc_color_depth display_color_depth;
 600         enum dc_pixel_encoding pixel_encoding;
 601         enum dc_aspect_ratio aspect_ratio;
 602         enum scanning_type scan_type;
 603
 604         struct dc_crtc_timing_flags flags;
 605 };
 606
 607 #endif /* DC_HW_TYPES_H */
 608