drivers/gpu/drm/amd/display/dc/dc_types.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef DC_TYPES_H_
  26 #define DC_TYPES_H_
  27
  28 #include "fixed32_32.h"
  29 #include "fixed31_32.h"
  30 #include "irq_types.h"
  31 #include "dc_dp_types.h"
  32 #include "dc_hw_types.h"
  33 #include "dal_types.h"
  34 #include "grph_object_defs.h"
  35
  36 /* forward declarations */
  37 struct dc_surface;
  38 struct dc_stream;
  39 struct dc_link;
  40 struct dc_sink;
  41 struct dal;
  42
  43 /********************************
  44  * Environment definitions
  45  ********************************/
  46 enum dce_environment {
  47         DCE_ENV_PRODUCTION_DRV = 0,
  48         /* Emulation on FPGA, in "Maximus" System.
  49          * This environment enforces that *only* DC registers accessed.
  50          * (access to non-DC registers will hang FPGA) */
  51         DCE_ENV_FPGA_MAXIMUS,
  52         /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
  53          * requirements of Diagnostics team. */
  54         DCE_ENV_DIAG
  55 };
  56
  57 /* Note: use these macro definitions instead of direct comparison! */
  58 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
  59         (dce_environment == DCE_ENV_FPGA_MAXIMUS)
  60
  61 #define IS_DIAG_DC(dce_environment) \
  62         (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
  63
  64 struct hw_asic_id {
  65         uint32_t chip_id;
  66         uint32_t chip_family;
  67         uint32_t pci_revision_id;
  68         uint32_t hw_internal_rev;
  69         uint32_t vram_type;
  70         uint32_t vram_width;
  71         uint32_t feature_flags;
  72         uint32_t fake_paths_num;
  73         void *atombios_base_address;
  74 };
  75
  76 struct dc_context {
  77         struct dc *dc;
  78
  79         void *driver_context; /* e.g. amdgpu_device */
  80
  81         struct dal_logger *logger;
  82         void *cgs_device;
  83
  84         enum dce_environment dce_environment;
  85         struct hw_asic_id asic_id;
  86
  87         /* todo: below should probably move to dc.  to facilitate removal
  88          * of AS we will store these here
  89          */
  90         enum dce_version dce_version;
  91         struct dc_bios *dc_bios;
  92         bool created_bios;
  93         struct gpio_service *gpio_service;
  94         struct i2caux *i2caux;
  95 };
  96
  97
  98 #define MAX_EDID_BUFFER_SIZE 512
  99 #define EDID_BLOCK_SIZE 128
 100 #define MAX_SURFACE_NUM 4
 101 #define NUM_PIXEL_FORMATS 10
 102
 103 #include "dc_ddc_types.h"
 104
 105 enum tiling_mode {
 106         TILING_MODE_INVALID,
 107         TILING_MODE_LINEAR,
 108         TILING_MODE_TILED,
 109         TILING_MODE_COUNT
 110 };
 111
 112 enum view_3d_format {
 113         VIEW_3D_FORMAT_NONE = 0,
 114         VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
 115         VIEW_3D_FORMAT_SIDE_BY_SIDE,
 116         VIEW_3D_FORMAT_TOP_AND_BOTTOM,
 117         VIEW_3D_FORMAT_COUNT,
 118         VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
 119 };
 120
 121 enum plane_stereo_format {
 122         PLANE_STEREO_FORMAT_NONE = 0,
 123         PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
 124         PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
 125         PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
 126         PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
 127         PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
 128         PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
 129 };
 130
 131 /* TODO: Find way to calculate number of bits
 132  *  Please increase if pixel_format enum increases
 133  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
 134  */
 135
 136 enum dc_edid_connector_type {
 137         EDID_CONNECTOR_UNKNOWN = 0,
 138         EDID_CONNECTOR_ANALOG = 1,
 139         EDID_CONNECTOR_DIGITAL = 10,
 140         EDID_CONNECTOR_DVI = 11,
 141         EDID_CONNECTOR_HDMIA = 12,
 142         EDID_CONNECTOR_MDDI = 14,
 143         EDID_CONNECTOR_DISPLAYPORT = 15
 144 };
 145
 146 enum dc_edid_status {
 147         EDID_OK,
 148         EDID_BAD_INPUT,
 149         EDID_NO_RESPONSE,
 150         EDID_BAD_CHECKSUM,
 151 };
 152
 153 /* audio capability from EDID*/
 154 struct dc_cea_audio_mode {
 155         uint8_t format_code; /* ucData[0] [6:3]*/
 156         uint8_t channel_count; /* ucData[0] [2:0]*/
 157         uint8_t sample_rate; /* ucData[1]*/
 158         union {
 159                 uint8_t sample_size; /* for LPCM*/
 160                 /*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
 161                 uint8_t max_bit_rate;
 162                 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
 163         };
 164 };
 165
 166 struct dc_edid {
 167         uint32_t length;
 168         uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
 169 };
 170
 171 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
 172  * is used. In this case we assume speaker location are: front left, front
 173  * right and front center. */
 174 #define DEFAULT_SPEAKER_LOCATION 5
 175
 176 #define DC_MAX_AUDIO_DESC_COUNT 16
 177
 178 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
 179
 180 union display_content_support {
 181         unsigned int raw;
 182         struct {
 183                 unsigned int valid_content_type :1;
 184                 unsigned int game_content :1;
 185                 unsigned int cinema_content :1;
 186                 unsigned int photo_content :1;
 187                 unsigned int graphics_content :1;
 188                 unsigned int reserved :27;
 189         } bits;
 190 };
 191
 192 struct dc_edid_caps {
 193         /* sink identification */
 194         uint16_t manufacturer_id;
 195         uint16_t product_id;
 196         uint32_t serial_number;
 197         uint8_t manufacture_week;
 198         uint8_t manufacture_year;
 199         uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 200
 201         /* audio caps */
 202         uint8_t speaker_flags;
 203         uint32_t audio_mode_count;
 204         struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
 205         uint32_t audio_latency;
 206         uint32_t video_latency;
 207
 208         union display_content_support content_support;
 209
 210         uint8_t qs_bit;
 211         uint8_t qy_bit;
 212
 213         /*HDMI 2.0 caps*/
 214         bool lte_340mcsc_scramble;
 215
 216         bool edid_hdmi;
 217 };
 218
 219 struct view {
 220         uint32_t width;
 221         uint32_t height;
 222 };
 223
 224 struct dc_mode_flags {
 225         /* note: part of refresh rate flag*/
 226         uint32_t INTERLACE :1;
 227         /* native display timing*/
 228         uint32_t NATIVE :1;
 229         /* preferred is the recommended mode, one per display */
 230         uint32_t PREFERRED :1;
 231         /* true if this mode should use reduced blanking timings
 232          *_not_ related to the Reduced Blanking adjustment*/
 233         uint32_t REDUCED_BLANKING :1;
 234         /* note: part of refreshrate flag*/
 235         uint32_t VIDEO_OPTIMIZED_RATE :1;
 236         /* should be reported to upper layers as mode_flags*/
 237         uint32_t PACKED_PIXEL_FORMAT :1;
 238         /*< preferred view*/
 239         uint32_t PREFERRED_VIEW :1;
 240         /* this timing should be used only in tiled mode*/
 241         uint32_t TILED_MODE :1;
 242         uint32_t DSE_MODE :1;
 243         /* Refresh rate divider when Miracast sink is using a
 244          different rate than the output display device
 245          Must be zero for wired displays and non-zero for
 246          Miracast displays*/
 247         uint32_t MIRACAST_REFRESH_DIVIDER;
 248 };
 249
 250
 251 enum dc_timing_source {
 252         TIMING_SOURCE_UNDEFINED,
 253
 254         /* explicitly specifed by user, most important*/
 255         TIMING_SOURCE_USER_FORCED,
 256         TIMING_SOURCE_USER_OVERRIDE,
 257         TIMING_SOURCE_CUSTOM,
 258         TIMING_SOURCE_EXPLICIT,
 259
 260         /* explicitly specified by the display device, more important*/
 261         TIMING_SOURCE_EDID_CEA_SVD_3D,
 262         TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
 263         TIMING_SOURCE_EDID_CEA_SVD_420,
 264         TIMING_SOURCE_EDID_DETAILED,
 265         TIMING_SOURCE_EDID_ESTABLISHED,
 266         TIMING_SOURCE_EDID_STANDARD,
 267         TIMING_SOURCE_EDID_CEA_SVD,
 268         TIMING_SOURCE_EDID_CVT_3BYTE,
 269         TIMING_SOURCE_EDID_4BYTE,
 270         TIMING_SOURCE_VBIOS,
 271         TIMING_SOURCE_CV,
 272         TIMING_SOURCE_TV,
 273         TIMING_SOURCE_HDMI_VIC,
 274
 275         /* implicitly specified by display device, still safe but less important*/
 276         TIMING_SOURCE_DEFAULT,
 277
 278         /* only used for custom base modes */
 279         TIMING_SOURCE_CUSTOM_BASE,
 280
 281         /* these timing might not work, least important*/
 282         TIMING_SOURCE_RANGELIMIT,
 283         TIMING_SOURCE_OS_FORCED,
 284         TIMING_SOURCE_IMPLICIT,
 285
 286         /* only used by default mode list*/
 287         TIMING_SOURCE_BASICMODE,
 288
 289         TIMING_SOURCE_COUNT
 290 };
 291
 292
 293 struct stereo_3d_features {
 294         bool supported                  ;
 295         bool allTimings                 ;
 296         bool cloneMode                  ;
 297         bool scaling                    ;
 298         bool singleFrameSWPacked;
 299 };
 300
 301 enum dc_timing_support_method {
 302         TIMING_SUPPORT_METHOD_UNDEFINED,
 303         TIMING_SUPPORT_METHOD_EXPLICIT,
 304         TIMING_SUPPORT_METHOD_IMPLICIT,
 305         TIMING_SUPPORT_METHOD_NATIVE
 306 };
 307
 308 struct dc_mode_info {
 309         uint32_t pixel_width;
 310         uint32_t pixel_height;
 311         uint32_t field_rate;
 312         /* Vertical refresh rate for progressive modes.
 313         * Field rate for interlaced modes.*/
 314
 315         enum dc_timing_standard timing_standard;
 316         enum dc_timing_source timing_source;
 317         struct dc_mode_flags flags;
 318 };
 319
 320 enum dc_power_state {
 321         DC_POWER_STATE_ON = 1,
 322         DC_POWER_STATE_STANDBY,
 323         DC_POWER_STATE_SUSPEND,
 324         DC_POWER_STATE_OFF
 325 };
 326
 327 /* DC PowerStates */
 328 enum dc_video_power_state {
 329         DC_VIDEO_POWER_UNSPECIFIED = 0,
 330         DC_VIDEO_POWER_ON = 1,
 331         DC_VIDEO_POWER_STANDBY,
 332         DC_VIDEO_POWER_SUSPEND,
 333         DC_VIDEO_POWER_OFF,
 334         DC_VIDEO_POWER_HIBERNATE,
 335         DC_VIDEO_POWER_SHUTDOWN,
 336         DC_VIDEO_POWER_ULPS,    /* BACO or Ultra-Light-Power-State */
 337         DC_VIDEO_POWER_AFTER_RESET,
 338         DC_VIDEO_POWER_MAXIMUM
 339 };
 340
 341 enum dc_acpi_cm_power_state {
 342         DC_ACPI_CM_POWER_STATE_D0 = 1,
 343         DC_ACPI_CM_POWER_STATE_D1 = 2,
 344         DC_ACPI_CM_POWER_STATE_D2 = 4,
 345         DC_ACPI_CM_POWER_STATE_D3 = 8
 346 };
 347
 348 enum dc_connection_type {
 349         dc_connection_none,
 350         dc_connection_single,
 351         dc_connection_mst_branch,
 352         dc_connection_active_dongle
 353 };
 354
 355 struct dc_csc_adjustments {
 356         struct fixed31_32 contrast;
 357         struct fixed31_32 saturation;
 358         struct fixed31_32 brightness;
 359         struct fixed31_32 hue;
 360 };
 361
 362 enum {
 363         MAX_LANES = 2,
 364         MAX_COFUNC_PATH = 6,
 365         LAYER_INDEX_PRIMARY = -1,
 366 };
 367
 368 enum dpcd_downstream_port_max_bpc {
 369         DOWN_STREAM_MAX_8BPC = 0,
 370         DOWN_STREAM_MAX_10BPC,
 371         DOWN_STREAM_MAX_12BPC,
 372         DOWN_STREAM_MAX_16BPC
 373 };
 374 struct dc_dongle_caps {
 375         /* dongle type (DP converter, CV smart dongle) */
 376         enum display_dongle_type dongle_type;
 377         bool extendedCapValid;
 378         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 379         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 380         bool is_dp_hdmi_s3d_converter;
 381         bool is_dp_hdmi_ycbcr422_pass_through;
 382         bool is_dp_hdmi_ycbcr420_pass_through;
 383         bool is_dp_hdmi_ycbcr422_converter;
 384         bool is_dp_hdmi_ycbcr420_converter;
 385         uint32_t dp_hdmi_max_bpc;
 386         uint32_t dp_hdmi_max_pixel_clk;
 387 };
 388 /* Scaling format */
 389 enum scaling_transformation {
 390         SCALING_TRANSFORMATION_UNINITIALIZED,
 391         SCALING_TRANSFORMATION_IDENTITY = 0x0001,
 392         SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
 393         SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
 394         SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
 395         SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
 396         SCALING_TRANSFORMATION_INVALID = 0x80000000,
 397
 398         /* Flag the first and last */
 399         SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
 400         SCALING_TRANSFORMATION_END =
 401                 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
 402 };
 403
 404 enum display_content_type {
 405         DISPLAY_CONTENT_TYPE_NO_DATA = 0,
 406         DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
 407         DISPLAY_CONTENT_TYPE_PHOTO = 2,
 408         DISPLAY_CONTENT_TYPE_CINEMA = 4,
 409         DISPLAY_CONTENT_TYPE_GAME = 8
 410 };
 411
 412 /* audio*/
 413
 414 union audio_sample_rates {
 415         struct sample_rates {
 416                 uint8_t RATE_32:1;
 417                 uint8_t RATE_44_1:1;
 418                 uint8_t RATE_48:1;
 419                 uint8_t RATE_88_2:1;
 420                 uint8_t RATE_96:1;
 421                 uint8_t RATE_176_4:1;
 422                 uint8_t RATE_192:1;
 423         } rate;
 424
 425         uint8_t all;
 426 };
 427
 428 struct audio_speaker_flags {
 429     uint32_t FL_FR:1;
 430     uint32_t LFE:1;
 431     uint32_t FC:1;
 432     uint32_t RL_RR:1;
 433     uint32_t RC:1;
 434     uint32_t FLC_FRC:1;
 435     uint32_t RLC_RRC:1;
 436     uint32_t SUPPORT_AI:1;
 437 };
 438
 439 struct audio_speaker_info {
 440         uint32_t ALLSPEAKERS:7;
 441         uint32_t SUPPORT_AI:1;
 442 };
 443
 444
 445 struct audio_info_flags {
 446
 447         union {
 448
 449                 struct audio_speaker_flags speaker_flags;
 450                 struct audio_speaker_info   info;
 451
 452                 uint8_t all;
 453         };
 454 };
 455
 456 enum audio_format_code {
 457         AUDIO_FORMAT_CODE_FIRST = 1,
 458         AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
 459
 460         AUDIO_FORMAT_CODE_AC3,
 461         /*Layers 1 & 2 */
 462         AUDIO_FORMAT_CODE_MPEG1,
 463         /*MPEG1 Layer 3 */
 464         AUDIO_FORMAT_CODE_MP3,
 465         /*multichannel */
 466         AUDIO_FORMAT_CODE_MPEG2,
 467         AUDIO_FORMAT_CODE_AAC,
 468         AUDIO_FORMAT_CODE_DTS,
 469         AUDIO_FORMAT_CODE_ATRAC,
 470         AUDIO_FORMAT_CODE_1BITAUDIO,
 471         AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
 472         AUDIO_FORMAT_CODE_DTS_HD,
 473         AUDIO_FORMAT_CODE_MAT_MLP,
 474         AUDIO_FORMAT_CODE_DST,
 475         AUDIO_FORMAT_CODE_WMAPRO,
 476         AUDIO_FORMAT_CODE_LAST,
 477         AUDIO_FORMAT_CODE_COUNT =
 478                 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
 479 };
 480
 481 struct audio_mode {
 482          /* ucData[0] [6:3] */
 483         enum audio_format_code format_code;
 484         /* ucData[0] [2:0] */
 485         uint8_t channel_count;
 486         /* ucData[1] */
 487         union audio_sample_rates sample_rates;
 488         union {
 489                 /* for LPCM */
 490                 uint8_t sample_size;
 491                 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
 492                 uint8_t max_bit_rate;
 493                 /* for Audio Formats 9-15 */
 494                 uint8_t vendor_specific;
 495         };
 496 };
 497
 498 struct audio_info {
 499         struct audio_info_flags flags;
 500         uint32_t video_latency;
 501         uint32_t audio_latency;
 502         uint32_t display_index;
 503         uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 504         uint32_t manufacture_id;
 505         uint32_t product_id;
 506         /* PortID used for ContainerID when defined */
 507         uint32_t port_id[2];
 508         uint32_t mode_count;
 509         /* this field must be last in this struct */
 510         struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
 511 };
 512
 513 struct freesync_context {
 514         bool supported;
 515         bool enabled;
 516         bool active;
 517
 518         unsigned int min_refresh_in_micro_hz;
 519         unsigned int nominal_refresh_in_micro_hz;
 520 };
 521
 522 struct psr_config {
 523         unsigned char psr_version;
 524         unsigned int psr_rfb_setup_time;
 525         bool psr_exit_link_training_required;
 526
 527         bool psr_frame_capture_indication_req;
 528         unsigned int psr_sdp_transmit_line_num_deadline;
 529 };
 530
 531 union dmcu_psr_level {
 532         struct {
 533                 unsigned int SKIP_CRC:1;
 534                 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
 535                 unsigned int SKIP_PHY_POWER_DOWN:1;
 536                 unsigned int SKIP_AUX_ACK_CHECK:1;
 537                 unsigned int SKIP_CRTC_DISABLE:1;
 538                 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
 539                 unsigned int SKIP_SMU_NOTIFICATION:1;
 540                 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 541                 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 542                 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
 543                 unsigned int RESERVED:22;
 544         } bits;
 545         unsigned int u32all;
 546 };
 547
 548 enum physical_phy_id {
 549         PHYLD_0,
 550         PHYLD_1,
 551         PHYLD_2,
 552         PHYLD_3,
 553         PHYLD_4,
 554         PHYLD_5,
 555         PHYLD_6,
 556         PHYLD_7,
 557         PHYLD_8,
 558         PHYLD_9,
 559         PHYLD_COUNT,
 560         PHYLD_UNKNOWN = (-1L)
 561 };
 562
 563 enum phy_type {
 564         PHY_TYPE_UNKNOWN  = 1,
 565         PHY_TYPE_PCIE_PHY = 2,
 566         PHY_TYPE_UNIPHY = 3,
 567 };
 568
 569 struct psr_context {
 570         /* ddc line */
 571         enum channel_id channel;
 572         /* Transmitter id */
 573         enum transmitter transmitterId;
 574         /* Engine Id is used for Dig Be source select */
 575         enum engine_id engineId;
 576         /* Controller Id used for Dig Fe source select */
 577         enum controller_id controllerId;
 578         /* Pcie or Uniphy */
 579         enum phy_type phyType;
 580         /* Physical PHY Id used by SMU interpretation */
 581         enum physical_phy_id smuPhyId;
 582         /* Vertical total pixels from crtc timing.
 583          * This is used for static screen detection.
 584          * ie. If we want to detect half a frame,
 585          * we use this to determine the hyst lines.
 586          */
 587         unsigned int crtcTimingVerticalTotal;
 588         /* PSR supported from panel capabilities and
 589          * current display configuration
 590          */
 591         bool psrSupportedDisplayConfig;
 592         /* Whether fast link training is supported by the panel */
 593         bool psrExitLinkTrainingRequired;
 594         /* If RFB setup time is greater than the total VBLANK time,
 595          * it is not possible for the sink to capture the video frame
 596          * in the same frame the SDP is sent. In this case,
 597          * the frame capture indication bit should be set and an extra
 598          * static frame should be transmitted to the sink.
 599          */
 600         bool psrFrameCaptureIndicationReq;
 601         /* Set the last possible line SDP may be transmitted without violating
 602          * the RFB setup time or entering the active video frame.
 603          */
 604         unsigned int sdpTransmitLineNumDeadline;
 605         /* The VSync rate in Hz used to calculate the
 606          * step size for smooth brightness feature
 607          */
 608         unsigned int vsyncRateHz;
 609         unsigned int skipPsrWaitForPllLock;
 610         unsigned int numberOfControllers;
 611         /* Unused, for future use. To indicate that first changed frame from
 612          * state3 shouldn't result in psr_inactive, but rather to perform
 613          * an automatic single frame rfb_update.
 614          */
 615         bool rfb_update_auto_en;
 616         /* Number of frame before entering static screen */
 617         unsigned int timehyst_frames;
 618         /* Partial frames before entering static screen */
 619         unsigned int hyst_lines;
 620         /* # of repeated AUX transaction attempts to make before
 621          * indicating failure to the driver
 622          */
 623         unsigned int aux_repeats;
 624         /* Controls hw blocks to power down during PSR active state */
 625         union dmcu_psr_level psr_level;
 626         /* Controls additional delay after remote frame capture before
 627          * continuing powerd own
 628          */
 629         unsigned int frame_delay;
 630 };
 631
 632 struct colorspace_transform {
 633         struct fixed31_32 matrix[12];
 634         bool enable_remap;
 635 };
 636
 637 struct csc_transform {
 638         uint16_t matrix[12];
 639         bool enable_adjustment;
 640 };
 641
 642 enum i2c_mot_mode {
 643         I2C_MOT_UNDEF,
 644         I2C_MOT_TRUE,
 645         I2C_MOT_FALSE
 646 };
 647
 648 #endif /* DC_TYPES_H_ */