drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "core_types.h"
  27 #include "link_encoder.h"
  28 #include "dce_dmcu.h"
  29 #include "dm_services.h"
  30 #include "reg_helper.h"
  31 #include "fixed32_32.h"
  32 #include "dc.h"
  33
  34 #define TO_DCE_DMCU(dmcu)\
  35         container_of(dmcu, struct dce_dmcu, base)
  36
  37 #define REG(reg) \
  38         (dmcu_dce->regs->reg)
  39
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
  43
  44 #define CTX \
  45         dmcu_dce->base.ctx
  46
  47 /* PSR related commands */
  48 #define PSR_ENABLE 0x20
  49 #define PSR_EXIT 0x21
  50 #define PSR_SET 0x23
  51 #define PSR_SET_WAITLOOP 0x31
  52 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
  53 unsigned int cached_wait_loop_number = 0;
  54
  55 bool dce_dmcu_load_iram(struct dmcu *dmcu,
  56                 unsigned int start_offset,
  57                 const char *src,
  58                 unsigned int bytes)
  59 {
  60         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
  61         unsigned int count = 0;
  62
  63         /* Enable write access to IRAM */
  64         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
  65                         IRAM_HOST_ACCESS_EN, 1,
  66                         IRAM_WR_ADDR_AUTO_INC, 1);
  67
  68         REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
  69
  70         REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
  71
  72         for (count = 0; count < bytes; count++)
  73                 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
  74
  75         /* Disable write access to IRAM to allow dynamic sleep state */
  76         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
  77                         IRAM_HOST_ACCESS_EN, 0,
  78                         IRAM_WR_ADDR_AUTO_INC, 0);
  79
  80         return true;
  81 }
  82
  83 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
  84 {
  85         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
  86
  87         uint32_t psrStateOffset = 0xf0;
  88
  89         /* Enable write access to IRAM */
  90         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
  91
  92         REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
  93
  94         /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
  95         REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
  96
  97         /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
  98         *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
  99
 100         /* Disable write access to IRAM after finished using IRAM
 101          * in order to allow dynamic sleep state
 102          */
 103         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
 104 }
 105
 106 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 107 {
 108         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 109         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 110         unsigned int dmcu_wait_reg_ready_interval = 100;
 111
 112         unsigned int retryCount;
 113         uint32_t psr_state = 0;
 114
 115         /* waitDMCUReadyForCmd */
 116         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 117                                 dmcu_wait_reg_ready_interval,
 118                                 dmcu_max_retry_on_wait_reg_ready);
 119
 120         /* setDMCUParam_Cmd */
 121         if (enable)
 122                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 123                                 PSR_ENABLE);
 124         else
 125                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 126                                 PSR_EXIT);
 127
 128         /* notifyDMCUMsg */
 129         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 130         if (wait == true) {
 131                 for (retryCount = 0; retryCount <= 100; retryCount++) {
 132                         dce_get_dmcu_psr_state(dmcu, &psr_state);
 133                                 if (enable) {
 134                                         if (psr_state != 0)
 135                                                 break;
 136                                 } else {
 137                                         if (psr_state == 0)
 138                                                 break;
 139                                 }
 140                                 udelay(10);
 141                 }
 142         }
 143 }
 144
 145 static void dce_dmcu_setup_psr(struct dmcu *dmcu,
 146                 struct dc_link *link,
 147                 struct psr_context *psr_context)
 148 {
 149         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 150
 151         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 152         unsigned int dmcu_wait_reg_ready_interval = 100;
 153
 154         union dce_dmcu_psr_config_data_reg1 masterCmdData1;
 155         union dce_dmcu_psr_config_data_reg2 masterCmdData2;
 156         union dce_dmcu_psr_config_data_reg3 masterCmdData3;
 157
 158         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 159                         psr_context->psrExitLinkTrainingRequired);
 160
 161         /* Enable static screen interrupts for PSR supported display */
 162         /* Disable the interrupt coming from other displays. */
 163         REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
 164                         STATIC_SCREEN1_INT_TO_UC_EN, 0,
 165                         STATIC_SCREEN2_INT_TO_UC_EN, 0,
 166                         STATIC_SCREEN3_INT_TO_UC_EN, 0,
 167                         STATIC_SCREEN4_INT_TO_UC_EN, 0);
 168
 169         switch (psr_context->controllerId) {
 170         /* Driver uses case 1 for unconfigured */
 171         case 1:
 172                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 173                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 174                 break;
 175         case 2:
 176                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 177                                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
 178                 break;
 179         case 3:
 180                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 181                                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
 182                 break;
 183         case 4:
 184                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 185                                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
 186                 break;
 187         case 5:
 188                 /* CZ/NL only has 4 CRTC!!
 189                  * really valid.
 190                  * There is no interrupt enable mask for these instances.
 191                  */
 192                 break;
 193         case 6:
 194                 /* CZ/NL only has 4 CRTC!!
 195                  * These are here because they are defined in HW regspec,
 196                  * but not really valid. There is no interrupt enable mask
 197                  * for these instances.
 198                  */
 199                 break;
 200         default:
 201                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 202                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 203                 break;
 204         }
 205
 206         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 207                         psr_context->sdpTransmitLineNumDeadline);
 208
 209         if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
 210                 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 211
 212         /* waitDMCUReadyForCmd */
 213         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 214                                         dmcu_wait_reg_ready_interval,
 215                                         dmcu_max_retry_on_wait_reg_ready);
 216
 217         /* setDMCUParam_PSRHostConfigData */
 218         masterCmdData1.u32All = 0;
 219         masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
 220         masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
 221         masterCmdData1.bits.rfb_update_auto_en =
 222                         psr_context->rfb_update_auto_en;
 223         masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
 224         masterCmdData1.bits.dcp_sel = psr_context->controllerId;
 225         masterCmdData1.bits.phy_type  = psr_context->phyType;
 226         masterCmdData1.bits.frame_cap_ind =
 227                         psr_context->psrFrameCaptureIndicationReq;
 228         masterCmdData1.bits.aux_chan = psr_context->channel;
 229         masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
 230         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
 231                                         masterCmdData1.u32All);
 232
 233         masterCmdData2.u32All = 0;
 234         masterCmdData2.bits.dig_fe = psr_context->engineId;
 235         masterCmdData2.bits.dig_be = psr_context->transmitterId;
 236         masterCmdData2.bits.skip_wait_for_pll_lock =
 237                         psr_context->skipPsrWaitForPllLock;
 238         masterCmdData2.bits.frame_delay = psr_context->frame_delay;
 239         masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
 240         masterCmdData2.bits.num_of_controllers =
 241                         psr_context->numberOfControllers;
 242         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
 243                         masterCmdData2.u32All);
 244
 245         masterCmdData3.u32All = 0;
 246         masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
 247         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
 248                         masterCmdData3.u32All);
 249
 250         /* setDMCUParam_Cmd */
 251         REG_UPDATE(MASTER_COMM_CMD_REG,
 252                         MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
 253
 254         /* notifyDMCUMsg */
 255         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 256 }
 257
 258 static void dce_psr_wait_loop(
 259         struct dmcu *dmcu,
 260         unsigned int wait_loop_number)
 261 {
 262         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 263         union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
 264         if (cached_wait_loop_number == wait_loop_number)
 265                 return;
 266
 267         /* waitDMCUReadyForCmd */
 268         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
 269
 270         masterCmdData1.u32 = 0;
 271         masterCmdData1.bits.wait_loop = wait_loop_number;
 272         cached_wait_loop_number = wait_loop_number;
 273         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
 274
 275         /* setDMCUParam_Cmd */
 276         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
 277
 278         /* notifyDMCUMsg */
 279         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 280 }
 281
 282 static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
 283 {
 284         *psr_wait_loop_number = cached_wait_loop_number;
 285         return;
 286 }
 287
 288 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 289 bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
 290                 unsigned int start_offset,
 291                 const char *src,
 292                 unsigned int bytes)
 293 {
 294         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 295         unsigned int count = 0;
 296
 297         REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1);
 298
 299         /* Enable write access to IRAM */
 300         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 301                         IRAM_HOST_ACCESS_EN, 1,
 302                         IRAM_WR_ADDR_AUTO_INC, 1);
 303
 304         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 305
 306         REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
 307
 308         for (count = 0; count < bytes; count++)
 309                 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
 310
 311         /* Disable write access to IRAM to allow dynamic sleep state */
 312         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 313                         IRAM_HOST_ACCESS_EN, 0,
 314                         IRAM_WR_ADDR_AUTO_INC, 0);
 315
 316         return true;
 317 }
 318
 319 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
 320 {
 321         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 322
 323         uint32_t psrStateOffset = 0xf0;
 324
 325         /* Enable write access to IRAM */
 326         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
 327
 328         REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 329
 330         /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
 331         REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
 332
 333         /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
 334         *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
 335
 336         /* Disable write access to IRAM after finished using IRAM
 337          * in order to allow dynamic sleep state
 338          */
 339         REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
 340 }
 341
 342 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
 343 {
 344         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 345         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 346         unsigned int dmcu_wait_reg_ready_interval = 100;
 347
 348         unsigned int retryCount;
 349         uint32_t psr_state = 0;
 350
 351         /* waitDMCUReadyForCmd */
 352         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 353                                 dmcu_wait_reg_ready_interval,
 354                                 dmcu_max_retry_on_wait_reg_ready);
 355
 356         /* setDMCUParam_Cmd */
 357         if (enable)
 358                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 359                                 PSR_ENABLE);
 360         else
 361                 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
 362                                 PSR_EXIT);
 363
 364         /* notifyDMCUMsg */
 365         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 366
 367         /* Below loops 1000 x 500us = 500 ms.
 368          *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
 369          *  least a few frames. Should never hit the max retry assert below.
 370          */
 371         if (wait == true) {
 372         for (retryCount = 0; retryCount <= 1000; retryCount++) {
 373                 dcn10_get_dmcu_psr_state(dmcu, &psr_state);
 374                 if (enable) {
 375                         if (psr_state != 0)
 376                                 break;
 377                 } else {
 378                         if (psr_state == 0)
 379                                 break;
 380                 }
 381                 udelay(500);
 382         }
 383
 384         /* assert if max retry hit */
 385         ASSERT(retryCount <= 1000);
 386         }
 387 }
 388
 389 static void dcn10_dmcu_setup_psr(struct dmcu *dmcu,
 390                 struct dc_link *link,
 391                 struct psr_context *psr_context)
 392 {
 393         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 394
 395         unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 396         unsigned int dmcu_wait_reg_ready_interval = 100;
 397
 398         union dce_dmcu_psr_config_data_reg1 masterCmdData1;
 399         union dce_dmcu_psr_config_data_reg2 masterCmdData2;
 400         union dce_dmcu_psr_config_data_reg3 masterCmdData3;
 401
 402         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 403                         psr_context->psrExitLinkTrainingRequired);
 404
 405         /* Enable static screen interrupts for PSR supported display */
 406         /* Disable the interrupt coming from other displays. */
 407         REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
 408                         STATIC_SCREEN1_INT_TO_UC_EN, 0,
 409                         STATIC_SCREEN2_INT_TO_UC_EN, 0,
 410                         STATIC_SCREEN3_INT_TO_UC_EN, 0,
 411                         STATIC_SCREEN4_INT_TO_UC_EN, 0);
 412
 413         switch (psr_context->controllerId) {
 414         /* Driver uses case 1 for unconfigured */
 415         case 1:
 416                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 417                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 418                 break;
 419         case 2:
 420                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 421                                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
 422                 break;
 423         case 3:
 424                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 425                                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
 426                 break;
 427         case 4:
 428                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 429                                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
 430                 break;
 431         case 5:
 432                 /* CZ/NL only has 4 CRTC!!
 433                  * really valid.
 434                  * There is no interrupt enable mask for these instances.
 435                  */
 436                 break;
 437         case 6:
 438                 /* CZ/NL only has 4 CRTC!!
 439                  * These are here because they are defined in HW regspec,
 440                  * but not really valid. There is no interrupt enable mask
 441                  * for these instances.
 442                  */
 443                 break;
 444         default:
 445                 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
 446                                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
 447                 break;
 448         }
 449
 450         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 451                         psr_context->sdpTransmitLineNumDeadline);
 452
 453         if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
 454                 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 455
 456         /* waitDMCUReadyForCmd */
 457         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 458                         dmcu_wait_reg_ready_interval,
 459                         dmcu_max_retry_on_wait_reg_ready);
 460
 461         /* setDMCUParam_PSRHostConfigData */
 462         masterCmdData1.u32All = 0;
 463         masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
 464         masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
 465         masterCmdData1.bits.rfb_update_auto_en =
 466                         psr_context->rfb_update_auto_en;
 467         masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
 468         masterCmdData1.bits.dcp_sel = psr_context->controllerId;
 469         masterCmdData1.bits.phy_type  = psr_context->phyType;
 470         masterCmdData1.bits.frame_cap_ind =
 471                         psr_context->psrFrameCaptureIndicationReq;
 472         masterCmdData1.bits.aux_chan = psr_context->channel;
 473         masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
 474         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
 475                                         masterCmdData1.u32All);
 476
 477         masterCmdData2.u32All = 0;
 478         masterCmdData2.bits.dig_fe = psr_context->engineId;
 479         masterCmdData2.bits.dig_be = psr_context->transmitterId;
 480         masterCmdData2.bits.skip_wait_for_pll_lock =
 481                         psr_context->skipPsrWaitForPllLock;
 482         masterCmdData2.bits.frame_delay = psr_context->frame_delay;
 483         masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
 484         masterCmdData2.bits.num_of_controllers =
 485                         psr_context->numberOfControllers;
 486         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
 487                         masterCmdData2.u32All);
 488
 489         masterCmdData3.u32All = 0;
 490         masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
 491         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
 492                         masterCmdData3.u32All);
 493
 494         /* setDMCUParam_Cmd */
 495         REG_UPDATE(MASTER_COMM_CMD_REG,
 496                         MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
 497
 498         /* notifyDMCUMsg */
 499         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 500 }
 501
 502 static void dcn10_psr_wait_loop(
 503         struct dmcu *dmcu,
 504         unsigned int wait_loop_number)
 505 {
 506         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 507         union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
 508         if (wait_loop_number != 0) {
 509         /* waitDMCUReadyForCmd */
 510         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
 511
 512         masterCmdData1.u32 = 0;
 513         masterCmdData1.bits.wait_loop = wait_loop_number;
 514         cached_wait_loop_number = wait_loop_number;
 515         dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
 516
 517         /* setDMCUParam_Cmd */
 518         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
 519
 520         /* notifyDMCUMsg */
 521         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 522         }
 523 }
 524
 525 static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
 526 {
 527         *psr_wait_loop_number = cached_wait_loop_number;
 528         return;
 529 }
 530
 531 #endif
 532
 533 static const struct dmcu_funcs dce_funcs = {
 534         .load_iram = dce_dmcu_load_iram,
 535         .set_psr_enable = dce_dmcu_set_psr_enable,
 536         .setup_psr = dce_dmcu_setup_psr,
 537         .get_psr_state = dce_get_dmcu_psr_state,
 538         .set_psr_wait_loop = dce_psr_wait_loop,
 539         .get_psr_wait_loop = dce_get_psr_wait_loop
 540 };
 541
 542 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 543 static const struct dmcu_funcs dcn10_funcs = {
 544         .load_iram = dcn10_dmcu_load_iram,
 545         .set_psr_enable = dcn10_dmcu_set_psr_enable,
 546         .setup_psr = dcn10_dmcu_setup_psr,
 547         .get_psr_state = dcn10_get_dmcu_psr_state,
 548         .set_psr_wait_loop = dcn10_psr_wait_loop,
 549         .get_psr_wait_loop = dcn10_get_psr_wait_loop
 550 };
 551 #endif
 552
 553 static void dce_dmcu_construct(
 554         struct dce_dmcu *dmcu_dce,
 555         struct dc_context *ctx,
 556         const struct dce_dmcu_registers *regs,
 557         const struct dce_dmcu_shift *dmcu_shift,
 558         const struct dce_dmcu_mask *dmcu_mask)
 559 {
 560         struct dmcu *base = &dmcu_dce->base;
 561
 562         base->ctx = ctx;
 563         base->funcs = &dce_funcs;
 564
 565         dmcu_dce->regs = regs;
 566         dmcu_dce->dmcu_shift = dmcu_shift;
 567         dmcu_dce->dmcu_mask = dmcu_mask;
 568 }
 569
 570 struct dmcu *dce_dmcu_create(
 571         struct dc_context *ctx,
 572         const struct dce_dmcu_registers *regs,
 573         const struct dce_dmcu_shift *dmcu_shift,
 574         const struct dce_dmcu_mask *dmcu_mask)
 575 {
 576         struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
 577
 578         if (dmcu_dce == NULL) {
 579                 BREAK_TO_DEBUGGER();
 580                 return NULL;
 581         }
 582
 583         dce_dmcu_construct(
 584                 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
 585
 586         dmcu_dce->base.funcs = &dce_funcs;
 587
 588         return &dmcu_dce->base;
 589 }
 590
 591 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 592 struct dmcu *dcn10_dmcu_create(
 593         struct dc_context *ctx,
 594         const struct dce_dmcu_registers *regs,
 595         const struct dce_dmcu_shift *dmcu_shift,
 596         const struct dce_dmcu_mask *dmcu_mask)
 597 {
 598         struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
 599
 600         if (dmcu_dce == NULL) {
 601                 BREAK_TO_DEBUGGER();
 602                 return NULL;
 603         }
 604
 605         dce_dmcu_construct(
 606                 dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
 607
 608         dmcu_dce->base.funcs = &dcn10_funcs;
 609
 610         return &dmcu_dce->base;
 611 }
 612 #endif
 613
 614 void dce_dmcu_destroy(struct dmcu **dmcu)
 615 {
 616         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
 617
 618         kfree(dmcu_dce);
 619         *dmcu = NULL;
 620 }