drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef _DCE_DMCU_H_
  28 #define _DCE_DMCU_H_
  29
  30 #include "dmcu.h"
  31
  32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
  33         SR(DMCU_RAM_ACCESS_CTRL), \
  34         SR(DMCU_IRAM_WR_CTRL), \
  35         SR(DMCU_IRAM_WR_DATA)
  36
  37 #define DMCU_DCE110_COMMON_REG_LIST() \
  38         DMCU_COMMON_REG_LIST_DCE_BASE(), \
  39         SR(DCI_MEM_PWR_STATUS)
  40
  41 #define DMCU_SF(reg_name, field_name, post_fix)\
  42         .field_name = reg_name ## __ ## field_name ## post_fix
  43
  44 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
  45         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
  46                         IRAM_HOST_ACCESS_EN, mask_sh), \
  47         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
  48                         IRAM_WR_ADDR_AUTO_INC, mask_sh)
  49
  50 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
  51         DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
  52         DMCU_SF(DCI_MEM_PWR_STATUS, \
  53                         DMCU_IRAM_MEM_PWR_STATE, mask_sh)
  54
  55 #define DMCU_REG_FIELD_LIST(type) \
  56         type DMCU_IRAM_MEM_PWR_STATE; \
  57         type IRAM_HOST_ACCESS_EN; \
  58         type IRAM_WR_ADDR_AUTO_INC
  59
  60 struct dce_dmcu_shift {
  61         DMCU_REG_FIELD_LIST(uint8_t);
  62 };
  63
  64 struct dce_dmcu_mask {
  65         DMCU_REG_FIELD_LIST(uint32_t);
  66 };
  67
  68 struct dce_dmcu_registers {
  69         uint32_t DMCU_RAM_ACCESS_CTRL;
  70         uint32_t DCI_MEM_PWR_STATUS;
  71         uint32_t DMU_MEM_PWR_CNTL;
  72         uint32_t DMCU_IRAM_WR_CTRL;
  73         uint32_t DMCU_IRAM_WR_DATA;
  74 };
  75
  76 struct dce_dmcu {
  77         struct dmcu base;
  78         const struct dce_dmcu_registers *regs;
  79         const struct dce_dmcu_shift *dmcu_shift;
  80         const struct dce_dmcu_mask *dmcu_mask;
  81 };
  82
  83 struct dmcu *dce_dmcu_create(
  84         struct dc_context *ctx,
  85         const struct dce_dmcu_registers *regs,
  86         const struct dce_dmcu_shift *dmcu_shift,
  87         const struct dce_dmcu_mask *dmcu_mask);
  88
  89 void dce_dmcu_destroy(struct dmcu **dmcu);
  90
  91 #endif /* _DCE_ABM_H_ */