drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DCE_HWSEQ_H__
  26 #define __DCE_HWSEQ_H__
  27
  28 #include "hw_sequencer.h"
  29
  30 #define BL_REG_LIST()\
  31         SR(LVTMA_PWRSEQ_CNTL), \
  32         SR(LVTMA_PWRSEQ_STATE)
  33
  34 #define HWSEQ_DCEF_REG_LIST_DCE8() \
  35         .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
  36         .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
  37         .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
  38         .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
  39         .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
  40         .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
  41
  42 #define HWSEQ_DCEF_REG_LIST() \
  43         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  44         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  45         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
  46         SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
  47         SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
  48         SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
  49         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
  50
  51 #define HWSEQ_BLND_REG_LIST() \
  52         SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
  53         SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
  54         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
  55         SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
  56         SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
  57         SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
  58         SRII(BLND_CONTROL, BLND, 0), \
  59         SRII(BLND_CONTROL, BLND, 1), \
  60         SRII(BLND_CONTROL, BLND, 2), \
  61         SRII(BLND_CONTROL, BLND, 3), \
  62         SRII(BLND_CONTROL, BLND, 4), \
  63         SRII(BLND_CONTROL, BLND, 5)
  64
  65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
  66         SRII(PIXEL_RATE_CNTL, blk, 0), \
  67         SRII(PIXEL_RATE_CNTL, blk, 1), \
  68         SRII(PIXEL_RATE_CNTL, blk, 2), \
  69         SRII(PIXEL_RATE_CNTL, blk, 3), \
  70         SRII(PIXEL_RATE_CNTL, blk, 4), \
  71         SRII(PIXEL_RATE_CNTL, blk, 5)
  72
  73 #define HWSEQ_PHYPLL_REG_LIST(blk) \
  74         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
  75         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
  76         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
  77         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
  78         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
  79         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
  80
  81 #define HWSEQ_DCE11_REG_LIST_BASE() \
  82         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
  83         SR(DCFEV_CLOCK_CONTROL), \
  84         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  85         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  86         SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
  87         SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
  88         SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
  89         SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
  90         SRII(BLND_CONTROL, BLND, 0),\
  91         SRII(BLND_CONTROL, BLND, 1),\
  92         SR(BLNDV_CONTROL),\
  93         HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
  94         BL_REG_LIST()
  95
  96 #define HWSEQ_DCE8_REG_LIST() \
  97         HWSEQ_DCEF_REG_LIST_DCE8(), \
  98         HWSEQ_BLND_REG_LIST(), \
  99         HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
 100         BL_REG_LIST()
 101
 102 #define HWSEQ_DCE10_REG_LIST() \
 103         HWSEQ_DCEF_REG_LIST(), \
 104         HWSEQ_BLND_REG_LIST(), \
 105         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 106         BL_REG_LIST()
 107
 108 #define HWSEQ_ST_REG_LIST() \
 109         HWSEQ_DCE11_REG_LIST_BASE(), \
 110         .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
 111         .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
 112         .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
 113         .BLND_CONTROL[2] = mmBLNDV_CONTROL
 114
 115 #define HWSEQ_CZ_REG_LIST() \
 116         HWSEQ_DCE11_REG_LIST_BASE(), \
 117         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
 118         SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
 119         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
 120         SRII(BLND_CONTROL, BLND, 2), \
 121         .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
 122         .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
 123         .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
 124         .BLND_CONTROL[3] = mmBLNDV_CONTROL
 125
 126 #define HWSEQ_DCE120_REG_LIST() \
 127         HWSEQ_DCE10_REG_LIST(), \
 128         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 129         HWSEQ_PHYPLL_REG_LIST(CRTC), \
 130         SR(DCHUB_FB_LOCATION),\
 131         SR(DCHUB_AGP_BASE),\
 132         SR(DCHUB_AGP_BOT),\
 133         SR(DCHUB_AGP_TOP), \
 134         BL_REG_LIST()
 135
 136 #define HWSEQ_DCE112_REG_LIST() \
 137         HWSEQ_DCE10_REG_LIST(), \
 138         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 139         HWSEQ_PHYPLL_REG_LIST(CRTC), \
 140         BL_REG_LIST()
 141
 142 #define HWSEQ_DCN_REG_LIST()\
 143         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
 144         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
 145         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
 146         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
 147         SRII(DCHUBP_CNTL, HUBP, 0), \
 148         SRII(DCHUBP_CNTL, HUBP, 1), \
 149         SRII(DCHUBP_CNTL, HUBP, 2), \
 150         SRII(DCHUBP_CNTL, HUBP, 3), \
 151         SRII(HUBP_CLK_CNTL, HUBP, 0), \
 152         SRII(HUBP_CLK_CNTL, HUBP, 1), \
 153         SRII(HUBP_CLK_CNTL, HUBP, 2), \
 154         SRII(HUBP_CLK_CNTL, HUBP, 3), \
 155         SRII(DPP_CONTROL, DPP_TOP, 0), \
 156         SRII(DPP_CONTROL, DPP_TOP, 1), \
 157         SRII(DPP_CONTROL, DPP_TOP, 2), \
 158         SRII(DPP_CONTROL, DPP_TOP, 3), \
 159         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
 160         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
 161         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
 162         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
 163         SR(REFCLK_CNTL), \
 164         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
 165         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
 166         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
 167         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
 168         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
 169         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
 170         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
 171         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
 172         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
 173         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
 174         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
 175         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
 176         SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
 177         SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
 178         SR(DCHUBBUB_ARB_SAT_LEVEL),\
 179         SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
 180         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 181         SR(DCHUBBUB_TEST_DEBUG_INDEX), \
 182         SR(DCHUBBUB_TEST_DEBUG_DATA), \
 183         SR(DIO_MEM_PWR_CTRL), \
 184         SR(DCCG_GATE_DISABLE_CNTL), \
 185         SR(DCCG_GATE_DISABLE_CNTL2), \
 186         SR(DCFCLK_CNTL),\
 187         SR(DCFCLK_CNTL), \
 188         /* todo:  get these from GVM instead of reading registers ourselves */\
 189         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
 190         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
 191         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
 192         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
 193         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
 194         MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
 195         MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
 196         MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
 197         MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
 198         MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
 199         MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
 200         MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
 201
 202 #define HWSEQ_SR_WATERMARK_REG_LIST()\
 203         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
 204         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
 205         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
 206         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
 207         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
 208         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
 209         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
 210         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
 211
 212 #define HWSEQ_DCN1_REG_LIST()\
 213         HWSEQ_DCN_REG_LIST(), \
 214         HWSEQ_SR_WATERMARK_REG_LIST(), \
 215         HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
 216         HWSEQ_PHYPLL_REG_LIST(OTG), \
 217         SR(DCHUBBUB_SDPIF_FB_TOP),\
 218         SR(DCHUBBUB_SDPIF_FB_BASE),\
 219         SR(DCHUBBUB_SDPIF_FB_OFFSET),\
 220         SR(DCHUBBUB_SDPIF_AGP_BASE),\
 221         SR(DCHUBBUB_SDPIF_AGP_BOT),\
 222         SR(DCHUBBUB_SDPIF_AGP_TOP),\
 223         SR(DOMAIN0_PG_CONFIG), \
 224         SR(DOMAIN1_PG_CONFIG), \
 225         SR(DOMAIN2_PG_CONFIG), \
 226         SR(DOMAIN3_PG_CONFIG), \
 227         SR(DOMAIN4_PG_CONFIG), \
 228         SR(DOMAIN5_PG_CONFIG), \
 229         SR(DOMAIN6_PG_CONFIG), \
 230         SR(DOMAIN7_PG_CONFIG), \
 231         SR(DOMAIN0_PG_STATUS), \
 232         SR(DOMAIN1_PG_STATUS), \
 233         SR(DOMAIN2_PG_STATUS), \
 234         SR(DOMAIN3_PG_STATUS), \
 235         SR(DOMAIN4_PG_STATUS), \
 236         SR(DOMAIN5_PG_STATUS), \
 237         SR(DOMAIN6_PG_STATUS), \
 238         SR(DOMAIN7_PG_STATUS), \
 239         SR(D1VGA_CONTROL), \
 240         SR(D2VGA_CONTROL), \
 241         SR(D3VGA_CONTROL), \
 242         SR(D4VGA_CONTROL), \
 243         SR(VGA_TEST_CONTROL), \
 244         SR(DC_IP_REQUEST_CNTL), \
 245         BL_REG_LIST()
 246
 247 struct dce_hwseq_registers {
 248
 249                 /* Backlight registers */
 250         uint32_t LVTMA_PWRSEQ_CNTL;
 251         uint32_t LVTMA_PWRSEQ_STATE;
 252
 253         uint32_t DCFE_CLOCK_CONTROL[6];
 254         uint32_t DCFEV_CLOCK_CONTROL;
 255         uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
 256         uint32_t BLND_V_UPDATE_LOCK[6];
 257         uint32_t BLND_CONTROL[6];
 258         uint32_t BLNDV_CONTROL;
 259         uint32_t CRTC_H_BLANK_START_END[6];
 260         uint32_t PIXEL_RATE_CNTL[6];
 261         uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
 262         /*DCHUB*/
 263         uint32_t DCHUB_FB_LOCATION;
 264         uint32_t DCHUB_AGP_BASE;
 265         uint32_t DCHUB_AGP_BOT;
 266         uint32_t DCHUB_AGP_TOP;
 267
 268         uint32_t OTG_GLOBAL_SYNC_STATUS[4];
 269         uint32_t DCHUBP_CNTL[4];
 270         uint32_t HUBP_CLK_CNTL[4];
 271         uint32_t DPP_CONTROL[4];
 272         uint32_t OPP_PIPE_CONTROL[4];
 273         uint32_t REFCLK_CNTL;
 274         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
 275         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
 276         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
 277         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
 278         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
 279         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
 280         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
 281         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
 282         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
 283         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
 284         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
 285         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
 286         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
 287         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
 288         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
 289         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
 290         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
 291         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
 292         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
 293         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
 294         uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
 295         uint32_t DCHUBBUB_ARB_SAT_LEVEL;
 296         uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
 297         uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
 298         uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
 299         uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
 300         uint32_t DCHUBBUB_TEST_DEBUG_DATA;
 301         uint32_t DCHUBBUB_SDPIF_FB_TOP;
 302         uint32_t DCHUBBUB_SDPIF_FB_BASE;
 303         uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
 304         uint32_t DCHUBBUB_SDPIF_AGP_BASE;
 305         uint32_t DCHUBBUB_SDPIF_AGP_BOT;
 306         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
 307         uint32_t DC_IP_REQUEST_CNTL;
 308         uint32_t DOMAIN0_PG_CONFIG;
 309         uint32_t DOMAIN1_PG_CONFIG;
 310         uint32_t DOMAIN2_PG_CONFIG;
 311         uint32_t DOMAIN3_PG_CONFIG;
 312         uint32_t DOMAIN4_PG_CONFIG;
 313         uint32_t DOMAIN5_PG_CONFIG;
 314         uint32_t DOMAIN6_PG_CONFIG;
 315         uint32_t DOMAIN7_PG_CONFIG;
 316         uint32_t DOMAIN0_PG_STATUS;
 317         uint32_t DOMAIN1_PG_STATUS;
 318         uint32_t DOMAIN2_PG_STATUS;
 319         uint32_t DOMAIN3_PG_STATUS;
 320         uint32_t DOMAIN4_PG_STATUS;
 321         uint32_t DOMAIN5_PG_STATUS;
 322         uint32_t DOMAIN6_PG_STATUS;
 323         uint32_t DOMAIN7_PG_STATUS;
 324         uint32_t DIO_MEM_PWR_CTRL;
 325         uint32_t DCCG_GATE_DISABLE_CNTL;
 326         uint32_t DCCG_GATE_DISABLE_CNTL2;
 327         uint32_t DCFCLK_CNTL;
 328         uint32_t MICROSECOND_TIME_BASE_DIV;
 329         uint32_t MILLISECOND_TIME_BASE_DIV;
 330         uint32_t DISPCLK_FREQ_CHANGE_CNTL;
 331         uint32_t RBBMIF_TIMEOUT_DIS;
 332         uint32_t RBBMIF_TIMEOUT_DIS_2;
 333         uint32_t DENTIST_DISPCLK_CNTL;
 334         uint32_t DCHUBBUB_CRC_CTRL;
 335         uint32_t DPP_TOP0_DPP_CRC_CTRL;
 336         uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
 337         uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
 338         uint32_t MPC_CRC_CTRL;
 339         uint32_t MPC_CRC_RESULT_GB;
 340         uint32_t MPC_CRC_RESULT_C;
 341         uint32_t MPC_CRC_RESULT_AR;
 342         uint32_t D1VGA_CONTROL;
 343         uint32_t D2VGA_CONTROL;
 344         uint32_t D3VGA_CONTROL;
 345         uint32_t D4VGA_CONTROL;
 346         uint32_t VGA_TEST_CONTROL;
 347         /* MMHUB registers. read only. temporary hack */
 348         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
 349         uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 350         uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
 351         uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
 352         uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
 353         uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
 354         uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
 355         uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
 356         uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
 357         uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
 358         uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
 359         uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
 360 };
 361  /* set field name */
 362 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
 363         .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 364
 365 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
 366         .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
 367
 368
 369 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
 370         HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
 371         SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
 372
 373 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
 374         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 375         HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 376         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 377         HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
 378         HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
 379         HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
 380         HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
 381         HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
 382         HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
 383
 384 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
 385         HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
 386         HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 387
 388 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
 389         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
 390         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
 391
 392 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
 393         .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
 394         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 395         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 396         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 397         HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
 398         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
 399         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
 400         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 401
 402 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
 403         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
 404         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
 405         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
 406         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
 407         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 408
 409 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
 410         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 411         SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
 412         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
 413         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
 414         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 415
 416 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
 417         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 418         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
 419         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
 420         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 421
 422 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
 423         SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
 424         SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
 425         SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
 426         SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
 427         SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
 428         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
 429         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 430
 431 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
 432         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
 433         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
 434         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 435         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
 436         HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
 437         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
 438         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 439
 440 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
 441         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
 442         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
 443         HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
 444         HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
 445         HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
 446         HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
 447         HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
 448         HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
 449         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
 450         HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
 451         HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
 452         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
 453         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
 454         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
 455         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
 456         HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
 457         HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
 458         HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
 459
 460 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
 461         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 462         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
 463         HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
 464         HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
 465         HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
 466         HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
 467         HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
 468         HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
 469         HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \
 470         /* todo:  get these from GVM instead of reading registers ourselves */\
 471         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
 472         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
 473         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
 474         HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
 475         HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
 476         HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
 477         HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
 478         HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
 479         HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
 480         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
 481         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
 482         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
 483         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
 484         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
 485         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
 486         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
 487         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
 488         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
 489         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
 490         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
 491         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
 492         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
 493         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
 494         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
 495         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
 496         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
 497         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
 498         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
 499         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
 500         HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
 501         HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
 502         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
 503         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
 504         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 505         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
 506         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
 507         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
 508         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
 509
 510 #define HWSEQ_REG_FIELD_LIST(type) \
 511         type DCFE_CLOCK_ENABLE; \
 512         type DCFEV_CLOCK_ENABLE; \
 513         type DC_MEM_GLOBAL_PWR_REQ_DIS; \
 514         type BLND_DCP_GRPH_V_UPDATE_LOCK; \
 515         type BLND_SCL_V_UPDATE_LOCK; \
 516         type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
 517         type BLND_BLND_V_UPDATE_LOCK; \
 518         type BLND_V_UPDATE_LOCK_MODE; \
 519         type BLND_FEEDTHROUGH_EN; \
 520         type BLND_ALPHA_MODE; \
 521         type BLND_MODE; \
 522         type BLND_MULTIPLIED_MODE; \
 523         type DP_DTO0_ENABLE; \
 524         type PIXEL_RATE_SOURCE; \
 525         type PHYPLL_PIXEL_RATE_SOURCE; \
 526         type PIXEL_RATE_PLL_SOURCE; \
 527         /* todo:  get these from GVM instead of reading registers ourselves */\
 528         type PAGE_DIRECTORY_ENTRY_HI32;\
 529         type PAGE_DIRECTORY_ENTRY_LO32;\
 530         type LOGICAL_PAGE_NUMBER_HI4;\
 531         type LOGICAL_PAGE_NUMBER_LO32;\
 532         type PHYSICAL_PAGE_ADDR_HI4;\
 533         type PHYSICAL_PAGE_ADDR_LO32;\
 534         type PHYSICAL_PAGE_NUMBER_MSB;\
 535         type PHYSICAL_PAGE_NUMBER_LSB;\
 536         type LOGICAL_ADDR; \
 537         type ENABLE_L1_TLB;\
 538         type SYSTEM_ACCESS_MODE;\
 539         type LVTMA_BLON;\
 540         type LVTMA_PWRSEQ_TARGET_STATE_R;
 541
 542 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
 543         type VUPDATE_NO_LOCK_EVENT_CLEAR; \
 544         type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
 545         type HUBP_VTG_SEL; \
 546         type HUBP_CLOCK_ENABLE; \
 547         type DPP_CLOCK_ENABLE; \
 548         type DPPCLK_RATE_CONTROL; \
 549         type SDPIF_FB_TOP;\
 550         type SDPIF_FB_BASE;\
 551         type SDPIF_FB_OFFSET;\
 552         type SDPIF_AGP_BASE;\
 553         type SDPIF_AGP_BOT;\
 554         type SDPIF_AGP_TOP;\
 555         type FB_TOP;\
 556         type FB_BASE;\
 557         type FB_OFFSET;\
 558         type AGP_BASE;\
 559         type AGP_BOT;\
 560         type AGP_TOP;\
 561         type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
 562         type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
 563         type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
 564         type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
 565         type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
 566         type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
 567         type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
 568         type DCHUBBUB_ARB_SAT_LEVEL;\
 569         type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
 570         type OPP_PIPE_CLOCK_EN;\
 571         type IP_REQUEST_EN; \
 572         type DOMAIN0_POWER_FORCEON; \
 573         type DOMAIN0_POWER_GATE; \
 574         type DOMAIN1_POWER_FORCEON; \
 575         type DOMAIN1_POWER_GATE; \
 576         type DOMAIN2_POWER_FORCEON; \
 577         type DOMAIN2_POWER_GATE; \
 578         type DOMAIN3_POWER_FORCEON; \
 579         type DOMAIN3_POWER_GATE; \
 580         type DOMAIN4_POWER_FORCEON; \
 581         type DOMAIN4_POWER_GATE; \
 582         type DOMAIN5_POWER_FORCEON; \
 583         type DOMAIN5_POWER_GATE; \
 584         type DOMAIN6_POWER_FORCEON; \
 585         type DOMAIN6_POWER_GATE; \
 586         type DOMAIN7_POWER_FORCEON; \
 587         type DOMAIN7_POWER_GATE; \
 588         type DOMAIN0_PGFSM_PWR_STATUS; \
 589         type DOMAIN1_PGFSM_PWR_STATUS; \
 590         type DOMAIN2_PGFSM_PWR_STATUS; \
 591         type DOMAIN3_PGFSM_PWR_STATUS; \
 592         type DOMAIN4_PGFSM_PWR_STATUS; \
 593         type DOMAIN5_PGFSM_PWR_STATUS; \
 594         type DOMAIN6_PGFSM_PWR_STATUS; \
 595         type DOMAIN7_PGFSM_PWR_STATUS; \
 596         type DCFCLK_GATE_DIS; \
 597         type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
 598         type DENTIST_DPPCLK_WDIVIDER; \
 599         type DENTIST_DISPCLK_WDIVIDER; \
 600         type VGA_TEST_ENABLE; \
 601         type VGA_TEST_RENDER_START;
 602
 603 struct dce_hwseq_shift {
 604         HWSEQ_REG_FIELD_LIST(uint8_t)
 605         HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 606 };
 607
 608 struct dce_hwseq_mask {
 609         HWSEQ_REG_FIELD_LIST(uint32_t)
 610         HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
 611 };
 612
 613
 614 enum blnd_mode {
 615         BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
 616         BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
 617         BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
 618 };
 619
 620 void dce_enable_fe_clock(struct dce_hwseq *hwss,
 621                 unsigned int inst, bool enable);
 622
 623 void dce_pipe_control_lock(struct dc *dc,
 624                 struct pipe_ctx *pipe,
 625                 bool lock);
 626
 627 void dce_set_blender_mode(struct dce_hwseq *hws,
 628         unsigned int blnd_inst, enum blnd_mode mode);
 629
 630 void dce_clock_gating_power_up(struct dce_hwseq *hws,
 631                 bool enable);
 632
 633 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 634                 struct clock_source *clk_src,
 635                 unsigned int tg_inst);
 636
 637 bool dce_use_lut(const struct dc_plane_state *plane_state);
 638 #endif   /*__DCE_HWSEQ_H__*/