drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DCE_HWSEQ_H__
  26 #define __DCE_HWSEQ_H__
  27
  28 #include "hw_sequencer.h"
  29
  30 #define HWSEQ_DCEF_REG_LIST_DCE8() \
  31         .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
  32         .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
  33         .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
  34         .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
  35         .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
  36         .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
  37
  38 #define HWSEQ_DCEF_REG_LIST() \
  39         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  40         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  41         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
  42         SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
  43         SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
  44         SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
  45         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
  46
  47 #define HWSEQ_BLND_REG_LIST() \
  48         SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
  49         SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
  50         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
  51         SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
  52         SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
  53         SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
  54         SRII(BLND_CONTROL, BLND, 0), \
  55         SRII(BLND_CONTROL, BLND, 1), \
  56         SRII(BLND_CONTROL, BLND, 2), \
  57         SRII(BLND_CONTROL, BLND, 3), \
  58         SRII(BLND_CONTROL, BLND, 4), \
  59         SRII(BLND_CONTROL, BLND, 5)
  60
  61 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
  62         SRII(PIXEL_RATE_CNTL, blk, 0), \
  63         SRII(PIXEL_RATE_CNTL, blk, 1), \
  64         SRII(PIXEL_RATE_CNTL, blk, 2), \
  65         SRII(PIXEL_RATE_CNTL, blk, 3), \
  66         SRII(PIXEL_RATE_CNTL, blk, 4), \
  67         SRII(PIXEL_RATE_CNTL, blk, 5)
  68
  69 #define HWSEQ_PHYPLL_REG_LIST(blk) \
  70         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
  71         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
  72         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
  73         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
  74         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
  75         SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
  76
  77 #define HWSEQ_DCE11_REG_LIST_BASE() \
  78         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
  79         SR(DCFEV_CLOCK_CONTROL), \
  80         SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
  81         SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
  82         SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
  83         SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
  84         SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
  85         SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
  86         SRII(BLND_CONTROL, BLND, 0),\
  87         SRII(BLND_CONTROL, BLND, 1),\
  88         SR(BLNDV_CONTROL),\
  89         HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
  90
  91 #define HWSEQ_DCE8_REG_LIST() \
  92         HWSEQ_DCEF_REG_LIST_DCE8(), \
  93         HWSEQ_BLND_REG_LIST(), \
  94         HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
  95
  96 #define HWSEQ_DCE10_REG_LIST() \
  97         HWSEQ_DCEF_REG_LIST(), \
  98         HWSEQ_BLND_REG_LIST(), \
  99         HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
 100
 101 #define HWSEQ_ST_REG_LIST() \
 102         HWSEQ_DCE11_REG_LIST_BASE(), \
 103         .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
 104         .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
 105         .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
 106         .BLND_CONTROL[2] = mmBLNDV_CONTROL,
 107
 108 #define HWSEQ_CZ_REG_LIST() \
 109         HWSEQ_DCE11_REG_LIST_BASE(), \
 110         SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
 111         SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
 112         SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
 113         SRII(BLND_CONTROL, BLND, 2), \
 114         .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
 115         .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
 116         .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
 117         .BLND_CONTROL[3] = mmBLNDV_CONTROL
 118
 119 #define HWSEQ_DCE120_REG_LIST() \
 120         HWSEQ_DCE10_REG_LIST(), \
 121         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 122         HWSEQ_PHYPLL_REG_LIST(CRTC), \
 123         SR(DCHUB_FB_LOCATION),\
 124         SR(DCHUB_AGP_BASE),\
 125         SR(DCHUB_AGP_BOT),\
 126         SR(DCHUB_AGP_TOP)
 127
 128 #define HWSEQ_DCE112_REG_LIST() \
 129         HWSEQ_DCE10_REG_LIST(), \
 130         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
 131         HWSEQ_PHYPLL_REG_LIST(CRTC)
 132
 133 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 134 #define HWSEQ_DCN_REG_LIST()\
 135         HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
 136         HWSEQ_PHYPLL_REG_LIST(OTG), \
 137         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
 138         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
 139         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
 140         SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
 141         SRII(DCHUBP_CNTL, HUBP, 0), \
 142         SRII(DCHUBP_CNTL, HUBP, 1), \
 143         SRII(DCHUBP_CNTL, HUBP, 2), \
 144         SRII(DCHUBP_CNTL, HUBP, 3), \
 145         SRII(HUBP_CLK_CNTL, HUBP, 0), \
 146         SRII(HUBP_CLK_CNTL, HUBP, 1), \
 147         SRII(HUBP_CLK_CNTL, HUBP, 2), \
 148         SRII(HUBP_CLK_CNTL, HUBP, 3), \
 149         SRII(DPP_CONTROL, DPP_TOP, 0), \
 150         SRII(DPP_CONTROL, DPP_TOP, 1), \
 151         SRII(DPP_CONTROL, DPP_TOP, 2), \
 152         SRII(DPP_CONTROL, DPP_TOP, 3), \
 153         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
 154         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
 155         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
 156         SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
 157         SR(REFCLK_CNTL), \
 158         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
 159         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
 160         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
 161         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
 162         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
 163         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
 164         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
 165         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
 166         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
 167         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
 168         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
 169         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
 170         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
 171         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
 172         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
 173         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
 174         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
 175         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
 176         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
 177         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
 178         SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
 179         SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
 180         SR(DCHUBBUB_ARB_SAT_LEVEL),\
 181         SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
 182         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 183         SR(DCHUBBUB_TEST_DEBUG_INDEX), \
 184         SR(DCHUBBUB_TEST_DEBUG_DATA), \
 185         SR(DC_IP_REQUEST_CNTL), \
 186         SR(DOMAIN0_PG_CONFIG), \
 187         SR(DOMAIN1_PG_CONFIG), \
 188         SR(DOMAIN2_PG_CONFIG), \
 189         SR(DOMAIN3_PG_CONFIG), \
 190         SR(DOMAIN4_PG_CONFIG), \
 191         SR(DOMAIN5_PG_CONFIG), \
 192         SR(DOMAIN6_PG_CONFIG), \
 193         SR(DOMAIN7_PG_CONFIG), \
 194         SR(DOMAIN0_PG_STATUS), \
 195         SR(DOMAIN1_PG_STATUS), \
 196         SR(DOMAIN2_PG_STATUS), \
 197         SR(DOMAIN3_PG_STATUS), \
 198         SR(DOMAIN4_PG_STATUS), \
 199         SR(DOMAIN5_PG_STATUS), \
 200         SR(DOMAIN6_PG_STATUS), \
 201         SR(DOMAIN7_PG_STATUS), \
 202         SR(DIO_MEM_PWR_CTRL), \
 203         SR(DCCG_GATE_DISABLE_CNTL), \
 204         SR(DCCG_GATE_DISABLE_CNTL2), \
 205         SR(DCFCLK_CNTL),\
 206         SR(DCFCLK_CNTL), \
 207         SR(D1VGA_CONTROL), \
 208         SR(D2VGA_CONTROL), \
 209         SR(D3VGA_CONTROL), \
 210         SR(D4VGA_CONTROL)
 211 #endif
 212
 213 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 214 #define HWSEQ_DCN1_REG_LIST()\
 215         HWSEQ_DCN_REG_LIST(), \
 216         SR(DCHUBBUB_SDPIF_FB_TOP),\
 217         SR(DCHUBBUB_SDPIF_FB_BASE),\
 218         SR(DCHUBBUB_SDPIF_FB_OFFSET),\
 219         SR(DCHUBBUB_SDPIF_AGP_BASE),\
 220         SR(DCHUBBUB_SDPIF_AGP_BOT),\
 221         SR(DCHUBBUB_SDPIF_AGP_TOP)
 222 #endif
 223
 224
 225 struct dce_hwseq_registers {
 226         uint32_t DCFE_CLOCK_CONTROL[6];
 227         uint32_t DCFEV_CLOCK_CONTROL;
 228         uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
 229         uint32_t BLND_V_UPDATE_LOCK[6];
 230         uint32_t BLND_CONTROL[6];
 231         uint32_t BLNDV_CONTROL;
 232         uint32_t CRTC_H_BLANK_START_END[6];
 233         uint32_t PIXEL_RATE_CNTL[6];
 234         uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
 235         /*DCHUB*/
 236         uint32_t DCHUB_FB_LOCATION;
 237         uint32_t DCHUB_AGP_BASE;
 238         uint32_t DCHUB_AGP_BOT;
 239         uint32_t DCHUB_AGP_TOP;
 240
 241 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 242         uint32_t OTG_GLOBAL_SYNC_STATUS[4];
 243         uint32_t DCHUBP_CNTL[4];
 244         uint32_t HUBP_CLK_CNTL[4];
 245         uint32_t DPP_CONTROL[4];
 246         uint32_t OPP_PIPE_CONTROL[4];
 247         uint32_t REFCLK_CNTL;
 248         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
 249         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
 250         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
 251         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
 252         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
 253         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
 254         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
 255         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
 256         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
 257         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
 258         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
 259         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
 260         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
 261         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
 262         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
 263         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
 264         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
 265         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
 266         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
 267         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
 268         uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
 269         uint32_t DCHUBBUB_ARB_SAT_LEVEL;
 270         uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
 271         uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
 272         uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
 273         uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
 274         uint32_t DCHUBBUB_TEST_DEBUG_DATA;
 275         uint32_t DCHUBBUB_SDPIF_FB_TOP;
 276         uint32_t DCHUBBUB_SDPIF_FB_BASE;
 277         uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
 278         uint32_t DCHUBBUB_SDPIF_AGP_BASE;
 279         uint32_t DCHUBBUB_SDPIF_AGP_BOT;
 280         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
 281         uint32_t DC_IP_REQUEST_CNTL;
 282         uint32_t DOMAIN0_PG_CONFIG;
 283         uint32_t DOMAIN1_PG_CONFIG;
 284         uint32_t DOMAIN2_PG_CONFIG;
 285         uint32_t DOMAIN3_PG_CONFIG;
 286         uint32_t DOMAIN4_PG_CONFIG;
 287         uint32_t DOMAIN5_PG_CONFIG;
 288         uint32_t DOMAIN6_PG_CONFIG;
 289         uint32_t DOMAIN7_PG_CONFIG;
 290         uint32_t DOMAIN0_PG_STATUS;
 291         uint32_t DOMAIN1_PG_STATUS;
 292         uint32_t DOMAIN2_PG_STATUS;
 293         uint32_t DOMAIN3_PG_STATUS;
 294         uint32_t DOMAIN4_PG_STATUS;
 295         uint32_t DOMAIN5_PG_STATUS;
 296         uint32_t DOMAIN6_PG_STATUS;
 297         uint32_t DOMAIN7_PG_STATUS;
 298         uint32_t DIO_MEM_PWR_CTRL;
 299         uint32_t DCCG_GATE_DISABLE_CNTL;
 300         uint32_t DCCG_GATE_DISABLE_CNTL2;
 301         uint32_t DCFCLK_CNTL;
 302         uint32_t MICROSECOND_TIME_BASE_DIV;
 303         uint32_t MILLISECOND_TIME_BASE_DIV;
 304         uint32_t DISPCLK_FREQ_CHANGE_CNTL;
 305         uint32_t RBBMIF_TIMEOUT_DIS;
 306         uint32_t RBBMIF_TIMEOUT_DIS_2;
 307         uint32_t DENTIST_DISPCLK_CNTL;
 308         uint32_t DCHUBBUB_CRC_CTRL;
 309         uint32_t DPP_TOP0_DPP_CRC_CTRL;
 310         uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
 311         uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
 312         uint32_t MPC_CRC_CTRL;
 313         uint32_t MPC_CRC_RESULT_GB;
 314         uint32_t MPC_CRC_RESULT_C;
 315         uint32_t MPC_CRC_RESULT_AR;
 316         uint32_t D1VGA_CONTROL;
 317         uint32_t D2VGA_CONTROL;
 318         uint32_t D3VGA_CONTROL;
 319         uint32_t D4VGA_CONTROL;
 320 #endif
 321 };
 322  /* set field name */
 323 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
 324         .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 325
 326 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
 327         .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
 328
 329
 330 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
 331         HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
 332         SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
 333
 334 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
 335         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 336         HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 337         HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 338         HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
 339         HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
 340         HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
 341         HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
 342         HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
 343         HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
 344
 345 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
 346         HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
 347         HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 348
 349 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
 350         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
 351         HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
 352
 353 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
 354         .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
 355         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 356         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 357         HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
 358         HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
 359         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 360
 361 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
 362         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
 363         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
 364         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 365
 366 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
 367         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 368         SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
 369         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 370
 371 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
 372         HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
 373         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 374
 375 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
 376         SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
 377         SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
 378         SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
 379         SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
 380         SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
 381
 382 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
 383         HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
 384         HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
 385         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
 386         HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
 387         HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
 388
 389 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 390 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
 391         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
 392         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
 393         HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
 394         HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
 395         HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
 396         HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
 397         HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
 398         HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
 399         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
 400         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 401         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
 402         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
 403         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
 404         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
 405         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
 406         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
 407         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
 408         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
 409         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
 410         HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
 411         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
 412         HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
 413         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
 414         HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
 415         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
 416         HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
 417         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
 418         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
 419         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
 420         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
 421         HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
 422         HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
 423         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
 424         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
 425         HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
 426         HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
 427         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
 428         HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
 429         HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
 430         HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
 431         HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
 432 #endif
 433
 434 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 435 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
 436         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 437         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
 438         HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
 439         HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
 440         HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
 441         HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
 442         HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
 443         HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
 444         HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
 445 #endif
 446
 447 #define HWSEQ_REG_FIELD_LIST(type) \
 448         type DCFE_CLOCK_ENABLE; \
 449         type DCFEV_CLOCK_ENABLE; \
 450         type DC_MEM_GLOBAL_PWR_REQ_DIS; \
 451         type BLND_DCP_GRPH_V_UPDATE_LOCK; \
 452         type BLND_SCL_V_UPDATE_LOCK; \
 453         type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
 454         type BLND_BLND_V_UPDATE_LOCK; \
 455         type BLND_V_UPDATE_LOCK_MODE; \
 456         type BLND_FEEDTHROUGH_EN; \
 457         type BLND_ALPHA_MODE; \
 458         type BLND_MODE; \
 459         type BLND_MULTIPLIED_MODE; \
 460         type DP_DTO0_ENABLE; \
 461         type PIXEL_RATE_SOURCE; \
 462         type PHYPLL_PIXEL_RATE_SOURCE; \
 463         type PIXEL_RATE_PLL_SOURCE; \
 464
 465 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
 466         type VUPDATE_NO_LOCK_EVENT_CLEAR; \
 467         type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
 468         type HUBP_VTG_SEL; \
 469         type HUBP_CLOCK_ENABLE; \
 470         type DPP_CLOCK_ENABLE; \
 471         type DPPCLK_RATE_CONTROL; \
 472         type SDPIF_FB_TOP;\
 473         type SDPIF_FB_BASE;\
 474         type SDPIF_FB_OFFSET;\
 475         type SDPIF_AGP_BASE;\
 476         type SDPIF_AGP_BOT;\
 477         type SDPIF_AGP_TOP;\
 478         type FB_TOP;\
 479         type FB_BASE;\
 480         type FB_OFFSET;\
 481         type AGP_BASE;\
 482         type AGP_BOT;\
 483         type AGP_TOP;\
 484         type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
 485         type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
 486         type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
 487         type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
 488         type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
 489         type DCHUBBUB_ARB_SAT_LEVEL;\
 490         type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
 491         type OPP_PIPE_CLOCK_EN;\
 492         type IP_REQUEST_EN; \
 493         type DOMAIN0_POWER_FORCEON; \
 494         type DOMAIN0_POWER_GATE; \
 495         type DOMAIN1_POWER_FORCEON; \
 496         type DOMAIN1_POWER_GATE; \
 497         type DOMAIN2_POWER_FORCEON; \
 498         type DOMAIN2_POWER_GATE; \
 499         type DOMAIN3_POWER_FORCEON; \
 500         type DOMAIN3_POWER_GATE; \
 501         type DOMAIN4_POWER_FORCEON; \
 502         type DOMAIN4_POWER_GATE; \
 503         type DOMAIN5_POWER_FORCEON; \
 504         type DOMAIN5_POWER_GATE; \
 505         type DOMAIN6_POWER_FORCEON; \
 506         type DOMAIN6_POWER_GATE; \
 507         type DOMAIN7_POWER_FORCEON; \
 508         type DOMAIN7_POWER_GATE; \
 509         type DOMAIN0_PGFSM_PWR_STATUS; \
 510         type DOMAIN1_PGFSM_PWR_STATUS; \
 511         type DOMAIN2_PGFSM_PWR_STATUS; \
 512         type DOMAIN3_PGFSM_PWR_STATUS; \
 513         type DOMAIN4_PGFSM_PWR_STATUS; \
 514         type DOMAIN5_PGFSM_PWR_STATUS; \
 515         type DOMAIN6_PGFSM_PWR_STATUS; \
 516         type DOMAIN7_PGFSM_PWR_STATUS; \
 517         type DCFCLK_GATE_DIS; \
 518         type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
 519         type DENTIST_DPPCLK_WDIVIDER;
 520
 521 struct dce_hwseq_shift {
 522         HWSEQ_REG_FIELD_LIST(uint8_t)
 523         HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 524 };
 525
 526 struct dce_hwseq_mask {
 527         HWSEQ_REG_FIELD_LIST(uint32_t)
 528         HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
 529 };
 530
 531
 532 enum blnd_mode {
 533         BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
 534         BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
 535         BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
 536 };
 537
 538 void dce_enable_fe_clock(struct dce_hwseq *hwss,
 539                 unsigned int inst, bool enable);
 540
 541 void dce_pipe_control_lock(struct core_dc *dc,
 542                 struct pipe_ctx *pipe,
 543                 bool lock);
 544
 545 void dce_set_blender_mode(struct dce_hwseq *hws,
 546         unsigned int blnd_inst, enum blnd_mode mode);
 547
 548 void dce_clock_gating_power_up(struct dce_hwseq *hws,
 549                 bool enable);
 550
 551 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
 552                 struct clock_source *clk_src,
 553                 unsigned int tg_inst);
 554
 555 bool dce_use_lut(const struct dc_plane_state *surface);
 556 #endif   /*__DCE_HWSEQ_H__*/