2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "reg_helper.h"
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dce_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "i2caux_interface.h"
33 #include "dc_bios_types.h"
35 #include "gpio_service_interface.h"
37 #include "dce/dce_11_0_d.h"
38 #include "dce/dce_11_0_sh_mask.h"
39 #include "dce/dce_11_0_enum.h"
41 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
42 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
49 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
50 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
53 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
54 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
61 (enc110->link_regs->reg)
64 (enc110->aux_regs->reg)
67 (enc110->hpd_regs->reg)
69 #define DEFAULT_AUX_MAX_DATA_SIZE 16
70 #define AUX_MAX_DEFER_WRITE_RETRY 20
73 * Trigger Source Select
74 * ASIC-dependent, actual values for register programming
76 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
77 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
84 /* all values are in milliseconds */
85 /* For eDP, after power-up/power/down,
86 * 300/500 msec max. delay from LCDVCC to black video generation */
87 #define PANEL_POWER_UP_TIMEOUT 300
88 #define PANEL_POWER_DOWN_TIMEOUT 500
89 #define HPD_CHECK_INTERVAL 10
91 /* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
92 #define TMDS_MIN_PIXEL_CLOCK 25000
93 /* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
94 #define TMDS_MAX_PIXEL_CLOCK 165000
95 /* For current ASICs pixel clock - 600MHz */
96 #define MAX_ENCODER_CLOCK 600000
99 DP_MST_UPDATE_MAX_RETRY
= 50
102 #define DIG_REG(reg)\
103 (reg + enc110->offsets.dig)
106 (reg + enc110->offsets.dp)
108 static const struct link_encoder_funcs dce110_lnk_enc_funcs
= {
109 .validate_output_with_stream
=
110 dce110_link_encoder_validate_output_with_stream
,
111 .hw_init
= dce110_link_encoder_hw_init
,
112 .setup
= dce110_link_encoder_setup
,
113 .enable_tmds_output
= dce110_link_encoder_enable_tmds_output
,
114 .enable_dp_output
= dce110_link_encoder_enable_dp_output
,
115 .enable_dp_mst_output
= dce110_link_encoder_enable_dp_mst_output
,
116 .disable_output
= dce110_link_encoder_disable_output
,
117 .dp_set_lane_settings
= dce110_link_encoder_dp_set_lane_settings
,
118 .dp_set_phy_pattern
= dce110_link_encoder_dp_set_phy_pattern
,
119 .update_mst_stream_allocation_table
=
120 dce110_link_encoder_update_mst_stream_allocation_table
,
121 .psr_program_dp_dphy_fast_training
=
122 dce110_psr_program_dp_dphy_fast_training
,
123 .psr_program_secondary_packet
= dce110_psr_program_secondary_packet
,
124 .backlight_control
= dce110_link_encoder_edp_backlight_control
,
125 .power_control
= dce110_link_encoder_edp_power_control
,
126 .connect_dig_be_to_fe
= dce110_link_encoder_connect_dig_be_to_fe
,
127 .enable_hpd
= dce110_link_encoder_enable_hpd
,
128 .disable_hpd
= dce110_link_encoder_disable_hpd
,
129 .destroy
= dce110_link_encoder_destroy
132 static enum bp_result
link_transmitter_control(
133 struct dce110_link_encoder
*enc110
,
134 struct bp_transmitter_control
*cntl
)
136 enum bp_result result
;
137 struct dc_bios
*bp
= enc110
->base
.ctx
->dc_bios
;
139 result
= bp
->funcs
->transmitter_control(bp
, cntl
);
144 static void enable_phy_bypass_mode(
145 struct dce110_link_encoder
*enc110
,
148 /* This register resides in DP back end block;
149 * transmitter is used for the offset */
151 REG_UPDATE(DP_DPHY_CNTL
, DPHY_BYPASS
, enable
);
155 static void disable_prbs_symbols(
156 struct dce110_link_encoder
*enc110
,
159 /* This register resides in DP back end block;
160 * transmitter is used for the offset */
162 REG_UPDATE_4(DP_DPHY_CNTL
,
163 DPHY_ATEST_SEL_LANE0
, disable
,
164 DPHY_ATEST_SEL_LANE1
, disable
,
165 DPHY_ATEST_SEL_LANE2
, disable
,
166 DPHY_ATEST_SEL_LANE3
, disable
);
169 static void disable_prbs_mode(
170 struct dce110_link_encoder
*enc110
)
172 REG_UPDATE(DP_DPHY_PRBS_CNTL
, DPHY_PRBS_EN
, 0);
175 static void program_pattern_symbols(
176 struct dce110_link_encoder
*enc110
,
177 uint16_t pattern_symbols
[8])
179 /* This register resides in DP back end block;
180 * transmitter is used for the offset */
182 REG_SET_3(DP_DPHY_SYM0
, 0,
183 DPHY_SYM1
, pattern_symbols
[0],
184 DPHY_SYM2
, pattern_symbols
[1],
185 DPHY_SYM3
, pattern_symbols
[2]);
187 /* This register resides in DP back end block;
188 * transmitter is used for the offset */
190 REG_SET_3(DP_DPHY_SYM1
, 0,
191 DPHY_SYM4
, pattern_symbols
[3],
192 DPHY_SYM5
, pattern_symbols
[4],
193 DPHY_SYM6
, pattern_symbols
[5]);
195 /* This register resides in DP back end block;
196 * transmitter is used for the offset */
198 REG_SET_2(DP_DPHY_SYM2
, 0,
199 DPHY_SYM7
, pattern_symbols
[6],
200 DPHY_SYM8
, pattern_symbols
[7]);
203 static void set_dp_phy_pattern_d102(
204 struct dce110_link_encoder
*enc110
)
206 /* Disable PHY Bypass mode to setup the test pattern */
207 enable_phy_bypass_mode(enc110
, false);
209 /* For 10-bit PRBS or debug symbols
210 * please use the following sequence: */
212 /* Enable debug symbols on the lanes */
214 disable_prbs_symbols(enc110
, true);
216 /* Disable PRBS mode */
217 disable_prbs_mode(enc110
);
219 /* Program debug symbols to be output */
221 uint16_t pattern_symbols
[8] = {
222 0x2AA, 0x2AA, 0x2AA, 0x2AA,
223 0x2AA, 0x2AA, 0x2AA, 0x2AA
226 program_pattern_symbols(enc110
, pattern_symbols
);
229 /* Enable phy bypass mode to enable the test pattern */
231 enable_phy_bypass_mode(enc110
, true);
234 static void set_link_training_complete(
235 struct dce110_link_encoder
*enc110
,
238 /* This register resides in DP back end block;
239 * transmitter is used for the offset */
241 REG_UPDATE(DP_LINK_CNTL
, DP_LINK_TRAINING_COMPLETE
, complete
);
245 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
246 struct link_encoder
*enc
,
249 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
250 /* Write Training Pattern */
252 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL
, index
);
254 /* Set HW Register Training Complete to false */
256 set_link_training_complete(enc110
, false);
258 /* Disable PHY Bypass mode to output Training Pattern */
260 enable_phy_bypass_mode(enc110
, false);
262 /* Disable PRBS mode */
263 disable_prbs_mode(enc110
);
266 static void setup_panel_mode(
267 struct dce110_link_encoder
*enc110
,
268 enum dp_panel_mode panel_mode
)
272 ASSERT(REG(DP_DPHY_INTERNAL_CTRL
));
273 value
= REG_READ(DP_DPHY_INTERNAL_CTRL
);
275 switch (panel_mode
) {
276 case DP_PANEL_MODE_EDP
:
279 case DP_PANEL_MODE_SPECIAL
:
287 REG_WRITE(DP_DPHY_INTERNAL_CTRL
, value
);
290 static void set_dp_phy_pattern_symbol_error(
291 struct dce110_link_encoder
*enc110
)
293 /* Disable PHY Bypass mode to setup the test pattern */
294 enable_phy_bypass_mode(enc110
, false);
296 /* program correct panel mode*/
297 setup_panel_mode(enc110
, DP_PANEL_MODE_DEFAULT
);
299 /* A PRBS23 pattern is used for most DP electrical measurements. */
301 /* Enable PRBS symbols on the lanes */
302 disable_prbs_symbols(enc110
, false);
304 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
305 REG_UPDATE_2(DP_DPHY_PRBS_CNTL
,
309 /* Enable phy bypass mode to enable the test pattern */
310 enable_phy_bypass_mode(enc110
, true);
313 static void set_dp_phy_pattern_prbs7(
314 struct dce110_link_encoder
*enc110
)
316 /* Disable PHY Bypass mode to setup the test pattern */
317 enable_phy_bypass_mode(enc110
, false);
319 /* A PRBS7 pattern is used for most DP electrical measurements. */
321 /* Enable PRBS symbols on the lanes */
322 disable_prbs_symbols(enc110
, false);
324 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
325 REG_UPDATE_2(DP_DPHY_PRBS_CNTL
,
329 /* Enable phy bypass mode to enable the test pattern */
330 enable_phy_bypass_mode(enc110
, true);
333 static void set_dp_phy_pattern_80bit_custom(
334 struct dce110_link_encoder
*enc110
,
335 const uint8_t *pattern
)
337 /* Disable PHY Bypass mode to setup the test pattern */
338 enable_phy_bypass_mode(enc110
, false);
340 /* Enable debug symbols on the lanes */
342 disable_prbs_symbols(enc110
, true);
344 /* Enable PHY bypass mode to enable the test pattern */
345 /* TODO is it really needed ? */
347 enable_phy_bypass_mode(enc110
, true);
349 /* Program 80 bit custom pattern */
351 uint16_t pattern_symbols
[8];
354 ((pattern
[1] & 0x03) << 8) | pattern
[0];
356 ((pattern
[2] & 0x0f) << 6) | ((pattern
[1] >> 2) & 0x3f);
358 ((pattern
[3] & 0x3f) << 4) | ((pattern
[2] >> 4) & 0x0f);
360 (pattern
[4] << 2) | ((pattern
[3] >> 6) & 0x03);
362 ((pattern
[6] & 0x03) << 8) | pattern
[5];
364 ((pattern
[7] & 0x0f) << 6) | ((pattern
[6] >> 2) & 0x3f);
366 ((pattern
[8] & 0x3f) << 4) | ((pattern
[7] >> 4) & 0x0f);
368 (pattern
[9] << 2) | ((pattern
[8] >> 6) & 0x03);
370 program_pattern_symbols(enc110
, pattern_symbols
);
373 /* Enable phy bypass mode to enable the test pattern */
375 enable_phy_bypass_mode(enc110
, true);
378 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
379 struct dce110_link_encoder
*enc110
,
380 unsigned int cp2520_pattern
)
383 /* previously there is a register DP_HBR2_EYE_PATTERN
384 * that is enabled to get the pattern.
385 * But it does not work with the latest spec change,
386 * so we are programming the following registers manually.
388 * The following settings have been confirmed
389 * by Nick Chorney and Sandra Liu */
391 /* Disable PHY Bypass mode to setup the test pattern */
393 enable_phy_bypass_mode(enc110
, false);
395 /* Setup DIG encoder in DP SST mode */
396 enc110
->base
.funcs
->setup(&enc110
->base
, SIGNAL_TYPE_DISPLAY_PORT
);
398 /* ensure normal panel mode. */
399 setup_panel_mode(enc110
, DP_PANEL_MODE_DEFAULT
);
401 /* no vbid after BS (SR)
402 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
403 * 11000260 / 11000104 / 110000FC */
404 REG_UPDATE_3(DP_LINK_FRAMING_CNTL
,
405 DP_IDLE_BS_INTERVAL
, 0xFC,
407 DP_VID_ENHANCED_FRAME_MODE
, 1);
409 /* swap every BS with SR */
410 REG_UPDATE(DP_DPHY_SCRAM_CNTL
, DPHY_SCRAMBLER_BS_COUNT
, 0);
412 /* select cp2520 patterns */
413 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL
))
414 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL
,
415 DP_DPHY_HBR2_PATTERN_CONTROL
, cp2520_pattern
);
417 /* pre-DCE11 can only generate CP2520 pattern 2 */
418 ASSERT(cp2520_pattern
== 2);
420 /* set link training complete */
421 set_link_training_complete(enc110
, true);
423 /* disable video stream */
424 REG_UPDATE(DP_VID_STREAM_CNTL
, DP_VID_STREAM_ENABLE
, 0);
426 /* Disable PHY Bypass mode to setup the test pattern */
427 enable_phy_bypass_mode(enc110
, false);
430 static void set_dp_phy_pattern_passthrough_mode(
431 struct dce110_link_encoder
*enc110
,
432 enum dp_panel_mode panel_mode
)
434 /* program correct panel mode */
435 setup_panel_mode(enc110
, panel_mode
);
437 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
438 * in case we were doing HBR2 compliance pattern before
440 REG_UPDATE_3(DP_LINK_FRAMING_CNTL
,
441 DP_IDLE_BS_INTERVAL
, 0x2000,
443 DP_VID_ENHANCED_FRAME_MODE
, 1);
445 REG_UPDATE(DP_DPHY_SCRAM_CNTL
, DPHY_SCRAMBLER_BS_COUNT
, 0x1FF);
447 /* set link training complete */
448 set_link_training_complete(enc110
, true);
450 /* Disable PHY Bypass mode to setup the test pattern */
451 enable_phy_bypass_mode(enc110
, false);
453 /* Disable PRBS mode */
454 disable_prbs_mode(enc110
);
457 /* return value is bit-vector */
458 static uint8_t get_frontend_source(
459 enum engine_id engine
)
463 return DCE110_DIG_FE_SOURCE_SELECT_DIGA
;
465 return DCE110_DIG_FE_SOURCE_SELECT_DIGB
;
467 return DCE110_DIG_FE_SOURCE_SELECT_DIGC
;
469 return DCE110_DIG_FE_SOURCE_SELECT_DIGD
;
471 return DCE110_DIG_FE_SOURCE_SELECT_DIGE
;
473 return DCE110_DIG_FE_SOURCE_SELECT_DIGF
;
475 ASSERT_CRITICAL(false);
476 return DCE110_DIG_FE_SOURCE_SELECT_INVALID
;
480 static void configure_encoder(
481 struct dce110_link_encoder
*enc110
,
482 const struct dc_link_settings
*link_settings
)
484 /* set number of lanes */
486 REG_SET(DP_CONFIG
, 0,
487 DP_UDI_LANES
, link_settings
->lane_count
- LANE_COUNT_ONE
);
489 /* setup scrambler */
490 REG_UPDATE(DP_DPHY_SCRAM_CNTL
, DPHY_SCRAMBLER_ADVANCE
, 1);
493 static bool is_panel_powered_on(struct dce110_link_encoder
*enc110
)
498 REG_GET(LVTMA_PWRSEQ_STATE
, LVTMA_PWRSEQ_TARGET_STATE_R
, &value
);
505 /* TODO duplicate of dc_link.c version */
506 static struct gpio
*get_hpd_gpio(const struct link_encoder
*enc
)
508 enum bp_result bp_result
;
509 struct dc_bios
*dcb
= enc
->ctx
->dc_bios
;
510 struct graphics_object_hpd_info hpd_info
;
511 struct gpio_pin_info pin_info
;
513 if (dcb
->funcs
->get_hpd_info(dcb
, enc
->connector
, &hpd_info
) != BP_RESULT_OK
)
516 bp_result
= dcb
->funcs
->get_gpio_pin_info(dcb
,
517 hpd_info
.hpd_int_gpio_uid
, &pin_info
);
519 if (bp_result
!= BP_RESULT_OK
) {
520 ASSERT(bp_result
== BP_RESULT_NORECORD
);
524 return dal_gpio_service_create_irq(
525 enc
->ctx
->gpio_service
,
534 static void link_encoder_edp_wait_for_hpd_ready(
535 struct dce110_link_encoder
*enc110
,
538 struct dc_context
*ctx
= enc110
->base
.ctx
;
539 struct graphics_object_id connector
= enc110
->base
.connector
;
541 bool edp_hpd_high
= false;
542 uint32_t time_elapsed
= 0;
543 uint32_t timeout
= power_up
?
544 PANEL_POWER_UP_TIMEOUT
: PANEL_POWER_DOWN_TIMEOUT
;
546 if (dal_graphics_object_id_get_connector_id(connector
) !=
553 /* from KV, we will not HPD low after turning off VCC -
554 * instead, we will check the SW timer in power_up(). */
557 /* when we power on/off the eDP panel,
558 * we need to wait until SENSE bit is high/low */
561 /* TODO what to do with this? */
562 hpd
= get_hpd_gpio(&enc110
->base
);
569 dal_gpio_open(hpd
, GPIO_MODE_INTERRUPT
);
571 /* wait until timeout or panel detected */
574 uint32_t detected
= 0;
576 dal_gpio_get_value(hpd
, &detected
);
578 if (!(detected
^ power_up
)) {
583 msleep(HPD_CHECK_INTERVAL
);
585 time_elapsed
+= HPD_CHECK_INTERVAL
;
586 } while (time_elapsed
< timeout
);
590 dal_gpio_destroy_irq(&hpd
);
592 if (false == edp_hpd_high
) {
593 dm_logger_write(ctx
->logger
, LOG_ERROR
,
594 "%s: wait timed out!\n", __func__
);
600 * eDP only. Control the power of the eDP panel.
602 void dce110_link_encoder_edp_power_control(
603 struct link_encoder
*enc
,
606 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
607 struct dc_context
*ctx
= enc110
->base
.ctx
;
608 struct bp_transmitter_control cntl
= { 0 };
609 enum bp_result bp_result
;
611 if (dal_graphics_object_id_get_connector_id(enc110
->base
.connector
) !=
617 if ((power_up
&& !is_panel_powered_on(enc110
)) ||
618 (!power_up
&& is_panel_powered_on(enc110
))) {
620 /* Send VBIOS command to prompt eDP panel power */
622 dm_logger_write(ctx
->logger
, LOG_HW_RESUME_S3
,
623 "%s: Panel Power action: %s\n",
624 __func__
, (power_up
? "On":"Off"));
626 cntl
.action
= power_up
?
627 TRANSMITTER_CONTROL_POWER_ON
:
628 TRANSMITTER_CONTROL_POWER_OFF
;
629 cntl
.transmitter
= enc110
->base
.transmitter
;
630 cntl
.connector_obj_id
= enc110
->base
.connector
;
631 cntl
.coherent
= false;
632 cntl
.lanes_number
= LANE_COUNT_FOUR
;
633 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
635 bp_result
= link_transmitter_control(enc110
, &cntl
);
637 if (BP_RESULT_OK
!= bp_result
) {
639 dm_logger_write(ctx
->logger
, LOG_ERROR
,
640 "%s: Panel Power bp_result: %d\n",
641 __func__
, bp_result
);
644 dm_logger_write(ctx
->logger
, LOG_HW_RESUME_S3
,
645 "%s: Skipping Panel Power action: %s\n",
646 __func__
, (power_up
? "On":"Off"));
649 link_encoder_edp_wait_for_hpd_ready(enc110
, true);
652 static void aux_initialize(
653 struct dce110_link_encoder
*enc110
)
655 struct dc_context
*ctx
= enc110
->base
.ctx
;
656 enum hpd_source_id hpd_source
= enc110
->base
.hpd_source
;
657 uint32_t addr
= AUX_REG(AUX_CONTROL
);
658 uint32_t value
= dm_read_reg(ctx
, addr
);
660 set_reg_field_value(value
, hpd_source
, AUX_CONTROL
, AUX_HPD_SEL
);
661 set_reg_field_value(value
, 0, AUX_CONTROL
, AUX_LS_READ_EN
);
662 dm_write_reg(ctx
, addr
, value
);
664 addr
= AUX_REG(AUX_DPHY_RX_CONTROL0
);
665 value
= dm_read_reg(ctx
, addr
);
667 /* 1/4 window (the maximum allowed) */
668 set_reg_field_value(value
, 1,
669 AUX_DPHY_RX_CONTROL0
, AUX_RX_RECEIVE_WINDOW
);
670 dm_write_reg(ctx
, addr
, value
);
674 /*todo: cloned in stream enc, fix*/
675 static bool is_panel_backlight_on(struct dce110_link_encoder
*enc110
)
679 REG_GET(LVTMA_PWRSEQ_CNTL
, LVTMA_BLON
, &value
);
684 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder
*enc
,
685 bool exit_link_training_required
)
687 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
689 if (exit_link_training_required
)
690 REG_UPDATE(DP_DPHY_FAST_TRAINING
,
691 DPHY_RX_FAST_TRAINING_CAPABLE
, 1);
693 REG_UPDATE(DP_DPHY_FAST_TRAINING
,
694 DPHY_RX_FAST_TRAINING_CAPABLE
, 0);
695 /*In DCE 11, we are able to pre-program a Force SR register
696 * to be able to trigger SR symbol after 5 idle patterns
697 * transmitted. Upon PSR Exit, DMCU can trigger
698 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
699 * DPHY_LOAD_BS_COUNT_START and the internal counter
700 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
701 * replaced by SR symbol once.
704 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL
, DPHY_LOAD_BS_COUNT
, 0x5);
708 void dce110_psr_program_secondary_packet(struct link_encoder
*enc
,
709 unsigned int sdp_transmit_line_num_deadline
)
711 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
713 REG_UPDATE_2(DP_SEC_CNTL1
,
714 DP_SEC_GSP0_LINE_NUM
, sdp_transmit_line_num_deadline
,
715 DP_SEC_GSP0_PRIORITY
, 1);
718 /*todo: cloned in stream enc, fix*/
721 * eDP only. Control the backlight of the eDP panel
723 void dce110_link_encoder_edp_backlight_control(
724 struct link_encoder
*enc
,
727 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
728 struct dc_context
*ctx
= enc110
->base
.ctx
;
729 struct bp_transmitter_control cntl
= { 0 };
731 if (dal_graphics_object_id_get_connector_id(enc110
->base
.connector
)
732 != CONNECTOR_ID_EDP
) {
737 if (enable
&& is_panel_backlight_on(enc110
)) {
738 dm_logger_write(ctx
->logger
, LOG_HW_RESUME_S3
,
739 "%s: panel already powered up. Do nothing.\n",
744 if (!enable
&& !is_panel_powered_on(enc110
)) {
745 dm_logger_write(ctx
->logger
, LOG_HW_RESUME_S3
,
746 "%s: panel already powered down. Do nothing.\n",
751 /* Send VBIOS command to control eDP panel backlight */
753 dm_logger_write(ctx
->logger
, LOG_HW_RESUME_S3
,
754 "%s: backlight action: %s\n",
755 __func__
, (enable
? "On":"Off"));
757 cntl
.action
= enable
?
758 TRANSMITTER_CONTROL_BACKLIGHT_ON
:
759 TRANSMITTER_CONTROL_BACKLIGHT_OFF
;
760 /*cntl.engine_id = ctx->engine;*/
761 cntl
.transmitter
= enc110
->base
.transmitter
;
762 cntl
.connector_obj_id
= enc110
->base
.connector
;
764 cntl
.lanes_number
= LANE_COUNT_FOUR
;
765 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
767 /* For eDP, the following delays might need to be considered
768 * after link training completed:
769 * idle period - min. accounts for required BS-Idle pattern,
770 * max. allows for source frame synchronization);
771 * 50 msec max. delay from valid video data from source
772 * to video on dislpay or backlight enable.
774 * Disable the delay for now.
775 * Enable it in the future if necessary.
777 /* dc_service_sleep_in_milliseconds(50); */
778 link_transmitter_control(enc110
, &cntl
);
781 static bool is_dig_enabled(const struct dce110_link_encoder
*enc110
)
785 REG_GET(DIG_BE_EN_CNTL
, DIG_ENABLE
, &value
);
789 static void link_encoder_disable(struct dce110_link_encoder
*enc110
)
791 /* reset training pattern */
792 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL
, 0,
793 DPHY_TRAINING_PATTERN_SEL
, 0);
795 /* reset training complete */
796 REG_UPDATE(DP_LINK_CNTL
, DP_LINK_TRAINING_COMPLETE
, 0);
798 /* reset panel mode */
799 setup_panel_mode(enc110
, DP_PANEL_MODE_DEFAULT
);
802 static void hpd_initialize(
803 struct dce110_link_encoder
*enc110
)
805 /* Associate HPD with DIG_BE */
806 enum hpd_source_id hpd_source
= enc110
->base
.hpd_source
;
808 REG_UPDATE(DIG_BE_CNTL
, DIG_HPD_SELECT
, hpd_source
);
811 bool dce110_link_encoder_validate_dvi_output(
812 const struct dce110_link_encoder
*enc110
,
813 enum signal_type connector_signal
,
814 enum signal_type signal
,
815 const struct dc_crtc_timing
*crtc_timing
)
817 uint32_t max_pixel_clock
= TMDS_MAX_PIXEL_CLOCK
;
819 if (signal
== SIGNAL_TYPE_DVI_DUAL_LINK
)
820 max_pixel_clock
*= 2;
822 /* This handles the case of HDMI downgrade to DVI we don't want to
823 * we don't want to cap the pixel clock if the DDI is not DVI.
825 if (connector_signal
!= SIGNAL_TYPE_DVI_DUAL_LINK
&&
826 connector_signal
!= SIGNAL_TYPE_DVI_SINGLE_LINK
)
827 max_pixel_clock
= enc110
->base
.features
.max_hdmi_pixel_clock
;
829 /* DVI only support RGB pixel encoding */
830 if (crtc_timing
->pixel_encoding
!= PIXEL_ENCODING_RGB
)
833 /*connect DVI via adpater's HDMI connector*/
834 if ((connector_signal
== SIGNAL_TYPE_DVI_SINGLE_LINK
||
835 connector_signal
== SIGNAL_TYPE_HDMI_TYPE_A
) &&
836 signal
!= SIGNAL_TYPE_HDMI_TYPE_A
&&
837 crtc_timing
->pix_clk_khz
> TMDS_MAX_PIXEL_CLOCK
)
839 if (crtc_timing
->pix_clk_khz
< TMDS_MIN_PIXEL_CLOCK
)
842 if (crtc_timing
->pix_clk_khz
> max_pixel_clock
)
845 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
846 switch (crtc_timing
->display_color_depth
) {
847 case COLOR_DEPTH_666
:
848 case COLOR_DEPTH_888
:
850 case COLOR_DEPTH_101010
:
851 case COLOR_DEPTH_161616
:
852 if (signal
!= SIGNAL_TYPE_DVI_DUAL_LINK
)
862 static bool dce110_link_encoder_validate_hdmi_output(
863 const struct dce110_link_encoder
*enc110
,
864 const struct dc_crtc_timing
*crtc_timing
,
865 int adjusted_pix_clk_khz
)
867 enum dc_color_depth max_deep_color
=
868 enc110
->base
.features
.max_hdmi_deep_color
;
870 if (max_deep_color
< crtc_timing
->display_color_depth
)
873 if (crtc_timing
->display_color_depth
< COLOR_DEPTH_888
)
875 if (adjusted_pix_clk_khz
< TMDS_MIN_PIXEL_CLOCK
)
878 if ((adjusted_pix_clk_khz
== 0) ||
879 (adjusted_pix_clk_khz
> enc110
->base
.features
.max_hdmi_pixel_clock
))
882 /* DCE11 HW does not support 420 */
883 if (!enc110
->base
.features
.ycbcr420_supported
&&
884 crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR420
)
890 bool dce110_link_encoder_validate_dp_output(
891 const struct dce110_link_encoder
*enc110
,
892 const struct dc_crtc_timing
*crtc_timing
)
894 /* default RGB only */
895 if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_RGB
)
898 if (enc110
->base
.features
.flags
.bits
.IS_YCBCR_CAPABLE
)
901 /* for DCE 8.x or later DP Y-only feature,
902 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
903 if (crtc_timing
->flags
.Y_ONLY
&&
904 enc110
->base
.features
.flags
.bits
.IS_YCBCR_CAPABLE
&&
905 crtc_timing
->display_color_depth
!= COLOR_DEPTH_666
)
911 bool dce110_link_encoder_construct(
912 struct dce110_link_encoder
*enc110
,
913 const struct encoder_init_data
*init_data
,
914 const struct encoder_feature_support
*enc_features
,
915 const struct dce110_link_enc_registers
*link_regs
,
916 const struct dce110_link_enc_aux_registers
*aux_regs
,
917 const struct dce110_link_enc_hpd_registers
*hpd_regs
)
919 struct bp_encoder_cap_info bp_cap_info
= {0};
920 const struct dc_vbios_funcs
*bp_funcs
= init_data
->ctx
->dc_bios
->funcs
;
922 enc110
->base
.funcs
= &dce110_lnk_enc_funcs
;
923 enc110
->base
.ctx
= init_data
->ctx
;
924 enc110
->base
.id
= init_data
->encoder
;
926 enc110
->base
.hpd_source
= init_data
->hpd_source
;
927 enc110
->base
.connector
= init_data
->connector
;
929 enc110
->base
.preferred_engine
= ENGINE_ID_UNKNOWN
;
931 enc110
->base
.features
= *enc_features
;
933 enc110
->base
.transmitter
= init_data
->transmitter
;
935 /* set the flag to indicate whether driver poll the I2C data pin
936 * while doing the DP sink detect
939 /* if (dal_adapter_service_is_feature_supported(as,
940 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
941 enc110->base.features.flags.bits.
942 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
944 enc110
->base
.output_signals
=
945 SIGNAL_TYPE_DVI_SINGLE_LINK
|
946 SIGNAL_TYPE_DVI_DUAL_LINK
|
948 SIGNAL_TYPE_DISPLAY_PORT
|
949 SIGNAL_TYPE_DISPLAY_PORT_MST
|
951 SIGNAL_TYPE_HDMI_TYPE_A
;
953 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
954 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
955 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
956 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
957 * Prefer DIG assignment is decided by board design.
958 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
959 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
960 * By this, adding DIGG should not hurt DCE 8.0.
961 * This will let DCE 8.1 share DCE 8.0 as much as possible
964 enc110
->link_regs
= link_regs
;
965 enc110
->aux_regs
= aux_regs
;
966 enc110
->hpd_regs
= hpd_regs
;
968 switch (enc110
->base
.transmitter
) {
969 case TRANSMITTER_UNIPHY_A
:
970 enc110
->base
.preferred_engine
= ENGINE_ID_DIGA
;
972 case TRANSMITTER_UNIPHY_B
:
973 enc110
->base
.preferred_engine
= ENGINE_ID_DIGB
;
975 case TRANSMITTER_UNIPHY_C
:
976 enc110
->base
.preferred_engine
= ENGINE_ID_DIGC
;
978 case TRANSMITTER_UNIPHY_D
:
979 enc110
->base
.preferred_engine
= ENGINE_ID_DIGD
;
981 case TRANSMITTER_UNIPHY_E
:
982 enc110
->base
.preferred_engine
= ENGINE_ID_DIGE
;
984 case TRANSMITTER_UNIPHY_F
:
985 enc110
->base
.preferred_engine
= ENGINE_ID_DIGF
;
988 ASSERT_CRITICAL(false);
989 enc110
->base
.preferred_engine
= ENGINE_ID_UNKNOWN
;
992 dm_logger_write(init_data
->ctx
->logger
, LOG_I2C_AUX
,
993 "Using channel: %s [%d]\n",
994 DECODE_CHANNEL_ID(init_data
->channel
),
997 /* Override features with DCE-specific values */
998 if (BP_RESULT_OK
== bp_funcs
->get_encoder_cap_info(
999 enc110
->base
.ctx
->dc_bios
, enc110
->base
.id
,
1001 enc110
->base
.features
.flags
.bits
.IS_HBR2_CAPABLE
=
1002 bp_cap_info
.DP_HBR2_EN
;
1003 enc110
->base
.features
.flags
.bits
.IS_HBR3_CAPABLE
=
1004 bp_cap_info
.DP_HBR3_EN
;
1010 bool dce110_link_encoder_validate_output_with_stream(
1011 struct link_encoder
*enc
,
1012 struct pipe_ctx
*pipe_ctx
)
1014 struct core_stream
*stream
= pipe_ctx
->stream
;
1015 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1018 switch (pipe_ctx
->stream
->signal
) {
1019 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
1020 case SIGNAL_TYPE_DVI_DUAL_LINK
:
1021 is_valid
= dce110_link_encoder_validate_dvi_output(
1023 stream
->sink
->link
->public.connector_signal
,
1024 pipe_ctx
->stream
->signal
,
1025 &stream
->public.timing
);
1027 case SIGNAL_TYPE_HDMI_TYPE_A
:
1028 is_valid
= dce110_link_encoder_validate_hdmi_output(
1030 &stream
->public.timing
,
1031 stream
->phy_pix_clk
);
1033 case SIGNAL_TYPE_DISPLAY_PORT
:
1034 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
1035 is_valid
= dce110_link_encoder_validate_dp_output(
1036 enc110
, &stream
->public.timing
);
1038 case SIGNAL_TYPE_EDP
:
1040 (stream
->public.timing
.
1041 pixel_encoding
== PIXEL_ENCODING_RGB
) ? true : false;
1043 case SIGNAL_TYPE_VIRTUAL
:
1054 void dce110_link_encoder_hw_init(
1055 struct link_encoder
*enc
)
1057 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1058 struct dc_context
*ctx
= enc110
->base
.ctx
;
1059 struct bp_transmitter_control cntl
= { 0 };
1060 enum bp_result result
;
1062 cntl
.action
= TRANSMITTER_CONTROL_INIT
;
1063 cntl
.engine_id
= ENGINE_ID_UNKNOWN
;
1064 cntl
.transmitter
= enc110
->base
.transmitter
;
1065 cntl
.connector_obj_id
= enc110
->base
.connector
;
1066 cntl
.lanes_number
= LANE_COUNT_FOUR
;
1067 cntl
.coherent
= false;
1068 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1070 result
= link_transmitter_control(enc110
, &cntl
);
1072 if (result
!= BP_RESULT_OK
) {
1073 dm_logger_write(ctx
->logger
, LOG_ERROR
,
1074 "%s: Failed to execute VBIOS command table!\n",
1076 BREAK_TO_DEBUGGER();
1080 if (enc110
->base
.connector
.id
== CONNECTOR_ID_LVDS
) {
1081 cntl
.action
= TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS
;
1083 result
= link_transmitter_control(enc110
, &cntl
);
1085 ASSERT(result
== BP_RESULT_OK
);
1087 } else if (enc110
->base
.connector
.id
== CONNECTOR_ID_EDP
) {
1088 enc
->funcs
->power_control(&enc110
->base
, true);
1090 aux_initialize(enc110
);
1092 /* reinitialize HPD.
1093 * hpd_initialize() will pass DIG_FE id to HW context.
1094 * All other routine within HW context will use fe_engine_offset
1095 * as DIG_FE id even caller pass DIG_FE id.
1096 * So this routine must be called first. */
1097 hpd_initialize(enc110
);
1100 void dce110_link_encoder_destroy(struct link_encoder
**enc
)
1102 dm_free(TO_DCE110_LINK_ENC(*enc
));
1106 void dce110_link_encoder_setup(
1107 struct link_encoder
*enc
,
1108 enum signal_type signal
)
1110 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1113 case SIGNAL_TYPE_EDP
:
1114 case SIGNAL_TYPE_DISPLAY_PORT
:
1116 REG_UPDATE(DIG_BE_CNTL
, DIG_MODE
, 0);
1118 case SIGNAL_TYPE_LVDS
:
1120 REG_UPDATE(DIG_BE_CNTL
, DIG_MODE
, 1);
1122 case SIGNAL_TYPE_DVI_SINGLE_LINK
:
1123 case SIGNAL_TYPE_DVI_DUAL_LINK
:
1125 REG_UPDATE(DIG_BE_CNTL
, DIG_MODE
, 2);
1127 case SIGNAL_TYPE_HDMI_TYPE_A
:
1129 REG_UPDATE(DIG_BE_CNTL
, DIG_MODE
, 3);
1131 case SIGNAL_TYPE_DISPLAY_PORT_MST
:
1133 REG_UPDATE(DIG_BE_CNTL
, DIG_MODE
, 5);
1136 ASSERT_CRITICAL(false);
1137 /* invalid mode ! */
1143 /* TODO: still need depth or just pass in adjusted pixel clock? */
1144 void dce110_link_encoder_enable_tmds_output(
1145 struct link_encoder
*enc
,
1146 enum clock_source_id clock_source
,
1147 enum dc_color_depth color_depth
,
1150 uint32_t pixel_clock
)
1152 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1153 struct dc_context
*ctx
= enc110
->base
.ctx
;
1154 struct bp_transmitter_control cntl
= { 0 };
1155 enum bp_result result
;
1157 /* Enable the PHY */
1159 cntl
.action
= TRANSMITTER_CONTROL_ENABLE
;
1160 cntl
.engine_id
= enc
->preferred_engine
;
1161 cntl
.transmitter
= enc110
->base
.transmitter
;
1162 cntl
.pll_id
= clock_source
;
1164 cntl
.signal
= SIGNAL_TYPE_HDMI_TYPE_A
;
1165 cntl
.lanes_number
= 4;
1166 } else if (dual_link
) {
1167 cntl
.signal
= SIGNAL_TYPE_DVI_DUAL_LINK
;
1168 cntl
.lanes_number
= 8;
1170 cntl
.signal
= SIGNAL_TYPE_DVI_SINGLE_LINK
;
1171 cntl
.lanes_number
= 4;
1173 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1175 cntl
.pixel_clock
= pixel_clock
;
1176 cntl
.color_depth
= color_depth
;
1178 result
= link_transmitter_control(enc110
, &cntl
);
1180 if (result
!= BP_RESULT_OK
) {
1181 dm_logger_write(ctx
->logger
, LOG_ERROR
,
1182 "%s: Failed to execute VBIOS command table!\n",
1184 BREAK_TO_DEBUGGER();
1188 /* enables DP PHY output */
1189 void dce110_link_encoder_enable_dp_output(
1190 struct link_encoder
*enc
,
1191 const struct dc_link_settings
*link_settings
,
1192 enum clock_source_id clock_source
)
1194 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1195 struct dc_context
*ctx
= enc110
->base
.ctx
;
1196 struct bp_transmitter_control cntl
= { 0 };
1197 enum bp_result result
;
1199 /* Enable the PHY */
1201 /* number_of_lanes is used for pixel clock adjust,
1202 * but it's not passed to asic_control.
1203 * We need to set number of lanes manually.
1205 configure_encoder(enc110
, link_settings
);
1207 cntl
.action
= TRANSMITTER_CONTROL_ENABLE
;
1208 cntl
.engine_id
= enc
->preferred_engine
;
1209 cntl
.transmitter
= enc110
->base
.transmitter
;
1210 cntl
.pll_id
= clock_source
;
1211 cntl
.signal
= SIGNAL_TYPE_DISPLAY_PORT
;
1212 cntl
.lanes_number
= link_settings
->lane_count
;
1213 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1214 cntl
.pixel_clock
= link_settings
->link_rate
1215 * LINK_RATE_REF_FREQ_IN_KHZ
;
1216 /* TODO: check if undefined works */
1217 cntl
.color_depth
= COLOR_DEPTH_UNDEFINED
;
1219 result
= link_transmitter_control(enc110
, &cntl
);
1221 if (result
!= BP_RESULT_OK
) {
1222 dm_logger_write(ctx
->logger
, LOG_ERROR
,
1223 "%s: Failed to execute VBIOS command table!\n",
1225 BREAK_TO_DEBUGGER();
1229 /* enables DP PHY output in MST mode */
1230 void dce110_link_encoder_enable_dp_mst_output(
1231 struct link_encoder
*enc
,
1232 const struct dc_link_settings
*link_settings
,
1233 enum clock_source_id clock_source
)
1235 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1236 struct dc_context
*ctx
= enc110
->base
.ctx
;
1237 struct bp_transmitter_control cntl
= { 0 };
1238 enum bp_result result
;
1240 /* Enable the PHY */
1242 /* number_of_lanes is used for pixel clock adjust,
1243 * but it's not passed to asic_control.
1244 * We need to set number of lanes manually.
1246 configure_encoder(enc110
, link_settings
);
1248 cntl
.action
= TRANSMITTER_CONTROL_ENABLE
;
1249 cntl
.engine_id
= ENGINE_ID_UNKNOWN
;
1250 cntl
.transmitter
= enc110
->base
.transmitter
;
1251 cntl
.pll_id
= clock_source
;
1252 cntl
.signal
= SIGNAL_TYPE_DISPLAY_PORT_MST
;
1253 cntl
.lanes_number
= link_settings
->lane_count
;
1254 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1255 cntl
.pixel_clock
= link_settings
->link_rate
1256 * LINK_RATE_REF_FREQ_IN_KHZ
;
1257 /* TODO: check if undefined works */
1258 cntl
.color_depth
= COLOR_DEPTH_UNDEFINED
;
1260 result
= link_transmitter_control(enc110
, &cntl
);
1262 if (result
!= BP_RESULT_OK
) {
1263 dm_logger_write(ctx
->logger
, LOG_ERROR
,
1264 "%s: Failed to execute VBIOS command table!\n",
1266 BREAK_TO_DEBUGGER();
1271 * Disable transmitter and its encoder
1273 void dce110_link_encoder_disable_output(
1274 struct link_encoder
*enc
,
1275 enum signal_type signal
)
1277 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1278 struct dc_context
*ctx
= enc110
->base
.ctx
;
1279 struct bp_transmitter_control cntl
= { 0 };
1280 enum bp_result result
;
1282 if (!is_dig_enabled(enc110
)) {
1283 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1286 /* Power-down RX and disable GPU PHY should be paired.
1287 * Disabling PHY without powering down RX may cause
1288 * symbol lock loss, on which we will get DP Sink interrupt. */
1290 /* There is a case for the DP active dongles
1291 * where we want to disable the PHY but keep RX powered,
1292 * for those we need to ignore DP Sink interrupt
1293 * by checking lane count that has been set
1294 * on the last do_enable_output(). */
1296 /* disable transmitter */
1297 cntl
.action
= TRANSMITTER_CONTROL_DISABLE
;
1298 cntl
.transmitter
= enc110
->base
.transmitter
;
1299 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1300 cntl
.signal
= signal
;
1301 cntl
.connector_obj_id
= enc110
->base
.connector
;
1303 result
= link_transmitter_control(enc110
, &cntl
);
1305 if (result
!= BP_RESULT_OK
) {
1306 dm_logger_write(ctx
->logger
, LOG_ERROR
,
1307 "%s: Failed to execute VBIOS command table!\n",
1309 BREAK_TO_DEBUGGER();
1313 /* disable encoder */
1314 if (dc_is_dp_signal(signal
))
1315 link_encoder_disable(enc110
);
1317 if (enc110
->base
.connector
.id
== CONNECTOR_ID_EDP
) {
1318 /* power down eDP panel */
1319 /* TODO: Power control cause regression, we should implement
1320 * it properly, for now just comment it.
1322 * link_encoder_edp_wait_for_hpd_ready(
1324 link_enc->connector,
1327 * link_encoder_edp_power_control(
1328 link_enc, false); */
1332 void dce110_link_encoder_dp_set_lane_settings(
1333 struct link_encoder
*enc
,
1334 const struct link_training_settings
*link_settings
)
1336 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1337 union dpcd_training_lane_set training_lane_set
= { { 0 } };
1339 struct bp_transmitter_control cntl
= { 0 };
1341 if (!link_settings
) {
1342 BREAK_TO_DEBUGGER();
1346 cntl
.action
= TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS
;
1347 cntl
.transmitter
= enc110
->base
.transmitter
;
1348 cntl
.connector_obj_id
= enc110
->base
.connector
;
1349 cntl
.lanes_number
= link_settings
->link_settings
.lane_count
;
1350 cntl
.hpd_sel
= enc110
->base
.hpd_source
;
1351 cntl
.pixel_clock
= link_settings
->link_settings
.link_rate
*
1352 LINK_RATE_REF_FREQ_IN_KHZ
;
1354 for (lane
= 0; lane
< link_settings
->link_settings
.lane_count
; lane
++) {
1355 /* translate lane settings */
1357 training_lane_set
.bits
.VOLTAGE_SWING_SET
=
1358 link_settings
->lane_settings
[lane
].VOLTAGE_SWING
;
1359 training_lane_set
.bits
.PRE_EMPHASIS_SET
=
1360 link_settings
->lane_settings
[lane
].PRE_EMPHASIS
;
1362 /* post cursor 2 setting only applies to HBR2 link rate */
1363 if (link_settings
->link_settings
.link_rate
== LINK_RATE_HIGH2
) {
1364 /* this is passed to VBIOS
1365 * to program post cursor 2 level */
1367 training_lane_set
.bits
.POST_CURSOR2_SET
=
1368 link_settings
->lane_settings
[lane
].POST_CURSOR2
;
1371 cntl
.lane_select
= lane
;
1372 cntl
.lane_settings
= training_lane_set
.raw
;
1374 /* call VBIOS table to set voltage swing and pre-emphasis */
1375 link_transmitter_control(enc110
, &cntl
);
1379 /* set DP PHY test and training patterns */
1380 void dce110_link_encoder_dp_set_phy_pattern(
1381 struct link_encoder
*enc
,
1382 const struct encoder_set_dp_phy_pattern_param
*param
)
1384 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1386 switch (param
->dp_phy_pattern
) {
1387 case DP_TEST_PATTERN_TRAINING_PATTERN1
:
1388 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc
, 0);
1390 case DP_TEST_PATTERN_TRAINING_PATTERN2
:
1391 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc
, 1);
1393 case DP_TEST_PATTERN_TRAINING_PATTERN3
:
1394 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc
, 2);
1396 case DP_TEST_PATTERN_TRAINING_PATTERN4
:
1397 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc
, 3);
1399 case DP_TEST_PATTERN_D102
:
1400 set_dp_phy_pattern_d102(enc110
);
1402 case DP_TEST_PATTERN_SYMBOL_ERROR
:
1403 set_dp_phy_pattern_symbol_error(enc110
);
1405 case DP_TEST_PATTERN_PRBS7
:
1406 set_dp_phy_pattern_prbs7(enc110
);
1408 case DP_TEST_PATTERN_80BIT_CUSTOM
:
1409 set_dp_phy_pattern_80bit_custom(
1410 enc110
, param
->custom_pattern
);
1412 case DP_TEST_PATTERN_CP2520_1
:
1413 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110
, 1);
1415 case DP_TEST_PATTERN_CP2520_2
:
1416 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110
, 2);
1418 case DP_TEST_PATTERN_CP2520_3
:
1419 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110
, 3);
1421 case DP_TEST_PATTERN_VIDEO_MODE
: {
1422 set_dp_phy_pattern_passthrough_mode(
1423 enc110
, param
->dp_panel_mode
);
1428 /* invalid phy pattern */
1429 ASSERT_CRITICAL(false);
1434 static void fill_stream_allocation_row_info(
1435 const struct link_mst_stream_allocation
*stream_allocation
,
1439 const struct stream_encoder
*stream_enc
= stream_allocation
->stream_enc
;
1442 *src
= stream_enc
->id
;
1443 *slots
= stream_allocation
->slot_count
;
1450 /* programs DP MST VC payload allocation */
1451 void dce110_link_encoder_update_mst_stream_allocation_table(
1452 struct link_encoder
*enc
,
1453 const struct link_mst_stream_allocation_table
*table
)
1455 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1456 uint32_t value0
= 0;
1457 uint32_t value1
= 0;
1458 uint32_t value2
= 0;
1461 uint32_t retries
= 0;
1463 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1465 /* --- Set MSE Stream Attribute -
1466 * Setup VC Payload Table on Tx Side,
1467 * Issue allocation change trigger
1468 * to commit payload on both tx and rx side */
1470 /* we should clean-up table each time */
1472 if (table
->stream_count
>= 1) {
1473 fill_stream_allocation_row_info(
1474 &table
->stream_allocations
[0],
1482 REG_UPDATE_2(DP_MSE_SAT0
,
1483 DP_MSE_SAT_SRC0
, src
,
1484 DP_MSE_SAT_SLOT_COUNT0
, slots
);
1486 if (table
->stream_count
>= 2) {
1487 fill_stream_allocation_row_info(
1488 &table
->stream_allocations
[1],
1496 REG_UPDATE_2(DP_MSE_SAT0
,
1497 DP_MSE_SAT_SRC1
, src
,
1498 DP_MSE_SAT_SLOT_COUNT1
, slots
);
1500 if (table
->stream_count
>= 3) {
1501 fill_stream_allocation_row_info(
1502 &table
->stream_allocations
[2],
1510 REG_UPDATE_2(DP_MSE_SAT1
,
1511 DP_MSE_SAT_SRC2
, src
,
1512 DP_MSE_SAT_SLOT_COUNT2
, slots
);
1514 if (table
->stream_count
>= 4) {
1515 fill_stream_allocation_row_info(
1516 &table
->stream_allocations
[3],
1524 REG_UPDATE_2(DP_MSE_SAT1
,
1525 DP_MSE_SAT_SRC3
, src
,
1526 DP_MSE_SAT_SLOT_COUNT3
, slots
);
1528 /* --- wait for transaction finish */
1530 /* send allocation change trigger (ACT) ?
1531 * this step first sends the ACT,
1532 * then double buffers the SAT into the hardware
1533 * making the new allocation active on the DP MST mode link */
1536 /* DP_MSE_SAT_UPDATE:
1538 * 1 - Update SAT with trigger
1539 * 2 - Update SAT without trigger */
1541 REG_UPDATE(DP_MSE_SAT_UPDATE
,
1542 DP_MSE_SAT_UPDATE
, 1);
1544 /* wait for update to complete
1545 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1546 * then wait for the transmission
1547 * of at least 16 MTP headers on immediate local link.
1548 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1549 * a value of 1 indicates that DP MST mode
1550 * is in the 16 MTP keepout region after a VC has been added.
1551 * MST stream bandwidth (VC rate) can be configured
1552 * after this bit is cleared */
1557 value0
= REG_READ(DP_MSE_SAT_UPDATE
);
1559 REG_GET(DP_MSE_SAT_UPDATE
,
1560 DP_MSE_SAT_UPDATE
, &value1
);
1562 REG_GET(DP_MSE_SAT_UPDATE
,
1563 DP_MSE_16_MTP_KEEPOUT
, &value2
);
1565 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1566 if (!value1
&& !value2
)
1569 } while (retries
< DP_MST_UPDATE_MAX_RETRY
);
1572 void dce110_link_encoder_connect_dig_be_to_fe(
1573 struct link_encoder
*enc
,
1574 enum engine_id engine
,
1577 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1580 if (engine
!= ENGINE_ID_UNKNOWN
) {
1582 REG_GET(DIG_BE_CNTL
, DIG_FE_SOURCE_SELECT
, &field
);
1585 field
|= get_frontend_source(engine
);
1587 field
&= ~get_frontend_source(engine
);
1589 REG_UPDATE(DIG_BE_CNTL
, DIG_FE_SOURCE_SELECT
, field
);
1593 void dce110_link_encoder_enable_hpd(struct link_encoder
*enc
)
1595 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1596 struct dc_context
*ctx
= enc110
->base
.ctx
;
1597 uint32_t addr
= HPD_REG(DC_HPD_CONTROL
);
1598 uint32_t hpd_enable
= 0;
1599 uint32_t value
= dm_read_reg(ctx
, addr
);
1601 get_reg_field_value(hpd_enable
, DC_HPD_CONTROL
, DC_HPD_EN
);
1603 if (hpd_enable
== 0)
1604 set_reg_field_value(value
, 1, DC_HPD_CONTROL
, DC_HPD_EN
);
1607 void dce110_link_encoder_disable_hpd(struct link_encoder
*enc
)
1609 struct dce110_link_encoder
*enc110
= TO_DCE110_LINK_ENC(enc
);
1610 struct dc_context
*ctx
= enc110
->base
.ctx
;
1611 uint32_t addr
= HPD_REG(DC_HPD_CONTROL
);
1612 uint32_t value
= dm_read_reg(ctx
, addr
);
1614 set_reg_field_value(value
, 0, DC_HPD_CONTROL
, DC_HPD_EN
);