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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / display / dc / dce / dce_stream_encoder.c
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27
28 #include "dc_bios_types.h"
29 #include "dce_stream_encoder.h"
30 #include "reg_helper.h"
31 #include "hw_shared.h"
32
33 #define DC_LOGGER \
34 enc110->base.ctx->logger
35
36
37 #define REG(reg)\
38 (enc110->regs->reg)
39
40 #undef FN
41 #define FN(reg_name, field_name) \
42 enc110->se_shift->field_name, enc110->se_mask->field_name
43
44 #define VBI_LINE_0 0
45 #define DP_BLANK_MAX_RETRY 20
46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
50 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
51 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
52 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
53 #endif
54
55 enum {
56 DP_MST_UPDATE_MAX_RETRY = 50
57 };
58
59 #define DCE110_SE(audio)\
60 container_of(audio, struct dce110_stream_encoder, base)
61
62 #define CTX \
63 enc110->base.ctx
64
65 static void dce110_update_generic_info_packet(
66 struct dce110_stream_encoder *enc110,
67 uint32_t packet_index,
68 const struct dc_info_packet *info_packet)
69 {
70 uint32_t regval;
71 /* TODOFPGA Figure out a proper number for max_retries polling for lock
72 * use 50 for now.
73 */
74 uint32_t max_retries = 50;
75
76 /*we need turn on clock before programming AFMT block*/
77 if (REG(AFMT_CNTL))
78 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
79
80 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
81 if (packet_index >= 8)
82 ASSERT(0);
83
84 /* poll dig_update_lock is not locked -> asic internal signal
85 * assume otg master lock will unlock it
86 */
87 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
88 0, 10, max_retries);*/
89
90 /* check if HW reading GSP memory */
91 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
92 0, 10, max_retries);
93
94 /* HW does is not reading GSP memory not reading too long ->
95 * something wrong. clear GPS memory access and notify?
96 * hw SW is writing to GSP memory
97 */
98 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
99 }
100 /* choose which generic packet to use */
101 {
102 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
104 AFMT_GENERIC_INDEX, packet_index);
105 }
106
107 /* write generic packet header
108 * (4th byte is for GENERIC0 only) */
109 {
110 REG_SET_4(AFMT_GENERIC_HDR, 0,
111 AFMT_GENERIC_HB0, info_packet->hb0,
112 AFMT_GENERIC_HB1, info_packet->hb1,
113 AFMT_GENERIC_HB2, info_packet->hb2,
114 AFMT_GENERIC_HB3, info_packet->hb3);
115 }
116
117 /* write generic packet contents
118 * (we never use last 4 bytes)
119 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
120 {
121 const uint32_t *content =
122 (const uint32_t *) &info_packet->sb[0];
123
124 REG_WRITE(AFMT_GENERIC_0, *content++);
125 REG_WRITE(AFMT_GENERIC_1, *content++);
126 REG_WRITE(AFMT_GENERIC_2, *content++);
127 REG_WRITE(AFMT_GENERIC_3, *content++);
128 REG_WRITE(AFMT_GENERIC_4, *content++);
129 REG_WRITE(AFMT_GENERIC_5, *content++);
130 REG_WRITE(AFMT_GENERIC_6, *content++);
131 REG_WRITE(AFMT_GENERIC_7, *content);
132 }
133
134 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
135 /* force double-buffered packet update */
136 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
137 AFMT_GENERIC0_UPDATE, (packet_index == 0),
138 AFMT_GENERIC2_UPDATE, (packet_index == 2));
139 }
140 #if defined(CONFIG_DRM_AMD_DC_DCN)
141 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
142 switch (packet_index) {
143 case 0:
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
145 AFMT_GENERIC0_FRAME_UPDATE, 1);
146 break;
147 case 1:
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
149 AFMT_GENERIC1_FRAME_UPDATE, 1);
150 break;
151 case 2:
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
153 AFMT_GENERIC2_FRAME_UPDATE, 1);
154 break;
155 case 3:
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
157 AFMT_GENERIC3_FRAME_UPDATE, 1);
158 break;
159 case 4:
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
161 AFMT_GENERIC4_FRAME_UPDATE, 1);
162 break;
163 case 5:
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
165 AFMT_GENERIC5_FRAME_UPDATE, 1);
166 break;
167 case 6:
168 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
169 AFMT_GENERIC6_FRAME_UPDATE, 1);
170 break;
171 case 7:
172 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
173 AFMT_GENERIC7_FRAME_UPDATE, 1);
174 break;
175 default:
176 break;
177 }
178 }
179 #endif
180 }
181
182 static void dce110_update_hdmi_info_packet(
183 struct dce110_stream_encoder *enc110,
184 uint32_t packet_index,
185 const struct dc_info_packet *info_packet)
186 {
187 uint32_t cont, send, line;
188
189 if (info_packet->valid) {
190 dce110_update_generic_info_packet(
191 enc110,
192 packet_index,
193 info_packet);
194
195 /* enable transmission of packet(s) -
196 * packet transmission begins on the next frame */
197 cont = 1;
198 /* send packet(s) every frame */
199 send = 1;
200 /* select line number to send packets on */
201 line = 2;
202 } else {
203 cont = 0;
204 send = 0;
205 line = 0;
206 }
207
208 /* choose which generic packet control to use */
209 switch (packet_index) {
210 case 0:
211 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
212 HDMI_GENERIC0_CONT, cont,
213 HDMI_GENERIC0_SEND, send,
214 HDMI_GENERIC0_LINE, line);
215 break;
216 case 1:
217 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
218 HDMI_GENERIC1_CONT, cont,
219 HDMI_GENERIC1_SEND, send,
220 HDMI_GENERIC1_LINE, line);
221 break;
222 case 2:
223 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
224 HDMI_GENERIC0_CONT, cont,
225 HDMI_GENERIC0_SEND, send,
226 HDMI_GENERIC0_LINE, line);
227 break;
228 case 3:
229 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
230 HDMI_GENERIC1_CONT, cont,
231 HDMI_GENERIC1_SEND, send,
232 HDMI_GENERIC1_LINE, line);
233 break;
234 #if defined(CONFIG_DRM_AMD_DC_DCN)
235 case 4:
236 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
237 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
238 HDMI_GENERIC0_CONT, cont,
239 HDMI_GENERIC0_SEND, send,
240 HDMI_GENERIC0_LINE, line);
241 break;
242 case 5:
243 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
244 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
245 HDMI_GENERIC1_CONT, cont,
246 HDMI_GENERIC1_SEND, send,
247 HDMI_GENERIC1_LINE, line);
248 break;
249 case 6:
250 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
251 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
252 HDMI_GENERIC0_CONT, cont,
253 HDMI_GENERIC0_SEND, send,
254 HDMI_GENERIC0_LINE, line);
255 break;
256 case 7:
257 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
258 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
259 HDMI_GENERIC1_CONT, cont,
260 HDMI_GENERIC1_SEND, send,
261 HDMI_GENERIC1_LINE, line);
262 break;
263 #endif
264 default:
265 /* invalid HW packet index */
266 DC_LOG_WARNING(
267 "Invalid HW packet index: %s()\n",
268 __func__);
269 return;
270 }
271 }
272
273 /* setup stream encoder in dp mode */
274 static void dce110_stream_encoder_dp_set_stream_attribute(
275 struct stream_encoder *enc,
276 struct dc_crtc_timing *crtc_timing,
277 enum dc_color_space output_color_space,
278 bool use_vsc_sdp_for_colorimetry,
279 uint32_t enable_sdp_splitting)
280 {
281 #if defined(CONFIG_DRM_AMD_DC_DCN)
282 uint32_t h_active_start;
283 uint32_t v_active_start;
284 uint32_t misc0 = 0;
285 uint32_t misc1 = 0;
286 uint32_t h_blank;
287 uint32_t h_back_porch;
288 uint8_t synchronous_clock = 0; /* asynchronous mode */
289 uint8_t colorimetry_bpc;
290 uint8_t dynamic_range_rgb = 0; /*full range*/
291 uint8_t dynamic_range_ycbcr = 1; /*bt709*/
292 #endif
293
294 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
295 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
296 if (hw_crtc_timing.flags.INTERLACE) {
297 /*the input timing is in VESA spec format with Interlace flag =1*/
298 hw_crtc_timing.v_total /= 2;
299 hw_crtc_timing.v_border_top /= 2;
300 hw_crtc_timing.v_addressable /= 2;
301 hw_crtc_timing.v_border_bottom /= 2;
302 hw_crtc_timing.v_front_porch /= 2;
303 hw_crtc_timing.v_sync_width /= 2;
304 }
305 /* set pixel encoding */
306 switch (hw_crtc_timing.pixel_encoding) {
307 case PIXEL_ENCODING_YCBCR422:
308 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
309 DP_PIXEL_ENCODING_TYPE_YCBCR422);
310 break;
311 case PIXEL_ENCODING_YCBCR444:
312 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
313 DP_PIXEL_ENCODING_TYPE_YCBCR444);
314
315 if (hw_crtc_timing.flags.Y_ONLY)
316 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
317 /* HW testing only, no use case yet.
318 * Color depth of Y-only could be
319 * 8, 10, 12, 16 bits */
320 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
321 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
322 /* Note: DP_MSA_MISC1 bit 7 is the indicator
323 * of Y-only mode.
324 * This bit is set in HW if register
325 * DP_PIXEL_ENCODING is programmed to 0x4 */
326 break;
327 case PIXEL_ENCODING_YCBCR420:
328 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
329 DP_PIXEL_ENCODING_TYPE_YCBCR420);
330 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
331 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
332
333 #if defined(CONFIG_DRM_AMD_DC_DCN)
334 if (enc110->se_mask->DP_VID_N_MUL)
335 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
336 #endif
337 break;
338 default:
339 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
340 DP_PIXEL_ENCODING_TYPE_RGB444);
341 break;
342 }
343
344 #if defined(CONFIG_DRM_AMD_DC_DCN)
345 if (REG(DP_MSA_MISC))
346 misc1 = REG_READ(DP_MSA_MISC);
347 #endif
348
349 /* set color depth */
350
351 switch (hw_crtc_timing.display_color_depth) {
352 case COLOR_DEPTH_666:
353 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
354 0);
355 break;
356 case COLOR_DEPTH_888:
357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
358 DP_COMPONENT_PIXEL_DEPTH_8BPC);
359 break;
360 case COLOR_DEPTH_101010:
361 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
362 DP_COMPONENT_PIXEL_DEPTH_10BPC);
363
364 break;
365 case COLOR_DEPTH_121212:
366 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
367 DP_COMPONENT_PIXEL_DEPTH_12BPC);
368 break;
369 default:
370 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
371 DP_COMPONENT_PIXEL_DEPTH_6BPC);
372 break;
373 }
374
375 /* set dynamic range and YCbCr range */
376
377
378 #if defined(CONFIG_DRM_AMD_DC_DCN)
379 switch (hw_crtc_timing.display_color_depth) {
380 case COLOR_DEPTH_666:
381 colorimetry_bpc = 0;
382 break;
383 case COLOR_DEPTH_888:
384 colorimetry_bpc = 1;
385 break;
386 case COLOR_DEPTH_101010:
387 colorimetry_bpc = 2;
388 break;
389 case COLOR_DEPTH_121212:
390 colorimetry_bpc = 3;
391 break;
392 default:
393 colorimetry_bpc = 0;
394 break;
395 }
396
397 misc0 = misc0 | synchronous_clock;
398 misc0 = colorimetry_bpc << 5;
399
400 if (REG(DP_MSA_TIMING_PARAM1)) {
401 switch (output_color_space) {
402 case COLOR_SPACE_SRGB:
403 misc0 = misc0 | 0x0;
404 misc1 = misc1 & ~0x80; /* bit7 = 0*/
405 dynamic_range_rgb = 0; /*full range*/
406 break;
407 case COLOR_SPACE_SRGB_LIMITED:
408 misc0 = misc0 | 0x8; /* bit3=1 */
409 misc1 = misc1 & ~0x80; /* bit7 = 0*/
410 dynamic_range_rgb = 1; /*limited range*/
411 break;
412 case COLOR_SPACE_YCBCR601:
413 case COLOR_SPACE_YCBCR601_LIMITED:
414 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
415 misc1 = misc1 & ~0x80; /* bit7 = 0*/
416 dynamic_range_ycbcr = 0; /*bt601*/
417 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
418 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
419 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
420 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
421 break;
422 case COLOR_SPACE_YCBCR709:
423 case COLOR_SPACE_YCBCR709_LIMITED:
424 case COLOR_SPACE_YCBCR709_BLACK:
425 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
426 misc1 = misc1 & ~0x80; /* bit7 = 0*/
427 dynamic_range_ycbcr = 1; /*bt709*/
428 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
429 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
430 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
431 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
432 break;
433 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
434 dynamic_range_rgb = 1; /*limited range*/
435 break;
436 case COLOR_SPACE_2020_RGB_FULLRANGE:
437 case COLOR_SPACE_2020_YCBCR:
438 case COLOR_SPACE_XR_RGB:
439 case COLOR_SPACE_MSREF_SCRGB:
440 case COLOR_SPACE_ADOBERGB:
441 case COLOR_SPACE_DCIP3:
442 case COLOR_SPACE_XV_YCC_709:
443 case COLOR_SPACE_XV_YCC_601:
444 case COLOR_SPACE_DISPLAYNATIVE:
445 case COLOR_SPACE_DOLBYVISION:
446 case COLOR_SPACE_APPCTRL:
447 case COLOR_SPACE_CUSTOMPOINTS:
448 case COLOR_SPACE_UNKNOWN:
449 /* do nothing */
450 break;
451 }
452 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
453 REG_UPDATE_2(
454 DP_PIXEL_FORMAT,
455 DP_DYN_RANGE, dynamic_range_rgb,
456 DP_YCBCR_RANGE, dynamic_range_ycbcr);
457
458 #if defined(CONFIG_DRM_AMD_DC_DCN)
459 if (REG(DP_MSA_COLORIMETRY))
460 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
461
462 if (REG(DP_MSA_MISC))
463 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
464
465 /* dcn new register
466 * dc_crtc_timing is vesa dmt struct. data from edid
467 */
468 if (REG(DP_MSA_TIMING_PARAM1))
469 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
470 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
471 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
472 #endif
473
474 /* calcuate from vesa timing parameters
475 * h_active_start related to leading edge of sync
476 */
477
478 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
479 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
480
481 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
482 hw_crtc_timing.h_sync_width;
483
484 /* start at begining of left border */
485 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
486
487
488 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
489 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
490 hw_crtc_timing.v_front_porch;
491
492
493 #if defined(CONFIG_DRM_AMD_DC_DCN)
494 /* start at begining of left border */
495 if (REG(DP_MSA_TIMING_PARAM2))
496 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
497 DP_MSA_HSTART, h_active_start,
498 DP_MSA_VSTART, v_active_start);
499
500 if (REG(DP_MSA_TIMING_PARAM3))
501 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
502 DP_MSA_HSYNCWIDTH,
503 hw_crtc_timing.h_sync_width,
504 DP_MSA_HSYNCPOLARITY,
505 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
506 DP_MSA_VSYNCWIDTH,
507 hw_crtc_timing.v_sync_width,
508 DP_MSA_VSYNCPOLARITY,
509 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
510
511 /* HWDITH include border or overscan */
512 if (REG(DP_MSA_TIMING_PARAM4))
513 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
514 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
515 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
516 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
517 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
518 #endif
519 }
520 #endif
521 }
522
523 static void dce110_stream_encoder_set_stream_attribute_helper(
524 struct dce110_stream_encoder *enc110,
525 struct dc_crtc_timing *crtc_timing)
526 {
527 if (enc110->regs->TMDS_CNTL) {
528 switch (crtc_timing->pixel_encoding) {
529 case PIXEL_ENCODING_YCBCR422:
530 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
531 break;
532 default:
533 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
534 break;
535 }
536 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
537 } else if (enc110->regs->DIG_FE_CNTL) {
538 switch (crtc_timing->pixel_encoding) {
539 case PIXEL_ENCODING_YCBCR422:
540 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
541 break;
542 default:
543 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
544 break;
545 }
546 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
547 }
548
549 }
550
551 /* setup stream encoder in hdmi mode */
552 static void dce110_stream_encoder_hdmi_set_stream_attribute(
553 struct stream_encoder *enc,
554 struct dc_crtc_timing *crtc_timing,
555 int actual_pix_clk_khz,
556 bool enable_audio)
557 {
558 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
559 struct bp_encoder_control cntl = {0};
560
561 cntl.action = ENCODER_CONTROL_SETUP;
562 cntl.engine_id = enc110->base.id;
563 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
564 cntl.enable_dp_audio = enable_audio;
565 cntl.pixel_clock = actual_pix_clk_khz;
566 cntl.lanes_number = LANE_COUNT_FOUR;
567 cntl.color_depth = crtc_timing->display_color_depth;
568
569 if (enc110->base.bp->funcs->encoder_control(
570 enc110->base.bp, &cntl) != BP_RESULT_OK)
571 return;
572
573 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
574
575 /* setup HDMI engine */
576 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
577 REG_UPDATE_3(HDMI_CONTROL,
578 HDMI_PACKET_GEN_VERSION, 1,
579 HDMI_KEEPOUT_MODE, 1,
580 HDMI_DEEP_COLOR_ENABLE, 0);
581 } else if (enc110->regs->DIG_FE_CNTL) {
582 REG_UPDATE_5(HDMI_CONTROL,
583 HDMI_PACKET_GEN_VERSION, 1,
584 HDMI_KEEPOUT_MODE, 1,
585 HDMI_DEEP_COLOR_ENABLE, 0,
586 HDMI_DATA_SCRAMBLE_EN, 0,
587 HDMI_CLOCK_CHANNEL_RATE, 0);
588 }
589
590 switch (crtc_timing->display_color_depth) {
591 case COLOR_DEPTH_888:
592 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
593 break;
594 case COLOR_DEPTH_101010:
595 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
596 REG_UPDATE_2(HDMI_CONTROL,
597 HDMI_DEEP_COLOR_DEPTH, 1,
598 HDMI_DEEP_COLOR_ENABLE, 0);
599 } else {
600 REG_UPDATE_2(HDMI_CONTROL,
601 HDMI_DEEP_COLOR_DEPTH, 1,
602 HDMI_DEEP_COLOR_ENABLE, 1);
603 }
604 break;
605 case COLOR_DEPTH_121212:
606 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
607 REG_UPDATE_2(HDMI_CONTROL,
608 HDMI_DEEP_COLOR_DEPTH, 2,
609 HDMI_DEEP_COLOR_ENABLE, 0);
610 } else {
611 REG_UPDATE_2(HDMI_CONTROL,
612 HDMI_DEEP_COLOR_DEPTH, 2,
613 HDMI_DEEP_COLOR_ENABLE, 1);
614 }
615 break;
616 case COLOR_DEPTH_161616:
617 REG_UPDATE_2(HDMI_CONTROL,
618 HDMI_DEEP_COLOR_DEPTH, 3,
619 HDMI_DEEP_COLOR_ENABLE, 1);
620 break;
621 default:
622 break;
623 }
624
625 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
626 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
627 /* enable HDMI data scrambler
628 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
629 * Clock channel frequency is 1/4 of character rate.
630 */
631 REG_UPDATE_2(HDMI_CONTROL,
632 HDMI_DATA_SCRAMBLE_EN, 1,
633 HDMI_CLOCK_CHANNEL_RATE, 1);
634 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
635
636 /* TODO: New feature for DCE11, still need to implement */
637
638 /* enable HDMI data scrambler
639 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
640 * Clock channel frequency is the same
641 * as character rate
642 */
643 REG_UPDATE_2(HDMI_CONTROL,
644 HDMI_DATA_SCRAMBLE_EN, 1,
645 HDMI_CLOCK_CHANNEL_RATE, 0);
646 }
647 }
648
649 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
650 HDMI_GC_CONT, 1,
651 HDMI_GC_SEND, 1,
652 HDMI_NULL_SEND, 1);
653
654 /* following belongs to audio */
655 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
656
657 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
658
659 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
660 VBI_LINE_0 + 2);
661
662 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
663
664 }
665
666 /* setup stream encoder in dvi mode */
667 static void dce110_stream_encoder_dvi_set_stream_attribute(
668 struct stream_encoder *enc,
669 struct dc_crtc_timing *crtc_timing,
670 bool is_dual_link)
671 {
672 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
673 struct bp_encoder_control cntl = {0};
674
675 cntl.action = ENCODER_CONTROL_SETUP;
676 cntl.engine_id = enc110->base.id;
677 cntl.signal = is_dual_link ?
678 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
679 cntl.enable_dp_audio = false;
680 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
681 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
682
683 if (enc110->base.bp->funcs->encoder_control(
684 enc110->base.bp, &cntl) != BP_RESULT_OK)
685 return;
686
687 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
688 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
689 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
690 }
691
692 /* setup stream encoder in LVDS mode */
693 static void dce110_stream_encoder_lvds_set_stream_attribute(
694 struct stream_encoder *enc,
695 struct dc_crtc_timing *crtc_timing)
696 {
697 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
698 struct bp_encoder_control cntl = {0};
699
700 cntl.action = ENCODER_CONTROL_SETUP;
701 cntl.engine_id = enc110->base.id;
702 cntl.signal = SIGNAL_TYPE_LVDS;
703 cntl.enable_dp_audio = false;
704 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
705 cntl.lanes_number = LANE_COUNT_FOUR;
706
707 if (enc110->base.bp->funcs->encoder_control(
708 enc110->base.bp, &cntl) != BP_RESULT_OK)
709 return;
710
711 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
712 }
713
714 static void dce110_stream_encoder_set_throttled_vcp_size(
715 struct stream_encoder *enc,
716 struct fixed31_32 avg_time_slots_per_mtp)
717 {
718 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
719 uint32_t x = dc_fixpt_floor(
720 avg_time_slots_per_mtp);
721 uint32_t y = dc_fixpt_ceil(
722 dc_fixpt_shl(
723 dc_fixpt_sub_int(
724 avg_time_slots_per_mtp,
725 x),
726 26));
727
728 {
729 REG_SET_2(DP_MSE_RATE_CNTL, 0,
730 DP_MSE_RATE_X, x,
731 DP_MSE_RATE_Y, y);
732 }
733
734 /* wait for update to be completed on the link */
735 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
736 /* is reset to 0 (not pending) */
737 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
738 0,
739 10, DP_MST_UPDATE_MAX_RETRY);
740 }
741
742 static void dce110_stream_encoder_update_hdmi_info_packets(
743 struct stream_encoder *enc,
744 const struct encoder_info_frame *info_frame)
745 {
746 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
747
748 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
749 enc110->se_mask->HDMI_AVI_INFO_SEND) {
750
751 if (info_frame->avi.valid) {
752 const uint32_t *content =
753 (const uint32_t *) &info_frame->avi.sb[0];
754 /*we need turn on clock before programming AFMT block*/
755 if (REG(AFMT_CNTL))
756 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
757
758 REG_WRITE(AFMT_AVI_INFO0, content[0]);
759
760 REG_WRITE(AFMT_AVI_INFO1, content[1]);
761
762 REG_WRITE(AFMT_AVI_INFO2, content[2]);
763
764 REG_WRITE(AFMT_AVI_INFO3, content[3]);
765
766 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
767 info_frame->avi.hb1);
768
769 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
770 HDMI_AVI_INFO_SEND, 1,
771 HDMI_AVI_INFO_CONT, 1);
772
773 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
774 VBI_LINE_0 + 2);
775
776 } else {
777 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
778 HDMI_AVI_INFO_SEND, 0,
779 HDMI_AVI_INFO_CONT, 0);
780 }
781 }
782
783 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
784 enc110->se_mask->HDMI_AVI_INFO_SEND) {
785 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
786 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
787 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
788 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
789 }
790
791 #if defined(CONFIG_DRM_AMD_DC_DCN)
792 if (enc110->se_mask->HDMI_DB_DISABLE) {
793 /* for bring up, disable dp double TODO */
794 if (REG(HDMI_DB_CONTROL))
795 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
796
797 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
798 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
799 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
800 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
801 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
802 }
803 #endif
804 }
805
806 static void dce110_stream_encoder_stop_hdmi_info_packets(
807 struct stream_encoder *enc)
808 {
809 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
810
811 /* stop generic packets 0 & 1 on HDMI */
812 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
813 HDMI_GENERIC1_CONT, 0,
814 HDMI_GENERIC1_LINE, 0,
815 HDMI_GENERIC1_SEND, 0,
816 HDMI_GENERIC0_CONT, 0,
817 HDMI_GENERIC0_LINE, 0,
818 HDMI_GENERIC0_SEND, 0);
819
820 /* stop generic packets 2 & 3 on HDMI */
821 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
822 HDMI_GENERIC0_CONT, 0,
823 HDMI_GENERIC0_LINE, 0,
824 HDMI_GENERIC0_SEND, 0,
825 HDMI_GENERIC1_CONT, 0,
826 HDMI_GENERIC1_LINE, 0,
827 HDMI_GENERIC1_SEND, 0);
828
829 #if defined(CONFIG_DRM_AMD_DC_DCN)
830 /* stop generic packets 2 & 3 on HDMI */
831 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
832 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
833 HDMI_GENERIC0_CONT, 0,
834 HDMI_GENERIC0_LINE, 0,
835 HDMI_GENERIC0_SEND, 0,
836 HDMI_GENERIC1_CONT, 0,
837 HDMI_GENERIC1_LINE, 0,
838 HDMI_GENERIC1_SEND, 0);
839
840 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
841 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
842 HDMI_GENERIC0_CONT, 0,
843 HDMI_GENERIC0_LINE, 0,
844 HDMI_GENERIC0_SEND, 0,
845 HDMI_GENERIC1_CONT, 0,
846 HDMI_GENERIC1_LINE, 0,
847 HDMI_GENERIC1_SEND, 0);
848 #endif
849 }
850
851 static void dce110_stream_encoder_update_dp_info_packets(
852 struct stream_encoder *enc,
853 const struct encoder_info_frame *info_frame)
854 {
855 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
856 uint32_t value = 0;
857
858 if (info_frame->vsc.valid)
859 dce110_update_generic_info_packet(
860 enc110,
861 0, /* packetIndex */
862 &info_frame->vsc);
863
864 if (info_frame->spd.valid)
865 dce110_update_generic_info_packet(
866 enc110,
867 2, /* packetIndex */
868 &info_frame->spd);
869
870 if (info_frame->hdrsmd.valid)
871 dce110_update_generic_info_packet(
872 enc110,
873 3, /* packetIndex */
874 &info_frame->hdrsmd);
875
876 /* enable/disable transmission of packet(s).
877 * If enabled, packet transmission begins on the next frame
878 */
879 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
880 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
881 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
882
883 /* This bit is the master enable bit.
884 * When enabling secondary stream engine,
885 * this master bit must also be set.
886 * This register shared with audio info frame.
887 * Therefore we need to enable master bit
888 * if at least on of the fields is not 0
889 */
890 value = REG_READ(DP_SEC_CNTL);
891 if (value)
892 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
893 }
894
895 static void dce110_stream_encoder_stop_dp_info_packets(
896 struct stream_encoder *enc)
897 {
898 /* stop generic packets on DP */
899 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
900 uint32_t value = 0;
901
902 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
903 REG_SET_7(DP_SEC_CNTL, 0,
904 DP_SEC_GSP0_ENABLE, 0,
905 DP_SEC_GSP1_ENABLE, 0,
906 DP_SEC_GSP2_ENABLE, 0,
907 DP_SEC_GSP3_ENABLE, 0,
908 DP_SEC_AVI_ENABLE, 0,
909 DP_SEC_MPG_ENABLE, 0,
910 DP_SEC_STREAM_ENABLE, 0);
911 }
912
913 /* this register shared with audio info frame.
914 * therefore we need to keep master enabled
915 * if at least one of the fields is not 0 */
916 value = REG_READ(DP_SEC_CNTL);
917 if (value)
918 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
919
920 }
921
922 static void dce110_stream_encoder_dp_blank(
923 struct stream_encoder *enc)
924 {
925 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
926 uint32_t reg1 = 0;
927 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
928
929 /* Note: For CZ, we are changing driver default to disable
930 * stream deferred to next VBLANK. If results are positive, we
931 * will make the same change to all DCE versions. There are a
932 * handful of panels that cannot handle disable stream at
933 * HBLANK and will result in a white line flash across the
934 * screen on stream disable. */
935 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
936 if ((reg1 & 0x1) == 0)
937 /*stream not enabled*/
938 return;
939 /* Specify the video stream disable point
940 * (2 = start of the next vertical blank) */
941 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
942 /* Larger delay to wait until VBLANK - use max retry of
943 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
944 * a little more because we may not trust delay accuracy.
945 */
946 max_retries = DP_BLANK_MAX_RETRY * 150;
947
948 /* disable DP stream */
949 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
950
951 /* the encoder stops sending the video stream
952 * at the start of the vertical blanking.
953 * Poll for DP_VID_STREAM_STATUS == 0
954 */
955
956 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
957 0,
958 10, max_retries);
959
960 /* Tell the DP encoder to ignore timing from CRTC, must be done after
961 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
962 * complete, stream status will be stuck in video stream enabled state,
963 * i.e. DP_VID_STREAM_STATUS stuck at 1.
964 */
965
966 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
967 }
968
969 /* output video stream to link encoder */
970 static void dce110_stream_encoder_dp_unblank(
971 struct stream_encoder *enc,
972 const struct encoder_unblank_param *param)
973 {
974 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
975
976 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
977 uint32_t n_vid = 0x8000;
978 uint32_t m_vid;
979
980 /* M / N = Fstream / Flink
981 * m_vid / n_vid = pixel rate / link rate
982 */
983
984 uint64_t m_vid_l = n_vid;
985
986 m_vid_l *= param->timing.pix_clk_100hz / 10;
987 m_vid_l = div_u64(m_vid_l,
988 param->link_settings.link_rate
989 * LINK_RATE_REF_FREQ_IN_KHZ);
990
991 m_vid = (uint32_t) m_vid_l;
992
993 /* enable auto measurement */
994
995 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
996
997 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
998 * therefore program initial value for Mvid and Nvid
999 */
1000
1001 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
1002
1003 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1004
1005 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1006 }
1007
1008 /* set DIG_START to 0x1 to resync FIFO */
1009
1010 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1011
1012 /* switch DP encoder to CRTC data */
1013
1014 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1015
1016 /* wait 100us for DIG/DP logic to prime
1017 * (i.e. a few video lines)
1018 */
1019 udelay(100);
1020
1021 /* the hardware would start sending video at the start of the next DP
1022 * frame (i.e. rising edge of the vblank).
1023 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1024 * register has no effect on enable transition! HW always guarantees
1025 * VID_STREAM enable at start of next frame, and this is not
1026 * programmable
1027 */
1028
1029 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1030 }
1031
1032 static void dce110_stream_encoder_set_avmute(
1033 struct stream_encoder *enc,
1034 bool enable)
1035 {
1036 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1037 unsigned int value = enable ? 1 : 0;
1038
1039 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1040 }
1041
1042
1043 static void dce110_reset_hdmi_stream_attribute(
1044 struct stream_encoder *enc)
1045 {
1046 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1047 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1048 REG_UPDATE_5(HDMI_CONTROL,
1049 HDMI_PACKET_GEN_VERSION, 1,
1050 HDMI_KEEPOUT_MODE, 1,
1051 HDMI_DEEP_COLOR_ENABLE, 0,
1052 HDMI_DATA_SCRAMBLE_EN, 0,
1053 HDMI_CLOCK_CHANNEL_RATE, 0);
1054 else
1055 REG_UPDATE_3(HDMI_CONTROL,
1056 HDMI_PACKET_GEN_VERSION, 1,
1057 HDMI_KEEPOUT_MODE, 1,
1058 HDMI_DEEP_COLOR_ENABLE, 0);
1059 }
1060
1061 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1062 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1063
1064 #include "include/audio_types.h"
1065
1066
1067 /* 25.2MHz/1.001*/
1068 /* 25.2MHz/1.001*/
1069 /* 25.2MHz*/
1070 /* 27MHz */
1071 /* 27MHz*1.001*/
1072 /* 27MHz*1.001*/
1073 /* 54MHz*/
1074 /* 54MHz*1.001*/
1075 /* 74.25MHz/1.001*/
1076 /* 74.25MHz*/
1077 /* 148.5MHz/1.001*/
1078 /* 148.5MHz*/
1079
1080 static const struct audio_clock_info audio_clock_info_table[16] = {
1081 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1082 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1083 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1084 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1085 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1086 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1087 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1088 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1089 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1090 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1091 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1092 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1093 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1094 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1095 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1096 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1097 };
1098
1099 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1100 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1101 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1102 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1103 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1104 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1105 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1106 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1107 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1108 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1109 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1110 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1111 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1112 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1113 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1114 };
1115
1116 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1117 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1118 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1119 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1120 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1121 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1122 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1123 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1124 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1125 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1126 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1127 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1128 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1129 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1130 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1131
1132
1133 };
1134
1135 static union audio_cea_channels speakers_to_channels(
1136 struct audio_speaker_flags speaker_flags)
1137 {
1138 union audio_cea_channels cea_channels = {0};
1139
1140 /* these are one to one */
1141 cea_channels.channels.FL = speaker_flags.FL_FR;
1142 cea_channels.channels.FR = speaker_flags.FL_FR;
1143 cea_channels.channels.LFE = speaker_flags.LFE;
1144 cea_channels.channels.FC = speaker_flags.FC;
1145
1146 /* if Rear Left and Right exist move RC speaker to channel 7
1147 * otherwise to channel 5
1148 */
1149 if (speaker_flags.RL_RR) {
1150 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1151 cea_channels.channels.RR = speaker_flags.RL_RR;
1152 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1153 } else {
1154 cea_channels.channels.RL_RC = speaker_flags.RC;
1155 }
1156
1157 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1158 if (speaker_flags.FLC_FRC) {
1159 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1160 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1161 } else {
1162 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1163 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1164 }
1165
1166 return cea_channels;
1167 }
1168
1169 static uint32_t calc_max_audio_packets_per_line(
1170 const struct audio_crtc_info *crtc_info)
1171 {
1172 uint32_t max_packets_per_line;
1173
1174 max_packets_per_line =
1175 crtc_info->h_total - crtc_info->h_active;
1176
1177 if (crtc_info->pixel_repetition)
1178 max_packets_per_line *= crtc_info->pixel_repetition;
1179
1180 /* for other hdmi features */
1181 max_packets_per_line -= 58;
1182 /* for Control Period */
1183 max_packets_per_line -= 16;
1184 /* Number of Audio Packets per Line */
1185 max_packets_per_line /= 32;
1186
1187 return max_packets_per_line;
1188 }
1189
1190 static void get_audio_clock_info(
1191 enum dc_color_depth color_depth,
1192 uint32_t crtc_pixel_clock_100Hz,
1193 uint32_t actual_pixel_clock_100Hz,
1194 struct audio_clock_info *audio_clock_info)
1195 {
1196 const struct audio_clock_info *clock_info;
1197 uint32_t index;
1198 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1199 uint32_t audio_array_size;
1200
1201 switch (color_depth) {
1202 case COLOR_DEPTH_161616:
1203 clock_info = audio_clock_info_table_48bpc;
1204 audio_array_size = ARRAY_SIZE(
1205 audio_clock_info_table_48bpc);
1206 break;
1207 case COLOR_DEPTH_121212:
1208 clock_info = audio_clock_info_table_36bpc;
1209 audio_array_size = ARRAY_SIZE(
1210 audio_clock_info_table_36bpc);
1211 break;
1212 default:
1213 clock_info = audio_clock_info_table;
1214 audio_array_size = ARRAY_SIZE(
1215 audio_clock_info_table);
1216 break;
1217 }
1218
1219 if (clock_info != NULL) {
1220 /* search for exact pixel clock in table */
1221 for (index = 0; index < audio_array_size; index++) {
1222 if (clock_info[index].pixel_clock_in_10khz >
1223 crtc_pixel_clock_in_10khz)
1224 break; /* not match */
1225 else if (clock_info[index].pixel_clock_in_10khz ==
1226 crtc_pixel_clock_in_10khz) {
1227 /* match found */
1228 *audio_clock_info = clock_info[index];
1229 return;
1230 }
1231 }
1232 }
1233
1234 /* not found */
1235 if (actual_pixel_clock_100Hz == 0)
1236 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1237
1238 /* See HDMI spec the table entry under
1239 * pixel clock of "Other". */
1240 audio_clock_info->pixel_clock_in_10khz =
1241 actual_pixel_clock_100Hz / 100;
1242 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1243 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1244 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1245
1246 audio_clock_info->n_32khz = 4096;
1247 audio_clock_info->n_44khz = 6272;
1248 audio_clock_info->n_48khz = 6144;
1249 }
1250
1251 static void dce110_se_audio_setup(
1252 struct stream_encoder *enc,
1253 unsigned int az_inst,
1254 struct audio_info *audio_info)
1255 {
1256 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1257
1258 uint32_t channels = 0;
1259
1260 ASSERT(audio_info);
1261 if (audio_info == NULL)
1262 /* This should not happen.it does so we don't get BSOD*/
1263 return;
1264
1265 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1266
1267 /* setup the audio stream source select (audio -> dig mapping) */
1268 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1269
1270 /* Channel allocation */
1271 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1272 }
1273
1274 static void dce110_se_setup_hdmi_audio(
1275 struct stream_encoder *enc,
1276 const struct audio_crtc_info *crtc_info)
1277 {
1278 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1279
1280 struct audio_clock_info audio_clock_info = {0};
1281 uint32_t max_packets_per_line;
1282
1283 /* For now still do calculation, although this field is ignored when
1284 above HDMI_PACKET_GEN_VERSION set to 1 */
1285 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1286
1287 /* HDMI_AUDIO_PACKET_CONTROL */
1288 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1289 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1290 HDMI_AUDIO_DELAY_EN, 1);
1291
1292 /* AFMT_AUDIO_PACKET_CONTROL */
1293 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1294
1295 /* AFMT_AUDIO_PACKET_CONTROL2 */
1296 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1297 AFMT_AUDIO_LAYOUT_OVRD, 0,
1298 AFMT_60958_OSF_OVRD, 0);
1299
1300 /* HDMI_ACR_PACKET_CONTROL */
1301 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1302 HDMI_ACR_AUTO_SEND, 1,
1303 HDMI_ACR_SOURCE, 0,
1304 HDMI_ACR_AUDIO_PRIORITY, 0);
1305
1306 /* Program audio clock sample/regeneration parameters */
1307 get_audio_clock_info(crtc_info->color_depth,
1308 crtc_info->requested_pixel_clock_100Hz,
1309 crtc_info->calculated_pixel_clock_100Hz,
1310 &audio_clock_info);
1311 DC_LOG_HW_AUDIO(
1312 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1313 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1314 crtc_info->requested_pixel_clock_100Hz, \
1315 crtc_info->calculated_pixel_clock_100Hz);
1316
1317 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1318 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1319
1320 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1321 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1322
1323 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1324 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1325
1326 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1327 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1328
1329 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1330 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1331
1332 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1333 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1334
1335 /* Video driver cannot know in advance which sample rate will
1336 be used by HD Audio driver
1337 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1338 programmed below in interruppt callback */
1339
1340 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1341 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1342 REG_UPDATE_2(AFMT_60958_0,
1343 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1344 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1345
1346 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1347 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1348
1349 /*AFMT_60958_2 now keep this settings until
1350 * Programming guide comes out*/
1351 REG_UPDATE_6(AFMT_60958_2,
1352 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1353 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1354 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1355 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1356 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1357 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1358 }
1359
1360 static void dce110_se_setup_dp_audio(
1361 struct stream_encoder *enc)
1362 {
1363 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1364
1365 /* --- DP Audio packet configurations --- */
1366
1367 /* ATP Configuration */
1368 REG_SET(DP_SEC_AUD_N, 0,
1369 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1370
1371 /* Async/auto-calc timestamp mode */
1372 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1373 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1374
1375 /* --- The following are the registers
1376 * copied from the SetupHDMI --- */
1377
1378 /* AFMT_AUDIO_PACKET_CONTROL */
1379 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1380
1381 /* AFMT_AUDIO_PACKET_CONTROL2 */
1382 /* Program the ATP and AIP next */
1383 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1384 AFMT_AUDIO_LAYOUT_OVRD, 0,
1385 AFMT_60958_OSF_OVRD, 0);
1386
1387 /* AFMT_INFOFRAME_CONTROL0 */
1388 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1389
1390 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1391 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1392 }
1393
1394 static void dce110_se_enable_audio_clock(
1395 struct stream_encoder *enc,
1396 bool enable)
1397 {
1398 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1399
1400 if (REG(AFMT_CNTL) == 0)
1401 return; /* DCE8/10 does not have this register */
1402
1403 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1404
1405 /* wait for AFMT clock to turn on,
1406 * expectation: this should complete in 1-2 reads
1407 *
1408 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1409 *
1410 * TODO: wait for clock_on does not work well. May need HW
1411 * program sequence. But audio seems work normally even without wait
1412 * for clock_on status change
1413 */
1414 }
1415
1416 static void dce110_se_enable_dp_audio(
1417 struct stream_encoder *enc)
1418 {
1419 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1420
1421 /* Enable Audio packets */
1422 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1423
1424 /* Program the ATP and AIP next */
1425 REG_UPDATE_2(DP_SEC_CNTL,
1426 DP_SEC_ATP_ENABLE, 1,
1427 DP_SEC_AIP_ENABLE, 1);
1428
1429 /* Program STREAM_ENABLE after all the other enables. */
1430 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1431 }
1432
1433 static void dce110_se_disable_dp_audio(
1434 struct stream_encoder *enc)
1435 {
1436 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1437 uint32_t value = 0;
1438
1439 /* Disable Audio packets */
1440 REG_UPDATE_5(DP_SEC_CNTL,
1441 DP_SEC_ASP_ENABLE, 0,
1442 DP_SEC_ATP_ENABLE, 0,
1443 DP_SEC_AIP_ENABLE, 0,
1444 DP_SEC_ACM_ENABLE, 0,
1445 DP_SEC_STREAM_ENABLE, 0);
1446
1447 /* This register shared with encoder info frame. Therefore we need to
1448 keep master enabled if at least on of the fields is not 0 */
1449 value = REG_READ(DP_SEC_CNTL);
1450 if (value != 0)
1451 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1452
1453 }
1454
1455 void dce110_se_audio_mute_control(
1456 struct stream_encoder *enc,
1457 bool mute)
1458 {
1459 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1460
1461 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1462 }
1463
1464 void dce110_se_dp_audio_setup(
1465 struct stream_encoder *enc,
1466 unsigned int az_inst,
1467 struct audio_info *info)
1468 {
1469 dce110_se_audio_setup(enc, az_inst, info);
1470 }
1471
1472 void dce110_se_dp_audio_enable(
1473 struct stream_encoder *enc)
1474 {
1475 dce110_se_enable_audio_clock(enc, true);
1476 dce110_se_setup_dp_audio(enc);
1477 dce110_se_enable_dp_audio(enc);
1478 }
1479
1480 void dce110_se_dp_audio_disable(
1481 struct stream_encoder *enc)
1482 {
1483 dce110_se_disable_dp_audio(enc);
1484 dce110_se_enable_audio_clock(enc, false);
1485 }
1486
1487 void dce110_se_hdmi_audio_setup(
1488 struct stream_encoder *enc,
1489 unsigned int az_inst,
1490 struct audio_info *info,
1491 struct audio_crtc_info *audio_crtc_info)
1492 {
1493 dce110_se_enable_audio_clock(enc, true);
1494 dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1495 dce110_se_audio_setup(enc, az_inst, info);
1496 }
1497
1498 void dce110_se_hdmi_audio_disable(
1499 struct stream_encoder *enc)
1500 {
1501 dce110_se_enable_audio_clock(enc, false);
1502 }
1503
1504
1505 static void setup_stereo_sync(
1506 struct stream_encoder *enc,
1507 int tg_inst, bool enable)
1508 {
1509 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1510 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1511 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1512 }
1513
1514 static void dig_connect_to_otg(
1515 struct stream_encoder *enc,
1516 int tg_inst)
1517 {
1518 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1519
1520 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1521 }
1522
1523 static unsigned int dig_source_otg(
1524 struct stream_encoder *enc)
1525 {
1526 uint32_t tg_inst = 0;
1527 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1528
1529 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1530
1531 return tg_inst;
1532 }
1533
1534 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1535 .dp_set_stream_attribute =
1536 dce110_stream_encoder_dp_set_stream_attribute,
1537 .hdmi_set_stream_attribute =
1538 dce110_stream_encoder_hdmi_set_stream_attribute,
1539 .dvi_set_stream_attribute =
1540 dce110_stream_encoder_dvi_set_stream_attribute,
1541 .lvds_set_stream_attribute =
1542 dce110_stream_encoder_lvds_set_stream_attribute,
1543 .set_throttled_vcp_size =
1544 dce110_stream_encoder_set_throttled_vcp_size,
1545 .update_hdmi_info_packets =
1546 dce110_stream_encoder_update_hdmi_info_packets,
1547 .stop_hdmi_info_packets =
1548 dce110_stream_encoder_stop_hdmi_info_packets,
1549 .update_dp_info_packets =
1550 dce110_stream_encoder_update_dp_info_packets,
1551 .stop_dp_info_packets =
1552 dce110_stream_encoder_stop_dp_info_packets,
1553 .dp_blank =
1554 dce110_stream_encoder_dp_blank,
1555 .dp_unblank =
1556 dce110_stream_encoder_dp_unblank,
1557 .audio_mute_control = dce110_se_audio_mute_control,
1558
1559 .dp_audio_setup = dce110_se_dp_audio_setup,
1560 .dp_audio_enable = dce110_se_dp_audio_enable,
1561 .dp_audio_disable = dce110_se_dp_audio_disable,
1562
1563 .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1564 .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1565 .setup_stereo_sync = setup_stereo_sync,
1566 .set_avmute = dce110_stream_encoder_set_avmute,
1567 .dig_connect_to_otg = dig_connect_to_otg,
1568 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1569 .dig_source_otg = dig_source_otg,
1570 };
1571
1572 void dce110_stream_encoder_construct(
1573 struct dce110_stream_encoder *enc110,
1574 struct dc_context *ctx,
1575 struct dc_bios *bp,
1576 enum engine_id eng_id,
1577 const struct dce110_stream_enc_registers *regs,
1578 const struct dce_stream_encoder_shift *se_shift,
1579 const struct dce_stream_encoder_mask *se_mask)
1580 {
1581 enc110->base.funcs = &dce110_str_enc_funcs;
1582 enc110->base.ctx = ctx;
1583 enc110->base.id = eng_id;
1584 enc110->base.bp = bp;
1585 enc110->regs = regs;
1586 enc110->se_shift = se_shift;
1587 enc110->se_mask = se_mask;
1588 }
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