2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dc_bios_types.h"
27 #include "dce_stream_encoder.h"
28 #include "reg_helper.h"
30 enum DP_PIXEL_ENCODING
{
31 DP_PIXEL_ENCODING_RGB444
= 0x00000000,
32 DP_PIXEL_ENCODING_YCBCR422
= 0x00000001,
33 DP_PIXEL_ENCODING_YCBCR444
= 0x00000002,
34 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT
= 0x00000003,
35 DP_PIXEL_ENCODING_Y_ONLY
= 0x00000004,
36 DP_PIXEL_ENCODING_YCBCR420
= 0x00000005,
37 DP_PIXEL_ENCODING_RESERVED
= 0x00000006,
41 enum DP_COMPONENT_DEPTH
{
42 DP_COMPONENT_DEPTH_6BPC
= 0x00000000,
43 DP_COMPONENT_DEPTH_8BPC
= 0x00000001,
44 DP_COMPONENT_DEPTH_10BPC
= 0x00000002,
45 DP_COMPONENT_DEPTH_12BPC
= 0x00000003,
46 DP_COMPONENT_DEPTH_16BPC
= 0x00000004,
47 DP_COMPONENT_DEPTH_RESERVED
= 0x00000005,
55 #define FN(reg_name, field_name) \
56 enc110->se_shift->field_name, enc110->se_mask->field_name
59 #define DP_BLANK_MAX_RETRY 20
60 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
62 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
63 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
64 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
65 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
66 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
70 DP_MST_UPDATE_MAX_RETRY
= 50
73 #define DCE110_SE(audio)\
74 container_of(audio, struct dce110_stream_encoder, base)
79 static void dce110_update_generic_info_packet(
80 struct dce110_stream_encoder
*enc110
,
81 uint32_t packet_index
,
82 const struct encoder_info_packet
*info_packet
)
85 /* TODOFPGA Figure out a proper number for max_retries polling for lock
88 uint32_t max_retries
= 50;
90 if (REG(AFMT_VBI_PACKET_CONTROL1
)) {
91 if (packet_index
>= 8)
94 /* poll dig_update_lock is not locked -> asic internal signal
95 * assume otg master lock will unlock it
97 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
98 0, 10, max_retries);*/
100 /* check if HW reading GSP memory */
101 REG_WAIT(AFMT_VBI_PACKET_CONTROL
, AFMT_GENERIC_CONFLICT
,
104 /* HW does is not reading GSP memory not reading too long ->
105 * something wrong. clear GPS memory access and notify?
106 * hw SW is writing to GSP memory
108 REG_UPDATE(AFMT_VBI_PACKET_CONTROL
, AFMT_GENERIC_CONFLICT_CLR
, 1);
110 /* choose which generic packet to use */
112 regval
= REG_READ(AFMT_VBI_PACKET_CONTROL
);
113 REG_UPDATE(AFMT_VBI_PACKET_CONTROL
,
114 AFMT_GENERIC_INDEX
, packet_index
);
117 /* write generic packet header
118 * (4th byte is for GENERIC0 only) */
120 REG_SET_4(AFMT_GENERIC_HDR
, 0,
121 AFMT_GENERIC_HB0
, info_packet
->hb0
,
122 AFMT_GENERIC_HB1
, info_packet
->hb1
,
123 AFMT_GENERIC_HB2
, info_packet
->hb2
,
124 AFMT_GENERIC_HB3
, info_packet
->hb3
);
127 /* write generic packet contents
128 * (we never use last 4 bytes)
129 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
131 const uint32_t *content
=
132 (const uint32_t *) &info_packet
->sb
[0];
134 REG_WRITE(AFMT_GENERIC_0
, *content
++);
135 REG_WRITE(AFMT_GENERIC_1
, *content
++);
136 REG_WRITE(AFMT_GENERIC_2
, *content
++);
137 REG_WRITE(AFMT_GENERIC_3
, *content
++);
138 REG_WRITE(AFMT_GENERIC_4
, *content
++);
139 REG_WRITE(AFMT_GENERIC_5
, *content
++);
140 REG_WRITE(AFMT_GENERIC_6
, *content
++);
141 REG_WRITE(AFMT_GENERIC_7
, *content
);
144 if (!REG(AFMT_VBI_PACKET_CONTROL1
)) {
145 /* force double-buffered packet update */
146 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL
,
147 AFMT_GENERIC0_UPDATE
, (packet_index
== 0),
148 AFMT_GENERIC2_UPDATE
, (packet_index
== 2));
150 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
151 if (REG(AFMT_VBI_PACKET_CONTROL1
)) {
152 switch (packet_index
) {
154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
155 AFMT_GENERIC0_FRAME_UPDATE
, 1);
158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
159 AFMT_GENERIC1_FRAME_UPDATE
, 1);
162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
163 AFMT_GENERIC2_FRAME_UPDATE
, 1);
166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
167 AFMT_GENERIC3_FRAME_UPDATE
, 1);
170 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
171 AFMT_GENERIC4_FRAME_UPDATE
, 1);
174 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
175 AFMT_GENERIC5_FRAME_UPDATE
, 1);
178 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
179 AFMT_GENERIC6_FRAME_UPDATE
, 1);
182 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1
,
183 AFMT_GENERIC7_FRAME_UPDATE
, 1);
192 static void dce110_update_hdmi_info_packet(
193 struct dce110_stream_encoder
*enc110
,
194 uint32_t packet_index
,
195 const struct encoder_info_packet
*info_packet
)
197 struct dc_context
*ctx
= enc110
->base
.ctx
;
198 uint32_t cont
, send
, line
;
200 if (info_packet
->valid
) {
201 dce110_update_generic_info_packet(
206 /* enable transmission of packet(s) -
207 * packet transmission begins on the next frame */
209 /* send packet(s) every frame */
211 /* select line number to send packets on */
219 /* choose which generic packet control to use */
220 switch (packet_index
) {
222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0
,
223 HDMI_GENERIC0_CONT
, cont
,
224 HDMI_GENERIC0_SEND
, send
,
225 HDMI_GENERIC0_LINE
, line
);
228 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0
,
229 HDMI_GENERIC1_CONT
, cont
,
230 HDMI_GENERIC1_SEND
, send
,
231 HDMI_GENERIC1_LINE
, line
);
234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1
,
235 HDMI_GENERIC0_CONT
, cont
,
236 HDMI_GENERIC0_SEND
, send
,
237 HDMI_GENERIC0_LINE
, line
);
240 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1
,
241 HDMI_GENERIC1_CONT
, cont
,
242 HDMI_GENERIC1_SEND
, send
,
243 HDMI_GENERIC1_LINE
, line
);
245 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
247 if (REG(HDMI_GENERIC_PACKET_CONTROL2
))
248 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2
,
249 HDMI_GENERIC0_CONT
, cont
,
250 HDMI_GENERIC0_SEND
, send
,
251 HDMI_GENERIC0_LINE
, line
);
254 if (REG(HDMI_GENERIC_PACKET_CONTROL2
))
255 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2
,
256 HDMI_GENERIC1_CONT
, cont
,
257 HDMI_GENERIC1_SEND
, send
,
258 HDMI_GENERIC1_LINE
, line
);
261 if (REG(HDMI_GENERIC_PACKET_CONTROL3
))
262 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3
,
263 HDMI_GENERIC0_CONT
, cont
,
264 HDMI_GENERIC0_SEND
, send
,
265 HDMI_GENERIC0_LINE
, line
);
268 if (REG(HDMI_GENERIC_PACKET_CONTROL3
))
269 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3
,
270 HDMI_GENERIC1_CONT
, cont
,
271 HDMI_GENERIC1_SEND
, send
,
272 HDMI_GENERIC1_LINE
, line
);
276 /* invalid HW packet index */
278 ctx
->logger
, LOG_WARNING
,
279 "Invalid HW packet index: %s()\n",
285 /* setup stream encoder in dp mode */
286 static void dce110_stream_encoder_dp_set_stream_attribute(
287 struct stream_encoder
*enc
,
288 struct dc_crtc_timing
*crtc_timing
,
289 enum dc_color_space output_color_space
)
291 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
292 uint32_t h_active_start
;
293 uint32_t v_active_start
;
297 uint32_t h_back_porch
;
298 uint8_t synchronous_clock
= 0; /* asynchronous mode */
299 uint8_t colorimetry_bpc
;
302 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
304 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
306 REG_UPDATE(DP_DB_CNTL
, DP_DB_DISABLE
, 1);
309 /* set pixel encoding */
310 switch (crtc_timing
->pixel_encoding
) {
311 case PIXEL_ENCODING_YCBCR422
:
312 REG_UPDATE(DP_PIXEL_FORMAT
, DP_PIXEL_ENCODING
,
313 DP_PIXEL_ENCODING_YCBCR422
);
315 case PIXEL_ENCODING_YCBCR444
:
316 REG_UPDATE(DP_PIXEL_FORMAT
, DP_PIXEL_ENCODING
,
317 DP_PIXEL_ENCODING_YCBCR444
);
319 if (crtc_timing
->flags
.Y_ONLY
)
320 if (crtc_timing
->display_color_depth
!= COLOR_DEPTH_666
)
321 /* HW testing only, no use case yet.
322 * Color depth of Y-only could be
323 * 8, 10, 12, 16 bits */
324 REG_UPDATE(DP_PIXEL_FORMAT
, DP_PIXEL_ENCODING
,
325 DP_PIXEL_ENCODING_Y_ONLY
);
326 /* Note: DP_MSA_MISC1 bit 7 is the indicator
328 * This bit is set in HW if register
329 * DP_PIXEL_ENCODING is programmed to 0x4 */
331 case PIXEL_ENCODING_YCBCR420
:
332 REG_UPDATE(DP_PIXEL_FORMAT
, DP_PIXEL_ENCODING
,
333 DP_PIXEL_ENCODING_YCBCR420
);
334 if (enc110
->se_mask
->DP_VID_M_DOUBLE_VALUE_EN
)
335 REG_UPDATE(DP_VID_TIMING
, DP_VID_M_DOUBLE_VALUE_EN
, 1);
337 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
338 if (enc110
->se_mask
->DP_VID_N_MUL
)
339 REG_UPDATE(DP_VID_TIMING
, DP_VID_N_MUL
, 1);
343 REG_UPDATE(DP_PIXEL_FORMAT
, DP_PIXEL_ENCODING
,
344 DP_PIXEL_ENCODING_RGB444
);
348 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
349 if (REG(DP_MSA_MISC
))
350 misc1
= REG_READ(DP_MSA_MISC
);
353 /* set color depth */
355 switch (crtc_timing
->display_color_depth
) {
356 case COLOR_DEPTH_666
:
357 REG_UPDATE(DP_PIXEL_FORMAT
, DP_COMPONENT_DEPTH
,
360 case COLOR_DEPTH_888
:
361 REG_UPDATE(DP_PIXEL_FORMAT
, DP_COMPONENT_DEPTH
,
362 DP_COMPONENT_DEPTH_8BPC
);
364 case COLOR_DEPTH_101010
:
365 REG_UPDATE(DP_PIXEL_FORMAT
, DP_COMPONENT_DEPTH
,
366 DP_COMPONENT_DEPTH_10BPC
);
369 case COLOR_DEPTH_121212
:
370 REG_UPDATE(DP_PIXEL_FORMAT
, DP_COMPONENT_DEPTH
,
371 DP_COMPONENT_DEPTH_12BPC
);
374 REG_UPDATE(DP_PIXEL_FORMAT
, DP_COMPONENT_DEPTH
,
375 DP_COMPONENT_DEPTH_6BPC
);
379 /* set dynamic range and YCbCr range */
380 if (enc110
->se_mask
->DP_DYN_RANGE
&& enc110
->se_mask
->DP_YCBCR_RANGE
)
386 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
387 switch (crtc_timing
->display_color_depth
) {
388 case COLOR_DEPTH_666
:
391 case COLOR_DEPTH_888
:
394 case COLOR_DEPTH_101010
:
397 case COLOR_DEPTH_121212
:
405 misc0
= misc0
| synchronous_clock
;
406 misc0
= colorimetry_bpc
<< 5;
408 if (REG(DP_MSA_TIMING_PARAM1
)) {
409 switch (output_color_space
) {
410 case COLOR_SPACE_SRGB
:
412 misc1
= misc1
& ~0x80; /* bit7 = 0*/
414 case COLOR_SPACE_SRGB_LIMITED
:
415 misc0
= misc0
| 0x8; /* bit3=1 */
416 misc1
= misc1
& ~0x80; /* bit7 = 0*/
418 case COLOR_SPACE_YCBCR601
:
419 misc0
= misc0
| 0x8; /* bit3=1, bit4=0 */
420 misc1
= misc1
& ~0x80; /* bit7 = 0*/
421 if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR422
)
422 misc0
= misc0
| 0x2; /* bit2=0, bit1=1 */
423 else if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR444
)
424 misc0
= misc0
| 0x4; /* bit2=1, bit1=0 */
426 case COLOR_SPACE_YCBCR709
:
427 misc0
= misc0
| 0x18; /* bit3=1, bit4=1 */
428 misc1
= misc1
& ~0x80; /* bit7 = 0*/
429 if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR422
)
430 misc0
= misc0
| 0x2; /* bit2=0, bit1=1 */
431 else if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR444
)
432 misc0
= misc0
| 0x4; /* bit2=1, bit1=0 */
434 case COLOR_SPACE_2020_RGB_FULLRANGE
:
435 case COLOR_SPACE_2020_RGB_LIMITEDRANGE
:
436 case COLOR_SPACE_2020_YCBCR
:
437 case COLOR_SPACE_ADOBERGB
:
438 case COLOR_SPACE_UNKNOWN
:
439 case COLOR_SPACE_YCBCR601_LIMITED
:
440 case COLOR_SPACE_YCBCR709_LIMITED
:
445 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
446 if (REG(DP_MSA_COLORIMETRY
))
447 REG_SET(DP_MSA_COLORIMETRY
, 0, DP_MSA_MISC0
, misc0
);
449 if (REG(DP_MSA_MISC
))
450 REG_WRITE(DP_MSA_MISC
, misc1
); /* MSA_MISC1 */
453 * dc_crtc_timing is vesa dmt struct. data from edid
455 if (REG(DP_MSA_TIMING_PARAM1
))
456 REG_SET_2(DP_MSA_TIMING_PARAM1
, 0,
457 DP_MSA_HTOTAL
, crtc_timing
->h_total
,
458 DP_MSA_VTOTAL
, crtc_timing
->v_total
);
461 /* calcuate from vesa timing parameters
462 * h_active_start related to leading edge of sync
465 h_blank
= crtc_timing
->h_total
- crtc_timing
->h_border_left
-
466 crtc_timing
->h_addressable
- crtc_timing
->h_border_right
;
468 h_back_porch
= h_blank
- crtc_timing
->h_front_porch
-
469 crtc_timing
->h_sync_width
;
471 /* start at begining of left border */
472 h_active_start
= crtc_timing
->h_sync_width
+ h_back_porch
;
475 v_active_start
= crtc_timing
->v_total
- crtc_timing
->v_border_top
-
476 crtc_timing
->v_addressable
- crtc_timing
->v_border_bottom
-
477 crtc_timing
->v_front_porch
;
480 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
481 /* start at begining of left border */
482 if (REG(DP_MSA_TIMING_PARAM2
))
483 REG_SET_2(DP_MSA_TIMING_PARAM2
, 0,
484 DP_MSA_HSTART
, h_active_start
,
485 DP_MSA_VSTART
, v_active_start
);
487 if (REG(DP_MSA_TIMING_PARAM3
))
488 REG_SET_4(DP_MSA_TIMING_PARAM3
, 0,
490 crtc_timing
->h_sync_width
,
491 DP_MSA_HSYNCPOLARITY
,
492 !crtc_timing
->flags
.HSYNC_POSITIVE_POLARITY
,
494 crtc_timing
->v_sync_width
,
495 DP_MSA_VSYNCPOLARITY
,
496 !crtc_timing
->flags
.VSYNC_POSITIVE_POLARITY
);
498 /* HWDITH include border or overscan */
499 if (REG(DP_MSA_TIMING_PARAM4
))
500 REG_SET_2(DP_MSA_TIMING_PARAM4
, 0,
501 DP_MSA_HWIDTH
, crtc_timing
->h_border_left
+
502 crtc_timing
->h_addressable
+ crtc_timing
->h_border_right
,
503 DP_MSA_VHEIGHT
, crtc_timing
->v_border_top
+
504 crtc_timing
->v_addressable
+ crtc_timing
->v_border_bottom
);
510 static void dce110_stream_encoder_set_stream_attribute_helper(
511 struct dce110_stream_encoder
*enc110
,
512 struct dc_crtc_timing
*crtc_timing
)
514 if (enc110
->regs
->TMDS_CNTL
) {
515 switch (crtc_timing
->pixel_encoding
) {
516 case PIXEL_ENCODING_YCBCR422
:
517 REG_UPDATE(TMDS_CNTL
, TMDS_PIXEL_ENCODING
, 1);
520 REG_UPDATE(TMDS_CNTL
, TMDS_PIXEL_ENCODING
, 0);
523 REG_UPDATE(TMDS_CNTL
, TMDS_COLOR_FORMAT
, 0);
524 } else if (enc110
->regs
->DIG_FE_CNTL
) {
525 switch (crtc_timing
->pixel_encoding
) {
526 case PIXEL_ENCODING_YCBCR422
:
527 REG_UPDATE(DIG_FE_CNTL
, TMDS_PIXEL_ENCODING
, 1);
530 REG_UPDATE(DIG_FE_CNTL
, TMDS_PIXEL_ENCODING
, 0);
533 REG_UPDATE(DIG_FE_CNTL
, TMDS_COLOR_FORMAT
, 0);
538 /* setup stream encoder in hdmi mode */
539 static void dce110_stream_encoder_hdmi_set_stream_attribute(
540 struct stream_encoder
*enc
,
541 struct dc_crtc_timing
*crtc_timing
,
542 int actual_pix_clk_khz
,
545 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
546 struct bp_encoder_control cntl
= {0};
548 cntl
.action
= ENCODER_CONTROL_SETUP
;
549 cntl
.engine_id
= enc110
->base
.id
;
550 cntl
.signal
= SIGNAL_TYPE_HDMI_TYPE_A
;
551 cntl
.enable_dp_audio
= enable_audio
;
552 cntl
.pixel_clock
= actual_pix_clk_khz
;
553 cntl
.lanes_number
= LANE_COUNT_FOUR
;
555 if (enc110
->base
.bp
->funcs
->encoder_control(
556 enc110
->base
.bp
, &cntl
) != BP_RESULT_OK
)
559 dce110_stream_encoder_set_stream_attribute_helper(enc110
, crtc_timing
);
561 /* setup HDMI engine */
562 if (!enc110
->se_mask
->HDMI_DATA_SCRAMBLE_EN
) {
563 REG_UPDATE_3(HDMI_CONTROL
,
564 HDMI_PACKET_GEN_VERSION
, 1,
565 HDMI_KEEPOUT_MODE
, 1,
566 HDMI_DEEP_COLOR_ENABLE
, 0);
567 } else if (enc110
->regs
->DIG_FE_CNTL
) {
568 REG_UPDATE_5(HDMI_CONTROL
,
569 HDMI_PACKET_GEN_VERSION
, 1,
570 HDMI_KEEPOUT_MODE
, 1,
571 HDMI_DEEP_COLOR_ENABLE
, 0,
572 HDMI_DATA_SCRAMBLE_EN
, 0,
573 HDMI_CLOCK_CHANNEL_RATE
, 0);
576 switch (crtc_timing
->display_color_depth
) {
577 case COLOR_DEPTH_888
:
578 REG_UPDATE(HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
580 case COLOR_DEPTH_101010
:
581 if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR422
) {
582 REG_UPDATE_2(HDMI_CONTROL
,
583 HDMI_DEEP_COLOR_DEPTH
, 1,
584 HDMI_DEEP_COLOR_ENABLE
, 0);
586 REG_UPDATE_2(HDMI_CONTROL
,
587 HDMI_DEEP_COLOR_DEPTH
, 1,
588 HDMI_DEEP_COLOR_ENABLE
, 1);
591 case COLOR_DEPTH_121212
:
592 if (crtc_timing
->pixel_encoding
== PIXEL_ENCODING_YCBCR422
) {
593 REG_UPDATE_2(HDMI_CONTROL
,
594 HDMI_DEEP_COLOR_DEPTH
, 2,
595 HDMI_DEEP_COLOR_ENABLE
, 0);
597 REG_UPDATE_2(HDMI_CONTROL
,
598 HDMI_DEEP_COLOR_DEPTH
, 2,
599 HDMI_DEEP_COLOR_ENABLE
, 1);
602 case COLOR_DEPTH_161616
:
603 REG_UPDATE_2(HDMI_CONTROL
,
604 HDMI_DEEP_COLOR_DEPTH
, 3,
605 HDMI_DEEP_COLOR_ENABLE
, 1);
611 if (enc110
->se_mask
->HDMI_DATA_SCRAMBLE_EN
) {
612 if (actual_pix_clk_khz
>= HDMI_CLOCK_CHANNEL_RATE_MORE_340M
) {
613 /* enable HDMI data scrambler
614 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
615 * Clock channel frequency is 1/4 of character rate.
617 REG_UPDATE_2(HDMI_CONTROL
,
618 HDMI_DATA_SCRAMBLE_EN
, 1,
619 HDMI_CLOCK_CHANNEL_RATE
, 1);
620 } else if (crtc_timing
->flags
.LTE_340MCSC_SCRAMBLE
) {
622 /* TODO: New feature for DCE11, still need to implement */
624 /* enable HDMI data scrambler
625 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
626 * Clock channel frequency is the same
629 REG_UPDATE_2(HDMI_CONTROL
,
630 HDMI_DATA_SCRAMBLE_EN
, 1,
631 HDMI_CLOCK_CHANNEL_RATE
, 0);
635 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL
,
640 /* following belongs to audio */
641 REG_UPDATE(HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
643 REG_UPDATE(AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
645 REG_UPDATE(HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
,
648 REG_UPDATE(HDMI_GC
, HDMI_GC_AVMUTE
, 0);
652 /* setup stream encoder in dvi mode */
653 static void dce110_stream_encoder_dvi_set_stream_attribute(
654 struct stream_encoder
*enc
,
655 struct dc_crtc_timing
*crtc_timing
,
658 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
659 struct bp_encoder_control cntl
= {0};
661 cntl
.action
= ENCODER_CONTROL_SETUP
;
662 cntl
.engine_id
= enc110
->base
.id
;
663 cntl
.signal
= is_dual_link
?
664 SIGNAL_TYPE_DVI_DUAL_LINK
: SIGNAL_TYPE_DVI_SINGLE_LINK
;
665 cntl
.enable_dp_audio
= false;
666 cntl
.pixel_clock
= crtc_timing
->pix_clk_khz
;
667 cntl
.lanes_number
= (is_dual_link
) ? LANE_COUNT_EIGHT
: LANE_COUNT_FOUR
;
669 if (enc110
->base
.bp
->funcs
->encoder_control(
670 enc110
->base
.bp
, &cntl
) != BP_RESULT_OK
)
673 ASSERT(crtc_timing
->pixel_encoding
== PIXEL_ENCODING_RGB
);
674 ASSERT(crtc_timing
->display_color_depth
== COLOR_DEPTH_888
);
675 dce110_stream_encoder_set_stream_attribute_helper(enc110
, crtc_timing
);
678 static void dce110_stream_encoder_set_mst_bandwidth(
679 struct stream_encoder
*enc
,
680 struct fixed31_32 avg_time_slots_per_mtp
)
682 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
683 uint32_t x
= dal_fixed31_32_floor(
684 avg_time_slots_per_mtp
);
685 uint32_t y
= dal_fixed31_32_ceil(
687 dal_fixed31_32_sub_int(
688 avg_time_slots_per_mtp
,
693 REG_SET_2(DP_MSE_RATE_CNTL
, 0,
698 /* wait for update to be completed on the link */
699 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
700 /* is reset to 0 (not pending) */
701 REG_WAIT(DP_MSE_RATE_UPDATE
, DP_MSE_RATE_UPDATE_PENDING
,
703 10, DP_MST_UPDATE_MAX_RETRY
);
706 static void dce110_stream_encoder_update_hdmi_info_packets(
707 struct stream_encoder
*enc
,
708 const struct encoder_info_frame
*info_frame
)
710 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
712 if (enc110
->se_mask
->HDMI_AVI_INFO_CONT
&&
713 enc110
->se_mask
->HDMI_AVI_INFO_SEND
) {
715 if (info_frame
->avi
.valid
) {
716 const uint32_t *content
=
717 (const uint32_t *) &info_frame
->avi
.sb
[0];
719 REG_WRITE(AFMT_AVI_INFO0
, content
[0]);
721 REG_WRITE(AFMT_AVI_INFO1
, content
[1]);
723 REG_WRITE(AFMT_AVI_INFO2
, content
[2]);
725 REG_WRITE(AFMT_AVI_INFO3
, content
[3]);
727 REG_UPDATE(AFMT_AVI_INFO3
, AFMT_AVI_INFO_VERSION
,
728 info_frame
->avi
.hb1
);
730 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0
,
731 HDMI_AVI_INFO_SEND
, 1,
732 HDMI_AVI_INFO_CONT
, 1);
734 REG_UPDATE(HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
,
738 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0
,
739 HDMI_AVI_INFO_SEND
, 0,
740 HDMI_AVI_INFO_CONT
, 0);
744 if (enc110
->se_mask
->HDMI_AVI_INFO_CONT
&&
745 enc110
->se_mask
->HDMI_AVI_INFO_SEND
) {
746 dce110_update_hdmi_info_packet(enc110
, 0, &info_frame
->vendor
);
747 dce110_update_hdmi_info_packet(enc110
, 1, &info_frame
->gamut
);
748 dce110_update_hdmi_info_packet(enc110
, 2, &info_frame
->spd
);
749 dce110_update_hdmi_info_packet(enc110
, 3, &info_frame
->hdrsmd
);
752 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
753 if (enc110
->se_mask
->HDMI_DB_DISABLE
) {
754 /* for bring up, disable dp double TODO */
755 if (REG(HDMI_DB_CONTROL
))
756 REG_UPDATE(HDMI_DB_CONTROL
, HDMI_DB_DISABLE
, 1);
758 dce110_update_hdmi_info_packet(enc110
, 0, &info_frame
->avi
);
759 dce110_update_hdmi_info_packet(enc110
, 1, &info_frame
->vendor
);
760 dce110_update_hdmi_info_packet(enc110
, 2, &info_frame
->gamut
);
761 dce110_update_hdmi_info_packet(enc110
, 3, &info_frame
->spd
);
762 dce110_update_hdmi_info_packet(enc110
, 4, &info_frame
->hdrsmd
);
767 static void dce110_stream_encoder_stop_hdmi_info_packets(
768 struct stream_encoder
*enc
)
770 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
772 /* stop generic packets 0 & 1 on HDMI */
773 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0
, 0,
774 HDMI_GENERIC1_CONT
, 0,
775 HDMI_GENERIC1_LINE
, 0,
776 HDMI_GENERIC1_SEND
, 0,
777 HDMI_GENERIC0_CONT
, 0,
778 HDMI_GENERIC0_LINE
, 0,
779 HDMI_GENERIC0_SEND
, 0);
781 /* stop generic packets 2 & 3 on HDMI */
782 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1
, 0,
783 HDMI_GENERIC0_CONT
, 0,
784 HDMI_GENERIC0_LINE
, 0,
785 HDMI_GENERIC0_SEND
, 0,
786 HDMI_GENERIC1_CONT
, 0,
787 HDMI_GENERIC1_LINE
, 0,
788 HDMI_GENERIC1_SEND
, 0);
790 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
791 /* stop generic packets 2 & 3 on HDMI */
792 if (REG(HDMI_GENERIC_PACKET_CONTROL2
))
793 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2
, 0,
794 HDMI_GENERIC0_CONT
, 0,
795 HDMI_GENERIC0_LINE
, 0,
796 HDMI_GENERIC0_SEND
, 0,
797 HDMI_GENERIC1_CONT
, 0,
798 HDMI_GENERIC1_LINE
, 0,
799 HDMI_GENERIC1_SEND
, 0);
801 if (REG(HDMI_GENERIC_PACKET_CONTROL3
))
802 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3
, 0,
803 HDMI_GENERIC0_CONT
, 0,
804 HDMI_GENERIC0_LINE
, 0,
805 HDMI_GENERIC0_SEND
, 0,
806 HDMI_GENERIC1_CONT
, 0,
807 HDMI_GENERIC1_LINE
, 0,
808 HDMI_GENERIC1_SEND
, 0);
812 static void dce110_stream_encoder_update_dp_info_packets(
813 struct stream_encoder
*enc
,
814 const struct encoder_info_frame
*info_frame
)
816 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
817 uint32_t value
= REG_READ(DP_SEC_CNTL
);
819 if (info_frame
->vsc
.valid
)
820 dce110_update_generic_info_packet(
825 if (info_frame
->spd
.valid
)
826 dce110_update_generic_info_packet(
831 if (info_frame
->hdrsmd
.valid
)
832 dce110_update_generic_info_packet(
835 &info_frame
->hdrsmd
);
837 /* enable/disable transmission of packet(s).
838 * If enabled, packet transmission begins on the next frame
840 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_GSP0_ENABLE
, info_frame
->vsc
.valid
);
841 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_GSP2_ENABLE
, info_frame
->spd
.valid
);
842 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_GSP3_ENABLE
, info_frame
->hdrsmd
.valid
);
844 /* This bit is the master enable bit.
845 * When enabling secondary stream engine,
846 * this master bit must also be set.
847 * This register shared with audio info frame.
848 * Therefore we need to enable master bit
849 * if at least on of the fields is not 0
852 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_STREAM_ENABLE
, 1);
855 static void dce110_stream_encoder_stop_dp_info_packets(
856 struct stream_encoder
*enc
)
858 /* stop generic packets on DP */
859 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
860 uint32_t value
= REG_READ(DP_SEC_CNTL
);
862 if (enc110
->se_mask
->DP_SEC_AVI_ENABLE
) {
863 REG_SET_7(DP_SEC_CNTL
, 0,
864 DP_SEC_GSP0_ENABLE
, 0,
865 DP_SEC_GSP1_ENABLE
, 0,
866 DP_SEC_GSP2_ENABLE
, 0,
867 DP_SEC_GSP3_ENABLE
, 0,
868 DP_SEC_AVI_ENABLE
, 0,
869 DP_SEC_MPG_ENABLE
, 0,
870 DP_SEC_STREAM_ENABLE
, 0);
873 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
874 if (enc110
->se_mask
->DP_SEC_GSP7_ENABLE
) {
875 REG_SET_10(DP_SEC_CNTL
, 0,
876 DP_SEC_GSP0_ENABLE
, 0,
877 DP_SEC_GSP1_ENABLE
, 0,
878 DP_SEC_GSP2_ENABLE
, 0,
879 DP_SEC_GSP3_ENABLE
, 0,
880 DP_SEC_GSP4_ENABLE
, 0,
881 DP_SEC_GSP5_ENABLE
, 0,
882 DP_SEC_GSP6_ENABLE
, 0,
883 DP_SEC_GSP7_ENABLE
, 0,
884 DP_SEC_MPG_ENABLE
, 0,
885 DP_SEC_STREAM_ENABLE
, 0);
888 /* this register shared with audio info frame.
889 * therefore we need to keep master enabled
890 * if at least one of the fields is not 0 */
893 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_STREAM_ENABLE
, 1);
897 static void dce110_stream_encoder_dp_blank(
898 struct stream_encoder
*enc
)
900 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
901 uint32_t retries
= 0;
902 uint32_t max_retries
= DP_BLANK_MAX_RETRY
* 10;
904 /* Note: For CZ, we are changing driver default to disable
905 * stream deferred to next VBLANK. If results are positive, we
906 * will make the same change to all DCE versions. There are a
907 * handful of panels that cannot handle disable stream at
908 * HBLANK and will result in a white line flash across the
909 * screen on stream disable. */
911 /* Specify the video stream disable point
912 * (2 = start of the next vertical blank) */
913 REG_UPDATE(DP_VID_STREAM_CNTL
, DP_VID_STREAM_DIS_DEFER
, 2);
914 /* Larger delay to wait until VBLANK - use max retry of
915 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
916 * a little more because we may not trust delay accuracy.
918 max_retries
= DP_BLANK_MAX_RETRY
* 150;
920 /* disable DP stream */
921 REG_UPDATE(DP_VID_STREAM_CNTL
, DP_VID_STREAM_ENABLE
, 0);
923 /* the encoder stops sending the video stream
924 * at the start of the vertical blanking.
925 * Poll for DP_VID_STREAM_STATUS == 0
928 REG_WAIT(DP_VID_STREAM_CNTL
, DP_VID_STREAM_STATUS
,
932 ASSERT(retries
<= max_retries
);
934 /* Tell the DP encoder to ignore timing from CRTC, must be done after
935 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
936 * complete, stream status will be stuck in video stream enabled state,
937 * i.e. DP_VID_STREAM_STATUS stuck at 1.
940 REG_UPDATE(DP_STEER_FIFO
, DP_STEER_FIFO_RESET
, true);
943 /* output video stream to link encoder */
944 static void dce110_stream_encoder_dp_unblank(
945 struct stream_encoder
*enc
,
946 const struct encoder_unblank_param
*param
)
948 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
950 if (param
->link_settings
.link_rate
!= LINK_RATE_UNKNOWN
) {
951 uint32_t n_vid
= 0x8000;
954 /* M / N = Fstream / Flink
955 * m_vid / n_vid = pixel rate / link rate
958 uint64_t m_vid_l
= n_vid
;
960 m_vid_l
*= param
->pixel_clk_khz
;
961 m_vid_l
= div_u64(m_vid_l
,
962 param
->link_settings
.link_rate
963 * LINK_RATE_REF_FREQ_IN_KHZ
);
965 m_vid
= (uint32_t) m_vid_l
;
967 /* enable auto measurement */
969 REG_UPDATE(DP_VID_TIMING
, DP_VID_M_N_GEN_EN
, 0);
971 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
972 * therefore program initial value for Mvid and Nvid
975 REG_UPDATE(DP_VID_N
, DP_VID_N
, n_vid
);
977 REG_UPDATE(DP_VID_M
, DP_VID_M
, m_vid
);
979 REG_UPDATE(DP_VID_TIMING
, DP_VID_M_N_GEN_EN
, 1);
982 /* set DIG_START to 0x1 to resync FIFO */
984 REG_UPDATE(DIG_FE_CNTL
, DIG_START
, 1);
986 /* switch DP encoder to CRTC data */
988 REG_UPDATE(DP_STEER_FIFO
, DP_STEER_FIFO_RESET
, 0);
990 /* wait 100us for DIG/DP logic to prime
991 * (i.e. a few video lines)
995 /* the hardware would start sending video at the start of the next DP
996 * frame (i.e. rising edge of the vblank).
997 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
998 * register has no effect on enable transition! HW always guarantees
999 * VID_STREAM enable at start of next frame, and this is not
1003 REG_UPDATE(DP_VID_STREAM_CNTL
, DP_VID_STREAM_ENABLE
, true);
1006 static void dce110_stream_encoder_set_avmute(
1007 struct stream_encoder
*enc
,
1010 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1011 unsigned int value
= enable
? 1 : 0;
1013 REG_UPDATE(HDMI_GC
, HDMI_GC_AVMUTE
, value
);
1017 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1018 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1020 #include "include/audio_types.h"
1023 * speakersToChannels
1026 * translate speakers to channels
1034 * FLC - Front Left Center
1035 * FRC - Front Right Center
1036 * RLC - Rear Left Center
1037 * RRC - Rear Right Center
1038 * LFE - Low Freq Effect
1052 * ch 8 7 6 5 4 3 2 1
1053 * 0b00000011 - - - - - - FR FL
1054 * 0b00000111 - - - - - LFE FR FL
1055 * 0b00001011 - - - - FC - FR FL
1056 * 0b00001111 - - - - FC LFE FR FL
1057 * 0b00010011 - - - RC - - FR FL
1058 * 0b00010111 - - - RC - LFE FR FL
1059 * 0b00011011 - - - RC FC - FR FL
1060 * 0b00011111 - - - RC FC LFE FR FL
1061 * 0b00110011 - - RR RL - - FR FL
1062 * 0b00110111 - - RR RL - LFE FR FL
1063 * 0b00111011 - - RR RL FC - FR FL
1064 * 0b00111111 - - RR RL FC LFE FR FL
1065 * 0b01110011 - RC RR RL - - FR FL
1066 * 0b01110111 - RC RR RL - LFE FR FL
1067 * 0b01111011 - RC RR RL FC - FR FL
1068 * 0b01111111 - RC RR RL FC LFE FR FL
1069 * 0b11110011 RRC RLC RR RL - - FR FL
1070 * 0b11110111 RRC RLC RR RL - LFE FR FL
1071 * 0b11111011 RRC RLC RR RL FC - FR FL
1072 * 0b11111111 RRC RLC RR RL FC LFE FR FL
1073 * 0b11000011 FRC FLC - - - - FR FL
1074 * 0b11000111 FRC FLC - - - LFE FR FL
1075 * 0b11001011 FRC FLC - - FC - FR FL
1076 * 0b11001111 FRC FLC - - FC LFE FR FL
1077 * 0b11010011 FRC FLC - RC - - FR FL
1078 * 0b11010111 FRC FLC - RC - LFE FR FL
1079 * 0b11011011 FRC FLC - RC FC - FR FL
1080 * 0b11011111 FRC FLC - RC FC LFE FR FL
1081 * 0b11110011 FRC FLC RR RL - - FR FL
1082 * 0b11110111 FRC FLC RR RL - LFE FR FL
1083 * 0b11111011 FRC FLC RR RL FC - FR FL
1084 * 0b11111111 FRC FLC RR RL FC LFE FR FL
1087 * speakers - speaker information as it comes from CEA audio block
1089 /* translate speakers to channels */
1091 union audio_cea_channels
{
1093 struct audio_cea_channels_bits
{
1100 uint32_t RC_RLC_FLC
:1;
1105 struct audio_clock_info
{
1106 /* pixel clock frequency*/
1107 uint32_t pixel_clock_in_10khz
;
1108 /* N - 32KHz audio */
1110 /* CTS - 32KHz audio*/
1131 static const struct audio_clock_info audio_clock_info_table
[16] = {
1132 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1133 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1134 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1135 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1136 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1137 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1138 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1139 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1140 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1141 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1142 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1143 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1144 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1145 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1146 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1147 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1150 static const struct audio_clock_info audio_clock_info_table_36bpc
[14] = {
1151 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1152 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1153 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1154 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1155 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1156 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1157 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1158 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1159 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1160 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1161 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1162 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1163 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1164 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1167 static const struct audio_clock_info audio_clock_info_table_48bpc
[14] = {
1168 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1169 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1170 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1171 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1172 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1173 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1174 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1175 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1176 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1177 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1178 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1179 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1180 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1181 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1186 static union audio_cea_channels
speakers_to_channels(
1187 struct audio_speaker_flags speaker_flags
)
1189 union audio_cea_channels cea_channels
= {0};
1191 /* these are one to one */
1192 cea_channels
.channels
.FL
= speaker_flags
.FL_FR
;
1193 cea_channels
.channels
.FR
= speaker_flags
.FL_FR
;
1194 cea_channels
.channels
.LFE
= speaker_flags
.LFE
;
1195 cea_channels
.channels
.FC
= speaker_flags
.FC
;
1197 /* if Rear Left and Right exist move RC speaker to channel 7
1198 * otherwise to channel 5
1200 if (speaker_flags
.RL_RR
) {
1201 cea_channels
.channels
.RL_RC
= speaker_flags
.RL_RR
;
1202 cea_channels
.channels
.RR
= speaker_flags
.RL_RR
;
1203 cea_channels
.channels
.RC_RLC_FLC
= speaker_flags
.RC
;
1205 cea_channels
.channels
.RL_RC
= speaker_flags
.RC
;
1208 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1209 if (speaker_flags
.FLC_FRC
) {
1210 cea_channels
.channels
.RC_RLC_FLC
= speaker_flags
.FLC_FRC
;
1211 cea_channels
.channels
.RRC_FRC
= speaker_flags
.FLC_FRC
;
1213 cea_channels
.channels
.RC_RLC_FLC
= speaker_flags
.RLC_RRC
;
1214 cea_channels
.channels
.RRC_FRC
= speaker_flags
.RLC_RRC
;
1217 return cea_channels
;
1220 static uint32_t calc_max_audio_packets_per_line(
1221 const struct audio_crtc_info
*crtc_info
)
1223 uint32_t max_packets_per_line
;
1225 max_packets_per_line
=
1226 crtc_info
->h_total
- crtc_info
->h_active
;
1228 if (crtc_info
->pixel_repetition
)
1229 max_packets_per_line
*= crtc_info
->pixel_repetition
;
1231 /* for other hdmi features */
1232 max_packets_per_line
-= 58;
1233 /* for Control Period */
1234 max_packets_per_line
-= 16;
1235 /* Number of Audio Packets per Line */
1236 max_packets_per_line
/= 32;
1238 return max_packets_per_line
;
1241 static void get_audio_clock_info(
1242 enum dc_color_depth color_depth
,
1243 uint32_t crtc_pixel_clock_in_khz
,
1244 uint32_t actual_pixel_clock_in_khz
,
1245 struct audio_clock_info
*audio_clock_info
)
1247 const struct audio_clock_info
*clock_info
;
1249 uint32_t crtc_pixel_clock_in_10khz
= crtc_pixel_clock_in_khz
/ 10;
1250 uint32_t audio_array_size
;
1252 switch (color_depth
) {
1253 case COLOR_DEPTH_161616
:
1254 clock_info
= audio_clock_info_table_48bpc
;
1255 audio_array_size
= ARRAY_SIZE(
1256 audio_clock_info_table_48bpc
);
1258 case COLOR_DEPTH_121212
:
1259 clock_info
= audio_clock_info_table_36bpc
;
1260 audio_array_size
= ARRAY_SIZE(
1261 audio_clock_info_table_36bpc
);
1264 clock_info
= audio_clock_info_table
;
1265 audio_array_size
= ARRAY_SIZE(
1266 audio_clock_info_table
);
1270 if (clock_info
!= NULL
) {
1271 /* search for exact pixel clock in table */
1272 for (index
= 0; index
< audio_array_size
; index
++) {
1273 if (clock_info
[index
].pixel_clock_in_10khz
>
1274 crtc_pixel_clock_in_10khz
)
1275 break; /* not match */
1276 else if (clock_info
[index
].pixel_clock_in_10khz
==
1277 crtc_pixel_clock_in_10khz
) {
1279 *audio_clock_info
= clock_info
[index
];
1286 if (actual_pixel_clock_in_khz
== 0)
1287 actual_pixel_clock_in_khz
= crtc_pixel_clock_in_khz
;
1289 /* See HDMI spec the table entry under
1290 * pixel clock of "Other". */
1291 audio_clock_info
->pixel_clock_in_10khz
=
1292 actual_pixel_clock_in_khz
/ 10;
1293 audio_clock_info
->cts_32khz
= actual_pixel_clock_in_khz
;
1294 audio_clock_info
->cts_44khz
= actual_pixel_clock_in_khz
;
1295 audio_clock_info
->cts_48khz
= actual_pixel_clock_in_khz
;
1297 audio_clock_info
->n_32khz
= 4096;
1298 audio_clock_info
->n_44khz
= 6272;
1299 audio_clock_info
->n_48khz
= 6144;
1302 static void dce110_se_audio_setup(
1303 struct stream_encoder
*enc
,
1304 unsigned int az_inst
,
1305 struct audio_info
*audio_info
)
1307 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1309 uint32_t speakers
= 0;
1310 uint32_t channels
= 0;
1313 if (audio_info
== NULL
)
1314 /* This should not happen.it does so we don't get BSOD*/
1317 speakers
= audio_info
->flags
.info
.ALLSPEAKERS
;
1318 channels
= speakers_to_channels(audio_info
->flags
.speaker_flags
).all
;
1320 /* setup the audio stream source select (audio -> dig mapping) */
1321 REG_SET(AFMT_AUDIO_SRC_CONTROL
, 0, AFMT_AUDIO_SRC_SELECT
, az_inst
);
1323 /* Channel allocation */
1324 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2
, AFMT_AUDIO_CHANNEL_ENABLE
, channels
);
1327 static void dce110_se_setup_hdmi_audio(
1328 struct stream_encoder
*enc
,
1329 const struct audio_crtc_info
*crtc_info
)
1331 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1333 struct audio_clock_info audio_clock_info
= {0};
1334 uint32_t max_packets_per_line
;
1336 /* For now still do calculation, although this field is ignored when
1337 above HDMI_PACKET_GEN_VERSION set to 1 */
1338 max_packets_per_line
= calc_max_audio_packets_per_line(crtc_info
);
1340 /* HDMI_AUDIO_PACKET_CONTROL */
1341 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL
,
1342 HDMI_AUDIO_PACKETS_PER_LINE
, max_packets_per_line
,
1343 HDMI_AUDIO_DELAY_EN
, 1);
1345 /* AFMT_AUDIO_PACKET_CONTROL */
1346 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1348 /* AFMT_AUDIO_PACKET_CONTROL2 */
1349 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2
,
1350 AFMT_AUDIO_LAYOUT_OVRD
, 0,
1351 AFMT_60958_OSF_OVRD
, 0);
1353 /* HDMI_ACR_PACKET_CONTROL */
1354 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL
,
1355 HDMI_ACR_AUTO_SEND
, 1,
1357 HDMI_ACR_AUDIO_PRIORITY
, 0);
1359 /* Program audio clock sample/regeneration parameters */
1360 get_audio_clock_info(crtc_info
->color_depth
,
1361 crtc_info
->requested_pixel_clock
,
1362 crtc_info
->calculated_pixel_clock
,
1364 dm_logger_write(enc
->ctx
->logger
, LOG_HW_AUDIO
,
1365 "\n%s:Input::requested_pixel_clock = %d" \
1366 "calculated_pixel_clock = %d \n", __func__
, \
1367 crtc_info
->requested_pixel_clock
, \
1368 crtc_info
->calculated_pixel_clock
);
1370 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1371 REG_UPDATE(HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, audio_clock_info
.cts_32khz
);
1373 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1374 REG_UPDATE(HDMI_ACR_32_1
, HDMI_ACR_N_32
, audio_clock_info
.n_32khz
);
1376 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1377 REG_UPDATE(HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, audio_clock_info
.cts_44khz
);
1379 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1380 REG_UPDATE(HDMI_ACR_44_1
, HDMI_ACR_N_44
, audio_clock_info
.n_44khz
);
1382 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1383 REG_UPDATE(HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, audio_clock_info
.cts_48khz
);
1385 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1386 REG_UPDATE(HDMI_ACR_48_1
, HDMI_ACR_N_48
, audio_clock_info
.n_48khz
);
1388 /* Video driver cannot know in advance which sample rate will
1389 be used by HD Audio driver
1390 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1391 programmed below in interruppt callback */
1393 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1394 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1395 REG_UPDATE_2(AFMT_60958_0
,
1396 AFMT_60958_CS_CHANNEL_NUMBER_L
, 1,
1397 AFMT_60958_CS_CLOCK_ACCURACY
, 0);
1399 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1400 REG_UPDATE(AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1402 /*AFMT_60958_2 now keep this settings until
1403 * Programming guide comes out*/
1404 REG_UPDATE_6(AFMT_60958_2
,
1405 AFMT_60958_CS_CHANNEL_NUMBER_2
, 3,
1406 AFMT_60958_CS_CHANNEL_NUMBER_3
, 4,
1407 AFMT_60958_CS_CHANNEL_NUMBER_4
, 5,
1408 AFMT_60958_CS_CHANNEL_NUMBER_5
, 6,
1409 AFMT_60958_CS_CHANNEL_NUMBER_6
, 7,
1410 AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1413 static void dce110_se_setup_dp_audio(
1414 struct stream_encoder
*enc
)
1416 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1418 /* --- DP Audio packet configurations --- */
1420 /* ATP Configuration */
1421 REG_SET(DP_SEC_AUD_N
, 0,
1422 DP_SEC_AUD_N
, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT
);
1424 /* Async/auto-calc timestamp mode */
1425 REG_SET(DP_SEC_TIMESTAMP
, 0, DP_SEC_TIMESTAMP_MODE
,
1426 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC
);
1428 /* --- The following are the registers
1429 * copied from the SetupHDMI --- */
1431 /* AFMT_AUDIO_PACKET_CONTROL */
1432 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1434 /* AFMT_AUDIO_PACKET_CONTROL2 */
1435 /* Program the ATP and AIP next */
1436 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2
,
1437 AFMT_AUDIO_LAYOUT_OVRD
, 0,
1438 AFMT_60958_OSF_OVRD
, 0);
1440 /* AFMT_INFOFRAME_CONTROL0 */
1441 REG_UPDATE(AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1443 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1444 REG_UPDATE(AFMT_60958_0
, AFMT_60958_CS_CLOCK_ACCURACY
, 0);
1447 static void dce110_se_enable_audio_clock(
1448 struct stream_encoder
*enc
,
1451 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1453 if (REG(AFMT_CNTL
) == 0)
1454 return; /* DCE8/10 does not have this register */
1456 REG_UPDATE(AFMT_CNTL
, AFMT_AUDIO_CLOCK_EN
, !!enable
);
1458 /* wait for AFMT clock to turn on,
1459 * expectation: this should complete in 1-2 reads
1461 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1463 * TODO: wait for clock_on does not work well. May need HW
1464 * program sequence. But audio seems work normally even without wait
1465 * for clock_on status change
1469 static void dce110_se_enable_dp_audio(
1470 struct stream_encoder
*enc
)
1472 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1474 /* Enable Audio packets */
1475 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_ASP_ENABLE
, 1);
1477 /* Program the ATP and AIP next */
1478 REG_UPDATE_2(DP_SEC_CNTL
,
1479 DP_SEC_ATP_ENABLE
, 1,
1480 DP_SEC_AIP_ENABLE
, 1);
1482 /* Program STREAM_ENABLE after all the other enables. */
1483 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_STREAM_ENABLE
, 1);
1486 static void dce110_se_disable_dp_audio(
1487 struct stream_encoder
*enc
)
1489 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1490 uint32_t value
= REG_READ(DP_SEC_CNTL
);
1492 /* Disable Audio packets */
1493 REG_UPDATE_5(DP_SEC_CNTL
,
1494 DP_SEC_ASP_ENABLE
, 0,
1495 DP_SEC_ATP_ENABLE
, 0,
1496 DP_SEC_AIP_ENABLE
, 0,
1497 DP_SEC_ACM_ENABLE
, 0,
1498 DP_SEC_STREAM_ENABLE
, 0);
1500 /* This register shared with encoder info frame. Therefore we need to
1501 keep master enabled if at least on of the fields is not 0 */
1503 REG_UPDATE(DP_SEC_CNTL
, DP_SEC_STREAM_ENABLE
, 1);
1507 void dce110_se_audio_mute_control(
1508 struct stream_encoder
*enc
,
1511 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1513 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, !mute
);
1516 void dce110_se_dp_audio_setup(
1517 struct stream_encoder
*enc
,
1518 unsigned int az_inst
,
1519 struct audio_info
*info
)
1521 dce110_se_audio_setup(enc
, az_inst
, info
);
1524 void dce110_se_dp_audio_enable(
1525 struct stream_encoder
*enc
)
1527 dce110_se_enable_audio_clock(enc
, true);
1528 dce110_se_setup_dp_audio(enc
);
1529 dce110_se_enable_dp_audio(enc
);
1532 void dce110_se_dp_audio_disable(
1533 struct stream_encoder
*enc
)
1535 dce110_se_disable_dp_audio(enc
);
1536 dce110_se_enable_audio_clock(enc
, false);
1539 void dce110_se_hdmi_audio_setup(
1540 struct stream_encoder
*enc
,
1541 unsigned int az_inst
,
1542 struct audio_info
*info
,
1543 struct audio_crtc_info
*audio_crtc_info
)
1545 dce110_se_enable_audio_clock(enc
, true);
1546 dce110_se_setup_hdmi_audio(enc
, audio_crtc_info
);
1547 dce110_se_audio_setup(enc
, az_inst
, info
);
1550 void dce110_se_hdmi_audio_disable(
1551 struct stream_encoder
*enc
)
1553 dce110_se_enable_audio_clock(enc
, false);
1557 static void setup_stereo_sync(
1558 struct stream_encoder
*enc
,
1559 int tg_inst
, bool enable
)
1561 struct dce110_stream_encoder
*enc110
= DCE110STRENC_FROM_STRENC(enc
);
1562 REG_UPDATE(DIG_FE_CNTL
, DIG_STEREOSYNC_SELECT
, tg_inst
);
1563 REG_UPDATE(DIG_FE_CNTL
, DIG_STEREOSYNC_GATE_EN
, !enable
);
1567 static const struct stream_encoder_funcs dce110_str_enc_funcs
= {
1568 .dp_set_stream_attribute
=
1569 dce110_stream_encoder_dp_set_stream_attribute
,
1570 .hdmi_set_stream_attribute
=
1571 dce110_stream_encoder_hdmi_set_stream_attribute
,
1572 .dvi_set_stream_attribute
=
1573 dce110_stream_encoder_dvi_set_stream_attribute
,
1574 .set_mst_bandwidth
=
1575 dce110_stream_encoder_set_mst_bandwidth
,
1576 .update_hdmi_info_packets
=
1577 dce110_stream_encoder_update_hdmi_info_packets
,
1578 .stop_hdmi_info_packets
=
1579 dce110_stream_encoder_stop_hdmi_info_packets
,
1580 .update_dp_info_packets
=
1581 dce110_stream_encoder_update_dp_info_packets
,
1582 .stop_dp_info_packets
=
1583 dce110_stream_encoder_stop_dp_info_packets
,
1585 dce110_stream_encoder_dp_blank
,
1587 dce110_stream_encoder_dp_unblank
,
1588 .audio_mute_control
= dce110_se_audio_mute_control
,
1590 .dp_audio_setup
= dce110_se_dp_audio_setup
,
1591 .dp_audio_enable
= dce110_se_dp_audio_enable
,
1592 .dp_audio_disable
= dce110_se_dp_audio_disable
,
1594 .hdmi_audio_setup
= dce110_se_hdmi_audio_setup
,
1595 .hdmi_audio_disable
= dce110_se_hdmi_audio_disable
,
1596 .setup_stereo_sync
= setup_stereo_sync
,
1597 .set_avmute
= dce110_stream_encoder_set_avmute
,
1601 void dce110_stream_encoder_construct(
1602 struct dce110_stream_encoder
*enc110
,
1603 struct dc_context
*ctx
,
1605 enum engine_id eng_id
,
1606 const struct dce110_stream_enc_registers
*regs
,
1607 const struct dce_stream_encoder_shift
*se_shift
,
1608 const struct dce_stream_encoder_mask
*se_mask
)
1610 enc110
->base
.funcs
= &dce110_str_enc_funcs
;
1611 enc110
->base
.ctx
= ctx
;
1612 enc110
->base
.id
= eng_id
;
1613 enc110
->base
.bp
= bp
;
1614 enc110
->regs
= regs
;
1615 enc110
->se_shift
= se_shift
;
1616 enc110
->se_mask
= se_mask
;