2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
28 #include "core_types.h"
29 #include "hw_sequencer.h"
30 #include "dce100_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
33 /* include DCE10 register header files */
34 #include "dce/dce_10_0_d.h"
35 #include "dce/dce_10_0_sh_mask.h"
37 struct dce100_hw_seq_reg_offsets
{
42 static const struct dce100_hw_seq_reg_offsets reg_offsets
[] = {
44 .crtc
= (mmCRTC0_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
47 .crtc
= (mmCRTC1_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
50 .crtc
= (mmCRTC2_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
53 .crtc
= (mmCRTC3_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
56 .crtc
= (mmCRTC4_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
59 .crtc
= (mmCRTC5_CRTC_GSL_CONTROL
- mmCRTC_GSL_CONTROL
),
63 #define HW_REG_CRTC(reg, id)\
64 (reg + reg_offsets[id].crtc)
66 /*******************************************************************************
68 ******************************************************************************/
69 /***************************PIPE_CONTROL***********************************/
71 static bool dce100_enable_display_power_gating(
73 uint8_t controller_id
,
75 enum pipe_gating_control power_gating
)
77 enum bp_result bp_result
= BP_RESULT_OK
;
78 enum bp_pipe_control_action cntl
;
79 struct dc_context
*ctx
= dc
->ctx
;
81 if (power_gating
== PIPE_GATING_CONTROL_INIT
)
82 cntl
= ASIC_PIPE_INIT
;
83 else if (power_gating
== PIPE_GATING_CONTROL_ENABLE
)
84 cntl
= ASIC_PIPE_ENABLE
;
86 cntl
= ASIC_PIPE_DISABLE
;
88 if (!(power_gating
== PIPE_GATING_CONTROL_INIT
&& controller_id
!= 0)){
90 bp_result
= dcb
->funcs
->enable_disp_power_gating(
91 dcb
, controller_id
+ 1, cntl
);
93 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
94 * by default when command table is called
97 HW_REG_CRTC(mmMASTER_UPDATE_MODE
, controller_id
),
101 if (bp_result
== BP_RESULT_OK
)
107 static void set_display_mark_for_pipe_if_needed(struct core_dc
*dc
,
108 struct pipe_ctx
*pipe_ctx
,
109 struct validate_context
*context
)
111 /* Do nothing until we have proper bandwitdth calcs */
114 static void set_displaymarks(
115 const struct core_dc
*dc
, struct validate_context
*context
)
117 /* Do nothing until we have proper bandwitdth calcs */
120 static void set_bandwidth(struct core_dc
*dc
)
122 /* Do nothing until we have proper bandwitdth calcs */
126 /**************************************************************************/
128 bool dce100_hw_sequencer_construct(struct core_dc
*dc
)
130 dce110_hw_sequencer_construct(dc
);
132 /* TODO: dce80 is empty implementation at the moment*/
133 dc
->hwss
.enable_display_power_gating
= dce100_enable_display_power_gating
;
134 dc
->hwss
.set_displaymarks
= set_displaymarks
;
135 dc
->hwss
.increase_watermarks_for_pipe
= set_display_mark_for_pipe_if_needed
;
136 dc
->hwss
.set_bandwidth
= set_bandwidth
;