drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "core_dc.h"
  28 #include "core_types.h"
  29 #include "hw_sequencer.h"
  30 #include "dce100_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32
  33 /* include DCE10 register header files */
  34 #include "dce/dce_10_0_d.h"
  35 #include "dce/dce_10_0_sh_mask.h"
  36
  37 struct dce100_hw_seq_reg_offsets {
  38         uint32_t blnd;
  39         uint32_t crtc;
  40 };
  41
  42 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
  43 {
  44         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  45 },
  46 {
  47         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  48 },
  49 {
  50         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  51 },
  52 {
  53         .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  54 },
  55 {
  56         .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  57 },
  58 {
  59         .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  60 }
  61 };
  62
  63 #define HW_REG_CRTC(reg, id)\
  64         (reg + reg_offsets[id].crtc)
  65
  66 /*******************************************************************************
  67  * Private definitions
  68  ******************************************************************************/
  69 /***************************PIPE_CONTROL***********************************/
  70
  71 static bool dce100_enable_display_power_gating(
  72         struct core_dc *dc,
  73         uint8_t controller_id,
  74         struct dc_bios *dcb,
  75         enum pipe_gating_control power_gating)
  76 {
  77         enum bp_result bp_result = BP_RESULT_OK;
  78         enum bp_pipe_control_action cntl;
  79         struct dc_context *ctx = dc->ctx;
  80
  81         if (power_gating == PIPE_GATING_CONTROL_INIT)
  82                 cntl = ASIC_PIPE_INIT;
  83         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
  84                 cntl = ASIC_PIPE_ENABLE;
  85         else
  86                 cntl = ASIC_PIPE_DISABLE;
  87
  88         if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
  89
  90                 bp_result = dcb->funcs->enable_disp_power_gating(
  91                                                 dcb, controller_id + 1, cntl);
  92
  93                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
  94                  * by default when command table is called
  95                  */
  96                 dm_write_reg(ctx,
  97                         HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
  98                         0);
  99         }
 100
 101         if (bp_result == BP_RESULT_OK)
 102                 return true;
 103         else
 104                 return false;
 105 }
 106
 107 static void set_display_mark_for_pipe_if_needed(struct core_dc *dc,
 108                 struct pipe_ctx *pipe_ctx,
 109                 struct validate_context *context)
 110 {
 111         /* Do nothing until we have proper bandwitdth calcs */
 112 }
 113
 114 static void set_displaymarks(
 115                 const struct core_dc *dc, struct validate_context *context)
 116 {
 117         /* Do nothing until we have proper bandwitdth calcs */
 118 }
 119
 120 static void set_bandwidth(struct core_dc *dc)
 121 {
 122         /* Do nothing until we have proper bandwitdth calcs */
 123 }
 124
 125
 126 /**************************************************************************/
 127
 128 bool dce100_hw_sequencer_construct(struct core_dc *dc)
 129 {
 130         dce110_hw_sequencer_construct(dc);
 131
 132         /* TODO: dce80 is empty implementation at the moment*/
 133         dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 134         dc->hwss.set_displaymarks = set_displaymarks;
 135         dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
 136         dc->hwss.set_bandwidth = set_bandwidth;
 137
 138         return true;
 139 }
 140