2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "link_encoder.h"
28 #include "stream_encoder.h"
31 #include "include/irq_service_interface.h"
32 #include "../virtual/virtual_stream_encoder.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "irq/dce110/irq_service_dce110.h"
36 #include "dce/dce_link_encoder.h"
37 #include "dce/dce_stream_encoder.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clocks.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "dce100/dce100_hw_sequencer.h"
49 #include "reg_helper.h"
51 #include "dce/dce_10_0_d.h"
52 #include "dce/dce_10_0_sh_mask.h"
54 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
55 #include "gmc/gmc_8_2_d.h"
56 #include "gmc/gmc_8_2_sh_mask.h"
59 #ifndef mmDP_DPHY_INTERNAL_CTRL
60 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
61 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
62 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
63 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
64 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
65 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
66 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
67 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
68 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
69 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
72 #ifndef mmBIOS_SCRATCH_2
73 #define mmBIOS_SCRATCH_2 0x05CB
74 #define mmBIOS_SCRATCH_6 0x05CF
77 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
78 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
79 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
80 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
81 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
82 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
83 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
84 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
85 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
88 #ifndef mmDP_DPHY_FAST_TRAINING
89 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
90 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
91 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
92 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
93 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
94 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
95 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
96 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
99 static const struct dce110_timing_generator_offsets dce100_tg_offsets
[] = {
101 .crtc
= (mmCRTC0_CRTC_CONTROL
- mmCRTC_CONTROL
),
102 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
105 .crtc
= (mmCRTC1_CRTC_CONTROL
- mmCRTC_CONTROL
),
106 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
109 .crtc
= (mmCRTC2_CRTC_CONTROL
- mmCRTC_CONTROL
),
110 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
113 .crtc
= (mmCRTC3_CRTC_CONTROL
- mmCRTC_CONTROL
),
114 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
117 .crtc
= (mmCRTC4_CRTC_CONTROL
- mmCRTC_CONTROL
),
118 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
121 .crtc
= (mmCRTC5_CRTC_CONTROL
- mmCRTC_CONTROL
),
122 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
126 /* set register offset */
127 #define SR(reg_name)\
128 .reg_name = mm ## reg_name
130 /* set register offset with instance */
131 #define SRI(reg_name, block, id)\
132 .reg_name = mm ## block ## id ## _ ## reg_name
135 static const struct dce_disp_clk_registers disp_clk_regs
= {
136 CLK_COMMON_REG_LIST_DCE_BASE()
139 static const struct dce_disp_clk_shift disp_clk_shift
= {
140 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
143 static const struct dce_disp_clk_mask disp_clk_mask
= {
144 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
147 #define ipp_regs(id)\
149 IPP_DCE100_REG_LIST_DCE_BASE(id)\
152 static const struct dce_ipp_registers ipp_regs
[] = {
161 static const struct dce_ipp_shift ipp_shift
= {
162 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
165 static const struct dce_ipp_mask ipp_mask
= {
166 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
169 #define transform_regs(id)\
171 XFM_COMMON_REG_LIST_DCE100(id)\
174 static const struct dce_transform_registers xfm_regs
[] = {
183 static const struct dce_transform_shift xfm_shift
= {
184 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
187 static const struct dce_transform_mask xfm_mask
= {
188 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK
)
191 #define aux_regs(id)\
196 static const struct dce110_link_enc_aux_registers link_enc_aux_regs
[] = {
205 #define hpd_regs(id)\
210 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs
[] = {
219 #define link_regs(id)\
221 LE_DCE100_REG_LIST(id)\
224 static const struct dce110_link_enc_registers link_enc_regs
[] = {
234 #define stream_enc_regs(id)\
236 SE_COMMON_REG_LIST_DCE_BASE(id),\
240 static const struct dce110_stream_enc_registers stream_enc_regs
[] = {
250 static const struct dce_stream_encoder_shift se_shift
= {
251 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT
)
254 static const struct dce_stream_encoder_mask se_mask
= {
255 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK
)
258 #define opp_regs(id)\
260 OPP_DCE_100_REG_LIST(id),\
263 static const struct dce_opp_registers opp_regs
[] = {
272 static const struct dce_opp_shift opp_shift
= {
273 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT
)
276 static const struct dce_opp_mask opp_mask
= {
277 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK
)
281 #define audio_regs(id)\
283 AUD_COMMON_REG_LIST(id)\
286 static const struct dce_audio_registers audio_regs
[] = {
296 static const struct dce_audio_shift audio_shift
= {
297 AUD_COMMON_MASK_SH_LIST(__SHIFT
)
300 static const struct dce_aduio_mask audio_mask
= {
301 AUD_COMMON_MASK_SH_LIST(_MASK
)
304 #define clk_src_regs(id)\
306 CS_COMMON_REG_LIST_DCE_100_110(id),\
309 static const struct dce110_clk_src_regs clk_src_regs
[] = {
315 static const struct dce110_clk_src_shift cs_shift
= {
316 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
319 static const struct dce110_clk_src_mask cs_mask
= {
320 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
325 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
327 static const struct bios_registers bios_regs
= {
328 .BIOS_SCRATCH_6
= mmBIOS_SCRATCH_6
331 static const struct resource_caps res_cap
= {
332 .num_timing_generator
= 6,
334 .num_stream_encoder
= 6,
339 #define REG(reg) mm ## reg
341 #ifndef mmCC_DC_HDMI_STRAPS
342 #define mmCC_DC_HDMI_STRAPS 0x1918
343 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
344 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
345 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
346 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
349 static void read_dce_straps(
350 struct dc_context
*ctx
,
351 struct resource_straps
*straps
)
353 REG_GET_2(CC_DC_HDMI_STRAPS
,
354 HDMI_DISABLE
, &straps
->hdmi_disable
,
355 AUDIO_STREAM_NUMBER
, &straps
->audio_stream_number
);
357 REG_GET(DC_PINSTRAPS
, DC_PINSTRAPS_AUDIO
, &straps
->dc_pinstraps_audio
);
360 static struct audio
*create_audio(
361 struct dc_context
*ctx
, unsigned int inst
)
363 return dce_audio_create(ctx
, inst
,
364 &audio_regs
[inst
], &audio_shift
, &audio_mask
);
367 static struct timing_generator
*dce100_timing_generator_create(
368 struct dc_context
*ctx
,
370 const struct dce110_timing_generator_offsets
*offsets
)
372 struct dce110_timing_generator
*tg110
=
373 dm_alloc(sizeof(struct dce110_timing_generator
));
378 if (dce110_timing_generator_construct(tg110
, ctx
, instance
,
387 static struct stream_encoder
*dce100_stream_encoder_create(
388 enum engine_id eng_id
,
389 struct dc_context
*ctx
)
391 struct dce110_stream_encoder
*enc110
=
392 dm_alloc(sizeof(struct dce110_stream_encoder
));
397 if (dce110_stream_encoder_construct(
398 enc110
, ctx
, ctx
->dc_bios
, eng_id
,
399 &stream_enc_regs
[eng_id
], &se_shift
, &se_mask
))
400 return &enc110
->base
;
407 #define SRII(reg_name, block, id)\
408 .reg_name[id] = mm ## block ## id ## _ ## reg_name
410 static const struct dce_hwseq_registers hwseq_reg
= {
411 HWSEQ_DCE10_REG_LIST()
414 static const struct dce_hwseq_shift hwseq_shift
= {
415 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT
)
418 static const struct dce_hwseq_mask hwseq_mask
= {
419 HWSEQ_DCE10_MASK_SH_LIST(_MASK
)
422 static struct dce_hwseq
*dce100_hwseq_create(
423 struct dc_context
*ctx
)
425 struct dce_hwseq
*hws
= dm_alloc(sizeof(struct dce_hwseq
));
429 hws
->regs
= &hwseq_reg
;
430 hws
->shifts
= &hwseq_shift
;
431 hws
->masks
= &hwseq_mask
;
436 static const struct resource_create_funcs res_create_funcs
= {
437 .read_dce_straps
= read_dce_straps
,
438 .create_audio
= create_audio
,
439 .create_stream_encoder
= dce100_stream_encoder_create
,
440 .create_hwseq
= dce100_hwseq_create
,
443 #define mi_inst_regs(id) { \
444 MI_DCE8_REG_LIST(id), \
445 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
447 static const struct dce_mem_input_registers mi_regs
[] = {
456 static const struct dce_mem_input_shift mi_shifts
= {
457 MI_DCE8_MASK_SH_LIST(__SHIFT
),
458 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
461 static const struct dce_mem_input_mask mi_masks
= {
462 MI_DCE8_MASK_SH_LIST(_MASK
),
463 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
466 static struct mem_input
*dce100_mem_input_create(
467 struct dc_context
*ctx
,
470 struct dce_mem_input
*dce_mi
= dm_alloc(sizeof(struct dce_mem_input
));
477 dce_mem_input_construct(dce_mi
, ctx
, inst
, &mi_regs
[inst
], &mi_shifts
, &mi_masks
);
478 dce_mi
->wa
.single_head_rdreq_dmif_limit
= 2;
479 return &dce_mi
->base
;
482 static void dce100_transform_destroy(struct transform
**xfm
)
484 dm_free(TO_DCE_TRANSFORM(*xfm
));
488 static struct transform
*dce100_transform_create(
489 struct dc_context
*ctx
,
492 struct dce_transform
*transform
=
493 dm_alloc(sizeof(struct dce_transform
));
498 if (dce_transform_construct(transform
, ctx
, inst
,
499 &xfm_regs
[inst
], &xfm_shift
, &xfm_mask
)) {
500 return &transform
->base
;
508 static struct input_pixel_processor
*dce100_ipp_create(
509 struct dc_context
*ctx
, uint32_t inst
)
511 struct dce_ipp
*ipp
= dm_alloc(sizeof(struct dce_ipp
));
518 dce_ipp_construct(ipp
, ctx
, inst
,
519 &ipp_regs
[inst
], &ipp_shift
, &ipp_mask
);
523 static const struct encoder_feature_support link_enc_feature
= {
524 .max_hdmi_deep_color
= COLOR_DEPTH_121212
,
525 .max_hdmi_pixel_clock
= 300000,
526 .flags
.bits
.IS_HBR2_CAPABLE
= true,
527 .flags
.bits
.IS_TPS3_CAPABLE
= true,
528 .flags
.bits
.IS_YCBCR_CAPABLE
= true
531 struct link_encoder
*dce100_link_encoder_create(
532 const struct encoder_init_data
*enc_init_data
)
534 struct dce110_link_encoder
*enc110
=
535 dm_alloc(sizeof(struct dce110_link_encoder
));
540 if (dce110_link_encoder_construct(
544 &link_enc_regs
[enc_init_data
->transmitter
],
545 &link_enc_aux_regs
[enc_init_data
->channel
- 1],
546 &link_enc_hpd_regs
[enc_init_data
->hpd_source
])) {
548 return &enc110
->base
;
556 struct output_pixel_processor
*dce100_opp_create(
557 struct dc_context
*ctx
,
560 struct dce110_opp
*opp
=
561 dm_alloc(sizeof(struct dce110_opp
));
566 if (dce110_opp_construct(opp
,
567 ctx
, inst
, &opp_regs
[inst
], &opp_shift
, &opp_mask
))
575 struct clock_source
*dce100_clock_source_create(
576 struct dc_context
*ctx
,
577 struct dc_bios
*bios
,
578 enum clock_source_id id
,
579 const struct dce110_clk_src_regs
*regs
,
582 struct dce110_clk_src
*clk_src
=
583 dm_alloc(sizeof(struct dce110_clk_src
));
588 if (dce110_clk_src_construct(clk_src
, ctx
, bios
, id
,
589 regs
, &cs_shift
, &cs_mask
)) {
590 clk_src
->base
.dp_clk_src
= dp_clk_src
;
591 return &clk_src
->base
;
598 void dce100_clock_source_destroy(struct clock_source
**clk_src
)
600 dm_free(TO_DCE110_CLK_SRC(*clk_src
));
604 static void destruct(struct dce110_resource_pool
*pool
)
608 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
609 if (pool
->base
.opps
[i
] != NULL
)
610 dce110_opp_destroy(&pool
->base
.opps
[i
]);
612 if (pool
->base
.transforms
[i
] != NULL
)
613 dce100_transform_destroy(&pool
->base
.transforms
[i
]);
615 if (pool
->base
.ipps
[i
] != NULL
)
616 dce_ipp_destroy(&pool
->base
.ipps
[i
]);
618 if (pool
->base
.mis
[i
] != NULL
) {
619 dm_free(TO_DCE_MEM_INPUT(pool
->base
.mis
[i
]));
620 pool
->base
.mis
[i
] = NULL
;
623 if (pool
->base
.timing_generators
[i
] != NULL
) {
624 dm_free(DCE110TG_FROM_TG(pool
->base
.timing_generators
[i
]));
625 pool
->base
.timing_generators
[i
] = NULL
;
629 for (i
= 0; i
< pool
->base
.stream_enc_count
; i
++) {
630 if (pool
->base
.stream_enc
[i
] != NULL
)
631 dm_free(DCE110STRENC_FROM_STRENC(pool
->base
.stream_enc
[i
]));
634 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
635 if (pool
->base
.clock_sources
[i
] != NULL
)
636 dce100_clock_source_destroy(&pool
->base
.clock_sources
[i
]);
639 if (pool
->base
.dp_clock_source
!= NULL
)
640 dce100_clock_source_destroy(&pool
->base
.dp_clock_source
);
642 for (i
= 0; i
< pool
->base
.audio_count
; i
++) {
643 if (pool
->base
.audios
[i
] != NULL
)
644 dce_aud_destroy(&pool
->base
.audios
[i
]);
647 if (pool
->base
.display_clock
!= NULL
)
648 dce_disp_clk_destroy(&pool
->base
.display_clock
);
650 if (pool
->base
.irqs
!= NULL
)
651 dal_irq_service_destroy(&pool
->base
.irqs
);
654 static enum dc_status
build_mapped_resource(
655 const struct core_dc
*dc
,
656 struct validate_context
*context
,
657 struct validate_context
*old_context
)
659 enum dc_status status
= DC_OK
;
662 for (i
= 0; i
< context
->stream_count
; i
++) {
663 struct dc_stream_state
*stream
= context
->streams
[i
];
665 if (old_context
&& resource_is_stream_unchanged(old_context
, stream
))
668 for (j
= 0; j
< MAX_PIPES
; j
++) {
669 struct pipe_ctx
*pipe_ctx
=
670 &context
->res_ctx
.pipe_ctx
[j
];
672 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
675 status
= dce110_resource_build_pipe_hw_param(pipe_ctx
);
680 resource_build_info_frame(pipe_ctx
);
682 /* do not need to validate non root pipes */
690 bool dce100_validate_bandwidth(
691 const struct core_dc
*dc
,
692 struct validate_context
*context
)
694 /* TODO implement when needed but for now hardcode max value*/
695 context
->bw
.dce
.dispclk_khz
= 681000;
696 context
->bw
.dce
.yclk_khz
= 250000 * MEMORY_TYPE_MULTIPLIER
;
701 static bool dce100_validate_surface_sets(
702 const struct dc_validation_set set
[],
707 for (i
= 0; i
< set_count
; i
++) {
708 if (set
[i
].surface_count
== 0)
711 if (set
[i
].surface_count
> 1)
714 if (set
[i
].surfaces
[0]->format
715 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
722 enum dc_status
dce100_validate_with_context(
723 const struct core_dc
*dc
,
724 const struct dc_validation_set set
[],
726 struct validate_context
*context
,
727 struct validate_context
*old_context
)
729 struct dc_context
*dc_ctx
= dc
->ctx
;
730 enum dc_status result
= DC_ERROR_UNEXPECTED
;
733 if (!dce100_validate_surface_sets(set
, set_count
))
734 return DC_FAIL_SURFACE_VALIDATE
;
736 for (i
= 0; i
< set_count
; i
++) {
737 context
->streams
[i
] = set
[i
].stream
;
738 dc_stream_retain(context
->streams
[i
]);
739 context
->stream_count
++;
742 result
= resource_map_pool_resources(dc
, context
, old_context
);
745 result
= resource_map_clock_resources(dc
, context
, old_context
);
747 if (!resource_validate_attach_surfaces(set
, set_count
,
748 old_context
, context
, dc
->res_pool
)) {
749 DC_ERROR("Failed to attach surface to stream!\n");
750 return DC_FAIL_ATTACH_SURFACES
;
754 result
= build_mapped_resource(dc
, context
, old_context
);
757 result
= resource_build_scaling_params_for_context(dc
, context
);
760 if (!dce100_validate_bandwidth(dc
, context
))
761 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
766 enum dc_status
dce100_validate_guaranteed(
767 const struct core_dc
*dc
,
768 struct dc_stream_state
*dc_stream
,
769 struct validate_context
*context
)
771 enum dc_status result
= DC_ERROR_UNEXPECTED
;
773 context
->streams
[0] = dc_stream
;
774 dc_stream_retain(context
->streams
[0]);
775 context
->stream_count
++;
777 result
= resource_map_pool_resources(dc
, context
, NULL
);
780 result
= resource_map_clock_resources(dc
, context
, NULL
);
783 result
= build_mapped_resource(dc
, context
, NULL
);
785 if (result
== DC_OK
) {
786 validate_guaranteed_copy_streams(
787 context
, dc
->public.caps
.max_streams
);
788 result
= resource_build_scaling_params_for_context(dc
, context
);
792 if (!dce100_validate_bandwidth(dc
, context
))
793 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
798 static void dce100_destroy_resource_pool(struct resource_pool
**pool
)
800 struct dce110_resource_pool
*dce110_pool
= TO_DCE110_RES_POOL(*pool
);
802 destruct(dce110_pool
);
803 dm_free(dce110_pool
);
807 enum dc_status
dce100_validate_plane(const struct dc_plane_state
*plane_state
)
810 if (plane_state
->format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
813 return DC_FAIL_SURFACE_VALIDATE
;
816 static const struct resource_funcs dce100_res_pool_funcs
= {
817 .destroy
= dce100_destroy_resource_pool
,
818 .link_enc_create
= dce100_link_encoder_create
,
819 .validate_with_context
= dce100_validate_with_context
,
820 .validate_guaranteed
= dce100_validate_guaranteed
,
821 .validate_bandwidth
= dce100_validate_bandwidth
,
822 .validate_plane
= dce100_validate_plane
,
825 static bool construct(
826 uint8_t num_virtual_links
,
828 struct dce110_resource_pool
*pool
)
831 struct dc_context
*ctx
= dc
->ctx
;
832 struct dc_firmware_info info
;
834 struct dm_pp_static_clock_info static_clk_info
= {0};
836 ctx
->dc_bios
->regs
= &bios_regs
;
838 pool
->base
.res_cap
= &res_cap
;
839 pool
->base
.funcs
= &dce100_res_pool_funcs
;
840 pool
->base
.underlay_pipe_index
= NO_UNDERLAY_PIPE
;
844 if ((bp
->funcs
->get_firmware_info(bp
, &info
) == BP_RESULT_OK
) &&
845 info
.external_clock_source_frequency_for_dp
!= 0) {
846 pool
->base
.dp_clock_source
=
847 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_EXTERNAL
, NULL
, true);
849 pool
->base
.clock_sources
[0] =
850 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL0
, &clk_src_regs
[0], false);
851 pool
->base
.clock_sources
[1] =
852 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL1
, &clk_src_regs
[1], false);
853 pool
->base
.clock_sources
[2] =
854 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL2
, &clk_src_regs
[2], false);
855 pool
->base
.clk_src_count
= 3;
858 pool
->base
.dp_clock_source
=
859 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL0
, &clk_src_regs
[0], true);
861 pool
->base
.clock_sources
[0] =
862 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL1
, &clk_src_regs
[1], false);
863 pool
->base
.clock_sources
[1] =
864 dce100_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL2
, &clk_src_regs
[2], false);
865 pool
->base
.clk_src_count
= 2;
868 if (pool
->base
.dp_clock_source
== NULL
) {
869 dm_error("DC: failed to create dp clock source!\n");
871 goto res_create_fail
;
874 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
875 if (pool
->base
.clock_sources
[i
] == NULL
) {
876 dm_error("DC: failed to create clock sources!\n");
878 goto res_create_fail
;
882 pool
->base
.display_clock
= dce_disp_clk_create(ctx
,
886 if (pool
->base
.display_clock
== NULL
) {
887 dm_error("DC: failed to create display clock!\n");
889 goto res_create_fail
;
893 /* get static clock information for PPLIB or firmware, save
896 if (dm_pp_get_static_clocks(ctx
, &static_clk_info
))
897 pool
->base
.display_clock
->max_clks_state
=
898 static_clk_info
.max_clocks_state
;
900 struct irq_service_init_data init_data
;
901 init_data
.ctx
= dc
->ctx
;
902 pool
->base
.irqs
= dal_irq_service_dce110_create(&init_data
);
903 if (!pool
->base
.irqs
)
904 goto res_create_fail
;
907 /*************************************************
908 * Resource + asic cap harcoding *
909 *************************************************/
910 pool
->base
.underlay_pipe_index
= NO_UNDERLAY_PIPE
;
911 pool
->base
.pipe_count
= res_cap
.num_timing_generator
;
912 dc
->public.caps
.max_downscale_ratio
= 200;
913 dc
->public.caps
.i2c_speed_in_khz
= 40;
914 dc
->public.caps
.max_cursor_size
= 128;
916 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
917 pool
->base
.timing_generators
[i
] =
918 dce100_timing_generator_create(
921 &dce100_tg_offsets
[i
]);
922 if (pool
->base
.timing_generators
[i
] == NULL
) {
924 dm_error("DC: failed to create tg!\n");
925 goto res_create_fail
;
928 pool
->base
.mis
[i
] = dce100_mem_input_create(ctx
, i
);
929 if (pool
->base
.mis
[i
] == NULL
) {
932 "DC: failed to create memory input!\n");
933 goto res_create_fail
;
936 pool
->base
.ipps
[i
] = dce100_ipp_create(ctx
, i
);
937 if (pool
->base
.ipps
[i
] == NULL
) {
940 "DC: failed to create input pixel processor!\n");
941 goto res_create_fail
;
944 pool
->base
.transforms
[i
] = dce100_transform_create(ctx
, i
);
945 if (pool
->base
.transforms
[i
] == NULL
) {
948 "DC: failed to create transform!\n");
949 goto res_create_fail
;
952 pool
->base
.opps
[i
] = dce100_opp_create(ctx
, i
);
953 if (pool
->base
.opps
[i
] == NULL
) {
956 "DC: failed to create output pixel processor!\n");
957 goto res_create_fail
;
961 dc
->public.caps
.max_surfaces
= pool
->base
.pipe_count
;
963 if (!resource_construct(num_virtual_links
, dc
, &pool
->base
,
965 goto res_create_fail
;
967 /* Create hardware sequencer */
968 if (!dce100_hw_sequencer_construct(dc
))
969 goto res_create_fail
;
979 struct resource_pool
*dce100_create_resource_pool(
980 uint8_t num_virtual_links
,
983 struct dce110_resource_pool
*pool
=
984 dm_alloc(sizeof(struct dce110_resource_pool
));
989 if (construct(num_virtual_links
, dc
, pool
))