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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_hw_sequencer.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dc.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
30 #include "resource.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35 #include "gpio_service_interface.h"
36
37 #if defined(CONFIG_DRM_AMD_DC_FBC)
38 #include "dce110_compressor.h"
39 #endif
40
41 #include "bios/bios_parser_helper.h"
42 #include "timing_generator.h"
43 #include "mem_input.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "transform.h"
47 #include "stream_encoder.h"
48 #include "link_encoder.h"
49 #include "link_hwss.h"
50 #include "clock_source.h"
51 #include "abm.h"
52 #include "audio.h"
53 #include "reg_helper.h"
54
55 /* include DCE11 register header files */
56 #include "dce/dce_11_0_d.h"
57 #include "dce/dce_11_0_sh_mask.h"
58 #include "custom_float.h"
59
60 /*
61 * All values are in milliseconds;
62 * For eDP, after power-up/power/down,
63 * 300/500 msec max. delay from LCDVCC to black video generation
64 */
65 #define PANEL_POWER_UP_TIMEOUT 300
66 #define PANEL_POWER_DOWN_TIMEOUT 500
67 #define HPD_CHECK_INTERVAL 10
68
69 #define CTX \
70 hws->ctx
71 #define REG(reg)\
72 hws->regs->reg
73
74 #undef FN
75 #define FN(reg_name, field_name) \
76 hws->shifts->field_name, hws->masks->field_name
77
78 struct dce110_hw_seq_reg_offsets {
79 uint32_t crtc;
80 };
81
82 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
83 {
84 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
85 },
86 {
87 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
88 },
89 {
90 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
91 },
92 {
93 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
94 }
95 };
96
97 #define HW_REG_BLND(reg, id)\
98 (reg + reg_offsets[id].blnd)
99
100 #define HW_REG_CRTC(reg, id)\
101 (reg + reg_offsets[id].crtc)
102
103 #define MAX_WATERMARK 0xFFFF
104 #define SAFE_NBP_MARK 0x7FFF
105
106 /*******************************************************************************
107 * Private definitions
108 ******************************************************************************/
109 /***************************PIPE_CONTROL***********************************/
110 static void dce110_init_pte(struct dc_context *ctx)
111 {
112 uint32_t addr;
113 uint32_t value = 0;
114 uint32_t chunk_int = 0;
115 uint32_t chunk_mul = 0;
116
117 addr = mmUNP_DVMM_PTE_CONTROL;
118 value = dm_read_reg(ctx, addr);
119
120 set_reg_field_value(
121 value,
122 0,
123 DVMM_PTE_CONTROL,
124 DVMM_USE_SINGLE_PTE);
125
126 set_reg_field_value(
127 value,
128 1,
129 DVMM_PTE_CONTROL,
130 DVMM_PTE_BUFFER_MODE0);
131
132 set_reg_field_value(
133 value,
134 1,
135 DVMM_PTE_CONTROL,
136 DVMM_PTE_BUFFER_MODE1);
137
138 dm_write_reg(ctx, addr, value);
139
140 addr = mmDVMM_PTE_REQ;
141 value = dm_read_reg(ctx, addr);
142
143 chunk_int = get_reg_field_value(
144 value,
145 DVMM_PTE_REQ,
146 HFLIP_PTEREQ_PER_CHUNK_INT);
147
148 chunk_mul = get_reg_field_value(
149 value,
150 DVMM_PTE_REQ,
151 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
152
153 if (chunk_int != 0x4 || chunk_mul != 0x4) {
154
155 set_reg_field_value(
156 value,
157 255,
158 DVMM_PTE_REQ,
159 MAX_PTEREQ_TO_ISSUE);
160
161 set_reg_field_value(
162 value,
163 4,
164 DVMM_PTE_REQ,
165 HFLIP_PTEREQ_PER_CHUNK_INT);
166
167 set_reg_field_value(
168 value,
169 4,
170 DVMM_PTE_REQ,
171 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
172
173 dm_write_reg(ctx, addr, value);
174 }
175 }
176 /**************************************************************************/
177
178 static void enable_display_pipe_clock_gating(
179 struct dc_context *ctx,
180 bool clock_gating)
181 {
182 /*TODO*/
183 }
184
185 static bool dce110_enable_display_power_gating(
186 struct dc *dc,
187 uint8_t controller_id,
188 struct dc_bios *dcb,
189 enum pipe_gating_control power_gating)
190 {
191 enum bp_result bp_result = BP_RESULT_OK;
192 enum bp_pipe_control_action cntl;
193 struct dc_context *ctx = dc->ctx;
194 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
195
196 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
197 return true;
198
199 if (power_gating == PIPE_GATING_CONTROL_INIT)
200 cntl = ASIC_PIPE_INIT;
201 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
202 cntl = ASIC_PIPE_ENABLE;
203 else
204 cntl = ASIC_PIPE_DISABLE;
205
206 if (controller_id == underlay_idx)
207 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
208
209 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
210
211 bp_result = dcb->funcs->enable_disp_power_gating(
212 dcb, controller_id + 1, cntl);
213
214 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
215 * by default when command table is called
216 *
217 * Bios parser accepts controller_id = 6 as indicative of
218 * underlay pipe in dce110. But we do not support more
219 * than 3.
220 */
221 if (controller_id < CONTROLLER_ID_MAX - 1)
222 dm_write_reg(ctx,
223 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
224 0);
225 }
226
227 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
228 dce110_init_pte(ctx);
229
230 if (bp_result == BP_RESULT_OK)
231 return true;
232 else
233 return false;
234 }
235
236 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
237 const struct dc_plane_state *plane_state)
238 {
239 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
240
241 switch (plane_state->format) {
242 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
243 prescale_params->scale = 0x2082;
244 break;
245 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
246 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
247 prescale_params->scale = 0x2020;
248 break;
249 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
250 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
251 prescale_params->scale = 0x2008;
252 break;
253 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
255 prescale_params->scale = 0x2000;
256 break;
257 default:
258 ASSERT(false);
259 break;
260 }
261 }
262
263 static bool dce110_set_input_transfer_func(
264 struct pipe_ctx *pipe_ctx,
265 const struct dc_plane_state *plane_state)
266 {
267 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
268 const struct dc_transfer_func *tf = NULL;
269 struct ipp_prescale_params prescale_params = { 0 };
270 bool result = true;
271
272 if (ipp == NULL)
273 return false;
274
275 if (plane_state->in_transfer_func)
276 tf = plane_state->in_transfer_func;
277
278 build_prescale_params(&prescale_params, plane_state);
279 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
280
281 if (plane_state->gamma_correction && dce_use_lut(plane_state))
282 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
283
284 if (tf == NULL) {
285 /* Default case if no input transfer function specified */
286 ipp->funcs->ipp_set_degamma(ipp,
287 IPP_DEGAMMA_MODE_HW_sRGB);
288 } else if (tf->type == TF_TYPE_PREDEFINED) {
289 switch (tf->tf) {
290 case TRANSFER_FUNCTION_SRGB:
291 ipp->funcs->ipp_set_degamma(ipp,
292 IPP_DEGAMMA_MODE_HW_sRGB);
293 break;
294 case TRANSFER_FUNCTION_BT709:
295 ipp->funcs->ipp_set_degamma(ipp,
296 IPP_DEGAMMA_MODE_HW_xvYCC);
297 break;
298 case TRANSFER_FUNCTION_LINEAR:
299 ipp->funcs->ipp_set_degamma(ipp,
300 IPP_DEGAMMA_MODE_BYPASS);
301 break;
302 case TRANSFER_FUNCTION_PQ:
303 result = false;
304 break;
305 default:
306 result = false;
307 break;
308 }
309 } else if (tf->type == TF_TYPE_BYPASS) {
310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
311 } else {
312 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
313 result = false;
314 }
315
316 return result;
317 }
318
319 static bool convert_to_custom_float(
320 struct pwl_result_data *rgb_resulted,
321 struct curve_points *arr_points,
322 uint32_t hw_points_num)
323 {
324 struct custom_float_format fmt;
325
326 struct pwl_result_data *rgb = rgb_resulted;
327
328 uint32_t i = 0;
329
330 fmt.exponenta_bits = 6;
331 fmt.mantissa_bits = 12;
332 fmt.sign = true;
333
334 if (!convert_to_custom_float_format(
335 arr_points[0].x,
336 &fmt,
337 &arr_points[0].custom_float_x)) {
338 BREAK_TO_DEBUGGER();
339 return false;
340 }
341
342 if (!convert_to_custom_float_format(
343 arr_points[0].offset,
344 &fmt,
345 &arr_points[0].custom_float_offset)) {
346 BREAK_TO_DEBUGGER();
347 return false;
348 }
349
350 if (!convert_to_custom_float_format(
351 arr_points[0].slope,
352 &fmt,
353 &arr_points[0].custom_float_slope)) {
354 BREAK_TO_DEBUGGER();
355 return false;
356 }
357
358 fmt.mantissa_bits = 10;
359 fmt.sign = false;
360
361 if (!convert_to_custom_float_format(
362 arr_points[1].x,
363 &fmt,
364 &arr_points[1].custom_float_x)) {
365 BREAK_TO_DEBUGGER();
366 return false;
367 }
368
369 if (!convert_to_custom_float_format(
370 arr_points[1].y,
371 &fmt,
372 &arr_points[1].custom_float_y)) {
373 BREAK_TO_DEBUGGER();
374 return false;
375 }
376
377 if (!convert_to_custom_float_format(
378 arr_points[2].slope,
379 &fmt,
380 &arr_points[2].custom_float_slope)) {
381 BREAK_TO_DEBUGGER();
382 return false;
383 }
384
385 fmt.mantissa_bits = 12;
386 fmt.sign = true;
387
388 while (i != hw_points_num) {
389 if (!convert_to_custom_float_format(
390 rgb->red,
391 &fmt,
392 &rgb->red_reg)) {
393 BREAK_TO_DEBUGGER();
394 return false;
395 }
396
397 if (!convert_to_custom_float_format(
398 rgb->green,
399 &fmt,
400 &rgb->green_reg)) {
401 BREAK_TO_DEBUGGER();
402 return false;
403 }
404
405 if (!convert_to_custom_float_format(
406 rgb->blue,
407 &fmt,
408 &rgb->blue_reg)) {
409 BREAK_TO_DEBUGGER();
410 return false;
411 }
412
413 if (!convert_to_custom_float_format(
414 rgb->delta_red,
415 &fmt,
416 &rgb->delta_red_reg)) {
417 BREAK_TO_DEBUGGER();
418 return false;
419 }
420
421 if (!convert_to_custom_float_format(
422 rgb->delta_green,
423 &fmt,
424 &rgb->delta_green_reg)) {
425 BREAK_TO_DEBUGGER();
426 return false;
427 }
428
429 if (!convert_to_custom_float_format(
430 rgb->delta_blue,
431 &fmt,
432 &rgb->delta_blue_reg)) {
433 BREAK_TO_DEBUGGER();
434 return false;
435 }
436
437 ++rgb;
438 ++i;
439 }
440
441 return true;
442 }
443
444 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
445 *output_tf, struct pwl_params *regamma_params)
446 {
447 struct curve_points *arr_points;
448 struct pwl_result_data *rgb_resulted;
449 struct pwl_result_data *rgb;
450 struct pwl_result_data *rgb_plus_1;
451 struct fixed31_32 y_r;
452 struct fixed31_32 y_g;
453 struct fixed31_32 y_b;
454 struct fixed31_32 y1_min;
455 struct fixed31_32 y3_max;
456
457 int32_t segment_start, segment_end;
458 uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
459
460 if (output_tf == NULL || regamma_params == NULL ||
461 output_tf->type == TF_TYPE_BYPASS)
462 return false;
463
464 arr_points = regamma_params->arr_points;
465 rgb_resulted = regamma_params->rgb_resulted;
466 hw_points = 0;
467
468 memset(regamma_params, 0, sizeof(struct pwl_params));
469
470 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
471 /* 16 segments
472 * segments are from 2^-11 to 2^5
473 */
474 segment_start = -11;
475 segment_end = 5;
476
477 seg_distr[0] = 2;
478 seg_distr[1] = 2;
479 seg_distr[2] = 2;
480 seg_distr[3] = 2;
481 seg_distr[4] = 2;
482 seg_distr[5] = 2;
483 seg_distr[6] = 3;
484 seg_distr[7] = 4;
485 seg_distr[8] = 4;
486 seg_distr[9] = 4;
487 seg_distr[10] = 4;
488 seg_distr[11] = 5;
489 seg_distr[12] = 5;
490 seg_distr[13] = 5;
491 seg_distr[14] = 5;
492 seg_distr[15] = 5;
493
494 } else {
495 /* 10 segments
496 * segment is from 2^-10 to 2^0
497 */
498 segment_start = -10;
499 segment_end = 0;
500
501 seg_distr[0] = 3;
502 seg_distr[1] = 4;
503 seg_distr[2] = 4;
504 seg_distr[3] = 4;
505 seg_distr[4] = 4;
506 seg_distr[5] = 4;
507 seg_distr[6] = 4;
508 seg_distr[7] = 4;
509 seg_distr[8] = 5;
510 seg_distr[9] = 5;
511 seg_distr[10] = -1;
512 seg_distr[11] = -1;
513 seg_distr[12] = -1;
514 seg_distr[13] = -1;
515 seg_distr[14] = -1;
516 seg_distr[15] = -1;
517 }
518
519 for (k = 0; k < 16; k++) {
520 if (seg_distr[k] != -1)
521 hw_points += (1 << seg_distr[k]);
522 }
523
524 j = 0;
525 for (k = 0; k < (segment_end - segment_start); k++) {
526 increment = 32 / (1 << seg_distr[k]);
527 start_index = (segment_start + k + 25) * 32;
528 for (i = start_index; i < start_index + 32; i += increment) {
529 if (j == hw_points - 1)
530 break;
531 rgb_resulted[j].red = output_tf->tf_pts.red[i];
532 rgb_resulted[j].green = output_tf->tf_pts.green[i];
533 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
534 j++;
535 }
536 }
537
538 /* last point */
539 start_index = (segment_end + 25) * 32;
540 rgb_resulted[hw_points - 1].red =
541 output_tf->tf_pts.red[start_index];
542 rgb_resulted[hw_points - 1].green =
543 output_tf->tf_pts.green[start_index];
544 rgb_resulted[hw_points - 1].blue =
545 output_tf->tf_pts.blue[start_index];
546
547 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
548 dal_fixed31_32_from_int(segment_start));
549 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
550 dal_fixed31_32_from_int(segment_end));
551 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
552 dal_fixed31_32_from_int(segment_end));
553
554 y_r = rgb_resulted[0].red;
555 y_g = rgb_resulted[0].green;
556 y_b = rgb_resulted[0].blue;
557
558 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
559
560 arr_points[0].y = y1_min;
561 arr_points[0].slope = dal_fixed31_32_div(
562 arr_points[0].y,
563 arr_points[0].x);
564
565 y_r = rgb_resulted[hw_points - 1].red;
566 y_g = rgb_resulted[hw_points - 1].green;
567 y_b = rgb_resulted[hw_points - 1].blue;
568
569 /* see comment above, m_arrPoints[1].y should be the Y value for the
570 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
571 */
572 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
573
574 arr_points[1].y = y3_max;
575 arr_points[2].y = y3_max;
576
577 arr_points[1].slope = dal_fixed31_32_zero;
578 arr_points[2].slope = dal_fixed31_32_zero;
579
580 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
581 /* for PQ, we want to have a straight line from last HW X point,
582 * and the slope to be such that we hit 1.0 at 10000 nits.
583 */
584 const struct fixed31_32 end_value =
585 dal_fixed31_32_from_int(125);
586
587 arr_points[1].slope = dal_fixed31_32_div(
588 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
589 dal_fixed31_32_sub(end_value, arr_points[1].x));
590 arr_points[2].slope = dal_fixed31_32_div(
591 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
592 dal_fixed31_32_sub(end_value, arr_points[1].x));
593 }
594
595 regamma_params->hw_points_num = hw_points;
596
597 i = 1;
598 for (k = 0; k < 16 && i < 16; k++) {
599 if (seg_distr[k] != -1) {
600 regamma_params->arr_curve_points[k].segments_num =
601 seg_distr[k];
602 regamma_params->arr_curve_points[i].offset =
603 regamma_params->arr_curve_points[k].
604 offset + (1 << seg_distr[k]);
605 }
606 i++;
607 }
608
609 if (seg_distr[k] != -1)
610 regamma_params->arr_curve_points[k].segments_num =
611 seg_distr[k];
612
613 rgb = rgb_resulted;
614 rgb_plus_1 = rgb_resulted + 1;
615
616 i = 1;
617
618 while (i != hw_points + 1) {
619 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
620 rgb_plus_1->red = rgb->red;
621 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
622 rgb_plus_1->green = rgb->green;
623 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
624 rgb_plus_1->blue = rgb->blue;
625
626 rgb->delta_red = dal_fixed31_32_sub(
627 rgb_plus_1->red,
628 rgb->red);
629 rgb->delta_green = dal_fixed31_32_sub(
630 rgb_plus_1->green,
631 rgb->green);
632 rgb->delta_blue = dal_fixed31_32_sub(
633 rgb_plus_1->blue,
634 rgb->blue);
635
636 ++rgb_plus_1;
637 ++rgb;
638 ++i;
639 }
640
641 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
642
643 return true;
644 }
645
646 static bool dce110_set_output_transfer_func(
647 struct pipe_ctx *pipe_ctx,
648 const struct dc_stream_state *stream)
649 {
650 struct transform *xfm = pipe_ctx->plane_res.xfm;
651
652 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
653 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
654
655 if (stream->out_transfer_func &&
656 stream->out_transfer_func->type ==
657 TF_TYPE_PREDEFINED &&
658 stream->out_transfer_func->tf ==
659 TRANSFER_FUNCTION_SRGB) {
660 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
661 } else if (dce110_translate_regamma_to_hw_format(
662 stream->out_transfer_func, &xfm->regamma_params)) {
663 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
664 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
665 } else {
666 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
667 }
668
669 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
670
671 return true;
672 }
673
674 static enum dc_status bios_parser_crtc_source_select(
675 struct pipe_ctx *pipe_ctx)
676 {
677 struct dc_bios *dcb;
678 /* call VBIOS table to set CRTC source for the HW
679 * encoder block
680 * note: video bios clears all FMT setting here. */
681 struct bp_crtc_source_select crtc_source_select = {0};
682 const struct dc_sink *sink = pipe_ctx->stream->sink;
683
684 crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
685 crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
686 /*TODO: Need to un-hardcode color depth, dp_audio and account for
687 * the case where signal and sink signal is different (translator
688 * encoder)*/
689 crtc_source_select.signal = pipe_ctx->stream->signal;
690 crtc_source_select.enable_dp_audio = false;
691 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
692
693 switch (pipe_ctx->stream->timing.display_color_depth) {
694 case COLOR_DEPTH_666:
695 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
696 break;
697 case COLOR_DEPTH_888:
698 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
699 break;
700 case COLOR_DEPTH_101010:
701 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
702 break;
703 case COLOR_DEPTH_121212:
704 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
705 break;
706 default:
707 BREAK_TO_DEBUGGER();
708 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
709 break;
710 }
711
712 dcb = sink->ctx->dc_bios;
713
714 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
715 dcb,
716 &crtc_source_select)) {
717 return DC_ERROR_UNEXPECTED;
718 }
719
720 return DC_OK;
721 }
722
723 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
724 {
725 ASSERT(pipe_ctx->stream);
726
727 if (pipe_ctx->stream_res.stream_enc == NULL)
728 return; /* this is not root pipe */
729
730 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
731 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
732 pipe_ctx->stream_res.stream_enc,
733 &pipe_ctx->stream_res.encoder_info_frame);
734 else if (dc_is_dp_signal(pipe_ctx->stream->signal))
735 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
736 pipe_ctx->stream_res.stream_enc,
737 &pipe_ctx->stream_res.encoder_info_frame);
738 }
739
740 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
741 {
742 enum dc_lane_count lane_count =
743 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
744
745 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
746 struct dc_link *link = pipe_ctx->stream->sink->link;
747
748 /* 1. update AVI info frame (HDMI, DP)
749 * we always need to update info frame
750 */
751 uint32_t active_total_with_borders;
752 uint32_t early_control = 0;
753 struct timing_generator *tg = pipe_ctx->stream_res.tg;
754
755 /* TODOFPGA may change to hwss.update_info_frame */
756 dce110_update_info_frame(pipe_ctx);
757 /* enable early control to avoid corruption on DP monitor*/
758 active_total_with_borders =
759 timing->h_addressable
760 + timing->h_border_left
761 + timing->h_border_right;
762
763 if (lane_count != 0)
764 early_control = active_total_with_borders % lane_count;
765
766 if (early_control == 0)
767 early_control = lane_count;
768
769 tg->funcs->set_early_control(tg, early_control);
770
771 /* enable audio only within mode set */
772 if (pipe_ctx->stream_res.audio != NULL) {
773 if (dc_is_dp_signal(pipe_ctx->stream->signal))
774 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
775 }
776
777 /* For MST, there are multiply stream go to only one link.
778 * connect DIG back_end to front_end while enable_stream and
779 * disconnect them during disable_stream
780 * BY this, it is logic clean to separate stream and link */
781 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
782 pipe_ctx->stream_res.stream_enc->id, true);
783
784 }
785
786 /*todo: cloned in stream enc, fix*/
787 static bool is_panel_backlight_on(struct dce_hwseq *hws)
788 {
789 uint32_t value;
790
791 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
792
793 return value;
794 }
795
796 static bool is_panel_powered_on(struct dce_hwseq *hws)
797 {
798 uint32_t value;
799
800 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
801 return value == 1;
802 }
803
804 static enum bp_result link_transmitter_control(
805 struct dc_bios *bios,
806 struct bp_transmitter_control *cntl)
807 {
808 enum bp_result result;
809
810 result = bios->funcs->transmitter_control(bios, cntl);
811
812 return result;
813 }
814
815 /*
816 * @brief
817 * eDP only.
818 */
819 void hwss_edp_wait_for_hpd_ready(
820 struct dc_link *link,
821 bool power_up)
822 {
823 struct dc_context *ctx = link->ctx;
824 struct graphics_object_id connector = link->link_enc->connector;
825 struct gpio *hpd;
826 bool edp_hpd_high = false;
827 uint32_t time_elapsed = 0;
828 uint32_t timeout = power_up ?
829 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
830
831 if (dal_graphics_object_id_get_connector_id(connector)
832 != CONNECTOR_ID_EDP) {
833 BREAK_TO_DEBUGGER();
834 return;
835 }
836
837 if (!power_up)
838 /*
839 * From KV, we will not HPD low after turning off VCC -
840 * instead, we will check the SW timer in power_up().
841 */
842 return;
843
844 /*
845 * When we power on/off the eDP panel,
846 * we need to wait until SENSE bit is high/low.
847 */
848
849 /* obtain HPD */
850 /* TODO what to do with this? */
851 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
852
853 if (!hpd) {
854 BREAK_TO_DEBUGGER();
855 return;
856 }
857
858 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
859
860 /* wait until timeout or panel detected */
861
862 do {
863 uint32_t detected = 0;
864
865 dal_gpio_get_value(hpd, &detected);
866
867 if (!(detected ^ power_up)) {
868 edp_hpd_high = true;
869 break;
870 }
871
872 msleep(HPD_CHECK_INTERVAL);
873
874 time_elapsed += HPD_CHECK_INTERVAL;
875 } while (time_elapsed < timeout);
876
877 dal_gpio_close(hpd);
878
879 dal_gpio_destroy_irq(&hpd);
880
881 if (false == edp_hpd_high) {
882 dm_logger_write(ctx->logger, LOG_ERROR,
883 "%s: wait timed out!\n", __func__);
884 }
885 }
886
887 void hwss_edp_power_control(
888 struct dc_link *link,
889 bool power_up)
890 {
891 struct dc_context *ctx = link->ctx;
892 struct dce_hwseq *hwseq = ctx->dc->hwseq;
893 struct bp_transmitter_control cntl = { 0 };
894 enum bp_result bp_result;
895
896
897 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
898 != CONNECTOR_ID_EDP) {
899 BREAK_TO_DEBUGGER();
900 return;
901 }
902
903 if (power_up != is_panel_powered_on(hwseq)) {
904 /* Send VBIOS command to prompt eDP panel power */
905
906 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
907 "%s: Panel Power action: %s\n",
908 __func__, (power_up ? "On":"Off"));
909
910 cntl.action = power_up ?
911 TRANSMITTER_CONTROL_POWER_ON :
912 TRANSMITTER_CONTROL_POWER_OFF;
913 cntl.transmitter = link->link_enc->transmitter;
914 cntl.connector_obj_id = link->link_enc->connector;
915 cntl.coherent = false;
916 cntl.lanes_number = LANE_COUNT_FOUR;
917 cntl.hpd_sel = link->link_enc->hpd_source;
918
919 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
920
921 if (bp_result != BP_RESULT_OK)
922 dm_logger_write(ctx->logger, LOG_ERROR,
923 "%s: Panel Power bp_result: %d\n",
924 __func__, bp_result);
925 } else {
926 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
927 "%s: Skipping Panel Power action: %s\n",
928 __func__, (power_up ? "On":"Off"));
929 }
930 }
931
932 /*todo: cloned in stream enc, fix*/
933 /*
934 * @brief
935 * eDP only. Control the backlight of the eDP panel
936 */
937 void hwss_edp_backlight_control(
938 struct dc_link *link,
939 bool enable)
940 {
941 struct dc_context *ctx = link->ctx;
942 struct dce_hwseq *hws = ctx->dc->hwseq;
943 struct bp_transmitter_control cntl = { 0 };
944
945 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
946 != CONNECTOR_ID_EDP) {
947 BREAK_TO_DEBUGGER();
948 return;
949 }
950
951 if (enable && is_panel_backlight_on(hws)) {
952 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
953 "%s: panel already powered up. Do nothing.\n",
954 __func__);
955 return;
956 }
957
958 /* Send VBIOS command to control eDP panel backlight */
959
960 dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
961 "%s: backlight action: %s\n",
962 __func__, (enable ? "On":"Off"));
963
964 cntl.action = enable ?
965 TRANSMITTER_CONTROL_BACKLIGHT_ON :
966 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
967
968 /*cntl.engine_id = ctx->engine;*/
969 cntl.transmitter = link->link_enc->transmitter;
970 cntl.connector_obj_id = link->link_enc->connector;
971 /*todo: unhardcode*/
972 cntl.lanes_number = LANE_COUNT_FOUR;
973 cntl.hpd_sel = link->link_enc->hpd_source;
974
975 /* For eDP, the following delays might need to be considered
976 * after link training completed:
977 * idle period - min. accounts for required BS-Idle pattern,
978 * max. allows for source frame synchronization);
979 * 50 msec max. delay from valid video data from source
980 * to video on dislpay or backlight enable.
981 *
982 * Disable the delay for now.
983 * Enable it in the future if necessary.
984 */
985 /* dc_service_sleep_in_milliseconds(50); */
986 link_transmitter_control(ctx->dc_bios, &cntl);
987 }
988
989 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
990 {
991 struct dc_stream_state *stream = pipe_ctx->stream;
992 struct dc_link *link = stream->sink->link;
993 struct dc *dc = pipe_ctx->stream->ctx->dc;
994
995 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
996 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
997 pipe_ctx->stream_res.stream_enc);
998
999 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1000 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1001 pipe_ctx->stream_res.stream_enc);
1002
1003 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1004 pipe_ctx->stream_res.stream_enc, true);
1005 if (pipe_ctx->stream_res.audio) {
1006 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1007
1008 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1009 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1010 pipe_ctx->stream_res.stream_enc);
1011 else
1012 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1013 pipe_ctx->stream_res.stream_enc);
1014 /*don't free audio if it is from retrain or internal disable stream*/
1015 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1016 /*we have to dynamic arbitrate the audio endpoints*/
1017 pipe_ctx->stream_res.audio = NULL;
1018 /*we free the resource, need reset is_audio_acquired*/
1019 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1020 }
1021
1022 /* TODO: notify audio driver for if audio modes list changed
1023 * add audio mode list change flag */
1024 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1025 * stream->stream_engine_id);
1026 */
1027 }
1028
1029 /* blank at encoder level */
1030 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1031 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1032
1033 link->link_enc->funcs->connect_dig_be_to_fe(
1034 link->link_enc,
1035 pipe_ctx->stream_res.stream_enc->id,
1036 false);
1037
1038 }
1039
1040 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1041 struct dc_link_settings *link_settings)
1042 {
1043 struct encoder_unblank_param params = { { 0 } };
1044 struct dc_stream_state *stream = pipe_ctx->stream;
1045 struct dc_link *link = stream->sink->link;
1046
1047 /* only 3 items below are used by unblank */
1048 params.pixel_clk_khz =
1049 pipe_ctx->stream->timing.pix_clk_khz;
1050 params.link_settings.link_rate = link_settings->link_rate;
1051
1052 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1053 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1054
1055 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1056 link->dc->hwss.edp_backlight_control(link, true);
1057 }
1058 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1059 {
1060 struct dc_stream_state *stream = pipe_ctx->stream;
1061 struct dc_link *link = stream->sink->link;
1062
1063 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1064 link->dc->hwss.edp_backlight_control(link, false);
1065
1066 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1067 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1068 }
1069
1070
1071 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1072 {
1073 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1074 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1075 }
1076
1077 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1078 {
1079 switch (crtc_id) {
1080 case CONTROLLER_ID_D0:
1081 return DTO_SOURCE_ID0;
1082 case CONTROLLER_ID_D1:
1083 return DTO_SOURCE_ID1;
1084 case CONTROLLER_ID_D2:
1085 return DTO_SOURCE_ID2;
1086 case CONTROLLER_ID_D3:
1087 return DTO_SOURCE_ID3;
1088 case CONTROLLER_ID_D4:
1089 return DTO_SOURCE_ID4;
1090 case CONTROLLER_ID_D5:
1091 return DTO_SOURCE_ID5;
1092 default:
1093 return DTO_SOURCE_UNKNOWN;
1094 }
1095 }
1096
1097 static void build_audio_output(
1098 struct dc_state *state,
1099 const struct pipe_ctx *pipe_ctx,
1100 struct audio_output *audio_output)
1101 {
1102 const struct dc_stream_state *stream = pipe_ctx->stream;
1103 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1104
1105 audio_output->signal = pipe_ctx->stream->signal;
1106
1107 /* audio_crtc_info */
1108
1109 audio_output->crtc_info.h_total =
1110 stream->timing.h_total;
1111
1112 /*
1113 * Audio packets are sent during actual CRTC blank physical signal, we
1114 * need to specify actual active signal portion
1115 */
1116 audio_output->crtc_info.h_active =
1117 stream->timing.h_addressable
1118 + stream->timing.h_border_left
1119 + stream->timing.h_border_right;
1120
1121 audio_output->crtc_info.v_active =
1122 stream->timing.v_addressable
1123 + stream->timing.v_border_top
1124 + stream->timing.v_border_bottom;
1125
1126 audio_output->crtc_info.pixel_repetition = 1;
1127
1128 audio_output->crtc_info.interlaced =
1129 stream->timing.flags.INTERLACE;
1130
1131 audio_output->crtc_info.refresh_rate =
1132 (stream->timing.pix_clk_khz*1000)/
1133 (stream->timing.h_total*stream->timing.v_total);
1134
1135 audio_output->crtc_info.color_depth =
1136 stream->timing.display_color_depth;
1137
1138 audio_output->crtc_info.requested_pixel_clock =
1139 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1140
1141 audio_output->crtc_info.calculated_pixel_clock =
1142 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1143
1144 /*for HDMI, audio ACR is with deep color ratio factor*/
1145 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1146 audio_output->crtc_info.requested_pixel_clock ==
1147 stream->timing.pix_clk_khz) {
1148 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1149 audio_output->crtc_info.requested_pixel_clock =
1150 audio_output->crtc_info.requested_pixel_clock/2;
1151 audio_output->crtc_info.calculated_pixel_clock =
1152 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1153
1154 }
1155 }
1156
1157 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1158 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1159 audio_output->pll_info.dp_dto_source_clock_in_khz =
1160 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1161 state->dis_clk);
1162 }
1163
1164 audio_output->pll_info.feed_back_divider =
1165 pipe_ctx->pll_settings.feedback_divider;
1166
1167 audio_output->pll_info.dto_source =
1168 translate_to_dto_source(
1169 pipe_ctx->pipe_idx + 1);
1170
1171 /* TODO hard code to enable for now. Need get from stream */
1172 audio_output->pll_info.ss_enabled = true;
1173
1174 audio_output->pll_info.ss_percentage =
1175 pipe_ctx->pll_settings.ss_percentage;
1176 }
1177
1178 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1179 struct tg_color *color)
1180 {
1181 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
1182
1183 switch (pipe_ctx->plane_res.scl_data.format) {
1184 case PIXEL_FORMAT_ARGB8888:
1185 /* set boarder color to red */
1186 color->color_r_cr = color_value;
1187 break;
1188
1189 case PIXEL_FORMAT_ARGB2101010:
1190 /* set boarder color to blue */
1191 color->color_b_cb = color_value;
1192 break;
1193 case PIXEL_FORMAT_420BPP8:
1194 /* set boarder color to green */
1195 color->color_g_y = color_value;
1196 break;
1197 case PIXEL_FORMAT_420BPP10:
1198 /* set boarder color to yellow */
1199 color->color_g_y = color_value;
1200 color->color_r_cr = color_value;
1201 break;
1202 case PIXEL_FORMAT_FP16:
1203 /* set boarder color to white */
1204 color->color_r_cr = color_value;
1205 color->color_b_cb = color_value;
1206 color->color_g_y = color_value;
1207 break;
1208 default:
1209 break;
1210 }
1211 }
1212
1213 static void program_scaler(const struct dc *dc,
1214 const struct pipe_ctx *pipe_ctx)
1215 {
1216 struct tg_color color = {0};
1217
1218 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1219 /* TOFPGA */
1220 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1221 return;
1222 #endif
1223
1224 if (dc->debug.surface_visual_confirm)
1225 get_surface_visual_confirm_color(pipe_ctx, &color);
1226 else
1227 color_space_to_black_color(dc,
1228 pipe_ctx->stream->output_color_space,
1229 &color);
1230
1231 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1232 pipe_ctx->plane_res.xfm,
1233 pipe_ctx->plane_res.scl_data.lb_params.depth,
1234 &pipe_ctx->stream->bit_depth_params);
1235
1236 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1237 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1238 pipe_ctx->stream_res.tg,
1239 &color);
1240
1241 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1242 &pipe_ctx->plane_res.scl_data);
1243 }
1244
1245 static enum dc_status dce110_prog_pixclk_crtc_otg(
1246 struct pipe_ctx *pipe_ctx,
1247 struct dc_state *context,
1248 struct dc *dc)
1249 {
1250 struct dc_stream_state *stream = pipe_ctx->stream;
1251 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1252 pipe_ctx[pipe_ctx->pipe_idx];
1253 struct tg_color black_color = {0};
1254
1255 if (!pipe_ctx_old->stream) {
1256
1257 /* program blank color */
1258 color_space_to_black_color(dc,
1259 stream->output_color_space, &black_color);
1260 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1261 pipe_ctx->stream_res.tg,
1262 &black_color);
1263
1264 /*
1265 * Must blank CRTC after disabling power gating and before any
1266 * programming, otherwise CRTC will be hung in bad state
1267 */
1268 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1269
1270 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1271 pipe_ctx->clock_source,
1272 &pipe_ctx->stream_res.pix_clk_params,
1273 &pipe_ctx->pll_settings)) {
1274 BREAK_TO_DEBUGGER();
1275 return DC_ERROR_UNEXPECTED;
1276 }
1277
1278 pipe_ctx->stream_res.tg->funcs->program_timing(
1279 pipe_ctx->stream_res.tg,
1280 &stream->timing,
1281 true);
1282
1283 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1284 pipe_ctx->stream_res.tg,
1285 0x182);
1286 }
1287
1288 if (!pipe_ctx_old->stream) {
1289 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1290 pipe_ctx->stream_res.tg)) {
1291 BREAK_TO_DEBUGGER();
1292 return DC_ERROR_UNEXPECTED;
1293 }
1294 }
1295
1296
1297
1298 return DC_OK;
1299 }
1300
1301 static enum dc_status apply_single_controller_ctx_to_hw(
1302 struct pipe_ctx *pipe_ctx,
1303 struct dc_state *context,
1304 struct dc *dc)
1305 {
1306 struct dc_stream_state *stream = pipe_ctx->stream;
1307 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1308 pipe_ctx[pipe_ctx->pipe_idx];
1309
1310 /* */
1311 dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
1312
1313 /* FPGA does not program backend */
1314 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1315 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1316 pipe_ctx->stream_res.opp,
1317 COLOR_SPACE_YCBCR601,
1318 stream->timing.display_color_depth,
1319 pipe_ctx->stream->signal);
1320
1321 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1322 pipe_ctx->stream_res.opp,
1323 &stream->bit_depth_params,
1324 &stream->clamping);
1325 return DC_OK;
1326 }
1327 /* TODO: move to stream encoder */
1328 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1329 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1330 BREAK_TO_DEBUGGER();
1331 return DC_ERROR_UNEXPECTED;
1332 }
1333 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1334 pipe_ctx->stream_res.opp,
1335 COLOR_SPACE_YCBCR601,
1336 stream->timing.display_color_depth,
1337 pipe_ctx->stream->signal);
1338
1339 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1340 stream->sink->link->link_enc->funcs->setup(
1341 stream->sink->link->link_enc,
1342 pipe_ctx->stream->signal);
1343
1344 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1345 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1346 pipe_ctx->stream_res.stream_enc,
1347 pipe_ctx->stream_res.tg->inst,
1348 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1349
1350
1351 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1352 pipe_ctx->stream_res.opp,
1353 &stream->bit_depth_params,
1354 &stream->clamping);
1355
1356 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1357 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1358 pipe_ctx->stream_res.stream_enc,
1359 &stream->timing,
1360 stream->output_color_space);
1361
1362 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1363 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1364 pipe_ctx->stream_res.stream_enc,
1365 &stream->timing,
1366 stream->phy_pix_clk,
1367 pipe_ctx->stream_res.audio != NULL);
1368
1369 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1370 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1371 pipe_ctx->stream_res.stream_enc,
1372 &stream->timing,
1373 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1374 true : false);
1375
1376 resource_build_info_frame(pipe_ctx);
1377 dce110_update_info_frame(pipe_ctx);
1378 if (!pipe_ctx_old->stream) {
1379 if (!pipe_ctx->stream->dpms_off)
1380 core_link_enable_stream(context, pipe_ctx);
1381 }
1382
1383 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1384
1385 pipe_ctx->stream->sink->link->psr_enabled = false;
1386
1387 return DC_OK;
1388 }
1389
1390 /******************************************************************************/
1391
1392 static void power_down_encoders(struct dc *dc)
1393 {
1394 int i;
1395 enum connector_id connector_id;
1396 enum signal_type signal = SIGNAL_TYPE_NONE;
1397
1398 /* do not know BIOS back-front mapping, simply blank all. It will not
1399 * hurt for non-DP
1400 */
1401 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1402 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1403 dc->res_pool->stream_enc[i]);
1404 }
1405
1406 for (i = 0; i < dc->link_count; i++) {
1407 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1408 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1409 (connector_id == CONNECTOR_ID_EDP)) {
1410
1411 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1412 dp_receiver_power_ctrl(dc->links[i], false);
1413 if (connector_id == CONNECTOR_ID_EDP)
1414 signal = SIGNAL_TYPE_EDP;
1415 }
1416
1417 dc->links[i]->link_enc->funcs->disable_output(
1418 dc->links[i]->link_enc, signal);
1419 }
1420 }
1421
1422 static void power_down_controllers(struct dc *dc)
1423 {
1424 int i;
1425
1426 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1427 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1428 dc->res_pool->timing_generators[i]);
1429 }
1430 }
1431
1432 static void power_down_clock_sources(struct dc *dc)
1433 {
1434 int i;
1435
1436 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1437 dc->res_pool->dp_clock_source) == false)
1438 dm_error("Failed to power down pll! (dp clk src)\n");
1439
1440 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1441 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1442 dc->res_pool->clock_sources[i]) == false)
1443 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1444 }
1445 }
1446
1447 static void power_down_all_hw_blocks(struct dc *dc)
1448 {
1449 power_down_encoders(dc);
1450
1451 power_down_controllers(dc);
1452
1453 power_down_clock_sources(dc);
1454
1455 #if defined(CONFIG_DRM_AMD_DC_FBC)
1456 if (dc->fbc_compressor)
1457 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1458 #endif
1459 }
1460
1461 static void disable_vga_and_power_gate_all_controllers(
1462 struct dc *dc)
1463 {
1464 int i;
1465 struct timing_generator *tg;
1466 struct dc_context *ctx = dc->ctx;
1467
1468 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1469 tg = dc->res_pool->timing_generators[i];
1470
1471 if (tg->funcs->disable_vga)
1472 tg->funcs->disable_vga(tg);
1473
1474 /* Enable CLOCK gating for each pipe BEFORE controller
1475 * powergating. */
1476 enable_display_pipe_clock_gating(ctx,
1477 true);
1478
1479 dc->hwss.power_down_front_end(dc, i);
1480 }
1481 }
1482
1483 /**
1484 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1485 * 1. Power down all DC HW blocks
1486 * 2. Disable VGA engine on all controllers
1487 * 3. Enable power gating for controller
1488 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1489 */
1490 void dce110_enable_accelerated_mode(struct dc *dc)
1491 {
1492 power_down_all_hw_blocks(dc);
1493
1494 disable_vga_and_power_gate_all_controllers(dc);
1495 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1496 }
1497
1498 static uint32_t compute_pstate_blackout_duration(
1499 struct bw_fixed blackout_duration,
1500 const struct dc_stream_state *stream)
1501 {
1502 uint32_t total_dest_line_time_ns;
1503 uint32_t pstate_blackout_duration_ns;
1504
1505 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1506
1507 total_dest_line_time_ns = 1000000UL *
1508 stream->timing.h_total /
1509 stream->timing.pix_clk_khz +
1510 pstate_blackout_duration_ns;
1511
1512 return total_dest_line_time_ns;
1513 }
1514
1515 void dce110_set_displaymarks(
1516 const struct dc *dc,
1517 struct dc_state *context)
1518 {
1519 uint8_t i, num_pipes;
1520 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1521
1522 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1523 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1524 uint32_t total_dest_line_time_ns;
1525
1526 if (pipe_ctx->stream == NULL)
1527 continue;
1528
1529 total_dest_line_time_ns = compute_pstate_blackout_duration(
1530 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1531 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1532 pipe_ctx->plane_res.mi,
1533 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1534 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1535 context->bw.dce.urgent_wm_ns[num_pipes],
1536 total_dest_line_time_ns);
1537 if (i == underlay_idx) {
1538 num_pipes++;
1539 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1540 pipe_ctx->plane_res.mi,
1541 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1542 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1543 context->bw.dce.urgent_wm_ns[num_pipes],
1544 total_dest_line_time_ns);
1545 }
1546 num_pipes++;
1547 }
1548 }
1549
1550 static void set_safe_displaymarks(
1551 struct resource_context *res_ctx,
1552 const struct resource_pool *pool)
1553 {
1554 int i;
1555 int underlay_idx = pool->underlay_pipe_index;
1556 struct dce_watermarks max_marks = {
1557 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1558 struct dce_watermarks nbp_marks = {
1559 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1560
1561 for (i = 0; i < MAX_PIPES; i++) {
1562 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1563 continue;
1564
1565 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1566 res_ctx->pipe_ctx[i].plane_res.mi,
1567 nbp_marks,
1568 max_marks,
1569 max_marks,
1570 MAX_WATERMARK);
1571
1572 if (i == underlay_idx)
1573 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1574 res_ctx->pipe_ctx[i].plane_res.mi,
1575 nbp_marks,
1576 max_marks,
1577 max_marks,
1578 MAX_WATERMARK);
1579
1580 }
1581 }
1582
1583 /*******************************************************************************
1584 * Public functions
1585 ******************************************************************************/
1586
1587 static void set_drr(struct pipe_ctx **pipe_ctx,
1588 int num_pipes, int vmin, int vmax)
1589 {
1590 int i = 0;
1591 struct drr_params params = {0};
1592
1593 params.vertical_total_max = vmax;
1594 params.vertical_total_min = vmin;
1595
1596 /* TODO: If multiple pipes are to be supported, you need
1597 * some GSL stuff
1598 */
1599
1600 for (i = 0; i < num_pipes; i++) {
1601 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1602 }
1603 }
1604
1605 static void get_position(struct pipe_ctx **pipe_ctx,
1606 int num_pipes,
1607 struct crtc_position *position)
1608 {
1609 int i = 0;
1610
1611 /* TODO: handle pipes > 1
1612 */
1613 for (i = 0; i < num_pipes; i++)
1614 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1615 }
1616
1617 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1618 int num_pipes, const struct dc_static_screen_events *events)
1619 {
1620 unsigned int i;
1621 unsigned int value = 0;
1622
1623 if (events->overlay_update)
1624 value |= 0x100;
1625 if (events->surface_update)
1626 value |= 0x80;
1627 if (events->cursor_update)
1628 value |= 0x2;
1629
1630 #if defined(CONFIG_DRM_AMD_DC_FBC)
1631 value |= 0x84;
1632 #endif
1633
1634 for (i = 0; i < num_pipes; i++)
1635 pipe_ctx[i]->stream_res.tg->funcs->
1636 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1637 }
1638
1639 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1640 * may not be programmed yet.
1641 * TODO: after mode set, pre_mode_set = false,
1642 * may read PLL register to get pixel clock
1643 */
1644 static uint32_t get_max_pixel_clock_for_all_paths(
1645 struct dc *dc,
1646 struct dc_state *context,
1647 bool pre_mode_set)
1648 {
1649 uint32_t max_pix_clk = 0;
1650 int i;
1651
1652 if (!pre_mode_set) {
1653 /* TODO: read ASIC register to get pixel clock */
1654 ASSERT(0);
1655 }
1656
1657 for (i = 0; i < MAX_PIPES; i++) {
1658 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1659
1660 if (pipe_ctx->stream == NULL)
1661 continue;
1662
1663 /* do not check under lay */
1664 if (pipe_ctx->top_pipe)
1665 continue;
1666
1667 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1668 max_pix_clk =
1669 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1670 }
1671
1672 if (max_pix_clk == 0)
1673 ASSERT(0);
1674
1675 return max_pix_clk;
1676 }
1677
1678 /*
1679 * Find clock state based on clock requested. if clock value is 0, simply
1680 * set clock state as requested without finding clock state by clock value
1681 */
1682
1683 static void apply_min_clocks(
1684 struct dc *dc,
1685 struct dc_state *context,
1686 enum dm_pp_clocks_state *clocks_state,
1687 bool pre_mode_set)
1688 {
1689 struct state_dependent_clocks req_clocks = {0};
1690
1691 if (!pre_mode_set) {
1692 /* set clock_state without verification */
1693 if (context->dis_clk->funcs->set_min_clocks_state) {
1694 context->dis_clk->funcs->set_min_clocks_state(
1695 context->dis_clk, *clocks_state);
1696 return;
1697 }
1698
1699 /* TODO: This is incorrect. Figure out how to fix. */
1700 context->dis_clk->funcs->apply_clock_voltage_request(
1701 context->dis_clk,
1702 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1703 context->dis_clk->cur_clocks_value.dispclk_in_khz,
1704 pre_mode_set,
1705 false);
1706
1707 context->dis_clk->funcs->apply_clock_voltage_request(
1708 context->dis_clk,
1709 DM_PP_CLOCK_TYPE_PIXELCLK,
1710 context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1711 pre_mode_set,
1712 false);
1713
1714 context->dis_clk->funcs->apply_clock_voltage_request(
1715 context->dis_clk,
1716 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1717 context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1718 pre_mode_set,
1719 false);
1720 return;
1721 }
1722
1723 /* get the required state based on state dependent clocks:
1724 * display clock and pixel clock
1725 */
1726 req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1727
1728 req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1729 dc, context, true);
1730
1731 if (context->dis_clk->funcs->get_required_clocks_state) {
1732 *clocks_state = context->dis_clk->funcs->get_required_clocks_state(
1733 context->dis_clk, &req_clocks);
1734 context->dis_clk->funcs->set_min_clocks_state(
1735 context->dis_clk, *clocks_state);
1736 } else {
1737 context->dis_clk->funcs->apply_clock_voltage_request(
1738 context->dis_clk,
1739 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1740 req_clocks.display_clk_khz,
1741 pre_mode_set,
1742 false);
1743
1744 context->dis_clk->funcs->apply_clock_voltage_request(
1745 context->dis_clk,
1746 DM_PP_CLOCK_TYPE_PIXELCLK,
1747 req_clocks.pixel_clk_khz,
1748 pre_mode_set,
1749 false);
1750
1751 context->dis_clk->funcs->apply_clock_voltage_request(
1752 context->dis_clk,
1753 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1754 req_clocks.pixel_clk_khz,
1755 pre_mode_set,
1756 false);
1757 }
1758 }
1759
1760 #if defined(CONFIG_DRM_AMD_DC_FBC)
1761
1762 /*
1763 * Check if FBC can be enabled
1764 */
1765 static enum dc_status validate_fbc(struct dc *dc,
1766 struct dc_state *context)
1767 {
1768 struct pipe_ctx *pipe_ctx =
1769 &context->res_ctx.pipe_ctx[0];
1770
1771 ASSERT(dc->fbc_compressor);
1772
1773 /* FBC memory should be allocated */
1774 if (!dc->ctx->fbc_gpu_addr)
1775 return DC_ERROR_UNEXPECTED;
1776
1777 /* Only supports single display */
1778 if (context->stream_count != 1)
1779 return DC_ERROR_UNEXPECTED;
1780
1781 /* Only supports eDP */
1782 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1783 return DC_ERROR_UNEXPECTED;
1784
1785 /* PSR should not be enabled */
1786 if (pipe_ctx->stream->sink->link->psr_enabled)
1787 return DC_ERROR_UNEXPECTED;
1788
1789 /* Nothing to compress */
1790 if (!pipe_ctx->plane_state)
1791 return DC_ERROR_UNEXPECTED;
1792
1793 /* Only for non-linear tiling */
1794 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1795 return DC_ERROR_UNEXPECTED;
1796
1797 return DC_OK;
1798 }
1799
1800 /*
1801 * Enable FBC
1802 */
1803 static enum dc_status enable_fbc(struct dc *dc,
1804 struct dc_state *context)
1805 {
1806 enum dc_status status = validate_fbc(dc, context);
1807
1808 if (status == DC_OK) {
1809 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1810 struct compr_addr_and_pitch_params params = {0, 0, 0};
1811 struct compressor *compr = dc->fbc_compressor;
1812 struct pipe_ctx *pipe_ctx =
1813 &context->res_ctx.pipe_ctx[0];
1814
1815 params.source_view_width =
1816 pipe_ctx->stream->timing.h_addressable;
1817 params.source_view_height =
1818 pipe_ctx->stream->timing.v_addressable;
1819
1820 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1821
1822 compr->funcs->surface_address_and_pitch(compr, &params);
1823 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1824
1825 compr->funcs->enable_fbc(compr, &params);
1826 }
1827 return status;
1828 }
1829 #endif
1830
1831 static enum dc_status apply_ctx_to_hw_fpga(
1832 struct dc *dc,
1833 struct dc_state *context)
1834 {
1835 enum dc_status status = DC_ERROR_UNEXPECTED;
1836 int i;
1837
1838 for (i = 0; i < MAX_PIPES; i++) {
1839 struct pipe_ctx *pipe_ctx_old =
1840 &dc->current_state->res_ctx.pipe_ctx[i];
1841 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1842
1843 if (pipe_ctx->stream == NULL)
1844 continue;
1845
1846 if (pipe_ctx->stream == pipe_ctx_old->stream)
1847 continue;
1848
1849 status = apply_single_controller_ctx_to_hw(
1850 pipe_ctx,
1851 context,
1852 dc);
1853
1854 if (status != DC_OK)
1855 return status;
1856 }
1857
1858 return DC_OK;
1859 }
1860
1861 static void dce110_reset_hw_ctx_wrap(
1862 struct dc *dc,
1863 struct dc_state *context)
1864 {
1865 int i;
1866
1867 /* Reset old context */
1868 /* look up the targets that have been removed since last commit */
1869 for (i = 0; i < MAX_PIPES; i++) {
1870 struct pipe_ctx *pipe_ctx_old =
1871 &dc->current_state->res_ctx.pipe_ctx[i];
1872 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1873
1874 /* Note: We need to disable output if clock sources change,
1875 * since bios does optimization and doesn't apply if changing
1876 * PHY when not already disabled.
1877 */
1878
1879 /* Skip underlay pipe since it will be handled in commit surface*/
1880 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1881 continue;
1882
1883 if (!pipe_ctx->stream ||
1884 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1885 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1886
1887 /* Disable if new stream is null. O/w, if stream is
1888 * disabled already, no need to disable again.
1889 */
1890 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1891 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1892
1893 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1894 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1895 dm_error("DC: failed to blank crtc!\n");
1896 BREAK_TO_DEBUGGER();
1897 }
1898 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1899 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1900 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1901
1902 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1903 dc->res_pool,
1904 old_clk))
1905 old_clk->funcs->cs_power_down(old_clk);
1906
1907 dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
1908
1909 pipe_ctx_old->stream = NULL;
1910 }
1911 }
1912 }
1913
1914
1915 enum dc_status dce110_apply_ctx_to_hw(
1916 struct dc *dc,
1917 struct dc_state *context)
1918 {
1919 struct dc_bios *dcb = dc->ctx->dc_bios;
1920 enum dc_status status;
1921 int i;
1922 enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1923
1924 /* Reset old context */
1925 /* look up the targets that have been removed since last commit */
1926 dc->hwss.reset_hw_ctx_wrap(dc, context);
1927
1928 /* Skip applying if no targets */
1929 if (context->stream_count <= 0)
1930 return DC_OK;
1931
1932 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1933 apply_ctx_to_hw_fpga(dc, context);
1934 return DC_OK;
1935 }
1936
1937 /* Apply new context */
1938 dcb->funcs->set_scratch_critical_state(dcb, true);
1939
1940 /* below is for real asic only */
1941 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1942 struct pipe_ctx *pipe_ctx_old =
1943 &dc->current_state->res_ctx.pipe_ctx[i];
1944 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1945
1946 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1947 continue;
1948
1949 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1950 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1951 dce_crtc_switch_to_clk_src(dc->hwseq,
1952 pipe_ctx->clock_source, i);
1953 continue;
1954 }
1955
1956 dc->hwss.enable_display_power_gating(
1957 dc, i, dc->ctx->dc_bios,
1958 PIPE_GATING_CONTROL_DISABLE);
1959 }
1960
1961 set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1962
1963 #if defined(CONFIG_DRM_AMD_DC_FBC)
1964 if (dc->fbc_compressor)
1965 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1966 #endif
1967 /*TODO: when pplib works*/
1968 apply_min_clocks(dc, context, &clocks_state, true);
1969
1970 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1971 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1972 if (context->bw.dcn.calc_clk.fclk_khz
1973 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
1974 struct dm_pp_clock_for_voltage_req clock;
1975
1976 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1977 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1978 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1979 dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1980 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1981 }
1982 if (context->bw.dcn.calc_clk.dcfclk_khz
1983 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
1984 struct dm_pp_clock_for_voltage_req clock;
1985
1986 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1987 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1988 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1989 dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1990 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1991 }
1992 if (context->bw.dcn.calc_clk.dispclk_khz
1993 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
1994 dc->res_pool->display_clock->funcs->set_clock(
1995 dc->res_pool->display_clock,
1996 context->bw.dcn.calc_clk.dispclk_khz);
1997 dc->current_state->bw.dcn.cur_clk.dispclk_khz =
1998 context->bw.dcn.calc_clk.dispclk_khz;
1999 context->bw.dcn.cur_clk.dispclk_khz =
2000 context->bw.dcn.calc_clk.dispclk_khz;
2001 }
2002 } else
2003 #endif
2004 if (context->bw.dce.dispclk_khz
2005 > dc->current_state->bw.dce.dispclk_khz) {
2006 dc->res_pool->display_clock->funcs->set_clock(
2007 dc->res_pool->display_clock,
2008 context->bw.dce.dispclk_khz * 115 / 100);
2009 }
2010 /* program audio wall clock. use HDMI as clock source if HDMI
2011 * audio active. Otherwise, use DP as clock source
2012 * first, loop to find any HDMI audio, if not, loop find DP audio
2013 */
2014 /* Setup audio rate clock source */
2015 /* Issue:
2016 * Audio lag happened on DP monitor when unplug a HDMI monitor
2017 *
2018 * Cause:
2019 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2020 * is set to either dto0 or dto1, audio should work fine.
2021 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2022 * set to dto0 will cause audio lag.
2023 *
2024 * Solution:
2025 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2026 * find first available pipe with audio, setup audio wall DTO per topology
2027 * instead of per pipe.
2028 */
2029 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2030 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2031
2032 if (pipe_ctx->stream == NULL)
2033 continue;
2034
2035 if (pipe_ctx->top_pipe)
2036 continue;
2037
2038 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2039 continue;
2040
2041 if (pipe_ctx->stream_res.audio != NULL) {
2042 struct audio_output audio_output;
2043
2044 build_audio_output(context, pipe_ctx, &audio_output);
2045
2046 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2047 pipe_ctx->stream_res.audio,
2048 pipe_ctx->stream->signal,
2049 &audio_output.crtc_info,
2050 &audio_output.pll_info);
2051 break;
2052 }
2053 }
2054
2055 /* no HDMI audio is found, try DP audio */
2056 if (i == dc->res_pool->pipe_count) {
2057 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2058 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2059
2060 if (pipe_ctx->stream == NULL)
2061 continue;
2062
2063 if (pipe_ctx->top_pipe)
2064 continue;
2065
2066 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2067 continue;
2068
2069 if (pipe_ctx->stream_res.audio != NULL) {
2070 struct audio_output audio_output;
2071
2072 build_audio_output(context, pipe_ctx, &audio_output);
2073
2074 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2075 pipe_ctx->stream_res.audio,
2076 pipe_ctx->stream->signal,
2077 &audio_output.crtc_info,
2078 &audio_output.pll_info);
2079 break;
2080 }
2081 }
2082 }
2083
2084 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2085 struct pipe_ctx *pipe_ctx_old =
2086 &dc->current_state->res_ctx.pipe_ctx[i];
2087 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2088
2089 if (pipe_ctx->stream == NULL)
2090 continue;
2091
2092 if (pipe_ctx->stream == pipe_ctx_old->stream)
2093 continue;
2094
2095 if (pipe_ctx->stream && pipe_ctx_old->stream
2096 && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2097 continue;
2098
2099 if (pipe_ctx->top_pipe)
2100 continue;
2101
2102 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
2103
2104 struct audio_output audio_output;
2105
2106 build_audio_output(context, pipe_ctx, &audio_output);
2107
2108 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2109 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
2110 pipe_ctx->stream_res.stream_enc,
2111 pipe_ctx->stream_res.audio->inst,
2112 &pipe_ctx->stream->audio_info);
2113 else
2114 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
2115 pipe_ctx->stream_res.stream_enc,
2116 pipe_ctx->stream_res.audio->inst,
2117 &pipe_ctx->stream->audio_info,
2118 &audio_output.crtc_info);
2119
2120 pipe_ctx->stream_res.audio->funcs->az_configure(
2121 pipe_ctx->stream_res.audio,
2122 pipe_ctx->stream->signal,
2123 &audio_output.crtc_info,
2124 &pipe_ctx->stream->audio_info);
2125 }
2126
2127 status = apply_single_controller_ctx_to_hw(
2128 pipe_ctx,
2129 context,
2130 dc);
2131
2132 if (dc->hwss.power_on_front_end)
2133 dc->hwss.power_on_front_end(dc, pipe_ctx, context);
2134
2135 if (DC_OK != status)
2136 return status;
2137 }
2138
2139 /* pplib is notified if disp_num changed */
2140 dc->hwss.set_bandwidth(dc, context, true);
2141
2142 /* to save power */
2143 apply_min_clocks(dc, context, &clocks_state, false);
2144
2145 dcb->funcs->set_scratch_critical_state(dcb, false);
2146
2147 #if defined(CONFIG_DRM_AMD_DC_FBC)
2148 if (dc->fbc_compressor)
2149 enable_fbc(dc, context);
2150
2151 #endif
2152
2153 return DC_OK;
2154 }
2155
2156 /*******************************************************************************
2157 * Front End programming
2158 ******************************************************************************/
2159 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2160 {
2161 struct default_adjustment default_adjust = { 0 };
2162
2163 default_adjust.force_hw_default = false;
2164 if (pipe_ctx->plane_state == NULL)
2165 default_adjust.in_color_space = COLOR_SPACE_SRGB;
2166 else
2167 default_adjust.in_color_space =
2168 pipe_ctx->plane_state->color_space;
2169 if (pipe_ctx->stream == NULL)
2170 default_adjust.out_color_space = COLOR_SPACE_SRGB;
2171 else
2172 default_adjust.out_color_space =
2173 pipe_ctx->stream->output_color_space;
2174 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2175 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2176
2177 /* display color depth */
2178 default_adjust.color_depth =
2179 pipe_ctx->stream->timing.display_color_depth;
2180
2181 /* Lb color depth */
2182 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2183
2184 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2185 pipe_ctx->plane_res.xfm, &default_adjust);
2186 }
2187
2188
2189 /*******************************************************************************
2190 * In order to turn on/off specific surface we will program
2191 * Blender + CRTC
2192 *
2193 * In case that we have two surfaces and they have a different visibility
2194 * we can't turn off the CRTC since it will turn off the entire display
2195 *
2196 * |----------------------------------------------- |
2197 * |bottom pipe|curr pipe | | |
2198 * |Surface |Surface | Blender | CRCT |
2199 * |visibility |visibility | Configuration| |
2200 * |------------------------------------------------|
2201 * | off | off | CURRENT_PIPE | blank |
2202 * | off | on | CURRENT_PIPE | unblank |
2203 * | on | off | OTHER_PIPE | unblank |
2204 * | on | on | BLENDING | unblank |
2205 * -------------------------------------------------|
2206 *
2207 ******************************************************************************/
2208 static void program_surface_visibility(const struct dc *dc,
2209 struct pipe_ctx *pipe_ctx)
2210 {
2211 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2212 bool blank_target = false;
2213
2214 if (pipe_ctx->bottom_pipe) {
2215
2216 /* For now we are supporting only two pipes */
2217 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2218
2219 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2220 if (pipe_ctx->plane_state->visible)
2221 blender_mode = BLND_MODE_BLENDING;
2222 else
2223 blender_mode = BLND_MODE_OTHER_PIPE;
2224
2225 } else if (!pipe_ctx->plane_state->visible)
2226 blank_target = true;
2227
2228 } else if (!pipe_ctx->plane_state->visible)
2229 blank_target = true;
2230
2231 dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
2232 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2233
2234 }
2235
2236 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2237 {
2238 struct xfm_grph_csc_adjustment adjust;
2239 memset(&adjust, 0, sizeof(adjust));
2240 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2241
2242
2243 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2244 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2245 adjust.temperature_matrix[0] =
2246 pipe_ctx->stream->
2247 gamut_remap_matrix.matrix[0];
2248 adjust.temperature_matrix[1] =
2249 pipe_ctx->stream->
2250 gamut_remap_matrix.matrix[1];
2251 adjust.temperature_matrix[2] =
2252 pipe_ctx->stream->
2253 gamut_remap_matrix.matrix[2];
2254 adjust.temperature_matrix[3] =
2255 pipe_ctx->stream->
2256 gamut_remap_matrix.matrix[4];
2257 adjust.temperature_matrix[4] =
2258 pipe_ctx->stream->
2259 gamut_remap_matrix.matrix[5];
2260 adjust.temperature_matrix[5] =
2261 pipe_ctx->stream->
2262 gamut_remap_matrix.matrix[6];
2263 adjust.temperature_matrix[6] =
2264 pipe_ctx->stream->
2265 gamut_remap_matrix.matrix[8];
2266 adjust.temperature_matrix[7] =
2267 pipe_ctx->stream->
2268 gamut_remap_matrix.matrix[9];
2269 adjust.temperature_matrix[8] =
2270 pipe_ctx->stream->
2271 gamut_remap_matrix.matrix[10];
2272 }
2273
2274 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2275 }
2276
2277 /**
2278 * TODO REMOVE, USE UPDATE INSTEAD
2279 */
2280 static void set_plane_config(
2281 const struct dc *dc,
2282 struct pipe_ctx *pipe_ctx,
2283 struct resource_context *res_ctx)
2284 {
2285 struct mem_input *mi = pipe_ctx->plane_res.mi;
2286 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2287 struct xfm_grph_csc_adjustment adjust;
2288 struct out_csc_color_matrix tbl_entry;
2289 unsigned int i;
2290
2291 memset(&adjust, 0, sizeof(adjust));
2292 memset(&tbl_entry, 0, sizeof(tbl_entry));
2293 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2294
2295 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2296
2297 set_default_colors(pipe_ctx);
2298 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2299 == true) {
2300 tbl_entry.color_space =
2301 pipe_ctx->stream->output_color_space;
2302
2303 for (i = 0; i < 12; i++)
2304 tbl_entry.regval[i] =
2305 pipe_ctx->stream->csc_color_matrix.matrix[i];
2306
2307 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2308 (pipe_ctx->plane_res.xfm, &tbl_entry);
2309 }
2310
2311 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2312 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2313 adjust.temperature_matrix[0] =
2314 pipe_ctx->stream->
2315 gamut_remap_matrix.matrix[0];
2316 adjust.temperature_matrix[1] =
2317 pipe_ctx->stream->
2318 gamut_remap_matrix.matrix[1];
2319 adjust.temperature_matrix[2] =
2320 pipe_ctx->stream->
2321 gamut_remap_matrix.matrix[2];
2322 adjust.temperature_matrix[3] =
2323 pipe_ctx->stream->
2324 gamut_remap_matrix.matrix[4];
2325 adjust.temperature_matrix[4] =
2326 pipe_ctx->stream->
2327 gamut_remap_matrix.matrix[5];
2328 adjust.temperature_matrix[5] =
2329 pipe_ctx->stream->
2330 gamut_remap_matrix.matrix[6];
2331 adjust.temperature_matrix[6] =
2332 pipe_ctx->stream->
2333 gamut_remap_matrix.matrix[8];
2334 adjust.temperature_matrix[7] =
2335 pipe_ctx->stream->
2336 gamut_remap_matrix.matrix[9];
2337 adjust.temperature_matrix[8] =
2338 pipe_ctx->stream->
2339 gamut_remap_matrix.matrix[10];
2340 }
2341
2342 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2343
2344 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2345 program_scaler(dc, pipe_ctx);
2346
2347 program_surface_visibility(dc, pipe_ctx);
2348
2349 mi->funcs->mem_input_program_surface_config(
2350 mi,
2351 plane_state->format,
2352 &plane_state->tiling_info,
2353 &plane_state->plane_size,
2354 plane_state->rotation,
2355 NULL,
2356 false);
2357 if (mi->funcs->set_blank)
2358 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2359
2360 if (dc->config.gpu_vm_support)
2361 mi->funcs->mem_input_program_pte_vm(
2362 pipe_ctx->plane_res.mi,
2363 plane_state->format,
2364 &plane_state->tiling_info,
2365 plane_state->rotation);
2366 }
2367
2368 static void update_plane_addr(const struct dc *dc,
2369 struct pipe_ctx *pipe_ctx)
2370 {
2371 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2372
2373 if (plane_state == NULL)
2374 return;
2375
2376 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2377 pipe_ctx->plane_res.mi,
2378 &plane_state->address,
2379 plane_state->flip_immediate);
2380
2381 plane_state->status.requested_address = plane_state->address;
2382 }
2383
2384 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2385 {
2386 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2387
2388 if (plane_state == NULL)
2389 return;
2390
2391 plane_state->status.is_flip_pending =
2392 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2393 pipe_ctx->plane_res.mi);
2394
2395 if (plane_state->status.is_flip_pending && !plane_state->visible)
2396 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2397
2398 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2399 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2400 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2401 plane_state->status.is_right_eye =\
2402 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2403 }
2404 }
2405
2406 void dce110_power_down(struct dc *dc)
2407 {
2408 power_down_all_hw_blocks(dc);
2409 disable_vga_and_power_gate_all_controllers(dc);
2410 }
2411
2412 static bool wait_for_reset_trigger_to_occur(
2413 struct dc_context *dc_ctx,
2414 struct timing_generator *tg)
2415 {
2416 bool rc = false;
2417
2418 /* To avoid endless loop we wait at most
2419 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2420 const uint32_t frames_to_wait_on_triggered_reset = 10;
2421 uint32_t i;
2422
2423 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2424
2425 if (!tg->funcs->is_counter_moving(tg)) {
2426 DC_ERROR("TG counter is not moving!\n");
2427 break;
2428 }
2429
2430 if (tg->funcs->did_triggered_reset_occur(tg)) {
2431 rc = true;
2432 /* usually occurs at i=1 */
2433 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2434 i);
2435 break;
2436 }
2437
2438 /* Wait for one frame. */
2439 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2440 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2441 }
2442
2443 if (false == rc)
2444 DC_ERROR("GSL: Timeout on reset trigger!\n");
2445
2446 return rc;
2447 }
2448
2449 /* Enable timing synchronization for a group of Timing Generators. */
2450 static void dce110_enable_timing_synchronization(
2451 struct dc *dc,
2452 int group_index,
2453 int group_size,
2454 struct pipe_ctx *grouped_pipes[])
2455 {
2456 struct dc_context *dc_ctx = dc->ctx;
2457 struct dcp_gsl_params gsl_params = { 0 };
2458 int i;
2459
2460 DC_SYNC_INFO("GSL: Setting-up...\n");
2461
2462 /* Designate a single TG in the group as a master.
2463 * Since HW doesn't care which one, we always assign
2464 * the 1st one in the group. */
2465 gsl_params.gsl_group = 0;
2466 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2467
2468 for (i = 0; i < group_size; i++)
2469 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2470 grouped_pipes[i]->stream_res.tg, &gsl_params);
2471
2472 /* Reset slave controllers on master VSync */
2473 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2474
2475 for (i = 1 /* skip the master */; i < group_size; i++)
2476 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2477 grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
2478
2479
2480
2481 for (i = 1 /* skip the master */; i < group_size; i++) {
2482 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2483 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2484 /* Regardless of success of the wait above, remove the reset or
2485 * the driver will start timing out on Display requests. */
2486 DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
2487 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
2488 }
2489
2490
2491 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2492 * is that the sync'ed displays will not drift out of sync over time*/
2493 DC_SYNC_INFO("GSL: Restoring register states.\n");
2494 for (i = 0; i < group_size; i++)
2495 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2496
2497 DC_SYNC_INFO("GSL: Set-up complete.\n");
2498 }
2499
2500 static void init_hw(struct dc *dc)
2501 {
2502 int i;
2503 struct dc_bios *bp;
2504 struct transform *xfm;
2505 struct abm *abm;
2506
2507 bp = dc->ctx->dc_bios;
2508 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2509 xfm = dc->res_pool->transforms[i];
2510 xfm->funcs->transform_reset(xfm);
2511
2512 dc->hwss.enable_display_power_gating(
2513 dc, i, bp,
2514 PIPE_GATING_CONTROL_INIT);
2515 dc->hwss.enable_display_power_gating(
2516 dc, i, bp,
2517 PIPE_GATING_CONTROL_DISABLE);
2518 dc->hwss.enable_display_pipe_clock_gating(
2519 dc->ctx,
2520 true);
2521 }
2522
2523 dce_clock_gating_power_up(dc->hwseq, false);
2524 /***************************************/
2525
2526 for (i = 0; i < dc->link_count; i++) {
2527 /****************************************/
2528 /* Power up AND update implementation according to the
2529 * required signal (which may be different from the
2530 * default signal on connector). */
2531 struct dc_link *link = dc->links[i];
2532
2533 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2534 dc->hwss.edp_power_control(link, true);
2535
2536 link->link_enc->funcs->hw_init(link->link_enc);
2537 }
2538
2539 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2540 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2541
2542 tg->funcs->disable_vga(tg);
2543
2544 /* Blank controller using driver code instead of
2545 * command table. */
2546 tg->funcs->set_blank(tg, true);
2547 hwss_wait_for_blank_complete(tg);
2548 }
2549
2550 for (i = 0; i < dc->res_pool->audio_count; i++) {
2551 struct audio *audio = dc->res_pool->audios[i];
2552 audio->funcs->hw_init(audio);
2553 }
2554
2555 abm = dc->res_pool->abm;
2556 if (abm != NULL) {
2557 abm->funcs->init_backlight(abm);
2558 abm->funcs->abm_init(abm);
2559 }
2560 #if defined(CONFIG_DRM_AMD_DC_FBC)
2561 if (dc->fbc_compressor)
2562 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2563 #endif
2564
2565 }
2566
2567 void dce110_fill_display_configs(
2568 const struct dc_state *context,
2569 struct dm_pp_display_configuration *pp_display_cfg)
2570 {
2571 int j;
2572 int num_cfgs = 0;
2573
2574 for (j = 0; j < context->stream_count; j++) {
2575 int k;
2576
2577 const struct dc_stream_state *stream = context->streams[j];
2578 struct dm_pp_single_disp_config *cfg =
2579 &pp_display_cfg->disp_configs[num_cfgs];
2580 const struct pipe_ctx *pipe_ctx = NULL;
2581
2582 for (k = 0; k < MAX_PIPES; k++)
2583 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2584 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2585 break;
2586 }
2587
2588 ASSERT(pipe_ctx != NULL);
2589
2590 num_cfgs++;
2591 cfg->signal = pipe_ctx->stream->signal;
2592 cfg->pipe_idx = pipe_ctx->pipe_idx;
2593 cfg->src_height = stream->src.height;
2594 cfg->src_width = stream->src.width;
2595 cfg->ddi_channel_mapping =
2596 stream->sink->link->ddi_channel_mapping.raw;
2597 cfg->transmitter =
2598 stream->sink->link->link_enc->transmitter;
2599 cfg->link_settings.lane_count =
2600 stream->sink->link->cur_link_settings.lane_count;
2601 cfg->link_settings.link_rate =
2602 stream->sink->link->cur_link_settings.link_rate;
2603 cfg->link_settings.link_spread =
2604 stream->sink->link->cur_link_settings.link_spread;
2605 cfg->sym_clock = stream->phy_pix_clk;
2606 /* Round v_refresh*/
2607 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2608 cfg->v_refresh /= stream->timing.h_total;
2609 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2610 / stream->timing.v_total;
2611 }
2612
2613 pp_display_cfg->display_count = num_cfgs;
2614 }
2615
2616 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2617 {
2618 uint8_t j;
2619 uint32_t min_vertical_blank_time = -1;
2620
2621 for (j = 0; j < context->stream_count; j++) {
2622 struct dc_stream_state *stream = context->streams[j];
2623 uint32_t vertical_blank_in_pixels = 0;
2624 uint32_t vertical_blank_time = 0;
2625
2626 vertical_blank_in_pixels = stream->timing.h_total *
2627 (stream->timing.v_total
2628 - stream->timing.v_addressable);
2629
2630 vertical_blank_time = vertical_blank_in_pixels
2631 * 1000 / stream->timing.pix_clk_khz;
2632
2633 if (min_vertical_blank_time > vertical_blank_time)
2634 min_vertical_blank_time = vertical_blank_time;
2635 }
2636
2637 return min_vertical_blank_time;
2638 }
2639
2640 static int determine_sclk_from_bounding_box(
2641 const struct dc *dc,
2642 int required_sclk)
2643 {
2644 int i;
2645
2646 /*
2647 * Some asics do not give us sclk levels, so we just report the actual
2648 * required sclk
2649 */
2650 if (dc->sclk_lvls.num_levels == 0)
2651 return required_sclk;
2652
2653 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2654 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2655 return dc->sclk_lvls.clocks_in_khz[i];
2656 }
2657 /*
2658 * even maximum level could not satisfy requirement, this
2659 * is unexpected at this stage, should have been caught at
2660 * validation time
2661 */
2662 ASSERT(0);
2663 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2664 }
2665
2666 static void pplib_apply_display_requirements(
2667 struct dc *dc,
2668 struct dc_state *context)
2669 {
2670 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2671
2672 pp_display_cfg->all_displays_in_sync =
2673 context->bw.dce.all_displays_in_sync;
2674 pp_display_cfg->nb_pstate_switch_disable =
2675 context->bw.dce.nbp_state_change_enable == false;
2676 pp_display_cfg->cpu_cc6_disable =
2677 context->bw.dce.cpuc_state_change_enable == false;
2678 pp_display_cfg->cpu_pstate_disable =
2679 context->bw.dce.cpup_state_change_enable == false;
2680 pp_display_cfg->cpu_pstate_separation_time =
2681 context->bw.dce.blackout_recovery_time_us;
2682
2683 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2684 / MEMORY_TYPE_MULTIPLIER;
2685
2686 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2687 dc,
2688 context->bw.dce.sclk_khz);
2689
2690 pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
2691
2692 pp_display_cfg->min_engine_clock_deep_sleep_khz
2693 = context->bw.dce.sclk_deep_sleep_khz;
2694
2695 pp_display_cfg->avail_mclk_switch_time_us =
2696 dce110_get_min_vblank_time_us(context);
2697 /* TODO: dce11.2*/
2698 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2699
2700 pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2701
2702 dce110_fill_display_configs(context, pp_display_cfg);
2703
2704 /* TODO: is this still applicable?*/
2705 if (pp_display_cfg->display_count == 1) {
2706 const struct dc_crtc_timing *timing =
2707 &context->streams[0]->timing;
2708
2709 pp_display_cfg->crtc_index =
2710 pp_display_cfg->disp_configs[0].pipe_idx;
2711 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2712 / timing->pix_clk_khz;
2713 }
2714
2715 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2716 struct dm_pp_display_configuration)) != 0)
2717 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2718
2719 dc->prev_display_config = *pp_display_cfg;
2720 }
2721
2722 static void dce110_set_bandwidth(
2723 struct dc *dc,
2724 struct dc_state *context,
2725 bool decrease_allowed)
2726 {
2727 dce110_set_displaymarks(dc, context);
2728
2729 if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
2730 dc->res_pool->display_clock->funcs->set_clock(
2731 dc->res_pool->display_clock,
2732 context->bw.dce.dispclk_khz * 115 / 100);
2733 dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2734 }
2735
2736 pplib_apply_display_requirements(dc, context);
2737 }
2738
2739 static void dce110_program_front_end_for_pipe(
2740 struct dc *dc, struct pipe_ctx *pipe_ctx)
2741 {
2742 struct mem_input *mi = pipe_ctx->plane_res.mi;
2743 struct pipe_ctx *old_pipe = NULL;
2744 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2745 struct xfm_grph_csc_adjustment adjust;
2746 struct out_csc_color_matrix tbl_entry;
2747 struct pipe_ctx *cur_pipe_ctx =
2748 &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2749 unsigned int i;
2750
2751 memset(&tbl_entry, 0, sizeof(tbl_entry));
2752
2753 if (dc->current_state)
2754 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2755
2756 memset(&adjust, 0, sizeof(adjust));
2757 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2758
2759 dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
2760
2761 set_default_colors(pipe_ctx);
2762 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2763 == true) {
2764 tbl_entry.color_space =
2765 pipe_ctx->stream->output_color_space;
2766
2767 for (i = 0; i < 12; i++)
2768 tbl_entry.regval[i] =
2769 pipe_ctx->stream->csc_color_matrix.matrix[i];
2770
2771 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2772 (pipe_ctx->plane_res.xfm, &tbl_entry);
2773 }
2774
2775 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2776 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2777 adjust.temperature_matrix[0] =
2778 pipe_ctx->stream->
2779 gamut_remap_matrix.matrix[0];
2780 adjust.temperature_matrix[1] =
2781 pipe_ctx->stream->
2782 gamut_remap_matrix.matrix[1];
2783 adjust.temperature_matrix[2] =
2784 pipe_ctx->stream->
2785 gamut_remap_matrix.matrix[2];
2786 adjust.temperature_matrix[3] =
2787 pipe_ctx->stream->
2788 gamut_remap_matrix.matrix[4];
2789 adjust.temperature_matrix[4] =
2790 pipe_ctx->stream->
2791 gamut_remap_matrix.matrix[5];
2792 adjust.temperature_matrix[5] =
2793 pipe_ctx->stream->
2794 gamut_remap_matrix.matrix[6];
2795 adjust.temperature_matrix[6] =
2796 pipe_ctx->stream->
2797 gamut_remap_matrix.matrix[8];
2798 adjust.temperature_matrix[7] =
2799 pipe_ctx->stream->
2800 gamut_remap_matrix.matrix[9];
2801 adjust.temperature_matrix[8] =
2802 pipe_ctx->stream->
2803 gamut_remap_matrix.matrix[10];
2804 }
2805
2806 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2807
2808 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2809
2810 program_scaler(dc, pipe_ctx);
2811
2812 #if defined(CONFIG_DRM_AMD_DC_FBC)
2813 if (dc->fbc_compressor && old_pipe->stream) {
2814 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2815 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2816 else
2817 enable_fbc(dc, dc->current_state);
2818 }
2819 #endif
2820
2821 mi->funcs->mem_input_program_surface_config(
2822 mi,
2823 plane_state->format,
2824 &plane_state->tiling_info,
2825 &plane_state->plane_size,
2826 plane_state->rotation,
2827 NULL,
2828 false);
2829 if (mi->funcs->set_blank)
2830 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2831
2832 if (dc->config.gpu_vm_support)
2833 mi->funcs->mem_input_program_pte_vm(
2834 pipe_ctx->plane_res.mi,
2835 plane_state->format,
2836 &plane_state->tiling_info,
2837 plane_state->rotation);
2838
2839 /* Moved programming gamma from dc to hwss */
2840 if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
2841 dc->hwss.set_input_transfer_func(
2842 pipe_ctx, pipe_ctx->plane_state);
2843 dc->hwss.set_output_transfer_func(
2844 pipe_ctx, pipe_ctx->stream);
2845 }
2846
2847 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2848 "Pipe:%d 0x%x: addr hi:0x%x, "
2849 "addr low:0x%x, "
2850 "src: %d, %d, %d,"
2851 " %d; dst: %d, %d, %d, %d;"
2852 "clip: %d, %d, %d, %d\n",
2853 pipe_ctx->pipe_idx,
2854 pipe_ctx->plane_state,
2855 pipe_ctx->plane_state->address.grph.addr.high_part,
2856 pipe_ctx->plane_state->address.grph.addr.low_part,
2857 pipe_ctx->plane_state->src_rect.x,
2858 pipe_ctx->plane_state->src_rect.y,
2859 pipe_ctx->plane_state->src_rect.width,
2860 pipe_ctx->plane_state->src_rect.height,
2861 pipe_ctx->plane_state->dst_rect.x,
2862 pipe_ctx->plane_state->dst_rect.y,
2863 pipe_ctx->plane_state->dst_rect.width,
2864 pipe_ctx->plane_state->dst_rect.height,
2865 pipe_ctx->plane_state->clip_rect.x,
2866 pipe_ctx->plane_state->clip_rect.y,
2867 pipe_ctx->plane_state->clip_rect.width,
2868 pipe_ctx->plane_state->clip_rect.height);
2869
2870 dm_logger_write(dc->ctx->logger, LOG_SURFACE,
2871 "Pipe %d: width, height, x, y\n"
2872 "viewport:%d, %d, %d, %d\n"
2873 "recout: %d, %d, %d, %d\n",
2874 pipe_ctx->pipe_idx,
2875 pipe_ctx->plane_res.scl_data.viewport.width,
2876 pipe_ctx->plane_res.scl_data.viewport.height,
2877 pipe_ctx->plane_res.scl_data.viewport.x,
2878 pipe_ctx->plane_res.scl_data.viewport.y,
2879 pipe_ctx->plane_res.scl_data.recout.width,
2880 pipe_ctx->plane_res.scl_data.recout.height,
2881 pipe_ctx->plane_res.scl_data.recout.x,
2882 pipe_ctx->plane_res.scl_data.recout.y);
2883 }
2884
2885 static void dce110_apply_ctx_for_surface(
2886 struct dc *dc,
2887 const struct dc_stream_state *stream,
2888 int num_planes,
2889 struct dc_state *context)
2890 {
2891 int i;
2892
2893 if (num_planes == 0)
2894 return;
2895
2896 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2897 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2898 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2899
2900 if (stream == pipe_ctx->stream) {
2901 if (!pipe_ctx->top_pipe &&
2902 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2903 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2904 }
2905 }
2906
2907 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2908 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2909
2910 if (pipe_ctx->stream != stream)
2911 continue;
2912
2913 /* Need to allocate mem before program front end for Fiji */
2914 if (pipe_ctx->plane_res.mi != NULL)
2915 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2916 pipe_ctx->plane_res.mi,
2917 pipe_ctx->stream->timing.h_total,
2918 pipe_ctx->stream->timing.v_total,
2919 pipe_ctx->stream->timing.pix_clk_khz,
2920 context->stream_count);
2921
2922 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2923
2924 dc->hwss.update_plane_addr(dc, pipe_ctx);
2925
2926 program_surface_visibility(dc, pipe_ctx);
2927
2928 }
2929
2930 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2931 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2932 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2933
2934 if ((stream == pipe_ctx->stream) &&
2935 (!pipe_ctx->top_pipe) &&
2936 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2937 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2938 }
2939 }
2940
2941 static void dce110_power_down_fe(struct dc *dc, int fe_idx)
2942 {
2943 /* Do not power down fe when stream is active on dce*/
2944 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2945 return;
2946
2947 dc->hwss.enable_display_power_gating(
2948 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2949
2950 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2951 dc->res_pool->transforms[fe_idx]);
2952 }
2953
2954 static void dce110_wait_for_mpcc_disconnect(
2955 struct dc *dc,
2956 struct resource_pool *res_pool,
2957 struct pipe_ctx *pipe_ctx)
2958 {
2959 /* do nothing*/
2960 }
2961
2962 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2963 enum dc_color_space colorspace,
2964 uint16_t *matrix)
2965 {
2966 int i;
2967 struct out_csc_color_matrix tbl_entry;
2968
2969 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2970 == true) {
2971 enum dc_color_space color_space =
2972 pipe_ctx->stream->output_color_space;
2973
2974 //uint16_t matrix[12];
2975 for (i = 0; i < 12; i++)
2976 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2977
2978 tbl_entry.color_space = color_space;
2979 //tbl_entry.regval = matrix;
2980 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2981 }
2982 }
2983
2984 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2985
2986 static void optimize_shared_resources(struct dc *dc) {}
2987
2988 static const struct hw_sequencer_funcs dce110_funcs = {
2989 .program_gamut_remap = program_gamut_remap,
2990 .program_csc_matrix = program_csc_matrix,
2991 .init_hw = init_hw,
2992 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2993 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2994 .set_plane_config = set_plane_config,
2995 .update_plane_addr = update_plane_addr,
2996 .update_pending_status = dce110_update_pending_status,
2997 .set_input_transfer_func = dce110_set_input_transfer_func,
2998 .set_output_transfer_func = dce110_set_output_transfer_func,
2999 .power_down = dce110_power_down,
3000 .enable_accelerated_mode = dce110_enable_accelerated_mode,
3001 .enable_timing_synchronization = dce110_enable_timing_synchronization,
3002 .update_info_frame = dce110_update_info_frame,
3003 .enable_stream = dce110_enable_stream,
3004 .disable_stream = dce110_disable_stream,
3005 .unblank_stream = dce110_unblank_stream,
3006 .blank_stream = dce110_blank_stream,
3007 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3008 .enable_display_power_gating = dce110_enable_display_power_gating,
3009 .power_down_front_end = dce110_power_down_fe,
3010 .pipe_control_lock = dce_pipe_control_lock,
3011 .set_bandwidth = dce110_set_bandwidth,
3012 .set_drr = set_drr,
3013 .get_position = get_position,
3014 .set_static_screen_control = set_static_screen_control,
3015 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3016 .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
3017 .setup_stereo = NULL,
3018 .set_avmute = dce110_set_avmute,
3019 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3020 .ready_shared_resources = ready_shared_resources,
3021 .optimize_shared_resources = optimize_shared_resources,
3022 .edp_backlight_control = hwss_edp_backlight_control,
3023 .edp_power_control = hwss_edp_power_control,
3024 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
3025 };
3026
3027 void dce110_hw_sequencer_construct(struct dc *dc)
3028 {
3029 dc->hwss = dce110_funcs;
3030 }
3031
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