2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
32 #include "dce110/dce110_resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dce/dce_audio.h"
36 #include "dce110/dce110_timing_generator.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce110/dce110_timing_generator_v.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce110/dce110_mem_input_v.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce110/dce110_transform_v.h"
46 #include "dce/dce_opp.h"
47 #include "dce110/dce110_opp_v.h"
48 #include "dce/dce_clocks.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dce/dce_abm.h"
53 #include "dce/dce_dmcu.h"
56 #include "dce110/dce110_compressor.h"
59 #include "reg_helper.h"
61 #include "dce/dce_11_0_d.h"
62 #include "dce/dce_11_0_sh_mask.h"
64 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
65 #include "gmc/gmc_8_2_d.h"
66 #include "gmc/gmc_8_2_sh_mask.h"
69 #ifndef mmDP_DPHY_INTERNAL_CTRL
70 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
71 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
72 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
73 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
74 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
77 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
78 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
79 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_2 0x05CB
84 #define mmBIOS_SCRATCH_6 0x05CF
87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
88 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
90 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
91 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
92 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
93 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
95 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
98 #ifndef mmDP_DPHY_FAST_TRAINING
99 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
100 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
101 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
102 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
103 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
104 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
105 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
106 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
109 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
110 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
113 static const struct dce110_timing_generator_offsets dce110_tg_offsets
[] = {
115 .crtc
= (mmCRTC0_CRTC_CONTROL
- mmCRTC_CONTROL
),
116 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
119 .crtc
= (mmCRTC1_CRTC_CONTROL
- mmCRTC_CONTROL
),
120 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
123 .crtc
= (mmCRTC2_CRTC_CONTROL
- mmCRTC_CONTROL
),
124 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
127 .crtc
= (mmCRTC3_CRTC_CONTROL
- mmCRTC_CONTROL
),
128 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
131 .crtc
= (mmCRTC4_CRTC_CONTROL
- mmCRTC_CONTROL
),
132 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
135 .crtc
= (mmCRTC5_CRTC_CONTROL
- mmCRTC_CONTROL
),
136 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
140 /* set register offset */
141 #define SR(reg_name)\
142 .reg_name = mm ## reg_name
144 /* set register offset with instance */
145 #define SRI(reg_name, block, id)\
146 .reg_name = mm ## block ## id ## _ ## reg_name
148 static const struct dce_disp_clk_registers disp_clk_regs
= {
149 CLK_COMMON_REG_LIST_DCE_BASE()
152 static const struct dce_disp_clk_shift disp_clk_shift
= {
153 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
156 static const struct dce_disp_clk_mask disp_clk_mask
= {
157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
160 static const struct dce_dmcu_registers dmcu_regs
= {
161 DMCU_DCE110_COMMON_REG_LIST()
164 static const struct dce_dmcu_shift dmcu_shift
= {
165 DMCU_MASK_SH_LIST_DCE110(__SHIFT
)
168 static const struct dce_dmcu_mask dmcu_mask
= {
169 DMCU_MASK_SH_LIST_DCE110(_MASK
)
172 static const struct dce_abm_registers abm_regs
= {
173 ABM_DCE110_COMMON_REG_LIST()
176 static const struct dce_abm_shift abm_shift
= {
177 ABM_MASK_SH_LIST_DCE110(__SHIFT
)
180 static const struct dce_abm_mask abm_mask
= {
181 ABM_MASK_SH_LIST_DCE110(_MASK
)
184 #define ipp_regs(id)\
186 IPP_DCE110_REG_LIST_DCE_BASE(id)\
189 static const struct dce_ipp_registers ipp_regs
[] = {
195 static const struct dce_ipp_shift ipp_shift
= {
196 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
199 static const struct dce_ipp_mask ipp_mask
= {
200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
203 #define transform_regs(id)\
205 XFM_COMMON_REG_LIST_DCE110(id)\
208 static const struct dce_transform_registers xfm_regs
[] = {
214 static const struct dce_transform_shift xfm_shift
= {
215 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
218 static const struct dce_transform_mask xfm_mask
= {
219 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK
)
222 #define aux_regs(id)\
227 static const struct dce110_link_enc_aux_registers link_enc_aux_regs
[] = {
236 #define hpd_regs(id)\
241 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs
[] = {
251 #define link_regs(id)\
253 LE_DCE110_REG_LIST(id)\
256 static const struct dce110_link_enc_registers link_enc_regs
[] = {
266 #define stream_enc_regs(id)\
268 SE_COMMON_REG_LIST(id),\
272 static const struct dce110_stream_enc_registers stream_enc_regs
[] = {
278 static const struct dce_stream_encoder_shift se_shift
= {
279 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
282 static const struct dce_stream_encoder_mask se_mask
= {
283 SE_COMMON_MASK_SH_LIST_DCE110(_MASK
)
286 #define opp_regs(id)\
288 OPP_DCE_110_REG_LIST(id),\
291 static const struct dce_opp_registers opp_regs
[] = {
300 static const struct dce_opp_shift opp_shift
= {
301 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT
)
304 static const struct dce_opp_mask opp_mask
= {
305 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK
)
308 #define audio_regs(id)\
310 AUD_COMMON_REG_LIST(id)\
313 static const struct dce_audio_registers audio_regs
[] = {
323 static const struct dce_audio_shift audio_shift
= {
324 AUD_COMMON_MASK_SH_LIST(__SHIFT
)
327 static const struct dce_aduio_mask audio_mask
= {
328 AUD_COMMON_MASK_SH_LIST(_MASK
)
331 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
334 #define clk_src_regs(id)\
336 CS_COMMON_REG_LIST_DCE_100_110(id),\
339 static const struct dce110_clk_src_regs clk_src_regs
[] = {
345 static const struct dce110_clk_src_shift cs_shift
= {
346 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
349 static const struct dce110_clk_src_mask cs_mask
= {
350 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
353 static const struct bios_registers bios_regs
= {
354 .BIOS_SCRATCH_6
= mmBIOS_SCRATCH_6
357 static const struct resource_caps carrizo_resource_cap
= {
358 .num_timing_generator
= 3,
359 .num_video_plane
= 1,
361 .num_stream_encoder
= 3,
365 static const struct resource_caps stoney_resource_cap
= {
366 .num_timing_generator
= 2,
367 .num_video_plane
= 1,
369 .num_stream_encoder
= 3,
374 #define REG(reg) mm ## reg
376 #ifndef mmCC_DC_HDMI_STRAPS
377 #define mmCC_DC_HDMI_STRAPS 0x4819
378 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
379 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
380 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
381 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
384 static void read_dce_straps(
385 struct dc_context
*ctx
,
386 struct resource_straps
*straps
)
388 REG_GET_2(CC_DC_HDMI_STRAPS
,
389 HDMI_DISABLE
, &straps
->hdmi_disable
,
390 AUDIO_STREAM_NUMBER
, &straps
->audio_stream_number
);
392 REG_GET(DC_PINSTRAPS
, DC_PINSTRAPS_AUDIO
, &straps
->dc_pinstraps_audio
);
395 static struct audio
*create_audio(
396 struct dc_context
*ctx
, unsigned int inst
)
398 return dce_audio_create(ctx
, inst
,
399 &audio_regs
[inst
], &audio_shift
, &audio_mask
);
402 static struct timing_generator
*dce110_timing_generator_create(
403 struct dc_context
*ctx
,
405 const struct dce110_timing_generator_offsets
*offsets
)
407 struct dce110_timing_generator
*tg110
=
408 dm_alloc(sizeof(struct dce110_timing_generator
));
413 if (dce110_timing_generator_construct(tg110
, ctx
, instance
, offsets
))
421 static struct stream_encoder
*dce110_stream_encoder_create(
422 enum engine_id eng_id
,
423 struct dc_context
*ctx
)
425 struct dce110_stream_encoder
*enc110
=
426 dm_alloc(sizeof(struct dce110_stream_encoder
));
431 if (dce110_stream_encoder_construct(
432 enc110
, ctx
, ctx
->dc_bios
, eng_id
,
433 &stream_enc_regs
[eng_id
], &se_shift
, &se_mask
))
434 return &enc110
->base
;
441 #define SRII(reg_name, block, id)\
442 .reg_name[id] = mm ## block ## id ## _ ## reg_name
444 static const struct dce_hwseq_registers hwseq_stoney_reg
= {
448 static const struct dce_hwseq_registers hwseq_cz_reg
= {
452 static const struct dce_hwseq_shift hwseq_shift
= {
453 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT
),
456 static const struct dce_hwseq_mask hwseq_mask
= {
457 HWSEQ_DCE11_MASK_SH_LIST(_MASK
),
460 static struct dce_hwseq
*dce110_hwseq_create(
461 struct dc_context
*ctx
)
463 struct dce_hwseq
*hws
= dm_alloc(sizeof(struct dce_hwseq
));
467 hws
->regs
= ASIC_REV_IS_STONEY(ctx
->asic_id
.hw_internal_rev
) ?
468 &hwseq_stoney_reg
: &hwseq_cz_reg
;
469 hws
->shifts
= &hwseq_shift
;
470 hws
->masks
= &hwseq_mask
;
471 hws
->wa
.blnd_crtc_trigger
= true;
476 static const struct resource_create_funcs res_create_funcs
= {
477 .read_dce_straps
= read_dce_straps
,
478 .create_audio
= create_audio
,
479 .create_stream_encoder
= dce110_stream_encoder_create
,
480 .create_hwseq
= dce110_hwseq_create
,
483 #define mi_inst_regs(id) { \
484 MI_DCE11_REG_LIST(id), \
485 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
487 static const struct dce_mem_input_registers mi_regs
[] = {
493 static const struct dce_mem_input_shift mi_shifts
= {
494 MI_DCE11_MASK_SH_LIST(__SHIFT
),
495 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
498 static const struct dce_mem_input_mask mi_masks
= {
499 MI_DCE11_MASK_SH_LIST(_MASK
),
500 .ENABLE
= MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
504 static struct mem_input
*dce110_mem_input_create(
505 struct dc_context
*ctx
,
508 struct dce_mem_input
*dce_mi
= dm_alloc(sizeof(struct dce_mem_input
));
515 dce_mem_input_construct(dce_mi
, ctx
, inst
, &mi_regs
[inst
], &mi_shifts
, &mi_masks
);
516 dce_mi
->wa
.single_head_rdreq_dmif_limit
= 3;
517 return &dce_mi
->base
;
520 static void dce110_transform_destroy(struct transform
**xfm
)
522 dm_free(TO_DCE_TRANSFORM(*xfm
));
526 static struct transform
*dce110_transform_create(
527 struct dc_context
*ctx
,
530 struct dce_transform
*transform
=
531 dm_alloc(sizeof(struct dce_transform
));
536 if (dce_transform_construct(transform
, ctx
, inst
,
537 &xfm_regs
[inst
], &xfm_shift
, &xfm_mask
))
538 return &transform
->base
;
545 static struct input_pixel_processor
*dce110_ipp_create(
546 struct dc_context
*ctx
, uint32_t inst
)
548 struct dce_ipp
*ipp
= dm_alloc(sizeof(struct dce_ipp
));
555 dce_ipp_construct(ipp
, ctx
, inst
,
556 &ipp_regs
[inst
], &ipp_shift
, &ipp_mask
);
560 static const struct encoder_feature_support link_enc_feature
= {
561 .max_hdmi_deep_color
= COLOR_DEPTH_121212
,
562 .max_hdmi_pixel_clock
= 594000,
563 .flags
.bits
.IS_HBR2_CAPABLE
= true,
564 .flags
.bits
.IS_TPS3_CAPABLE
= true,
565 .flags
.bits
.IS_YCBCR_CAPABLE
= true
568 struct link_encoder
*dce110_link_encoder_create(
569 const struct encoder_init_data
*enc_init_data
)
571 struct dce110_link_encoder
*enc110
=
572 dm_alloc(sizeof(struct dce110_link_encoder
));
577 if (dce110_link_encoder_construct(
581 &link_enc_regs
[enc_init_data
->transmitter
],
582 &link_enc_aux_regs
[enc_init_data
->channel
- 1],
583 &link_enc_hpd_regs
[enc_init_data
->hpd_source
])) {
585 return &enc110
->base
;
593 static struct output_pixel_processor
*dce110_opp_create(
594 struct dc_context
*ctx
,
597 struct dce110_opp
*opp
=
598 dm_alloc(sizeof(struct dce110_opp
));
603 if (dce110_opp_construct(opp
,
604 ctx
, inst
, &opp_regs
[inst
], &opp_shift
, &opp_mask
))
612 struct clock_source
*dce110_clock_source_create(
613 struct dc_context
*ctx
,
614 struct dc_bios
*bios
,
615 enum clock_source_id id
,
616 const struct dce110_clk_src_regs
*regs
,
619 struct dce110_clk_src
*clk_src
=
620 dm_alloc(sizeof(struct dce110_clk_src
));
625 if (dce110_clk_src_construct(clk_src
, ctx
, bios
, id
,
626 regs
, &cs_shift
, &cs_mask
)) {
627 clk_src
->base
.dp_clk_src
= dp_clk_src
;
628 return &clk_src
->base
;
635 void dce110_clock_source_destroy(struct clock_source
**clk_src
)
637 struct dce110_clk_src
*dce110_clk_src
;
642 dce110_clk_src
= TO_DCE110_CLK_SRC(*clk_src
);
644 if (dce110_clk_src
->dp_ss_params
)
645 dm_free(dce110_clk_src
->dp_ss_params
);
647 if (dce110_clk_src
->hdmi_ss_params
)
648 dm_free(dce110_clk_src
->hdmi_ss_params
);
650 if (dce110_clk_src
->dvi_ss_params
)
651 dm_free(dce110_clk_src
->dvi_ss_params
);
653 dm_free(dce110_clk_src
);
657 static void destruct(struct dce110_resource_pool
*pool
)
661 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
662 if (pool
->base
.opps
[i
] != NULL
)
663 dce110_opp_destroy(&pool
->base
.opps
[i
]);
665 if (pool
->base
.transforms
[i
] != NULL
)
666 dce110_transform_destroy(&pool
->base
.transforms
[i
]);
668 if (pool
->base
.ipps
[i
] != NULL
)
669 dce_ipp_destroy(&pool
->base
.ipps
[i
]);
671 if (pool
->base
.mis
[i
] != NULL
) {
672 dm_free(TO_DCE_MEM_INPUT(pool
->base
.mis
[i
]));
673 pool
->base
.mis
[i
] = NULL
;
676 if (pool
->base
.timing_generators
[i
] != NULL
) {
677 dm_free(DCE110TG_FROM_TG(pool
->base
.timing_generators
[i
]));
678 pool
->base
.timing_generators
[i
] = NULL
;
682 for (i
= 0; i
< pool
->base
.stream_enc_count
; i
++) {
683 if (pool
->base
.stream_enc
[i
] != NULL
)
684 dm_free(DCE110STRENC_FROM_STRENC(pool
->base
.stream_enc
[i
]));
687 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
688 if (pool
->base
.clock_sources
[i
] != NULL
) {
689 dce110_clock_source_destroy(&pool
->base
.clock_sources
[i
]);
693 if (pool
->base
.dp_clock_source
!= NULL
)
694 dce110_clock_source_destroy(&pool
->base
.dp_clock_source
);
696 for (i
= 0; i
< pool
->base
.audio_count
; i
++) {
697 if (pool
->base
.audios
[i
] != NULL
) {
698 dce_aud_destroy(&pool
->base
.audios
[i
]);
702 if (pool
->base
.abm
!= NULL
)
703 dce_abm_destroy(&pool
->base
.abm
);
705 if (pool
->base
.dmcu
!= NULL
)
706 dce_dmcu_destroy(&pool
->base
.dmcu
);
708 if (pool
->base
.display_clock
!= NULL
)
709 dce_disp_clk_destroy(&pool
->base
.display_clock
);
711 if (pool
->base
.irqs
!= NULL
) {
712 dal_irq_service_destroy(&pool
->base
.irqs
);
717 static void get_pixel_clock_parameters(
718 const struct pipe_ctx
*pipe_ctx
,
719 struct pixel_clk_params
*pixel_clk_params
)
721 const struct dc_stream_state
*stream
= pipe_ctx
->stream
;
723 /*TODO: is this halved for YCbCr 420? in that case we might want to move
724 * the pixel clock normalization for hdmi up to here instead of doing it
725 * in pll_adjust_pix_clk
727 pixel_clk_params
->requested_pix_clk
= stream
->timing
.pix_clk_khz
;
728 pixel_clk_params
->encoder_object_id
= stream
->sink
->link
->link_enc
->id
;
729 pixel_clk_params
->signal_type
= pipe_ctx
->stream
->signal
;
730 pixel_clk_params
->controller_id
= pipe_ctx
->pipe_idx
+ 1;
731 /* TODO: un-hardcode*/
732 pixel_clk_params
->requested_sym_clk
= LINK_RATE_LOW
*
733 LINK_RATE_REF_FREQ_IN_KHZ
;
734 pixel_clk_params
->flags
.ENABLE_SS
= 0;
735 pixel_clk_params
->color_depth
=
736 stream
->timing
.display_color_depth
;
737 pixel_clk_params
->flags
.DISPLAY_BLANKED
= 1;
738 pixel_clk_params
->flags
.SUPPORT_YCBCR420
= (stream
->timing
.pixel_encoding
==
739 PIXEL_ENCODING_YCBCR420
);
740 pixel_clk_params
->pixel_encoding
= stream
->timing
.pixel_encoding
;
741 if (stream
->timing
.pixel_encoding
== PIXEL_ENCODING_YCBCR422
) {
742 pixel_clk_params
->color_depth
= COLOR_DEPTH_888
;
744 if (stream
->timing
.pixel_encoding
== PIXEL_ENCODING_YCBCR420
) {
745 pixel_clk_params
->requested_pix_clk
= pixel_clk_params
->requested_pix_clk
/ 2;
749 enum dc_status
dce110_resource_build_pipe_hw_param(struct pipe_ctx
*pipe_ctx
)
751 get_pixel_clock_parameters(pipe_ctx
, &pipe_ctx
->pix_clk_params
);
752 pipe_ctx
->clock_source
->funcs
->get_pix_clk_dividers(
753 pipe_ctx
->clock_source
,
754 &pipe_ctx
->pix_clk_params
,
755 &pipe_ctx
->pll_settings
);
756 resource_build_bit_depth_reduction_params(pipe_ctx
->stream
,
757 &pipe_ctx
->stream
->bit_depth_params
);
758 pipe_ctx
->stream
->clamping
.pixel_encoding
= pipe_ctx
->stream
->timing
.pixel_encoding
;
763 static bool is_surface_pixel_format_supported(struct pipe_ctx
*pipe_ctx
, unsigned int underlay_idx
)
765 if (pipe_ctx
->pipe_idx
!= underlay_idx
)
767 if (!pipe_ctx
->surface
)
769 if (pipe_ctx
->surface
->format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
774 static enum dc_status
build_mapped_resource(
775 const struct core_dc
*dc
,
776 struct validate_context
*context
,
777 struct validate_context
*old_context
)
779 enum dc_status status
= DC_OK
;
782 for (i
= 0; i
< context
->stream_count
; i
++) {
783 struct dc_stream_state
*stream
= context
->streams
[i
];
785 if (old_context
&& resource_is_stream_unchanged(old_context
, stream
))
788 for (j
= 0; j
< MAX_PIPES
; j
++) {
789 struct pipe_ctx
*pipe_ctx
=
790 &context
->res_ctx
.pipe_ctx
[j
];
792 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
795 if (!is_surface_pixel_format_supported(pipe_ctx
,
796 dc
->res_pool
->underlay_pipe_index
))
797 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED
;
799 status
= dce110_resource_build_pipe_hw_param(pipe_ctx
);
804 /* TODO: validate audio ASIC caps, encoder */
806 resource_build_info_frame(pipe_ctx
);
808 /* do not need to validate non root pipes */
816 bool dce110_validate_bandwidth(
817 const struct core_dc
*dc
,
818 struct validate_context
*context
)
823 dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
831 context
->res_ctx
.pipe_ctx
,
832 dc
->res_pool
->pipe_count
,
837 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_VALIDATION
,
838 "%s: %dx%d@%d Bandwidth validation failed!\n",
840 context
->streams
[0]->timing
.h_addressable
,
841 context
->streams
[0]->timing
.v_addressable
,
842 context
->streams
[0]->timing
.pix_clk_khz
);
844 if (memcmp(&dc
->current_context
->bw
.dce
,
845 &context
->bw
.dce
, sizeof(context
->bw
.dce
))) {
846 struct log_entry log_entry
;
850 LOG_BANDWIDTH_CALCS
);
851 dm_logger_append(&log_entry
, "%s: finish,\n"
852 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
853 "stutMark_b: %d stutMark_a: %d\n",
855 context
->bw
.dce
.nbp_state_change_wm_ns
[0].b_mark
,
856 context
->bw
.dce
.nbp_state_change_wm_ns
[0].a_mark
,
857 context
->bw
.dce
.urgent_wm_ns
[0].b_mark
,
858 context
->bw
.dce
.urgent_wm_ns
[0].a_mark
,
859 context
->bw
.dce
.stutter_exit_wm_ns
[0].b_mark
,
860 context
->bw
.dce
.stutter_exit_wm_ns
[0].a_mark
);
861 dm_logger_append(&log_entry
,
862 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
863 "stutMark_b: %d stutMark_a: %d\n",
864 context
->bw
.dce
.nbp_state_change_wm_ns
[1].b_mark
,
865 context
->bw
.dce
.nbp_state_change_wm_ns
[1].a_mark
,
866 context
->bw
.dce
.urgent_wm_ns
[1].b_mark
,
867 context
->bw
.dce
.urgent_wm_ns
[1].a_mark
,
868 context
->bw
.dce
.stutter_exit_wm_ns
[1].b_mark
,
869 context
->bw
.dce
.stutter_exit_wm_ns
[1].a_mark
);
870 dm_logger_append(&log_entry
,
871 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
872 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
873 context
->bw
.dce
.nbp_state_change_wm_ns
[2].b_mark
,
874 context
->bw
.dce
.nbp_state_change_wm_ns
[2].a_mark
,
875 context
->bw
.dce
.urgent_wm_ns
[2].b_mark
,
876 context
->bw
.dce
.urgent_wm_ns
[2].a_mark
,
877 context
->bw
.dce
.stutter_exit_wm_ns
[2].b_mark
,
878 context
->bw
.dce
.stutter_exit_wm_ns
[2].a_mark
,
879 context
->bw
.dce
.stutter_mode_enable
);
880 dm_logger_append(&log_entry
,
881 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
882 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
883 context
->bw
.dce
.cpuc_state_change_enable
,
884 context
->bw
.dce
.cpup_state_change_enable
,
885 context
->bw
.dce
.nbp_state_change_enable
,
886 context
->bw
.dce
.all_displays_in_sync
,
887 context
->bw
.dce
.dispclk_khz
,
888 context
->bw
.dce
.sclk_khz
,
889 context
->bw
.dce
.sclk_deep_sleep_khz
,
890 context
->bw
.dce
.yclk_khz
,
891 context
->bw
.dce
.blackout_recovery_time_us
);
892 dm_logger_close(&log_entry
);
897 static bool dce110_validate_surface_sets(
898 const struct dc_validation_set set
[],
903 for (i
= 0; i
< set_count
; i
++) {
904 if (set
[i
].surface_count
== 0)
907 if (set
[i
].surface_count
> 2)
910 if (set
[i
].surfaces
[0]->format
911 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
914 if (set
[i
].surface_count
== 2) {
915 if (set
[i
].surfaces
[1]->format
916 < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
918 if (set
[i
].surfaces
[1]->src_rect
.width
> 1920
919 || set
[i
].surfaces
[1]->src_rect
.height
> 1080)
922 if (set
[i
].stream
->timing
.pixel_encoding
!= PIXEL_ENCODING_RGB
)
930 enum dc_status
dce110_validate_with_context(
931 const struct core_dc
*dc
,
932 const struct dc_validation_set set
[],
934 struct validate_context
*context
,
935 struct validate_context
*old_context
)
937 struct dc_context
*dc_ctx
= dc
->ctx
;
938 enum dc_status result
= DC_ERROR_UNEXPECTED
;
941 if (!dce110_validate_surface_sets(set
, set_count
))
942 return DC_FAIL_SURFACE_VALIDATE
;
944 for (i
= 0; i
< set_count
; i
++) {
945 context
->streams
[i
] = set
[i
].stream
;
946 dc_stream_retain(context
->streams
[i
]);
947 context
->stream_count
++;
950 result
= resource_map_pool_resources(dc
, context
, old_context
);
953 result
= resource_map_clock_resources(dc
, context
, old_context
);
955 if (!resource_validate_attach_surfaces(set
, set_count
,
956 old_context
, context
, dc
->res_pool
)) {
957 DC_ERROR("Failed to attach surface to stream!\n");
958 return DC_FAIL_ATTACH_SURFACES
;
962 result
= build_mapped_resource(dc
, context
, old_context
);
965 result
= resource_build_scaling_params_for_context(dc
, context
);
968 if (!dce110_validate_bandwidth(dc
, context
))
969 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
974 enum dc_status
dce110_validate_guaranteed(
975 const struct core_dc
*dc
,
976 struct dc_stream_state
*dc_stream
,
977 struct validate_context
*context
)
979 enum dc_status result
= DC_ERROR_UNEXPECTED
;
981 context
->streams
[0] = dc_stream
;
982 dc_stream_retain(context
->streams
[0]);
983 context
->stream_count
++;
985 result
= resource_map_pool_resources(dc
, context
, NULL
);
988 result
= resource_map_clock_resources(dc
, context
, NULL
);
991 result
= build_mapped_resource(dc
, context
, NULL
);
993 if (result
== DC_OK
) {
994 validate_guaranteed_copy_streams(
995 context
, dc
->public.caps
.max_streams
);
996 result
= resource_build_scaling_params_for_context(dc
, context
);
1000 if (!dce110_validate_bandwidth(dc
, context
))
1001 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
1006 static struct pipe_ctx
*dce110_acquire_underlay(
1007 struct validate_context
*context
,
1008 const struct resource_pool
*pool
,
1009 struct dc_stream_state
*stream
)
1011 struct core_dc
*dc
= DC_TO_CORE(stream
->ctx
->dc
);
1012 struct resource_context
*res_ctx
= &context
->res_ctx
;
1013 unsigned int underlay_idx
= pool
->underlay_pipe_index
;
1014 struct pipe_ctx
*pipe_ctx
= &res_ctx
->pipe_ctx
[underlay_idx
];
1016 if (res_ctx
->pipe_ctx
[underlay_idx
].stream
)
1019 pipe_ctx
->tg
= pool
->timing_generators
[underlay_idx
];
1020 pipe_ctx
->mi
= pool
->mis
[underlay_idx
];
1021 /*pipe_ctx->ipp = res_ctx->pool->ipps[underlay_idx];*/
1022 pipe_ctx
->xfm
= pool
->transforms
[underlay_idx
];
1023 pipe_ctx
->opp
= pool
->opps
[underlay_idx
];
1024 pipe_ctx
->dis_clk
= pool
->display_clock
;
1025 pipe_ctx
->pipe_idx
= underlay_idx
;
1027 pipe_ctx
->stream
= stream
;
1029 if (!dc
->current_context
->res_ctx
.pipe_ctx
[underlay_idx
].stream
) {
1030 struct tg_color black_color
= {0};
1031 struct dc_bios
*dcb
= dc
->ctx
->dc_bios
;
1033 dc
->hwss
.enable_display_power_gating(
1036 dcb
, PIPE_GATING_CONTROL_DISABLE
);
1039 * This is for powering on underlay, so crtc does not
1040 * need to be enabled
1043 pipe_ctx
->tg
->funcs
->program_timing(pipe_ctx
->tg
,
1047 pipe_ctx
->tg
->funcs
->enable_advanced_request(
1052 pipe_ctx
->mi
->funcs
->allocate_mem_input(pipe_ctx
->mi
,
1053 stream
->timing
.h_total
,
1054 stream
->timing
.v_total
,
1055 stream
->timing
.pix_clk_khz
,
1056 context
->stream_count
);
1058 color_space_to_black_color(dc
,
1059 COLOR_SPACE_YCBCR601
, &black_color
);
1060 pipe_ctx
->tg
->funcs
->set_blank_color(
1068 static void dce110_destroy_resource_pool(struct resource_pool
**pool
)
1070 struct dce110_resource_pool
*dce110_pool
= TO_DCE110_RES_POOL(*pool
);
1072 destruct(dce110_pool
);
1073 dm_free(dce110_pool
);
1078 static const struct resource_funcs dce110_res_pool_funcs
= {
1079 .destroy
= dce110_destroy_resource_pool
,
1080 .link_enc_create
= dce110_link_encoder_create
,
1081 .validate_with_context
= dce110_validate_with_context
,
1082 .validate_guaranteed
= dce110_validate_guaranteed
,
1083 .validate_bandwidth
= dce110_validate_bandwidth
,
1084 .acquire_idle_pipe_for_layer
= dce110_acquire_underlay
,
1087 static bool underlay_create(struct dc_context
*ctx
, struct resource_pool
*pool
)
1089 struct dce110_timing_generator
*dce110_tgv
= dm_alloc(sizeof (*dce110_tgv
));
1090 struct dce_transform
*dce110_xfmv
= dm_alloc(sizeof (*dce110_xfmv
));
1091 struct dce_mem_input
*dce110_miv
= dm_alloc(sizeof (*dce110_miv
));
1092 struct dce110_opp
*dce110_oppv
= dm_alloc(sizeof (*dce110_oppv
));
1094 if ((dce110_tgv
== NULL
) ||
1095 (dce110_xfmv
== NULL
) ||
1096 (dce110_miv
== NULL
) ||
1097 (dce110_oppv
== NULL
))
1100 if (!dce110_opp_v_construct(dce110_oppv
, ctx
))
1103 dce110_timing_generator_v_construct(dce110_tgv
, ctx
);
1104 dce110_mem_input_v_construct(dce110_miv
, ctx
);
1105 dce110_transform_v_construct(dce110_xfmv
, ctx
);
1107 pool
->opps
[pool
->pipe_count
] = &dce110_oppv
->base
;
1108 pool
->timing_generators
[pool
->pipe_count
] = &dce110_tgv
->base
;
1109 pool
->mis
[pool
->pipe_count
] = &dce110_miv
->base
;
1110 pool
->transforms
[pool
->pipe_count
] = &dce110_xfmv
->base
;
1113 /* update the public caps to indicate an underlay is available */
1114 ctx
->dc
->caps
.max_slave_planes
= 1;
1115 ctx
->dc
->caps
.max_slave_planes
= 1;
1120 static void bw_calcs_data_update_from_pplib(struct core_dc
*dc
)
1122 struct dm_pp_clock_levels clks
= {0};
1125 dm_pp_get_clock_levels_by_type(
1127 DM_PP_CLOCK_TYPE_ENGINE_CLK
,
1129 /* convert all the clock fro kHz to fix point mHz */
1130 dc
->bw_vbios
.high_sclk
= bw_frc_to_fixed(
1131 clks
.clocks_in_khz
[clks
.num_levels
-1], 1000);
1132 dc
->bw_vbios
.mid1_sclk
= bw_frc_to_fixed(
1133 clks
.clocks_in_khz
[clks
.num_levels
/8], 1000);
1134 dc
->bw_vbios
.mid2_sclk
= bw_frc_to_fixed(
1135 clks
.clocks_in_khz
[clks
.num_levels
*2/8], 1000);
1136 dc
->bw_vbios
.mid3_sclk
= bw_frc_to_fixed(
1137 clks
.clocks_in_khz
[clks
.num_levels
*3/8], 1000);
1138 dc
->bw_vbios
.mid4_sclk
= bw_frc_to_fixed(
1139 clks
.clocks_in_khz
[clks
.num_levels
*4/8], 1000);
1140 dc
->bw_vbios
.mid5_sclk
= bw_frc_to_fixed(
1141 clks
.clocks_in_khz
[clks
.num_levels
*5/8], 1000);
1142 dc
->bw_vbios
.mid6_sclk
= bw_frc_to_fixed(
1143 clks
.clocks_in_khz
[clks
.num_levels
*6/8], 1000);
1144 dc
->bw_vbios
.low_sclk
= bw_frc_to_fixed(
1145 clks
.clocks_in_khz
[0], 1000);
1146 dc
->sclk_lvls
= clks
;
1148 /*do display clock*/
1149 dm_pp_get_clock_levels_by_type(
1151 DM_PP_CLOCK_TYPE_DISPLAY_CLK
,
1153 dc
->bw_vbios
.high_voltage_max_dispclk
= bw_frc_to_fixed(
1154 clks
.clocks_in_khz
[clks
.num_levels
-1], 1000);
1155 dc
->bw_vbios
.mid_voltage_max_dispclk
= bw_frc_to_fixed(
1156 clks
.clocks_in_khz
[clks
.num_levels
>>1], 1000);
1157 dc
->bw_vbios
.low_voltage_max_dispclk
= bw_frc_to_fixed(
1158 clks
.clocks_in_khz
[0], 1000);
1161 dm_pp_get_clock_levels_by_type(
1163 DM_PP_CLOCK_TYPE_MEMORY_CLK
,
1166 dc
->bw_vbios
.low_yclk
= bw_frc_to_fixed(
1167 clks
.clocks_in_khz
[0] * MEMORY_TYPE_MULTIPLIER
, 1000);
1168 dc
->bw_vbios
.mid_yclk
= bw_frc_to_fixed(
1169 clks
.clocks_in_khz
[clks
.num_levels
>>1] * MEMORY_TYPE_MULTIPLIER
,
1171 dc
->bw_vbios
.high_yclk
= bw_frc_to_fixed(
1172 clks
.clocks_in_khz
[clks
.num_levels
-1] * MEMORY_TYPE_MULTIPLIER
,
1176 const struct resource_caps
*dce110_resource_cap(
1177 struct hw_asic_id
*asic_id
)
1179 if (ASIC_REV_IS_STONEY(asic_id
->hw_internal_rev
))
1180 return &stoney_resource_cap
;
1182 return &carrizo_resource_cap
;
1185 static bool construct(
1186 uint8_t num_virtual_links
,
1188 struct dce110_resource_pool
*pool
,
1189 struct hw_asic_id asic_id
)
1192 struct dc_context
*ctx
= dc
->ctx
;
1193 struct dc_firmware_info info
;
1195 struct dm_pp_static_clock_info static_clk_info
= {0};
1197 ctx
->dc_bios
->regs
= &bios_regs
;
1199 pool
->base
.res_cap
= dce110_resource_cap(&ctx
->asic_id
);
1200 pool
->base
.funcs
= &dce110_res_pool_funcs
;
1202 /*************************************************
1203 * Resource + asic cap harcoding *
1204 *************************************************/
1206 pool
->base
.pipe_count
= pool
->base
.res_cap
->num_timing_generator
;
1207 pool
->base
.underlay_pipe_index
= pool
->base
.pipe_count
;
1209 dc
->public.caps
.max_downscale_ratio
= 150;
1210 dc
->public.caps
.i2c_speed_in_khz
= 100;
1211 dc
->public.caps
.max_cursor_size
= 128;
1213 /*************************************************
1214 * Create resources *
1215 *************************************************/
1219 if ((bp
->funcs
->get_firmware_info(bp
, &info
) == BP_RESULT_OK
) &&
1220 info
.external_clock_source_frequency_for_dp
!= 0) {
1221 pool
->base
.dp_clock_source
=
1222 dce110_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_EXTERNAL
, NULL
, true);
1224 pool
->base
.clock_sources
[0] =
1225 dce110_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL0
,
1226 &clk_src_regs
[0], false);
1227 pool
->base
.clock_sources
[1] =
1228 dce110_clock_source_create(ctx
, bp
, CLOCK_SOURCE_ID_PLL1
,
1229 &clk_src_regs
[1], false);
1231 pool
->base
.clk_src_count
= 2;
1233 /* TODO: find out if CZ support 3 PLLs */
1236 if (pool
->base
.dp_clock_source
== NULL
) {
1237 dm_error("DC: failed to create dp clock source!\n");
1238 BREAK_TO_DEBUGGER();
1239 goto res_create_fail
;
1242 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
1243 if (pool
->base
.clock_sources
[i
] == NULL
) {
1244 dm_error("DC: failed to create clock sources!\n");
1245 BREAK_TO_DEBUGGER();
1246 goto res_create_fail
;
1250 pool
->base
.display_clock
= dce110_disp_clk_create(ctx
,
1254 if (pool
->base
.display_clock
== NULL
) {
1255 dm_error("DC: failed to create display clock!\n");
1256 BREAK_TO_DEBUGGER();
1257 goto res_create_fail
;
1260 pool
->base
.dmcu
= dce_dmcu_create(ctx
,
1264 if (pool
->base
.dmcu
== NULL
) {
1265 dm_error("DC: failed to create dmcu!\n");
1266 BREAK_TO_DEBUGGER();
1267 goto res_create_fail
;
1270 pool
->base
.abm
= dce_abm_create(ctx
,
1274 if (pool
->base
.abm
== NULL
) {
1275 dm_error("DC: failed to create abm!\n");
1276 BREAK_TO_DEBUGGER();
1277 goto res_create_fail
;
1280 /* get static clock information for PPLIB or firmware, save
1283 if (dm_pp_get_static_clocks(ctx
, &static_clk_info
))
1284 pool
->base
.display_clock
->max_clks_state
=
1285 static_clk_info
.max_clocks_state
;
1288 struct irq_service_init_data init_data
;
1289 init_data
.ctx
= dc
->ctx
;
1290 pool
->base
.irqs
= dal_irq_service_dce110_create(&init_data
);
1291 if (!pool
->base
.irqs
)
1292 goto res_create_fail
;
1295 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
1296 pool
->base
.timing_generators
[i
] = dce110_timing_generator_create(
1297 ctx
, i
, &dce110_tg_offsets
[i
]);
1298 if (pool
->base
.timing_generators
[i
] == NULL
) {
1299 BREAK_TO_DEBUGGER();
1300 dm_error("DC: failed to create tg!\n");
1301 goto res_create_fail
;
1304 pool
->base
.mis
[i
] = dce110_mem_input_create(ctx
, i
);
1305 if (pool
->base
.mis
[i
] == NULL
) {
1306 BREAK_TO_DEBUGGER();
1308 "DC: failed to create memory input!\n");
1309 goto res_create_fail
;
1312 pool
->base
.ipps
[i
] = dce110_ipp_create(ctx
, i
);
1313 if (pool
->base
.ipps
[i
] == NULL
) {
1314 BREAK_TO_DEBUGGER();
1316 "DC: failed to create input pixel processor!\n");
1317 goto res_create_fail
;
1320 pool
->base
.transforms
[i
] = dce110_transform_create(ctx
, i
);
1321 if (pool
->base
.transforms
[i
] == NULL
) {
1322 BREAK_TO_DEBUGGER();
1324 "DC: failed to create transform!\n");
1325 goto res_create_fail
;
1328 pool
->base
.opps
[i
] = dce110_opp_create(ctx
, i
);
1329 if (pool
->base
.opps
[i
] == NULL
) {
1330 BREAK_TO_DEBUGGER();
1332 "DC: failed to create output pixel processor!\n");
1333 goto res_create_fail
;
1338 dc
->fbc_compressor
= dce110_compressor_create(ctx
);
1343 if (!underlay_create(ctx
, &pool
->base
))
1344 goto res_create_fail
;
1346 if (!resource_construct(num_virtual_links
, dc
, &pool
->base
,
1348 goto res_create_fail
;
1350 /* Create hardware sequencer */
1351 if (!dce110_hw_sequencer_construct(dc
))
1352 goto res_create_fail
;
1354 dc
->public.caps
.max_surfaces
= pool
->base
.pipe_count
;
1356 bw_calcs_init(&dc
->bw_dceip
, &dc
->bw_vbios
, dc
->ctx
->asic_id
);
1358 bw_calcs_data_update_from_pplib(dc
);
1367 struct resource_pool
*dce110_create_resource_pool(
1368 uint8_t num_virtual_links
,
1370 struct hw_asic_id asic_id
)
1372 struct dce110_resource_pool
*pool
=
1373 dm_alloc(sizeof(struct dce110_resource_pool
));
1378 if (construct(num_virtual_links
, dc
, pool
, asic_id
))
1381 BREAK_TO_DEBUGGER();