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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce110 / dce110_resource.c
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "dce110/dce110_resource.h"
33
34 #include "include/irq_service_interface.h"
35 #include "dce/dce_audio.h"
36 #include "dce110/dce110_timing_generator.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce110/dce110_timing_generator_v.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce110/dce110_mem_input_v.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce110/dce110_transform_v.h"
46 #include "dce/dce_opp.h"
47 #include "dce110/dce110_opp_v.h"
48 #include "dce/dce_clocks.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce110/dce110_hw_sequencer.h"
52 #include "dce/dce_abm.h"
53 #include "dce/dce_dmcu.h"
54
55 #ifdef ENABLE_FBC
56 #include "dce110/dce110_compressor.h"
57 #endif
58
59 #include "reg_helper.h"
60
61 #include "dce/dce_11_0_d.h"
62 #include "dce/dce_11_0_sh_mask.h"
63
64 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
65 #include "gmc/gmc_8_2_d.h"
66 #include "gmc/gmc_8_2_sh_mask.h"
67 #endif
68
69 #ifndef mmDP_DPHY_INTERNAL_CTRL
70 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
71 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
72 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
73 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
74 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
77 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
78 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
79 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
80 #endif
81
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_2 0x05CB
84 #define mmBIOS_SCRATCH_6 0x05CF
85 #endif
86
87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
88 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
90 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
91 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
92 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
93 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
95 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
96 #endif
97
98 #ifndef mmDP_DPHY_FAST_TRAINING
99 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
100 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
101 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
102 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
103 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
104 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
105 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
106 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
107 #endif
108
109 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
110 #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
111 #endif
112
113 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
114 {
115 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
117 },
118 {
119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
129 },
130 {
131 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
133 },
134 {
135 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
136 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
137 }
138 };
139
140 /* set register offset */
141 #define SR(reg_name)\
142 .reg_name = mm ## reg_name
143
144 /* set register offset with instance */
145 #define SRI(reg_name, block, id)\
146 .reg_name = mm ## block ## id ## _ ## reg_name
147
148 static const struct dce_disp_clk_registers disp_clk_regs = {
149 CLK_COMMON_REG_LIST_DCE_BASE()
150 };
151
152 static const struct dce_disp_clk_shift disp_clk_shift = {
153 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
154 };
155
156 static const struct dce_disp_clk_mask disp_clk_mask = {
157 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
158 };
159
160 static const struct dce_dmcu_registers dmcu_regs = {
161 DMCU_DCE110_COMMON_REG_LIST()
162 };
163
164 static const struct dce_dmcu_shift dmcu_shift = {
165 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
166 };
167
168 static const struct dce_dmcu_mask dmcu_mask = {
169 DMCU_MASK_SH_LIST_DCE110(_MASK)
170 };
171
172 static const struct dce_abm_registers abm_regs = {
173 ABM_DCE110_COMMON_REG_LIST()
174 };
175
176 static const struct dce_abm_shift abm_shift = {
177 ABM_MASK_SH_LIST_DCE110(__SHIFT)
178 };
179
180 static const struct dce_abm_mask abm_mask = {
181 ABM_MASK_SH_LIST_DCE110(_MASK)
182 };
183
184 #define ipp_regs(id)\
185 [id] = {\
186 IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188
189 static const struct dce_ipp_registers ipp_regs[] = {
190 ipp_regs(0),
191 ipp_regs(1),
192 ipp_regs(2)
193 };
194
195 static const struct dce_ipp_shift ipp_shift = {
196 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
197 };
198
199 static const struct dce_ipp_mask ipp_mask = {
200 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
201 };
202
203 #define transform_regs(id)\
204 [id] = {\
205 XFM_COMMON_REG_LIST_DCE110(id)\
206 }
207
208 static const struct dce_transform_registers xfm_regs[] = {
209 transform_regs(0),
210 transform_regs(1),
211 transform_regs(2)
212 };
213
214 static const struct dce_transform_shift xfm_shift = {
215 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
216 };
217
218 static const struct dce_transform_mask xfm_mask = {
219 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
220 };
221
222 #define aux_regs(id)\
223 [id] = {\
224 AUX_REG_LIST(id)\
225 }
226
227 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
228 aux_regs(0),
229 aux_regs(1),
230 aux_regs(2),
231 aux_regs(3),
232 aux_regs(4),
233 aux_regs(5)
234 };
235
236 #define hpd_regs(id)\
237 [id] = {\
238 HPD_REG_LIST(id)\
239 }
240
241 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
242 hpd_regs(0),
243 hpd_regs(1),
244 hpd_regs(2),
245 hpd_regs(3),
246 hpd_regs(4),
247 hpd_regs(5)
248 };
249
250
251 #define link_regs(id)\
252 [id] = {\
253 LE_DCE110_REG_LIST(id)\
254 }
255
256 static const struct dce110_link_enc_registers link_enc_regs[] = {
257 link_regs(0),
258 link_regs(1),
259 link_regs(2),
260 link_regs(3),
261 link_regs(4),
262 link_regs(5),
263 link_regs(6),
264 };
265
266 #define stream_enc_regs(id)\
267 [id] = {\
268 SE_COMMON_REG_LIST(id),\
269 .TMDS_CNTL = 0,\
270 }
271
272 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
273 stream_enc_regs(0),
274 stream_enc_regs(1),
275 stream_enc_regs(2)
276 };
277
278 static const struct dce_stream_encoder_shift se_shift = {
279 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
280 };
281
282 static const struct dce_stream_encoder_mask se_mask = {
283 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
284 };
285
286 #define opp_regs(id)\
287 [id] = {\
288 OPP_DCE_110_REG_LIST(id),\
289 }
290
291 static const struct dce_opp_registers opp_regs[] = {
292 opp_regs(0),
293 opp_regs(1),
294 opp_regs(2),
295 opp_regs(3),
296 opp_regs(4),
297 opp_regs(5)
298 };
299
300 static const struct dce_opp_shift opp_shift = {
301 OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
302 };
303
304 static const struct dce_opp_mask opp_mask = {
305 OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
306 };
307
308 #define audio_regs(id)\
309 [id] = {\
310 AUD_COMMON_REG_LIST(id)\
311 }
312
313 static const struct dce_audio_registers audio_regs[] = {
314 audio_regs(0),
315 audio_regs(1),
316 audio_regs(2),
317 audio_regs(3),
318 audio_regs(4),
319 audio_regs(5),
320 audio_regs(6),
321 };
322
323 static const struct dce_audio_shift audio_shift = {
324 AUD_COMMON_MASK_SH_LIST(__SHIFT)
325 };
326
327 static const struct dce_aduio_mask audio_mask = {
328 AUD_COMMON_MASK_SH_LIST(_MASK)
329 };
330
331 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
332
333
334 #define clk_src_regs(id)\
335 [id] = {\
336 CS_COMMON_REG_LIST_DCE_100_110(id),\
337 }
338
339 static const struct dce110_clk_src_regs clk_src_regs[] = {
340 clk_src_regs(0),
341 clk_src_regs(1),
342 clk_src_regs(2)
343 };
344
345 static const struct dce110_clk_src_shift cs_shift = {
346 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
347 };
348
349 static const struct dce110_clk_src_mask cs_mask = {
350 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
351 };
352
353 static const struct bios_registers bios_regs = {
354 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
355 };
356
357 static const struct resource_caps carrizo_resource_cap = {
358 .num_timing_generator = 3,
359 .num_video_plane = 1,
360 .num_audio = 3,
361 .num_stream_encoder = 3,
362 .num_pll = 2,
363 };
364
365 static const struct resource_caps stoney_resource_cap = {
366 .num_timing_generator = 2,
367 .num_video_plane = 1,
368 .num_audio = 3,
369 .num_stream_encoder = 3,
370 .num_pll = 2,
371 };
372
373 #define CTX ctx
374 #define REG(reg) mm ## reg
375
376 #ifndef mmCC_DC_HDMI_STRAPS
377 #define mmCC_DC_HDMI_STRAPS 0x4819
378 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
379 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
380 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
381 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
382 #endif
383
384 static void read_dce_straps(
385 struct dc_context *ctx,
386 struct resource_straps *straps)
387 {
388 REG_GET_2(CC_DC_HDMI_STRAPS,
389 HDMI_DISABLE, &straps->hdmi_disable,
390 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
391
392 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
393 }
394
395 static struct audio *create_audio(
396 struct dc_context *ctx, unsigned int inst)
397 {
398 return dce_audio_create(ctx, inst,
399 &audio_regs[inst], &audio_shift, &audio_mask);
400 }
401
402 static struct timing_generator *dce110_timing_generator_create(
403 struct dc_context *ctx,
404 uint32_t instance,
405 const struct dce110_timing_generator_offsets *offsets)
406 {
407 struct dce110_timing_generator *tg110 =
408 dm_alloc(sizeof(struct dce110_timing_generator));
409
410 if (!tg110)
411 return NULL;
412
413 if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
414 return &tg110->base;
415
416 BREAK_TO_DEBUGGER();
417 dm_free(tg110);
418 return NULL;
419 }
420
421 static struct stream_encoder *dce110_stream_encoder_create(
422 enum engine_id eng_id,
423 struct dc_context *ctx)
424 {
425 struct dce110_stream_encoder *enc110 =
426 dm_alloc(sizeof(struct dce110_stream_encoder));
427
428 if (!enc110)
429 return NULL;
430
431 if (dce110_stream_encoder_construct(
432 enc110, ctx, ctx->dc_bios, eng_id,
433 &stream_enc_regs[eng_id], &se_shift, &se_mask))
434 return &enc110->base;
435
436 BREAK_TO_DEBUGGER();
437 dm_free(enc110);
438 return NULL;
439 }
440
441 #define SRII(reg_name, block, id)\
442 .reg_name[id] = mm ## block ## id ## _ ## reg_name
443
444 static const struct dce_hwseq_registers hwseq_stoney_reg = {
445 HWSEQ_ST_REG_LIST()
446 };
447
448 static const struct dce_hwseq_registers hwseq_cz_reg = {
449 HWSEQ_CZ_REG_LIST()
450 };
451
452 static const struct dce_hwseq_shift hwseq_shift = {
453 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
454 };
455
456 static const struct dce_hwseq_mask hwseq_mask = {
457 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
458 };
459
460 static struct dce_hwseq *dce110_hwseq_create(
461 struct dc_context *ctx)
462 {
463 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
464
465 if (hws) {
466 hws->ctx = ctx;
467 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
468 &hwseq_stoney_reg : &hwseq_cz_reg;
469 hws->shifts = &hwseq_shift;
470 hws->masks = &hwseq_mask;
471 hws->wa.blnd_crtc_trigger = true;
472 }
473 return hws;
474 }
475
476 static const struct resource_create_funcs res_create_funcs = {
477 .read_dce_straps = read_dce_straps,
478 .create_audio = create_audio,
479 .create_stream_encoder = dce110_stream_encoder_create,
480 .create_hwseq = dce110_hwseq_create,
481 };
482
483 #define mi_inst_regs(id) { \
484 MI_DCE11_REG_LIST(id), \
485 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
486 }
487 static const struct dce_mem_input_registers mi_regs[] = {
488 mi_inst_regs(0),
489 mi_inst_regs(1),
490 mi_inst_regs(2),
491 };
492
493 static const struct dce_mem_input_shift mi_shifts = {
494 MI_DCE11_MASK_SH_LIST(__SHIFT),
495 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
496 };
497
498 static const struct dce_mem_input_mask mi_masks = {
499 MI_DCE11_MASK_SH_LIST(_MASK),
500 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
501 };
502
503
504 static struct mem_input *dce110_mem_input_create(
505 struct dc_context *ctx,
506 uint32_t inst)
507 {
508 struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
509
510 if (!dce_mi) {
511 BREAK_TO_DEBUGGER();
512 return NULL;
513 }
514
515 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
516 dce_mi->wa.single_head_rdreq_dmif_limit = 3;
517 return &dce_mi->base;
518 }
519
520 static void dce110_transform_destroy(struct transform **xfm)
521 {
522 dm_free(TO_DCE_TRANSFORM(*xfm));
523 *xfm = NULL;
524 }
525
526 static struct transform *dce110_transform_create(
527 struct dc_context *ctx,
528 uint32_t inst)
529 {
530 struct dce_transform *transform =
531 dm_alloc(sizeof(struct dce_transform));
532
533 if (!transform)
534 return NULL;
535
536 if (dce_transform_construct(transform, ctx, inst,
537 &xfm_regs[inst], &xfm_shift, &xfm_mask))
538 return &transform->base;
539
540 BREAK_TO_DEBUGGER();
541 dm_free(transform);
542 return NULL;
543 }
544
545 static struct input_pixel_processor *dce110_ipp_create(
546 struct dc_context *ctx, uint32_t inst)
547 {
548 struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
549
550 if (!ipp) {
551 BREAK_TO_DEBUGGER();
552 return NULL;
553 }
554
555 dce_ipp_construct(ipp, ctx, inst,
556 &ipp_regs[inst], &ipp_shift, &ipp_mask);
557 return &ipp->base;
558 }
559
560 static const struct encoder_feature_support link_enc_feature = {
561 .max_hdmi_deep_color = COLOR_DEPTH_121212,
562 .max_hdmi_pixel_clock = 594000,
563 .flags.bits.IS_HBR2_CAPABLE = true,
564 .flags.bits.IS_TPS3_CAPABLE = true,
565 .flags.bits.IS_YCBCR_CAPABLE = true
566 };
567
568 struct link_encoder *dce110_link_encoder_create(
569 const struct encoder_init_data *enc_init_data)
570 {
571 struct dce110_link_encoder *enc110 =
572 dm_alloc(sizeof(struct dce110_link_encoder));
573
574 if (!enc110)
575 return NULL;
576
577 if (dce110_link_encoder_construct(
578 enc110,
579 enc_init_data,
580 &link_enc_feature,
581 &link_enc_regs[enc_init_data->transmitter],
582 &link_enc_aux_regs[enc_init_data->channel - 1],
583 &link_enc_hpd_regs[enc_init_data->hpd_source])) {
584
585 return &enc110->base;
586 }
587
588 BREAK_TO_DEBUGGER();
589 dm_free(enc110);
590 return NULL;
591 }
592
593 static struct output_pixel_processor *dce110_opp_create(
594 struct dc_context *ctx,
595 uint32_t inst)
596 {
597 struct dce110_opp *opp =
598 dm_alloc(sizeof(struct dce110_opp));
599
600 if (!opp)
601 return NULL;
602
603 if (dce110_opp_construct(opp,
604 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
605 return &opp->base;
606
607 BREAK_TO_DEBUGGER();
608 dm_free(opp);
609 return NULL;
610 }
611
612 struct clock_source *dce110_clock_source_create(
613 struct dc_context *ctx,
614 struct dc_bios *bios,
615 enum clock_source_id id,
616 const struct dce110_clk_src_regs *regs,
617 bool dp_clk_src)
618 {
619 struct dce110_clk_src *clk_src =
620 dm_alloc(sizeof(struct dce110_clk_src));
621
622 if (!clk_src)
623 return NULL;
624
625 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
626 regs, &cs_shift, &cs_mask)) {
627 clk_src->base.dp_clk_src = dp_clk_src;
628 return &clk_src->base;
629 }
630
631 BREAK_TO_DEBUGGER();
632 return NULL;
633 }
634
635 void dce110_clock_source_destroy(struct clock_source **clk_src)
636 {
637 struct dce110_clk_src *dce110_clk_src;
638
639 if (!clk_src)
640 return;
641
642 dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
643
644 if (dce110_clk_src->dp_ss_params)
645 dm_free(dce110_clk_src->dp_ss_params);
646
647 if (dce110_clk_src->hdmi_ss_params)
648 dm_free(dce110_clk_src->hdmi_ss_params);
649
650 if (dce110_clk_src->dvi_ss_params)
651 dm_free(dce110_clk_src->dvi_ss_params);
652
653 dm_free(dce110_clk_src);
654 *clk_src = NULL;
655 }
656
657 static void destruct(struct dce110_resource_pool *pool)
658 {
659 unsigned int i;
660
661 for (i = 0; i < pool->base.pipe_count; i++) {
662 if (pool->base.opps[i] != NULL)
663 dce110_opp_destroy(&pool->base.opps[i]);
664
665 if (pool->base.transforms[i] != NULL)
666 dce110_transform_destroy(&pool->base.transforms[i]);
667
668 if (pool->base.ipps[i] != NULL)
669 dce_ipp_destroy(&pool->base.ipps[i]);
670
671 if (pool->base.mis[i] != NULL) {
672 dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
673 pool->base.mis[i] = NULL;
674 }
675
676 if (pool->base.timing_generators[i] != NULL) {
677 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
678 pool->base.timing_generators[i] = NULL;
679 }
680 }
681
682 for (i = 0; i < pool->base.stream_enc_count; i++) {
683 if (pool->base.stream_enc[i] != NULL)
684 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
685 }
686
687 for (i = 0; i < pool->base.clk_src_count; i++) {
688 if (pool->base.clock_sources[i] != NULL) {
689 dce110_clock_source_destroy(&pool->base.clock_sources[i]);
690 }
691 }
692
693 if (pool->base.dp_clock_source != NULL)
694 dce110_clock_source_destroy(&pool->base.dp_clock_source);
695
696 for (i = 0; i < pool->base.audio_count; i++) {
697 if (pool->base.audios[i] != NULL) {
698 dce_aud_destroy(&pool->base.audios[i]);
699 }
700 }
701
702 if (pool->base.abm != NULL)
703 dce_abm_destroy(&pool->base.abm);
704
705 if (pool->base.dmcu != NULL)
706 dce_dmcu_destroy(&pool->base.dmcu);
707
708 if (pool->base.display_clock != NULL)
709 dce_disp_clk_destroy(&pool->base.display_clock);
710
711 if (pool->base.irqs != NULL) {
712 dal_irq_service_destroy(&pool->base.irqs);
713 }
714 }
715
716
717 static void get_pixel_clock_parameters(
718 const struct pipe_ctx *pipe_ctx,
719 struct pixel_clk_params *pixel_clk_params)
720 {
721 const struct dc_stream_state *stream = pipe_ctx->stream;
722
723 /*TODO: is this halved for YCbCr 420? in that case we might want to move
724 * the pixel clock normalization for hdmi up to here instead of doing it
725 * in pll_adjust_pix_clk
726 */
727 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
728 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
729 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
730 pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
731 /* TODO: un-hardcode*/
732 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
733 LINK_RATE_REF_FREQ_IN_KHZ;
734 pixel_clk_params->flags.ENABLE_SS = 0;
735 pixel_clk_params->color_depth =
736 stream->timing.display_color_depth;
737 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
738 pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
739 PIXEL_ENCODING_YCBCR420);
740 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
741 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
742 pixel_clk_params->color_depth = COLOR_DEPTH_888;
743 }
744 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
745 pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2;
746 }
747 }
748
749 enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
750 {
751 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
752 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
753 pipe_ctx->clock_source,
754 &pipe_ctx->pix_clk_params,
755 &pipe_ctx->pll_settings);
756 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
757 &pipe_ctx->stream->bit_depth_params);
758 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
759
760 return DC_OK;
761 }
762
763 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
764 {
765 if (pipe_ctx->pipe_idx != underlay_idx)
766 return true;
767 if (!pipe_ctx->plane_state)
768 return false;
769 if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
770 return false;
771 return true;
772 }
773
774 static enum dc_status build_mapped_resource(
775 const struct core_dc *dc,
776 struct validate_context *context,
777 struct validate_context *old_context)
778 {
779 enum dc_status status = DC_OK;
780 uint8_t i, j;
781
782 for (i = 0; i < context->stream_count; i++) {
783 struct dc_stream_state *stream = context->streams[i];
784
785 if (old_context && resource_is_stream_unchanged(old_context, stream))
786 continue;
787
788 for (j = 0; j < MAX_PIPES; j++) {
789 struct pipe_ctx *pipe_ctx =
790 &context->res_ctx.pipe_ctx[j];
791
792 if (context->res_ctx.pipe_ctx[j].stream != stream)
793 continue;
794
795 if (!is_surface_pixel_format_supported(pipe_ctx,
796 dc->res_pool->underlay_pipe_index))
797 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
798
799 status = dce110_resource_build_pipe_hw_param(pipe_ctx);
800
801 if (status != DC_OK)
802 return status;
803
804 /* TODO: validate audio ASIC caps, encoder */
805
806 resource_build_info_frame(pipe_ctx);
807
808 /* do not need to validate non root pipes */
809 break;
810 }
811 }
812
813 return DC_OK;
814 }
815
816 bool dce110_validate_bandwidth(
817 const struct core_dc *dc,
818 struct validate_context *context)
819 {
820 bool result = false;
821
822 dm_logger_write(
823 dc->ctx->logger, LOG_BANDWIDTH_CALCS,
824 "%s: start",
825 __func__);
826
827 if (bw_calcs(
828 dc->ctx,
829 &dc->bw_dceip,
830 &dc->bw_vbios,
831 context->res_ctx.pipe_ctx,
832 dc->res_pool->pipe_count,
833 &context->bw.dce))
834 result = true;
835
836 if (!result)
837 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
838 "%s: %dx%d@%d Bandwidth validation failed!\n",
839 __func__,
840 context->streams[0]->timing.h_addressable,
841 context->streams[0]->timing.v_addressable,
842 context->streams[0]->timing.pix_clk_khz);
843
844 if (memcmp(&dc->current_context->bw.dce,
845 &context->bw.dce, sizeof(context->bw.dce))) {
846 struct log_entry log_entry;
847 dm_logger_open(
848 dc->ctx->logger,
849 &log_entry,
850 LOG_BANDWIDTH_CALCS);
851 dm_logger_append(&log_entry, "%s: finish,\n"
852 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
853 "stutMark_b: %d stutMark_a: %d\n",
854 __func__,
855 context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
856 context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
857 context->bw.dce.urgent_wm_ns[0].b_mark,
858 context->bw.dce.urgent_wm_ns[0].a_mark,
859 context->bw.dce.stutter_exit_wm_ns[0].b_mark,
860 context->bw.dce.stutter_exit_wm_ns[0].a_mark);
861 dm_logger_append(&log_entry,
862 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
863 "stutMark_b: %d stutMark_a: %d\n",
864 context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
865 context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
866 context->bw.dce.urgent_wm_ns[1].b_mark,
867 context->bw.dce.urgent_wm_ns[1].a_mark,
868 context->bw.dce.stutter_exit_wm_ns[1].b_mark,
869 context->bw.dce.stutter_exit_wm_ns[1].a_mark);
870 dm_logger_append(&log_entry,
871 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
872 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
873 context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
874 context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
875 context->bw.dce.urgent_wm_ns[2].b_mark,
876 context->bw.dce.urgent_wm_ns[2].a_mark,
877 context->bw.dce.stutter_exit_wm_ns[2].b_mark,
878 context->bw.dce.stutter_exit_wm_ns[2].a_mark,
879 context->bw.dce.stutter_mode_enable);
880 dm_logger_append(&log_entry,
881 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
882 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
883 context->bw.dce.cpuc_state_change_enable,
884 context->bw.dce.cpup_state_change_enable,
885 context->bw.dce.nbp_state_change_enable,
886 context->bw.dce.all_displays_in_sync,
887 context->bw.dce.dispclk_khz,
888 context->bw.dce.sclk_khz,
889 context->bw.dce.sclk_deep_sleep_khz,
890 context->bw.dce.yclk_khz,
891 context->bw.dce.blackout_recovery_time_us);
892 dm_logger_close(&log_entry);
893 }
894 return result;
895 }
896
897 static bool dce110_validate_surface_sets(
898 const struct dc_validation_set set[],
899 int set_count)
900 {
901 int i;
902
903 for (i = 0; i < set_count; i++) {
904 if (set[i].plane_count == 0)
905 continue;
906
907 if (set[i].plane_count > 2)
908 return false;
909
910 if (set[i].plane_states[0]->format
911 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
912 return false;
913
914 if (set[i].plane_count == 2) {
915 if (set[i].plane_states[1]->format
916 < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
917 return false;
918 if (set[i].plane_states[1]->src_rect.width > 1920
919 || set[i].plane_states[1]->src_rect.height > 1080)
920 return false;
921
922 if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB)
923 return false;
924 }
925 }
926
927 return true;
928 }
929
930 enum dc_status dce110_validate_with_context(
931 const struct core_dc *dc,
932 const struct dc_validation_set set[],
933 int set_count,
934 struct validate_context *context,
935 struct validate_context *old_context)
936 {
937 struct dc_context *dc_ctx = dc->ctx;
938 enum dc_status result = DC_ERROR_UNEXPECTED;
939 int i;
940
941 if (!dce110_validate_surface_sets(set, set_count))
942 return DC_FAIL_SURFACE_VALIDATE;
943
944 for (i = 0; i < set_count; i++) {
945 context->streams[i] = set[i].stream;
946 dc_stream_retain(context->streams[i]);
947 context->stream_count++;
948 }
949
950 result = resource_map_pool_resources(dc, context, old_context);
951
952 if (result == DC_OK)
953 result = resource_map_clock_resources(dc, context, old_context);
954
955 if (!resource_validate_attach_surfaces(set, set_count,
956 old_context, context, dc->res_pool)) {
957 DC_ERROR("Failed to attach surface to stream!\n");
958 return DC_FAIL_ATTACH_SURFACES;
959 }
960
961 if (result == DC_OK)
962 result = build_mapped_resource(dc, context, old_context);
963
964 if (result == DC_OK)
965 result = resource_build_scaling_params_for_context(dc, context);
966
967 if (result == DC_OK)
968 if (!dce110_validate_bandwidth(dc, context))
969 result = DC_FAIL_BANDWIDTH_VALIDATE;
970
971 return result;
972 }
973
974 enum dc_status dce110_validate_guaranteed(
975 const struct core_dc *dc,
976 struct dc_stream_state *dc_stream,
977 struct validate_context *context)
978 {
979 enum dc_status result = DC_ERROR_UNEXPECTED;
980
981 context->streams[0] = dc_stream;
982 dc_stream_retain(context->streams[0]);
983 context->stream_count++;
984
985 result = resource_map_pool_resources(dc, context, NULL);
986
987 if (result == DC_OK)
988 result = resource_map_clock_resources(dc, context, NULL);
989
990 if (result == DC_OK)
991 result = build_mapped_resource(dc, context, NULL);
992
993 if (result == DC_OK) {
994 validate_guaranteed_copy_streams(
995 context, dc->public.caps.max_streams);
996 result = resource_build_scaling_params_for_context(dc, context);
997 }
998
999 if (result == DC_OK)
1000 if (!dce110_validate_bandwidth(dc, context))
1001 result = DC_FAIL_BANDWIDTH_VALIDATE;
1002
1003 return result;
1004 }
1005
1006 static struct pipe_ctx *dce110_acquire_underlay(
1007 struct validate_context *context,
1008 const struct resource_pool *pool,
1009 struct dc_stream_state *stream)
1010 {
1011 struct core_dc *dc = DC_TO_CORE(stream->ctx->dc);
1012 struct resource_context *res_ctx = &context->res_ctx;
1013 unsigned int underlay_idx = pool->underlay_pipe_index;
1014 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1015
1016 if (res_ctx->pipe_ctx[underlay_idx].stream)
1017 return NULL;
1018
1019 pipe_ctx->tg = pool->timing_generators[underlay_idx];
1020 pipe_ctx->mi = pool->mis[underlay_idx];
1021 /*pipe_ctx->ipp = res_ctx->pool->ipps[underlay_idx];*/
1022 pipe_ctx->xfm = pool->transforms[underlay_idx];
1023 pipe_ctx->opp = pool->opps[underlay_idx];
1024 pipe_ctx->dis_clk = pool->display_clock;
1025 pipe_ctx->pipe_idx = underlay_idx;
1026
1027 pipe_ctx->stream = stream;
1028
1029 if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) {
1030 struct tg_color black_color = {0};
1031 struct dc_bios *dcb = dc->ctx->dc_bios;
1032
1033 dc->hwss.enable_display_power_gating(
1034 dc,
1035 pipe_ctx->pipe_idx,
1036 dcb, PIPE_GATING_CONTROL_DISABLE);
1037
1038 /*
1039 * This is for powering on underlay, so crtc does not
1040 * need to be enabled
1041 */
1042
1043 pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg,
1044 &stream->timing,
1045 false);
1046
1047 pipe_ctx->tg->funcs->enable_advanced_request(
1048 pipe_ctx->tg,
1049 true,
1050 &stream->timing);
1051
1052 pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi,
1053 stream->timing.h_total,
1054 stream->timing.v_total,
1055 stream->timing.pix_clk_khz,
1056 context->stream_count);
1057
1058 color_space_to_black_color(dc,
1059 COLOR_SPACE_YCBCR601, &black_color);
1060 pipe_ctx->tg->funcs->set_blank_color(
1061 pipe_ctx->tg,
1062 &black_color);
1063 }
1064
1065 return pipe_ctx;
1066 }
1067
1068 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1069 {
1070 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1071
1072 destruct(dce110_pool);
1073 dm_free(dce110_pool);
1074 *pool = NULL;
1075 }
1076
1077
1078 static const struct resource_funcs dce110_res_pool_funcs = {
1079 .destroy = dce110_destroy_resource_pool,
1080 .link_enc_create = dce110_link_encoder_create,
1081 .validate_with_context = dce110_validate_with_context,
1082 .validate_guaranteed = dce110_validate_guaranteed,
1083 .validate_bandwidth = dce110_validate_bandwidth,
1084 .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1085 };
1086
1087 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1088 {
1089 struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv));
1090 struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv));
1091 struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
1092 struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));
1093
1094 if ((dce110_tgv == NULL) ||
1095 (dce110_xfmv == NULL) ||
1096 (dce110_miv == NULL) ||
1097 (dce110_oppv == NULL))
1098 return false;
1099
1100 if (!dce110_opp_v_construct(dce110_oppv, ctx))
1101 return false;
1102
1103 dce110_timing_generator_v_construct(dce110_tgv, ctx);
1104 dce110_mem_input_v_construct(dce110_miv, ctx);
1105 dce110_transform_v_construct(dce110_xfmv, ctx);
1106
1107 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1108 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1109 pool->mis[pool->pipe_count] = &dce110_miv->base;
1110 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1111 pool->pipe_count++;
1112
1113 /* update the public caps to indicate an underlay is available */
1114 ctx->dc->caps.max_slave_planes = 1;
1115 ctx->dc->caps.max_slave_planes = 1;
1116
1117 return true;
1118 }
1119
1120 static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
1121 {
1122 struct dm_pp_clock_levels clks = {0};
1123
1124 /*do system clock*/
1125 dm_pp_get_clock_levels_by_type(
1126 dc->ctx,
1127 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1128 &clks);
1129 /* convert all the clock fro kHz to fix point mHz */
1130 dc->bw_vbios.high_sclk = bw_frc_to_fixed(
1131 clks.clocks_in_khz[clks.num_levels-1], 1000);
1132 dc->bw_vbios.mid1_sclk = bw_frc_to_fixed(
1133 clks.clocks_in_khz[clks.num_levels/8], 1000);
1134 dc->bw_vbios.mid2_sclk = bw_frc_to_fixed(
1135 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1136 dc->bw_vbios.mid3_sclk = bw_frc_to_fixed(
1137 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1138 dc->bw_vbios.mid4_sclk = bw_frc_to_fixed(
1139 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1140 dc->bw_vbios.mid5_sclk = bw_frc_to_fixed(
1141 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1142 dc->bw_vbios.mid6_sclk = bw_frc_to_fixed(
1143 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1144 dc->bw_vbios.low_sclk = bw_frc_to_fixed(
1145 clks.clocks_in_khz[0], 1000);
1146 dc->sclk_lvls = clks;
1147
1148 /*do display clock*/
1149 dm_pp_get_clock_levels_by_type(
1150 dc->ctx,
1151 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1152 &clks);
1153 dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
1154 clks.clocks_in_khz[clks.num_levels-1], 1000);
1155 dc->bw_vbios.mid_voltage_max_dispclk = bw_frc_to_fixed(
1156 clks.clocks_in_khz[clks.num_levels>>1], 1000);
1157 dc->bw_vbios.low_voltage_max_dispclk = bw_frc_to_fixed(
1158 clks.clocks_in_khz[0], 1000);
1159
1160 /*do memory clock*/
1161 dm_pp_get_clock_levels_by_type(
1162 dc->ctx,
1163 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1164 &clks);
1165
1166 dc->bw_vbios.low_yclk = bw_frc_to_fixed(
1167 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1168 dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
1169 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1170 1000);
1171 dc->bw_vbios.high_yclk = bw_frc_to_fixed(
1172 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1173 1000);
1174 }
1175
1176 const struct resource_caps *dce110_resource_cap(
1177 struct hw_asic_id *asic_id)
1178 {
1179 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1180 return &stoney_resource_cap;
1181 else
1182 return &carrizo_resource_cap;
1183 }
1184
1185 static bool construct(
1186 uint8_t num_virtual_links,
1187 struct core_dc *dc,
1188 struct dce110_resource_pool *pool,
1189 struct hw_asic_id asic_id)
1190 {
1191 unsigned int i;
1192 struct dc_context *ctx = dc->ctx;
1193 struct dc_firmware_info info;
1194 struct dc_bios *bp;
1195 struct dm_pp_static_clock_info static_clk_info = {0};
1196
1197 ctx->dc_bios->regs = &bios_regs;
1198
1199 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1200 pool->base.funcs = &dce110_res_pool_funcs;
1201
1202 /*************************************************
1203 * Resource + asic cap harcoding *
1204 *************************************************/
1205
1206 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1207 pool->base.underlay_pipe_index = pool->base.pipe_count;
1208
1209 dc->public.caps.max_downscale_ratio = 150;
1210 dc->public.caps.i2c_speed_in_khz = 100;
1211 dc->public.caps.max_cursor_size = 128;
1212
1213 /*************************************************
1214 * Create resources *
1215 *************************************************/
1216
1217 bp = ctx->dc_bios;
1218
1219 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1220 info.external_clock_source_frequency_for_dp != 0) {
1221 pool->base.dp_clock_source =
1222 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1223
1224 pool->base.clock_sources[0] =
1225 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1226 &clk_src_regs[0], false);
1227 pool->base.clock_sources[1] =
1228 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1229 &clk_src_regs[1], false);
1230
1231 pool->base.clk_src_count = 2;
1232
1233 /* TODO: find out if CZ support 3 PLLs */
1234 }
1235
1236 if (pool->base.dp_clock_source == NULL) {
1237 dm_error("DC: failed to create dp clock source!\n");
1238 BREAK_TO_DEBUGGER();
1239 goto res_create_fail;
1240 }
1241
1242 for (i = 0; i < pool->base.clk_src_count; i++) {
1243 if (pool->base.clock_sources[i] == NULL) {
1244 dm_error("DC: failed to create clock sources!\n");
1245 BREAK_TO_DEBUGGER();
1246 goto res_create_fail;
1247 }
1248 }
1249
1250 pool->base.display_clock = dce110_disp_clk_create(ctx,
1251 &disp_clk_regs,
1252 &disp_clk_shift,
1253 &disp_clk_mask);
1254 if (pool->base.display_clock == NULL) {
1255 dm_error("DC: failed to create display clock!\n");
1256 BREAK_TO_DEBUGGER();
1257 goto res_create_fail;
1258 }
1259
1260 pool->base.dmcu = dce_dmcu_create(ctx,
1261 &dmcu_regs,
1262 &dmcu_shift,
1263 &dmcu_mask);
1264 if (pool->base.dmcu == NULL) {
1265 dm_error("DC: failed to create dmcu!\n");
1266 BREAK_TO_DEBUGGER();
1267 goto res_create_fail;
1268 }
1269
1270 pool->base.abm = dce_abm_create(ctx,
1271 &abm_regs,
1272 &abm_shift,
1273 &abm_mask);
1274 if (pool->base.abm == NULL) {
1275 dm_error("DC: failed to create abm!\n");
1276 BREAK_TO_DEBUGGER();
1277 goto res_create_fail;
1278 }
1279
1280 /* get static clock information for PPLIB or firmware, save
1281 * max_clock_state
1282 */
1283 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1284 pool->base.display_clock->max_clks_state =
1285 static_clk_info.max_clocks_state;
1286
1287 {
1288 struct irq_service_init_data init_data;
1289 init_data.ctx = dc->ctx;
1290 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1291 if (!pool->base.irqs)
1292 goto res_create_fail;
1293 }
1294
1295 for (i = 0; i < pool->base.pipe_count; i++) {
1296 pool->base.timing_generators[i] = dce110_timing_generator_create(
1297 ctx, i, &dce110_tg_offsets[i]);
1298 if (pool->base.timing_generators[i] == NULL) {
1299 BREAK_TO_DEBUGGER();
1300 dm_error("DC: failed to create tg!\n");
1301 goto res_create_fail;
1302 }
1303
1304 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1305 if (pool->base.mis[i] == NULL) {
1306 BREAK_TO_DEBUGGER();
1307 dm_error(
1308 "DC: failed to create memory input!\n");
1309 goto res_create_fail;
1310 }
1311
1312 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1313 if (pool->base.ipps[i] == NULL) {
1314 BREAK_TO_DEBUGGER();
1315 dm_error(
1316 "DC: failed to create input pixel processor!\n");
1317 goto res_create_fail;
1318 }
1319
1320 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1321 if (pool->base.transforms[i] == NULL) {
1322 BREAK_TO_DEBUGGER();
1323 dm_error(
1324 "DC: failed to create transform!\n");
1325 goto res_create_fail;
1326 }
1327
1328 pool->base.opps[i] = dce110_opp_create(ctx, i);
1329 if (pool->base.opps[i] == NULL) {
1330 BREAK_TO_DEBUGGER();
1331 dm_error(
1332 "DC: failed to create output pixel processor!\n");
1333 goto res_create_fail;
1334 }
1335 }
1336
1337 #ifdef ENABLE_FBC
1338 dc->fbc_compressor = dce110_compressor_create(ctx);
1339
1340
1341
1342 #endif
1343 if (!underlay_create(ctx, &pool->base))
1344 goto res_create_fail;
1345
1346 if (!resource_construct(num_virtual_links, dc, &pool->base,
1347 &res_create_funcs))
1348 goto res_create_fail;
1349
1350 /* Create hardware sequencer */
1351 if (!dce110_hw_sequencer_construct(dc))
1352 goto res_create_fail;
1353
1354 dc->public.caps.max_planes = pool->base.pipe_count;
1355
1356 bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
1357
1358 bw_calcs_data_update_from_pplib(dc);
1359
1360 return true;
1361
1362 res_create_fail:
1363 destruct(pool);
1364 return false;
1365 }
1366
1367 struct resource_pool *dce110_create_resource_pool(
1368 uint8_t num_virtual_links,
1369 struct core_dc *dc,
1370 struct hw_asic_id asic_id)
1371 {
1372 struct dce110_resource_pool *pool =
1373 dm_alloc(sizeof(struct dce110_resource_pool));
1374
1375 if (!pool)
1376 return NULL;
1377
1378 if (construct(num_virtual_links, dc, pool, asic_id))
1379 return &pool->base;
1380
1381 BREAK_TO_DEBUGGER();
1382 return NULL;
1383 }
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