2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
36 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce/dce_mem_input.h"
39 #include "dce/dce_transform.h"
40 #include "dce/dce_link_encoder.h"
41 #include "dce/dce_stream_encoder.h"
42 #include "dce/dce_audio.h"
43 #include "dce/dce_opp.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_clocks.h"
46 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
49 #include "dce112/dce112_hw_sequencer.h"
50 #include "dce/dce_abm.h"
51 #include "dce/dce_dmcu.h"
53 #include "reg_helper.h"
55 #include "dce/dce_11_2_d.h"
56 #include "dce/dce_11_2_sh_mask.h"
58 #include "dce100/dce100_resource.h"
60 #ifndef mmDP_DPHY_INTERNAL_CTRL
61 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
62 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
63 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
64 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
65 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
66 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
67 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
68 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
69 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
70 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
73 #ifndef mmBIOS_SCRATCH_2
74 #define mmBIOS_SCRATCH_2 0x05CB
75 #define mmBIOS_SCRATCH_6 0x05CF
78 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
79 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
80 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
81 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
82 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
83 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
84 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
85 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
86 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
89 #ifndef mmDP_DPHY_FAST_TRAINING
90 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
91 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
92 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
93 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
94 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
95 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
96 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
97 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
100 enum dce112_clk_src_array_id
{
111 static const struct dce110_timing_generator_offsets dce112_tg_offsets
[] = {
113 .crtc
= (mmCRTC0_CRTC_CONTROL
- mmCRTC_CONTROL
),
114 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
117 .crtc
= (mmCRTC1_CRTC_CONTROL
- mmCRTC_CONTROL
),
118 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
121 .crtc
= (mmCRTC2_CRTC_CONTROL
- mmCRTC_CONTROL
),
122 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
125 .crtc
= (mmCRTC3_CRTC_CONTROL
- mmCRTC_CONTROL
),
126 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
129 .crtc
= (mmCRTC4_CRTC_CONTROL
- mmCRTC_CONTROL
),
130 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
133 .crtc
= (mmCRTC5_CRTC_CONTROL
- mmCRTC_CONTROL
),
134 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
138 /* set register offset */
139 #define SR(reg_name)\
140 .reg_name = mm ## reg_name
142 /* set register offset with instance */
143 #define SRI(reg_name, block, id)\
144 .reg_name = mm ## block ## id ## _ ## reg_name
147 static const struct dce_disp_clk_registers disp_clk_regs
= {
148 CLK_COMMON_REG_LIST_DCE_BASE()
151 static const struct dce_disp_clk_shift disp_clk_shift
= {
152 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
155 static const struct dce_disp_clk_mask disp_clk_mask
= {
156 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
159 static const struct dce_dmcu_registers dmcu_regs
= {
160 DMCU_DCE110_COMMON_REG_LIST()
163 static const struct dce_dmcu_shift dmcu_shift
= {
164 DMCU_MASK_SH_LIST_DCE110(__SHIFT
)
167 static const struct dce_dmcu_mask dmcu_mask
= {
168 DMCU_MASK_SH_LIST_DCE110(_MASK
)
171 static const struct dce_abm_registers abm_regs
= {
172 ABM_DCE110_COMMON_REG_LIST()
175 static const struct dce_abm_shift abm_shift
= {
176 ABM_MASK_SH_LIST_DCE110(__SHIFT
)
179 static const struct dce_abm_mask abm_mask
= {
180 ABM_MASK_SH_LIST_DCE110(_MASK
)
183 #define ipp_regs(id)\
185 IPP_DCE110_REG_LIST_DCE_BASE(id)\
188 static const struct dce_ipp_registers ipp_regs
[] = {
197 static const struct dce_ipp_shift ipp_shift
= {
198 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
201 static const struct dce_ipp_mask ipp_mask
= {
202 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
205 #define transform_regs(id)\
207 XFM_COMMON_REG_LIST_DCE110(id)\
210 static const struct dce_transform_registers xfm_regs
[] = {
219 static const struct dce_transform_shift xfm_shift
= {
220 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
223 static const struct dce_transform_mask xfm_mask
= {
224 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK
)
227 #define aux_regs(id)\
232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs
[] = {
241 #define hpd_regs(id)\
246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs
[] = {
255 #define link_regs(id)\
257 LE_DCE110_REG_LIST(id)\
260 static const struct dce110_link_enc_registers link_enc_regs
[] = {
270 #define stream_enc_regs(id)\
272 SE_COMMON_REG_LIST(id),\
276 static const struct dce110_stream_enc_registers stream_enc_regs
[] = {
285 static const struct dce_stream_encoder_shift se_shift
= {
286 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT
)
289 static const struct dce_stream_encoder_mask se_mask
= {
290 SE_COMMON_MASK_SH_LIST_DCE112(_MASK
)
293 #define opp_regs(id)\
295 OPP_DCE_112_REG_LIST(id),\
298 static const struct dce_opp_registers opp_regs
[] = {
307 static const struct dce_opp_shift opp_shift
= {
308 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT
)
311 static const struct dce_opp_mask opp_mask
= {
312 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK
)
315 #define audio_regs(id)\
317 AUD_COMMON_REG_LIST(id)\
320 static const struct dce_audio_registers audio_regs
[] = {
329 static const struct dce_audio_shift audio_shift
= {
330 AUD_COMMON_MASK_SH_LIST(__SHIFT
)
333 static const struct dce_aduio_mask audio_mask
= {
334 AUD_COMMON_MASK_SH_LIST(_MASK
)
337 #define clk_src_regs(index, id)\
339 CS_COMMON_REG_LIST_DCE_112(id),\
342 static const struct dce110_clk_src_regs clk_src_regs
[] = {
351 static const struct dce110_clk_src_shift cs_shift
= {
352 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT
)
355 static const struct dce110_clk_src_mask cs_mask
= {
356 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK
)
359 static const struct bios_registers bios_regs
= {
360 .BIOS_SCRATCH_6
= mmBIOS_SCRATCH_6
363 static const struct resource_caps polaris_10_resource_cap
= {
364 .num_timing_generator
= 6,
366 .num_stream_encoder
= 6,
367 .num_pll
= 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
370 static const struct resource_caps polaris_11_resource_cap
= {
371 .num_timing_generator
= 5,
373 .num_stream_encoder
= 5,
374 .num_pll
= 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
378 #define REG(reg) mm ## reg
380 #ifndef mmCC_DC_HDMI_STRAPS
381 #define mmCC_DC_HDMI_STRAPS 0x4819
382 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
383 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
384 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
385 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
388 static void read_dce_straps(
389 struct dc_context
*ctx
,
390 struct resource_straps
*straps
)
392 REG_GET_2(CC_DC_HDMI_STRAPS
,
393 HDMI_DISABLE
, &straps
->hdmi_disable
,
394 AUDIO_STREAM_NUMBER
, &straps
->audio_stream_number
);
396 REG_GET(DC_PINSTRAPS
, DC_PINSTRAPS_AUDIO
, &straps
->dc_pinstraps_audio
);
399 static struct audio
*create_audio(
400 struct dc_context
*ctx
, unsigned int inst
)
402 return dce_audio_create(ctx
, inst
,
403 &audio_regs
[inst
], &audio_shift
, &audio_mask
);
407 static struct timing_generator
*dce112_timing_generator_create(
408 struct dc_context
*ctx
,
410 const struct dce110_timing_generator_offsets
*offsets
)
412 struct dce110_timing_generator
*tg110
=
413 dm_alloc(sizeof(struct dce110_timing_generator
));
418 if (dce110_timing_generator_construct(tg110
, ctx
, instance
, offsets
))
426 static struct stream_encoder
*dce112_stream_encoder_create(
427 enum engine_id eng_id
,
428 struct dc_context
*ctx
)
430 struct dce110_stream_encoder
*enc110
=
431 dm_alloc(sizeof(struct dce110_stream_encoder
));
436 if (dce110_stream_encoder_construct(
437 enc110
, ctx
, ctx
->dc_bios
, eng_id
,
438 &stream_enc_regs
[eng_id
], &se_shift
, &se_mask
))
439 return &enc110
->base
;
446 #define SRII(reg_name, block, id)\
447 .reg_name[id] = mm ## block ## id ## _ ## reg_name
449 static const struct dce_hwseq_registers hwseq_reg
= {
450 HWSEQ_DCE112_REG_LIST()
453 static const struct dce_hwseq_shift hwseq_shift
= {
454 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT
)
457 static const struct dce_hwseq_mask hwseq_mask
= {
458 HWSEQ_DCE112_MASK_SH_LIST(_MASK
)
461 static struct dce_hwseq
*dce112_hwseq_create(
462 struct dc_context
*ctx
)
464 struct dce_hwseq
*hws
= dm_alloc(sizeof(struct dce_hwseq
));
468 hws
->regs
= &hwseq_reg
;
469 hws
->shifts
= &hwseq_shift
;
470 hws
->masks
= &hwseq_mask
;
475 static const struct resource_create_funcs res_create_funcs
= {
476 .read_dce_straps
= read_dce_straps
,
477 .create_audio
= create_audio
,
478 .create_stream_encoder
= dce112_stream_encoder_create
,
479 .create_hwseq
= dce112_hwseq_create
,
482 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
483 static const struct dce_mem_input_registers mi_regs
[] = {
492 static const struct dce_mem_input_shift mi_shifts
= {
493 MI_DCE11_2_MASK_SH_LIST(__SHIFT
)
496 static const struct dce_mem_input_mask mi_masks
= {
497 MI_DCE11_2_MASK_SH_LIST(_MASK
)
500 static struct mem_input
*dce112_mem_input_create(
501 struct dc_context
*ctx
,
504 struct dce_mem_input
*dce_mi
= dm_alloc(sizeof(struct dce_mem_input
));
511 dce112_mem_input_construct(dce_mi
, ctx
, inst
, &mi_regs
[inst
], &mi_shifts
, &mi_masks
);
512 return &dce_mi
->base
;
515 static void dce112_transform_destroy(struct transform
**xfm
)
517 dm_free(TO_DCE_TRANSFORM(*xfm
));
521 static struct transform
*dce112_transform_create(
522 struct dc_context
*ctx
,
525 struct dce_transform
*transform
=
526 dm_alloc(sizeof(struct dce_transform
));
531 if (dce_transform_construct(transform
, ctx
, inst
,
532 &xfm_regs
[inst
], &xfm_shift
, &xfm_mask
)) {
533 transform
->lb_memory_size
= 0x1404; /*5124*/
534 return &transform
->base
;
542 static const struct encoder_feature_support link_enc_feature
= {
543 .max_hdmi_deep_color
= COLOR_DEPTH_121212
,
544 .max_hdmi_pixel_clock
= 600000,
545 .ycbcr420_supported
= true,
546 .flags
.bits
.IS_HBR2_CAPABLE
= true,
547 .flags
.bits
.IS_HBR3_CAPABLE
= true,
548 .flags
.bits
.IS_TPS3_CAPABLE
= true,
549 .flags
.bits
.IS_TPS4_CAPABLE
= true,
550 .flags
.bits
.IS_YCBCR_CAPABLE
= true
553 struct link_encoder
*dce112_link_encoder_create(
554 const struct encoder_init_data
*enc_init_data
)
556 struct dce110_link_encoder
*enc110
=
557 dm_alloc(sizeof(struct dce110_link_encoder
));
562 if (dce110_link_encoder_construct(
566 &link_enc_regs
[enc_init_data
->transmitter
],
567 &link_enc_aux_regs
[enc_init_data
->channel
- 1],
568 &link_enc_hpd_regs
[enc_init_data
->hpd_source
])) {
570 return &enc110
->base
;
578 static struct input_pixel_processor
*dce112_ipp_create(
579 struct dc_context
*ctx
, uint32_t inst
)
581 struct dce_ipp
*ipp
= dm_alloc(sizeof(struct dce_ipp
));
588 dce_ipp_construct(ipp
, ctx
, inst
,
589 &ipp_regs
[inst
], &ipp_shift
, &ipp_mask
);
593 struct output_pixel_processor
*dce112_opp_create(
594 struct dc_context
*ctx
,
597 struct dce110_opp
*opp
=
598 dm_alloc(sizeof(struct dce110_opp
));
603 if (dce110_opp_construct(opp
,
604 ctx
, inst
, &opp_regs
[inst
], &opp_shift
, &opp_mask
))
612 struct clock_source
*dce112_clock_source_create(
613 struct dc_context
*ctx
,
614 struct dc_bios
*bios
,
615 enum clock_source_id id
,
616 const struct dce110_clk_src_regs
*regs
,
619 struct dce110_clk_src
*clk_src
=
620 dm_alloc(sizeof(struct dce110_clk_src
));
625 if (dce110_clk_src_construct(clk_src
, ctx
, bios
, id
,
626 regs
, &cs_shift
, &cs_mask
)) {
627 clk_src
->base
.dp_clk_src
= dp_clk_src
;
628 return &clk_src
->base
;
635 void dce112_clock_source_destroy(struct clock_source
**clk_src
)
637 dm_free(TO_DCE110_CLK_SRC(*clk_src
));
641 static void destruct(struct dce110_resource_pool
*pool
)
645 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
646 if (pool
->base
.opps
[i
] != NULL
)
647 dce110_opp_destroy(&pool
->base
.opps
[i
]);
649 if (pool
->base
.transforms
[i
] != NULL
)
650 dce112_transform_destroy(&pool
->base
.transforms
[i
]);
652 if (pool
->base
.ipps
[i
] != NULL
)
653 dce_ipp_destroy(&pool
->base
.ipps
[i
]);
655 if (pool
->base
.mis
[i
] != NULL
) {
656 dm_free(TO_DCE_MEM_INPUT(pool
->base
.mis
[i
]));
657 pool
->base
.mis
[i
] = NULL
;
660 if (pool
->base
.timing_generators
[i
] != NULL
) {
661 dm_free(DCE110TG_FROM_TG(pool
->base
.timing_generators
[i
]));
662 pool
->base
.timing_generators
[i
] = NULL
;
666 for (i
= 0; i
< pool
->base
.stream_enc_count
; i
++) {
667 if (pool
->base
.stream_enc
[i
] != NULL
)
668 dm_free(DCE110STRENC_FROM_STRENC(pool
->base
.stream_enc
[i
]));
671 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
672 if (pool
->base
.clock_sources
[i
] != NULL
) {
673 dce112_clock_source_destroy(&pool
->base
.clock_sources
[i
]);
677 if (pool
->base
.dp_clock_source
!= NULL
)
678 dce112_clock_source_destroy(&pool
->base
.dp_clock_source
);
680 for (i
= 0; i
< pool
->base
.audio_count
; i
++) {
681 if (pool
->base
.audios
[i
] != NULL
) {
682 dce_aud_destroy(&pool
->base
.audios
[i
]);
686 if (pool
->base
.abm
!= NULL
)
687 dce_abm_destroy(&pool
->base
.abm
);
689 if (pool
->base
.dmcu
!= NULL
)
690 dce_dmcu_destroy(&pool
->base
.dmcu
);
692 if (pool
->base
.display_clock
!= NULL
)
693 dce_disp_clk_destroy(&pool
->base
.display_clock
);
695 if (pool
->base
.irqs
!= NULL
) {
696 dal_irq_service_destroy(&pool
->base
.irqs
);
700 static struct clock_source
*find_matching_pll(
701 struct resource_context
*res_ctx
,
702 const struct resource_pool
*pool
,
703 const struct dc_stream_state
*const stream
)
705 switch (stream
->sink
->link
->link_enc
->transmitter
) {
706 case TRANSMITTER_UNIPHY_A
:
707 return pool
->clock_sources
[DCE112_CLK_SRC_PLL0
];
708 case TRANSMITTER_UNIPHY_B
:
709 return pool
->clock_sources
[DCE112_CLK_SRC_PLL1
];
710 case TRANSMITTER_UNIPHY_C
:
711 return pool
->clock_sources
[DCE112_CLK_SRC_PLL2
];
712 case TRANSMITTER_UNIPHY_D
:
713 return pool
->clock_sources
[DCE112_CLK_SRC_PLL3
];
714 case TRANSMITTER_UNIPHY_E
:
715 return pool
->clock_sources
[DCE112_CLK_SRC_PLL4
];
716 case TRANSMITTER_UNIPHY_F
:
717 return pool
->clock_sources
[DCE112_CLK_SRC_PLL5
];
725 static enum dc_status
build_mapped_resource(
726 const struct core_dc
*dc
,
727 struct validate_context
*context
,
728 struct validate_context
*old_context
)
730 enum dc_status status
= DC_OK
;
733 for (i
= 0; i
< context
->stream_count
; i
++) {
734 struct dc_stream_state
*stream
= context
->streams
[i
];
736 if (old_context
&& resource_is_stream_unchanged(old_context
, stream
))
739 for (j
= 0; j
< MAX_PIPES
; j
++) {
740 struct pipe_ctx
*pipe_ctx
=
741 &context
->res_ctx
.pipe_ctx
[j
];
743 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
746 status
= dce110_resource_build_pipe_hw_param(pipe_ctx
);
751 resource_build_info_frame(pipe_ctx
);
753 /* do not need to validate non root pipes */
761 bool dce112_validate_bandwidth(
762 const struct core_dc
*dc
,
763 struct validate_context
*context
)
768 dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
776 context
->res_ctx
.pipe_ctx
,
777 dc
->res_pool
->pipe_count
,
782 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_VALIDATION
,
783 "%s: Bandwidth validation failed!",
786 if (memcmp(&dc
->current_context
->bw
.dce
,
787 &context
->bw
.dce
, sizeof(context
->bw
.dce
))) {
788 struct log_entry log_entry
;
792 LOG_BANDWIDTH_CALCS
);
793 dm_logger_append(&log_entry
, "%s: finish,\n"
794 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
795 "stutMark_b: %d stutMark_a: %d\n",
797 context
->bw
.dce
.nbp_state_change_wm_ns
[0].b_mark
,
798 context
->bw
.dce
.nbp_state_change_wm_ns
[0].a_mark
,
799 context
->bw
.dce
.urgent_wm_ns
[0].b_mark
,
800 context
->bw
.dce
.urgent_wm_ns
[0].a_mark
,
801 context
->bw
.dce
.stutter_exit_wm_ns
[0].b_mark
,
802 context
->bw
.dce
.stutter_exit_wm_ns
[0].a_mark
);
803 dm_logger_append(&log_entry
,
804 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
805 "stutMark_b: %d stutMark_a: %d\n",
806 context
->bw
.dce
.nbp_state_change_wm_ns
[1].b_mark
,
807 context
->bw
.dce
.nbp_state_change_wm_ns
[1].a_mark
,
808 context
->bw
.dce
.urgent_wm_ns
[1].b_mark
,
809 context
->bw
.dce
.urgent_wm_ns
[1].a_mark
,
810 context
->bw
.dce
.stutter_exit_wm_ns
[1].b_mark
,
811 context
->bw
.dce
.stutter_exit_wm_ns
[1].a_mark
);
812 dm_logger_append(&log_entry
,
813 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
814 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
815 context
->bw
.dce
.nbp_state_change_wm_ns
[2].b_mark
,
816 context
->bw
.dce
.nbp_state_change_wm_ns
[2].a_mark
,
817 context
->bw
.dce
.urgent_wm_ns
[2].b_mark
,
818 context
->bw
.dce
.urgent_wm_ns
[2].a_mark
,
819 context
->bw
.dce
.stutter_exit_wm_ns
[2].b_mark
,
820 context
->bw
.dce
.stutter_exit_wm_ns
[2].a_mark
,
821 context
->bw
.dce
.stutter_mode_enable
);
822 dm_logger_append(&log_entry
,
823 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
824 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
825 context
->bw
.dce
.cpuc_state_change_enable
,
826 context
->bw
.dce
.cpup_state_change_enable
,
827 context
->bw
.dce
.nbp_state_change_enable
,
828 context
->bw
.dce
.all_displays_in_sync
,
829 context
->bw
.dce
.dispclk_khz
,
830 context
->bw
.dce
.sclk_khz
,
831 context
->bw
.dce
.sclk_deep_sleep_khz
,
832 context
->bw
.dce
.yclk_khz
,
833 context
->bw
.dce
.blackout_recovery_time_us
);
834 dm_logger_close(&log_entry
);
839 enum dc_status
resource_map_phy_clock_resources(
840 const struct core_dc
*dc
,
841 struct validate_context
*context
,
842 struct validate_context
*old_context
)
846 /* acquire new resources */
847 for (i
= 0; i
< context
->stream_count
; i
++) {
848 struct dc_stream_state
*stream
= context
->streams
[i
];
850 if (old_context
&& resource_is_stream_unchanged(old_context
, stream
))
853 for (j
= 0; j
< MAX_PIPES
; j
++) {
854 struct pipe_ctx
*pipe_ctx
=
855 &context
->res_ctx
.pipe_ctx
[j
];
857 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
860 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
)
861 || pipe_ctx
->stream
->signal
== SIGNAL_TYPE_VIRTUAL
)
862 pipe_ctx
->clock_source
=
863 dc
->res_pool
->dp_clock_source
;
865 pipe_ctx
->clock_source
= find_matching_pll(
866 &context
->res_ctx
, dc
->res_pool
,
869 if (pipe_ctx
->clock_source
== NULL
)
870 return DC_NO_CLOCK_SOURCE_RESOURCE
;
872 resource_reference_clock_source(
875 pipe_ctx
->clock_source
);
877 /* only one cs per stream regardless of mpo */
885 static bool dce112_validate_surface_sets(
886 const struct dc_validation_set set
[],
891 for (i
= 0; i
< set_count
; i
++) {
892 if (set
[i
].plane_count
== 0)
895 if (set
[i
].plane_count
> 1)
898 if (set
[i
].plane_states
[0]->format
899 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
906 enum dc_status
dce112_validate_with_context(
907 const struct core_dc
*dc
,
908 const struct dc_validation_set set
[],
910 struct validate_context
*context
,
911 struct validate_context
*old_context
)
913 struct dc_context
*dc_ctx
= dc
->ctx
;
914 enum dc_status result
= DC_ERROR_UNEXPECTED
;
917 if (!dce112_validate_surface_sets(set
, set_count
))
918 return DC_FAIL_SURFACE_VALIDATE
;
920 for (i
= 0; i
< set_count
; i
++) {
921 context
->streams
[i
] = set
[i
].stream
;
922 dc_stream_retain(context
->streams
[i
]);
923 context
->stream_count
++;
926 result
= resource_map_pool_resources(dc
, context
, old_context
);
929 result
= resource_map_phy_clock_resources(dc
, context
, old_context
);
931 if (!resource_validate_attach_surfaces(set
, set_count
,
932 old_context
, context
, dc
->res_pool
)) {
933 DC_ERROR("Failed to attach surface to stream!\n");
934 return DC_FAIL_ATTACH_SURFACES
;
938 result
= build_mapped_resource(dc
, context
, old_context
);
941 result
= resource_build_scaling_params_for_context(dc
, context
);
944 if (!dce112_validate_bandwidth(dc
, context
))
945 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
950 enum dc_status
dce112_validate_guaranteed(
951 const struct core_dc
*dc
,
952 struct dc_stream_state
*stream
,
953 struct validate_context
*context
)
955 enum dc_status result
= DC_ERROR_UNEXPECTED
;
957 context
->streams
[0] = stream
;
958 dc_stream_retain(context
->streams
[0]);
959 context
->stream_count
++;
961 result
= resource_map_pool_resources(dc
, context
, NULL
);
964 result
= resource_map_phy_clock_resources(dc
, context
, NULL
);
967 result
= build_mapped_resource(dc
, context
, NULL
);
969 if (result
== DC_OK
) {
970 validate_guaranteed_copy_streams(
971 context
, dc
->public.caps
.max_streams
);
972 result
= resource_build_scaling_params_for_context(dc
, context
);
976 if (!dce112_validate_bandwidth(dc
, context
))
977 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
982 static void dce112_destroy_resource_pool(struct resource_pool
**pool
)
984 struct dce110_resource_pool
*dce110_pool
= TO_DCE110_RES_POOL(*pool
);
986 destruct(dce110_pool
);
987 dm_free(dce110_pool
);
991 static const struct resource_funcs dce112_res_pool_funcs
= {
992 .destroy
= dce112_destroy_resource_pool
,
993 .link_enc_create
= dce112_link_encoder_create
,
994 .validate_with_context
= dce112_validate_with_context
,
995 .validate_guaranteed
= dce112_validate_guaranteed
,
996 .validate_bandwidth
= dce112_validate_bandwidth
,
997 .validate_plane
= dce100_validate_plane
1000 static void bw_calcs_data_update_from_pplib(struct core_dc
*dc
)
1002 struct dm_pp_clock_levels_with_latency eng_clks
= {0};
1003 struct dm_pp_clock_levels_with_latency mem_clks
= {0};
1004 struct dm_pp_wm_sets_with_clock_ranges clk_ranges
= {0};
1005 struct dm_pp_clock_levels clks
= {0};
1007 /*do system clock TODO PPLIB: after PPLIB implement,
1008 * then remove old way
1010 if (!dm_pp_get_clock_levels_by_type_with_latency(
1012 DM_PP_CLOCK_TYPE_ENGINE_CLK
,
1015 /* This is only for temporary */
1016 dm_pp_get_clock_levels_by_type(
1018 DM_PP_CLOCK_TYPE_ENGINE_CLK
,
1020 /* convert all the clock fro kHz to fix point mHz */
1021 dc
->bw_vbios
.high_sclk
= bw_frc_to_fixed(
1022 clks
.clocks_in_khz
[clks
.num_levels
-1], 1000);
1023 dc
->bw_vbios
.mid1_sclk
= bw_frc_to_fixed(
1024 clks
.clocks_in_khz
[clks
.num_levels
/8], 1000);
1025 dc
->bw_vbios
.mid2_sclk
= bw_frc_to_fixed(
1026 clks
.clocks_in_khz
[clks
.num_levels
*2/8], 1000);
1027 dc
->bw_vbios
.mid3_sclk
= bw_frc_to_fixed(
1028 clks
.clocks_in_khz
[clks
.num_levels
*3/8], 1000);
1029 dc
->bw_vbios
.mid4_sclk
= bw_frc_to_fixed(
1030 clks
.clocks_in_khz
[clks
.num_levels
*4/8], 1000);
1031 dc
->bw_vbios
.mid5_sclk
= bw_frc_to_fixed(
1032 clks
.clocks_in_khz
[clks
.num_levels
*5/8], 1000);
1033 dc
->bw_vbios
.mid6_sclk
= bw_frc_to_fixed(
1034 clks
.clocks_in_khz
[clks
.num_levels
*6/8], 1000);
1035 dc
->bw_vbios
.low_sclk
= bw_frc_to_fixed(
1036 clks
.clocks_in_khz
[0], 1000);
1039 dm_pp_get_clock_levels_by_type(
1041 DM_PP_CLOCK_TYPE_MEMORY_CLK
,
1044 dc
->bw_vbios
.low_yclk
= bw_frc_to_fixed(
1045 clks
.clocks_in_khz
[0] * MEMORY_TYPE_MULTIPLIER
, 1000);
1046 dc
->bw_vbios
.mid_yclk
= bw_frc_to_fixed(
1047 clks
.clocks_in_khz
[clks
.num_levels
>>1] * MEMORY_TYPE_MULTIPLIER
,
1049 dc
->bw_vbios
.high_yclk
= bw_frc_to_fixed(
1050 clks
.clocks_in_khz
[clks
.num_levels
-1] * MEMORY_TYPE_MULTIPLIER
,
1056 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1057 dc
->bw_vbios
.high_sclk
= bw_frc_to_fixed(
1058 eng_clks
.data
[eng_clks
.num_levels
-1].clocks_in_khz
, 1000);
1059 dc
->bw_vbios
.mid1_sclk
= bw_frc_to_fixed(
1060 eng_clks
.data
[eng_clks
.num_levels
/8].clocks_in_khz
, 1000);
1061 dc
->bw_vbios
.mid2_sclk
= bw_frc_to_fixed(
1062 eng_clks
.data
[eng_clks
.num_levels
*2/8].clocks_in_khz
, 1000);
1063 dc
->bw_vbios
.mid3_sclk
= bw_frc_to_fixed(
1064 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
, 1000);
1065 dc
->bw_vbios
.mid4_sclk
= bw_frc_to_fixed(
1066 eng_clks
.data
[eng_clks
.num_levels
*4/8].clocks_in_khz
, 1000);
1067 dc
->bw_vbios
.mid5_sclk
= bw_frc_to_fixed(
1068 eng_clks
.data
[eng_clks
.num_levels
*5/8].clocks_in_khz
, 1000);
1069 dc
->bw_vbios
.mid6_sclk
= bw_frc_to_fixed(
1070 eng_clks
.data
[eng_clks
.num_levels
*6/8].clocks_in_khz
, 1000);
1071 dc
->bw_vbios
.low_sclk
= bw_frc_to_fixed(
1072 eng_clks
.data
[0].clocks_in_khz
, 1000);
1075 dm_pp_get_clock_levels_by_type_with_latency(
1077 DM_PP_CLOCK_TYPE_MEMORY_CLK
,
1080 /* we don't need to call PPLIB for validation clock since they
1081 * also give us the highest sclk and highest mclk (UMA clock).
1082 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1083 * YCLK = UMACLK*m_memoryTypeMultiplier
1085 dc
->bw_vbios
.low_yclk
= bw_frc_to_fixed(
1086 mem_clks
.data
[0].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
, 1000);
1087 dc
->bw_vbios
.mid_yclk
= bw_frc_to_fixed(
1088 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
,
1090 dc
->bw_vbios
.high_yclk
= bw_frc_to_fixed(
1091 mem_clks
.data
[mem_clks
.num_levels
-1].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
,
1094 /* Now notify PPLib/SMU about which Watermarks sets they should select
1095 * depending on DPM state they are in. And update BW MGR GFX Engine and
1096 * Memory clock member variables for Watermarks calculations for each
1099 clk_ranges
.num_wm_sets
= 4;
1100 clk_ranges
.wm_clk_ranges
[0].wm_set_id
= WM_SET_A
;
1101 clk_ranges
.wm_clk_ranges
[0].wm_min_eng_clk_in_khz
=
1102 eng_clks
.data
[0].clocks_in_khz
;
1103 clk_ranges
.wm_clk_ranges
[0].wm_max_eng_clk_in_khz
=
1104 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
- 1;
1105 clk_ranges
.wm_clk_ranges
[0].wm_min_memg_clk_in_khz
=
1106 mem_clks
.data
[0].clocks_in_khz
;
1107 clk_ranges
.wm_clk_ranges
[0].wm_max_mem_clk_in_khz
=
1108 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
- 1;
1110 clk_ranges
.wm_clk_ranges
[1].wm_set_id
= WM_SET_B
;
1111 clk_ranges
.wm_clk_ranges
[1].wm_min_eng_clk_in_khz
=
1112 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
;
1113 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1114 clk_ranges
.wm_clk_ranges
[1].wm_max_eng_clk_in_khz
= 5000000;
1115 clk_ranges
.wm_clk_ranges
[1].wm_min_memg_clk_in_khz
=
1116 mem_clks
.data
[0].clocks_in_khz
;
1117 clk_ranges
.wm_clk_ranges
[1].wm_max_mem_clk_in_khz
=
1118 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
- 1;
1120 clk_ranges
.wm_clk_ranges
[2].wm_set_id
= WM_SET_C
;
1121 clk_ranges
.wm_clk_ranges
[2].wm_min_eng_clk_in_khz
=
1122 eng_clks
.data
[0].clocks_in_khz
;
1123 clk_ranges
.wm_clk_ranges
[2].wm_max_eng_clk_in_khz
=
1124 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
- 1;
1125 clk_ranges
.wm_clk_ranges
[2].wm_min_memg_clk_in_khz
=
1126 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
;
1127 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1128 clk_ranges
.wm_clk_ranges
[2].wm_max_mem_clk_in_khz
= 5000000;
1130 clk_ranges
.wm_clk_ranges
[3].wm_set_id
= WM_SET_D
;
1131 clk_ranges
.wm_clk_ranges
[3].wm_min_eng_clk_in_khz
=
1132 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
;
1133 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1134 clk_ranges
.wm_clk_ranges
[3].wm_max_eng_clk_in_khz
= 5000000;
1135 clk_ranges
.wm_clk_ranges
[3].wm_min_memg_clk_in_khz
=
1136 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
;
1137 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1138 clk_ranges
.wm_clk_ranges
[3].wm_max_mem_clk_in_khz
= 5000000;
1140 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1141 dm_pp_notify_wm_clock_changes(dc
->ctx
, &clk_ranges
);
1144 const struct resource_caps
*dce112_resource_cap(
1145 struct hw_asic_id
*asic_id
)
1147 if (ASIC_REV_IS_POLARIS11_M(asic_id
->hw_internal_rev
) ||
1148 ASIC_REV_IS_POLARIS12_V(asic_id
->hw_internal_rev
))
1149 return &polaris_11_resource_cap
;
1151 return &polaris_10_resource_cap
;
1154 static bool construct(
1155 uint8_t num_virtual_links
,
1157 struct dce110_resource_pool
*pool
)
1160 struct dc_context
*ctx
= dc
->ctx
;
1161 struct dm_pp_static_clock_info static_clk_info
= {0};
1163 ctx
->dc_bios
->regs
= &bios_regs
;
1165 pool
->base
.res_cap
= dce112_resource_cap(&ctx
->asic_id
);
1166 pool
->base
.funcs
= &dce112_res_pool_funcs
;
1168 /*************************************************
1169 * Resource + asic cap harcoding *
1170 *************************************************/
1171 pool
->base
.underlay_pipe_index
= NO_UNDERLAY_PIPE
;
1172 pool
->base
.pipe_count
= pool
->base
.res_cap
->num_timing_generator
;
1173 dc
->public.caps
.max_downscale_ratio
= 200;
1174 dc
->public.caps
.i2c_speed_in_khz
= 100;
1175 dc
->public.caps
.max_cursor_size
= 128;
1177 /*************************************************
1178 * Create resources *
1179 *************************************************/
1181 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL0
] =
1182 dce112_clock_source_create(
1184 CLOCK_SOURCE_COMBO_PHY_PLL0
,
1185 &clk_src_regs
[0], false);
1186 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL1
] =
1187 dce112_clock_source_create(
1189 CLOCK_SOURCE_COMBO_PHY_PLL1
,
1190 &clk_src_regs
[1], false);
1191 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL2
] =
1192 dce112_clock_source_create(
1194 CLOCK_SOURCE_COMBO_PHY_PLL2
,
1195 &clk_src_regs
[2], false);
1196 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL3
] =
1197 dce112_clock_source_create(
1199 CLOCK_SOURCE_COMBO_PHY_PLL3
,
1200 &clk_src_regs
[3], false);
1201 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL4
] =
1202 dce112_clock_source_create(
1204 CLOCK_SOURCE_COMBO_PHY_PLL4
,
1205 &clk_src_regs
[4], false);
1206 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL5
] =
1207 dce112_clock_source_create(
1209 CLOCK_SOURCE_COMBO_PHY_PLL5
,
1210 &clk_src_regs
[5], false);
1211 pool
->base
.clk_src_count
= DCE112_CLK_SRC_TOTAL
;
1213 pool
->base
.dp_clock_source
= dce112_clock_source_create(
1215 CLOCK_SOURCE_ID_DP_DTO
, &clk_src_regs
[0], true);
1218 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
1219 if (pool
->base
.clock_sources
[i
] == NULL
) {
1220 dm_error("DC: failed to create clock sources!\n");
1221 BREAK_TO_DEBUGGER();
1222 goto res_create_fail
;
1226 pool
->base
.display_clock
= dce112_disp_clk_create(ctx
,
1230 if (pool
->base
.display_clock
== NULL
) {
1231 dm_error("DC: failed to create display clock!\n");
1232 BREAK_TO_DEBUGGER();
1233 goto res_create_fail
;
1236 pool
->base
.dmcu
= dce_dmcu_create(ctx
,
1240 if (pool
->base
.dmcu
== NULL
) {
1241 dm_error("DC: failed to create dmcu!\n");
1242 BREAK_TO_DEBUGGER();
1243 goto res_create_fail
;
1246 pool
->base
.abm
= dce_abm_create(ctx
,
1250 if (pool
->base
.abm
== NULL
) {
1251 dm_error("DC: failed to create abm!\n");
1252 BREAK_TO_DEBUGGER();
1253 goto res_create_fail
;
1256 /* get static clock information for PPLIB or firmware, save
1259 if (dm_pp_get_static_clocks(ctx
, &static_clk_info
))
1260 pool
->base
.display_clock
->max_clks_state
=
1261 static_clk_info
.max_clocks_state
;
1264 struct irq_service_init_data init_data
;
1265 init_data
.ctx
= dc
->ctx
;
1266 pool
->base
.irqs
= dal_irq_service_dce110_create(&init_data
);
1267 if (!pool
->base
.irqs
)
1268 goto res_create_fail
;
1271 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
1272 pool
->base
.timing_generators
[i
] =
1273 dce112_timing_generator_create(
1276 &dce112_tg_offsets
[i
]);
1277 if (pool
->base
.timing_generators
[i
] == NULL
) {
1278 BREAK_TO_DEBUGGER();
1279 dm_error("DC: failed to create tg!\n");
1280 goto res_create_fail
;
1283 pool
->base
.mis
[i
] = dce112_mem_input_create(ctx
, i
);
1284 if (pool
->base
.mis
[i
] == NULL
) {
1285 BREAK_TO_DEBUGGER();
1287 "DC: failed to create memory input!\n");
1288 goto res_create_fail
;
1291 pool
->base
.ipps
[i
] = dce112_ipp_create(ctx
, i
);
1292 if (pool
->base
.ipps
[i
] == NULL
) {
1293 BREAK_TO_DEBUGGER();
1295 "DC:failed to create input pixel processor!\n");
1296 goto res_create_fail
;
1299 pool
->base
.transforms
[i
] = dce112_transform_create(ctx
, i
);
1300 if (pool
->base
.transforms
[i
] == NULL
) {
1301 BREAK_TO_DEBUGGER();
1303 "DC: failed to create transform!\n");
1304 goto res_create_fail
;
1307 pool
->base
.opps
[i
] = dce112_opp_create(
1310 if (pool
->base
.opps
[i
] == NULL
) {
1311 BREAK_TO_DEBUGGER();
1313 "DC:failed to create output pixel processor!\n");
1314 goto res_create_fail
;
1318 if (!resource_construct(num_virtual_links
, dc
, &pool
->base
,
1320 goto res_create_fail
;
1322 dc
->public.caps
.max_planes
= pool
->base
.pipe_count
;
1324 /* Create hardware sequencer */
1325 if (!dce112_hw_sequencer_construct(dc
))
1326 goto res_create_fail
;
1328 bw_calcs_init(&dc
->bw_dceip
, &dc
->bw_vbios
, dc
->ctx
->asic_id
);
1330 bw_calcs_data_update_from_pplib(dc
);
1339 struct resource_pool
*dce112_create_resource_pool(
1340 uint8_t num_virtual_links
,
1343 struct dce110_resource_pool
*pool
=
1344 dm_alloc(sizeof(struct dce110_resource_pool
));
1349 if (construct(num_virtual_links
, dc
, pool
))
1352 BREAK_TO_DEBUGGER();