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drm/amd/display: restyle display clock calls part 1
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dce112 / dce112_resource.c
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "dce112/dce112_mem_input.h"
36
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce112/dce112_opp.h"
43 #include "dce110/dce110_ipp.h"
44 #include "dce/dce_clock_source.h"
45
46 #include "dce/dce_hwseq.h"
47 #include "dce112/dce112_hw_sequencer.h"
48
49 #include "reg_helper.h"
50
51 #include "dce/dce_11_2_d.h"
52 #include "dce/dce_11_2_sh_mask.h"
53
54 #ifndef mmDP_DPHY_INTERNAL_CTRL
55 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
56 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
57 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
58 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
59 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
60 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
61 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
62 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
63 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
64 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
65 #endif
66
67 #ifndef mmBIOS_SCRATCH_2
68 #define mmBIOS_SCRATCH_2 0x05CB
69 #define mmBIOS_SCRATCH_6 0x05CF
70 #endif
71
72 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
73 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
74 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
75 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
76 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
77 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
78 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
79 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
80 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
81 #endif
82
83 #ifndef mmDP_DPHY_FAST_TRAINING
84 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
85 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
86 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
87 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
88 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
89 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
90 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
91 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
92 #endif
93
94 enum dce112_clk_src_array_id {
95 DCE112_CLK_SRC_PLL0,
96 DCE112_CLK_SRC_PLL1,
97 DCE112_CLK_SRC_PLL2,
98 DCE112_CLK_SRC_PLL3,
99 DCE112_CLK_SRC_PLL4,
100 DCE112_CLK_SRC_PLL5,
101
102 DCE112_CLK_SRC_TOTAL
103 };
104
105 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
106 {
107 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
108 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
109 },
110 {
111 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
112 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
113 },
114 {
115 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
117 },
118 {
119 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
129 }
130 };
131
132 static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = {
133 {
134 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
135 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
136 - mmDPG_WATERMARK_MASK_CONTROL),
137 .pipe = (mmPIPE0_DMIF_BUFFER_CONTROL
138 - mmPIPE0_DMIF_BUFFER_CONTROL),
139 },
140 {
141 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
142 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
143 - mmDPG_WATERMARK_MASK_CONTROL),
144 .pipe = (mmPIPE1_DMIF_BUFFER_CONTROL
145 - mmPIPE0_DMIF_BUFFER_CONTROL),
146 },
147 {
148 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
149 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
150 - mmDPG_WATERMARK_MASK_CONTROL),
151 .pipe = (mmPIPE2_DMIF_BUFFER_CONTROL
152 - mmPIPE0_DMIF_BUFFER_CONTROL),
153 },
154 {
155 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
156 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
157 - mmDPG_WATERMARK_MASK_CONTROL),
158 .pipe = (mmPIPE3_DMIF_BUFFER_CONTROL
159 - mmPIPE0_DMIF_BUFFER_CONTROL),
160 },
161 {
162 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
163 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
164 - mmDPG_WATERMARK_MASK_CONTROL),
165 .pipe = (mmPIPE4_DMIF_BUFFER_CONTROL
166 - mmPIPE0_DMIF_BUFFER_CONTROL),
167 },
168 {
169 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
170 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
171 - mmDPG_WATERMARK_MASK_CONTROL),
172 .pipe = (mmPIPE5_DMIF_BUFFER_CONTROL
173 - mmPIPE0_DMIF_BUFFER_CONTROL),
174 }
175 };
176
177 static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
178 {
179 .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
180 },
181 {
182 .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
183 },
184 {
185 .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
186 },
187 {
188 .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
189 },
190 {
191 .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
192 },
193 {
194 .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
195 }
196 };
197
198
199 /* set register offset */
200 #define SR(reg_name)\
201 .reg_name = mm ## reg_name
202
203 /* set register offset with instance */
204 #define SRI(reg_name, block, id)\
205 .reg_name = mm ## block ## id ## _ ## reg_name
206
207 #define transform_regs(id)\
208 [id] = {\
209 XFM_COMMON_REG_LIST_DCE110(id)\
210 }
211
212 static const struct dce_transform_registers xfm_regs[] = {
213 transform_regs(0),
214 transform_regs(1),
215 transform_regs(2),
216 transform_regs(3),
217 transform_regs(4),
218 transform_regs(5)
219 };
220
221 static const struct dce_transform_shift xfm_shift = {
222 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
223 };
224
225 static const struct dce_transform_mask xfm_mask = {
226 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
227 };
228
229 #define aux_regs(id)\
230 [id] = {\
231 AUX_REG_LIST(id)\
232 }
233
234 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
235 aux_regs(0),
236 aux_regs(1),
237 aux_regs(2),
238 aux_regs(3),
239 aux_regs(4),
240 aux_regs(5)
241 };
242
243 #define hpd_regs(id)\
244 [id] = {\
245 HPD_REG_LIST(id)\
246 }
247
248 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
249 hpd_regs(0),
250 hpd_regs(1),
251 hpd_regs(2),
252 hpd_regs(3),
253 hpd_regs(4),
254 hpd_regs(5)
255 };
256
257 #define link_regs(id)\
258 [id] = {\
259 LE_DCE110_REG_LIST(id)\
260 }
261
262 static const struct dce110_link_enc_registers link_enc_regs[] = {
263 link_regs(0),
264 link_regs(1),
265 link_regs(2),
266 link_regs(3),
267 link_regs(4),
268 link_regs(5),
269 link_regs(6),
270 };
271
272 #define stream_enc_regs(id)\
273 [id] = {\
274 SE_COMMON_REG_LIST(id),\
275 .TMDS_CNTL = 0,\
276 }
277
278 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
279 stream_enc_regs(0),
280 stream_enc_regs(1),
281 stream_enc_regs(2),
282 stream_enc_regs(3),
283 stream_enc_regs(4),
284 stream_enc_regs(5)
285 };
286
287 static const struct dce_stream_encoder_shift se_shift = {
288 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
289 };
290
291 static const struct dce_stream_encoder_mask se_mask = {
292 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
293 };
294
295 #define audio_regs(id)\
296 [id] = {\
297 AUD_COMMON_REG_LIST(id)\
298 }
299
300 static const struct dce_audio_registers audio_regs[] = {
301 audio_regs(0),
302 audio_regs(1),
303 audio_regs(2),
304 audio_regs(3),
305 audio_regs(4),
306 audio_regs(5)
307 };
308
309 static const struct dce_audio_shift audio_shift = {
310 AUD_COMMON_MASK_SH_LIST(__SHIFT)
311 };
312
313 static const struct dce_aduio_mask audio_mask = {
314 AUD_COMMON_MASK_SH_LIST(_MASK)
315 };
316
317
318 static const struct dce110_opp_reg_offsets dce112_opp_reg_offsets[] = {
319 {
320 .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
321 .fmt_mem_offset = (mmFMT_MEMORY0_CONTROL - mmFMT_MEMORY0_CONTROL),
322 .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
323 .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
324 },
325 { .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
326 .fmt_mem_offset = (mmFMT_MEMORY1_CONTROL - mmFMT_MEMORY0_CONTROL),
327 .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
328 .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
329 },
330 { .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
331 .fmt_mem_offset = (mmFMT_MEMORY2_CONTROL - mmFMT_MEMORY0_CONTROL),
332 .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
333 .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
334 },
335 {
336 .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
337 .fmt_mem_offset = (mmFMT_MEMORY3_CONTROL - mmFMT_MEMORY0_CONTROL),
338 .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
339 .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
340 },
341 { .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
342 .fmt_mem_offset = (mmFMT_MEMORY4_CONTROL - mmFMT_MEMORY0_CONTROL),
343 .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
344 .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
345 },
346 { .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
347 .fmt_mem_offset = (mmFMT_MEMORY5_CONTROL - mmFMT_MEMORY0_CONTROL),
348 .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
349 .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
350 }
351 };
352
353 #define clk_src_regs(index, id)\
354 [index] = {\
355 CS_COMMON_REG_LIST_DCE_112(id),\
356 }
357
358 static const struct dce110_clk_src_regs clk_src_regs[] = {
359 clk_src_regs(0, A),
360 clk_src_regs(1, B),
361 clk_src_regs(2, C),
362 clk_src_regs(3, D),
363 clk_src_regs(4, E),
364 clk_src_regs(5, F)
365 };
366
367 static const struct dce110_clk_src_shift cs_shift = {
368 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
369 };
370
371 static const struct dce110_clk_src_mask cs_mask = {
372 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
373 };
374
375 static const struct bios_registers bios_regs = {
376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 };
378
379 static const struct resource_caps polaris_10_resource_cap = {
380 .num_timing_generator = 6,
381 .num_audio = 6,
382 .num_stream_encoder = 6,
383 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
384 };
385
386 static const struct resource_caps polaris_11_resource_cap = {
387 .num_timing_generator = 5,
388 .num_audio = 5,
389 .num_stream_encoder = 5,
390 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
391 };
392
393 #define CTX ctx
394 #define REG(reg) mm ## reg
395
396 #ifndef mmCC_DC_HDMI_STRAPS
397 #define mmCC_DC_HDMI_STRAPS 0x4819
398 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
399 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
400 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
401 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
402 #endif
403
404 static void read_dce_straps(
405 struct dc_context *ctx,
406 struct resource_straps *straps)
407 {
408 REG_GET_2(CC_DC_HDMI_STRAPS,
409 HDMI_DISABLE, &straps->hdmi_disable,
410 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
411
412 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
413 }
414
415 static struct audio *create_audio(
416 struct dc_context *ctx, unsigned int inst)
417 {
418 return dce_audio_create(ctx, inst,
419 &audio_regs[inst], &audio_shift, &audio_mask);
420 }
421
422
423 static struct timing_generator *dce112_timing_generator_create(
424 struct dc_context *ctx,
425 uint32_t instance,
426 const struct dce110_timing_generator_offsets *offsets)
427 {
428 struct dce110_timing_generator *tg110 =
429 dm_alloc(sizeof(struct dce110_timing_generator));
430
431 if (!tg110)
432 return NULL;
433
434 if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
435 return &tg110->base;
436
437 BREAK_TO_DEBUGGER();
438 dm_free(tg110);
439 return NULL;
440 }
441
442 static struct stream_encoder *dce112_stream_encoder_create(
443 enum engine_id eng_id,
444 struct dc_context *ctx)
445 {
446 struct dce110_stream_encoder *enc110 =
447 dm_alloc(sizeof(struct dce110_stream_encoder));
448
449 if (!enc110)
450 return NULL;
451
452 if (dce110_stream_encoder_construct(
453 enc110, ctx, ctx->dc_bios, eng_id,
454 &stream_enc_regs[eng_id], &se_shift, &se_mask))
455 return &enc110->base;
456
457 BREAK_TO_DEBUGGER();
458 dm_free(enc110);
459 return NULL;
460 }
461
462 #define SRII(reg_name, block, id)\
463 .reg_name[id] = mm ## block ## id ## _ ## reg_name
464
465 static const struct dce_hwseq_registers hwseq_reg = {
466 HWSEQ_DCE112_REG_LIST()
467 };
468
469 static const struct dce_hwseq_shift hwseq_shift = {
470 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
471 };
472
473 static const struct dce_hwseq_mask hwseq_mask = {
474 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
475 };
476
477 static struct dce_hwseq *dce112_hwseq_create(
478 struct dc_context *ctx)
479 {
480 struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
481
482 if (hws) {
483 hws->ctx = ctx;
484 hws->regs = &hwseq_reg;
485 hws->shifts = &hwseq_shift;
486 hws->masks = &hwseq_mask;
487 }
488 return hws;
489 }
490
491 static const struct resource_create_funcs res_create_funcs = {
492 .read_dce_straps = read_dce_straps,
493 .create_audio = create_audio,
494 .create_stream_encoder = dce112_stream_encoder_create,
495 .create_hwseq = dce112_hwseq_create,
496 };
497
498 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
499 static const struct dce_mem_input_registers mi_regs[] = {
500 mi_inst_regs(0),
501 mi_inst_regs(1),
502 mi_inst_regs(2),
503 mi_inst_regs(3),
504 mi_inst_regs(4),
505 mi_inst_regs(5),
506 };
507
508 static const struct dce_mem_input_shift mi_shifts = {
509 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
510 };
511
512 static const struct dce_mem_input_mask mi_masks = {
513 MI_DCE11_2_MASK_SH_LIST(_MASK)
514 };
515
516 static struct mem_input *dce112_mem_input_create(
517 struct dc_context *ctx,
518 uint32_t inst,
519 const struct dce110_mem_input_reg_offsets *offset)
520 {
521 struct dce110_mem_input *mem_input110 =
522 dm_alloc(sizeof(struct dce110_mem_input));
523
524 if (!mem_input110)
525 return NULL;
526
527 if (dce112_mem_input_construct(mem_input110, ctx, inst, offset)) {
528 struct mem_input *mi = &mem_input110->base;
529
530 mi->regs = &mi_regs[inst];
531 mi->shifts = &mi_shifts;
532 mi->masks = &mi_masks;
533 return mi;
534 }
535
536 BREAK_TO_DEBUGGER();
537 dm_free(mem_input110);
538 return NULL;
539 }
540
541 static void dce112_transform_destroy(struct transform **xfm)
542 {
543 dm_free(TO_DCE_TRANSFORM(*xfm));
544 *xfm = NULL;
545 }
546
547 static struct transform *dce112_transform_create(
548 struct dc_context *ctx,
549 uint32_t inst)
550 {
551 struct dce_transform *transform =
552 dm_alloc(sizeof(struct dce_transform));
553
554 if (!transform)
555 return NULL;
556
557 if (dce_transform_construct(transform, ctx, inst,
558 &xfm_regs[inst], &xfm_shift, &xfm_mask)) {
559 transform->lb_memory_size = 0x1404; /*5124*/
560 return &transform->base;
561 }
562
563 BREAK_TO_DEBUGGER();
564 dm_free(transform);
565 return NULL;
566 }
567 struct link_encoder *dce112_link_encoder_create(
568 const struct encoder_init_data *enc_init_data)
569 {
570 struct dce110_link_encoder *enc110 =
571 dm_alloc(sizeof(struct dce110_link_encoder));
572
573 if (!enc110)
574 return NULL;
575
576 if (dce110_link_encoder_construct(
577 enc110,
578 enc_init_data,
579 &link_enc_regs[enc_init_data->transmitter],
580 &link_enc_aux_regs[enc_init_data->channel - 1],
581 &link_enc_hpd_regs[enc_init_data->hpd_source])) {
582
583 enc110->base.features.ycbcr420_supported = false;
584 enc110->base.features.max_hdmi_pixel_clock = 600000;
585 return &enc110->base;
586 }
587
588 BREAK_TO_DEBUGGER();
589 dm_free(enc110);
590 return NULL;
591 }
592
593 struct input_pixel_processor *dce112_ipp_create(
594 struct dc_context *ctx,
595 uint32_t inst,
596 const struct dce110_ipp_reg_offsets *offset)
597 {
598 struct dce110_ipp *ipp =
599 dm_alloc(sizeof(struct dce110_ipp));
600
601 if (!ipp)
602 return NULL;
603
604 if (dce110_ipp_construct(ipp, ctx, inst, offset))
605 return &ipp->base;
606
607 BREAK_TO_DEBUGGER();
608 dm_free(ipp);
609 return NULL;
610 }
611
612 void dce112_ipp_destroy(struct input_pixel_processor **ipp)
613 {
614 dm_free(TO_DCE110_IPP(*ipp));
615 *ipp = NULL;
616 }
617
618 struct output_pixel_processor *dce112_opp_create(
619 struct dc_context *ctx,
620 uint32_t inst,
621 const struct dce110_opp_reg_offsets *offset)
622 {
623 struct dce110_opp *opp =
624 dm_alloc(sizeof(struct dce110_opp));
625
626 if (!opp)
627 return NULL;
628
629 if (dce112_opp_construct(opp,
630 ctx, inst, offset))
631 return &opp->base;
632
633 BREAK_TO_DEBUGGER();
634 dm_free(opp);
635 return NULL;
636 }
637
638 void dce112_opp_destroy(struct output_pixel_processor **opp)
639 {
640 struct dce110_opp *dce110_opp;
641
642 if (!opp || !*opp)
643 return;
644
645 dce110_opp = FROM_DCE11_OPP(*opp);
646
647 dm_free(dce110_opp->regamma.coeff128_dx);
648 dm_free(dce110_opp->regamma.coeff128_oem);
649 dm_free(dce110_opp->regamma.coeff128);
650 dm_free(dce110_opp->regamma.axis_x_1025);
651 dm_free(dce110_opp->regamma.axis_x_256);
652 dm_free(dce110_opp->regamma.coordinates_x);
653 dm_free(dce110_opp->regamma.rgb_regamma);
654 dm_free(dce110_opp->regamma.rgb_resulted);
655 dm_free(dce110_opp->regamma.rgb_oem);
656 dm_free(dce110_opp->regamma.rgb_user);
657
658 dm_free(dce110_opp);
659 *opp = NULL;
660 }
661
662 struct clock_source *dce112_clock_source_create(
663 struct dc_context *ctx,
664 struct dc_bios *bios,
665 enum clock_source_id id,
666 const struct dce110_clk_src_regs *regs,
667 bool dp_clk_src)
668 {
669 struct dce110_clk_src *clk_src =
670 dm_alloc(sizeof(struct dce110_clk_src));
671
672 if (!clk_src)
673 return NULL;
674
675 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
676 regs, &cs_shift, &cs_mask)) {
677 clk_src->base.dp_clk_src = dp_clk_src;
678 return &clk_src->base;
679 }
680
681 BREAK_TO_DEBUGGER();
682 return NULL;
683 }
684
685 void dce112_clock_source_destroy(struct clock_source **clk_src)
686 {
687 dm_free(TO_DCE110_CLK_SRC(*clk_src));
688 *clk_src = NULL;
689 }
690
691 static void destruct(struct dce110_resource_pool *pool)
692 {
693 unsigned int i;
694
695 for (i = 0; i < pool->base.pipe_count; i++) {
696 if (pool->base.opps[i] != NULL)
697 dce112_opp_destroy(&pool->base.opps[i]);
698
699 if (pool->base.transforms[i] != NULL)
700 dce112_transform_destroy(&pool->base.transforms[i]);
701
702 if (pool->base.ipps[i] != NULL)
703 dce112_ipp_destroy(&pool->base.ipps[i]);
704
705 if (pool->base.mis[i] != NULL) {
706 dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
707 pool->base.mis[i] = NULL;
708 }
709
710 if (pool->base.timing_generators[i] != NULL) {
711 dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
712 pool->base.timing_generators[i] = NULL;
713 }
714 }
715
716 for (i = 0; i < pool->base.stream_enc_count; i++) {
717 if (pool->base.stream_enc[i] != NULL)
718 dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
719 }
720
721 for (i = 0; i < pool->base.clk_src_count; i++) {
722 if (pool->base.clock_sources[i] != NULL) {
723 dce112_clock_source_destroy(&pool->base.clock_sources[i]);
724 }
725 }
726
727 if (pool->base.dp_clock_source != NULL)
728 dce112_clock_source_destroy(&pool->base.dp_clock_source);
729
730 for (i = 0; i < pool->base.audio_count; i++) {
731 if (pool->base.audios[i] != NULL) {
732 dce_aud_destroy(&pool->base.audios[i]);
733 }
734 }
735
736 if (pool->base.display_clock != NULL) {
737 dal_display_clock_destroy(&pool->base.display_clock);
738 }
739
740 if (pool->base.irqs != NULL) {
741 dal_irq_service_destroy(&pool->base.irqs);
742 }
743 }
744
745 static struct clock_source *find_matching_pll(struct resource_context *res_ctx,
746 const struct core_stream *const stream)
747 {
748 switch (stream->sink->link->link_enc->transmitter) {
749 case TRANSMITTER_UNIPHY_A:
750 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL0];
751 case TRANSMITTER_UNIPHY_B:
752 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL1];
753 case TRANSMITTER_UNIPHY_C:
754 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL2];
755 case TRANSMITTER_UNIPHY_D:
756 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL3];
757 case TRANSMITTER_UNIPHY_E:
758 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL4];
759 case TRANSMITTER_UNIPHY_F:
760 return res_ctx->pool->clock_sources[DCE112_CLK_SRC_PLL5];
761 default:
762 return NULL;
763 };
764
765 return 0;
766 }
767
768 static enum dc_status validate_mapped_resource(
769 const struct core_dc *dc,
770 struct validate_context *context)
771 {
772 enum dc_status status = DC_OK;
773 uint8_t i, j, k;
774
775 for (i = 0; i < context->target_count; i++) {
776 struct core_target *target = context->targets[i];
777
778 for (j = 0; j < target->public.stream_count; j++) {
779 struct core_stream *stream =
780 DC_STREAM_TO_CORE(target->public.streams[j]);
781 struct core_link *link = stream->sink->link;
782
783 if (resource_is_stream_unchanged(dc->current_context, stream))
784 continue;
785
786 for (k = 0; k < MAX_PIPES; k++) {
787 struct pipe_ctx *pipe_ctx =
788 &context->res_ctx.pipe_ctx[k];
789
790 if (context->res_ctx.pipe_ctx[k].stream != stream)
791 continue;
792
793 if (!pipe_ctx->tg->funcs->validate_timing(
794 pipe_ctx->tg, &stream->public.timing))
795 return DC_FAIL_CONTROLLER_VALIDATE;
796
797 status = dce110_resource_build_pipe_hw_param(pipe_ctx);
798
799 if (status != DC_OK)
800 return status;
801
802 if (!link->link_enc->funcs->validate_output_with_stream(
803 link->link_enc,
804 pipe_ctx))
805 return DC_FAIL_ENC_VALIDATE;
806
807 /* TODO: validate audio ASIC caps, encoder */
808
809 status = dc_link_validate_mode_timing(stream,
810 link,
811 &stream->public.timing);
812
813 if (status != DC_OK)
814 return status;
815
816 resource_build_info_frame(pipe_ctx);
817
818 /* do not need to validate non root pipes */
819 break;
820 }
821 }
822 }
823
824 return DC_OK;
825 }
826
827 enum dc_status dce112_validate_bandwidth(
828 const struct core_dc *dc,
829 struct validate_context *context)
830 {
831 enum dc_status result = DC_ERROR_UNEXPECTED;
832
833 dm_logger_write(
834 dc->ctx->logger, LOG_BANDWIDTH_CALCS,
835 "%s: start",
836 __func__);
837
838 if (!bw_calcs(
839 dc->ctx,
840 &dc->bw_dceip,
841 &dc->bw_vbios,
842 context->res_ctx.pipe_ctx,
843 context->res_ctx.pool->pipe_count,
844 &context->bw_results))
845 result = DC_FAIL_BANDWIDTH_VALIDATE;
846 else
847 result = DC_OK;
848
849 if (result == DC_FAIL_BANDWIDTH_VALIDATE)
850 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
851 "%s: Bandwidth validation failed!",
852 __func__);
853
854 if (memcmp(&dc->current_context->bw_results,
855 &context->bw_results, sizeof(context->bw_results))) {
856 struct log_entry log_entry;
857 dm_logger_open(
858 dc->ctx->logger,
859 &log_entry,
860 LOG_BANDWIDTH_CALCS);
861 dm_logger_append(&log_entry, "%s: finish,\n"
862 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
863 "stutMark_b: %d stutMark_a: %d\n",
864 __func__,
865 context->bw_results.nbp_state_change_wm_ns[0].b_mark,
866 context->bw_results.nbp_state_change_wm_ns[0].a_mark,
867 context->bw_results.urgent_wm_ns[0].b_mark,
868 context->bw_results.urgent_wm_ns[0].a_mark,
869 context->bw_results.stutter_exit_wm_ns[0].b_mark,
870 context->bw_results.stutter_exit_wm_ns[0].a_mark);
871 dm_logger_append(&log_entry,
872 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
873 "stutMark_b: %d stutMark_a: %d\n",
874 context->bw_results.nbp_state_change_wm_ns[1].b_mark,
875 context->bw_results.nbp_state_change_wm_ns[1].a_mark,
876 context->bw_results.urgent_wm_ns[1].b_mark,
877 context->bw_results.urgent_wm_ns[1].a_mark,
878 context->bw_results.stutter_exit_wm_ns[1].b_mark,
879 context->bw_results.stutter_exit_wm_ns[1].a_mark);
880 dm_logger_append(&log_entry,
881 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
882 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
883 context->bw_results.nbp_state_change_wm_ns[2].b_mark,
884 context->bw_results.nbp_state_change_wm_ns[2].a_mark,
885 context->bw_results.urgent_wm_ns[2].b_mark,
886 context->bw_results.urgent_wm_ns[2].a_mark,
887 context->bw_results.stutter_exit_wm_ns[2].b_mark,
888 context->bw_results.stutter_exit_wm_ns[2].a_mark,
889 context->bw_results.stutter_mode_enable);
890 dm_logger_append(&log_entry,
891 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
892 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
893 context->bw_results.cpuc_state_change_enable,
894 context->bw_results.cpup_state_change_enable,
895 context->bw_results.nbp_state_change_enable,
896 context->bw_results.all_displays_in_sync,
897 context->bw_results.dispclk_khz,
898 context->bw_results.required_sclk,
899 context->bw_results.required_sclk_deep_sleep,
900 context->bw_results.required_yclk,
901 context->bw_results.blackout_recovery_time_us);
902 dm_logger_close(&log_entry);
903 }
904 return result;
905 }
906
907 enum dc_status resource_map_phy_clock_resources(
908 const struct core_dc *dc,
909 struct validate_context *context)
910 {
911 uint8_t i, j, k;
912
913 /* acquire new resources */
914 for (i = 0; i < context->target_count; i++) {
915 struct core_target *target = context->targets[i];
916
917 for (j = 0; j < target->public.stream_count; j++) {
918 struct core_stream *stream =
919 DC_STREAM_TO_CORE(target->public.streams[j]);
920
921 if (resource_is_stream_unchanged(dc->current_context, stream))
922 continue;
923
924 for (k = 0; k < MAX_PIPES; k++) {
925 struct pipe_ctx *pipe_ctx =
926 &context->res_ctx.pipe_ctx[k];
927
928 if (context->res_ctx.pipe_ctx[k].stream != stream)
929 continue;
930
931 if (dc_is_dp_signal(pipe_ctx->stream->signal)
932 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
933 pipe_ctx->clock_source =
934 context->res_ctx.pool->dp_clock_source;
935 else
936 pipe_ctx->clock_source =
937 find_matching_pll(&context->res_ctx,
938 stream);
939
940 if (pipe_ctx->clock_source == NULL)
941 return DC_NO_CLOCK_SOURCE_RESOURCE;
942
943 resource_reference_clock_source(
944 &context->res_ctx,
945 pipe_ctx->clock_source);
946
947 /* only one cs per stream regardless of mpo */
948 break;
949 }
950 }
951 }
952
953 return DC_OK;
954 }
955
956 static bool dce112_validate_surface_sets(
957 const struct dc_validation_set set[],
958 int set_count)
959 {
960 int i;
961
962 for (i = 0; i < set_count; i++) {
963 if (set[i].surface_count == 0)
964 continue;
965
966 if (set[i].surface_count > 1)
967 return false;
968
969 if (set[i].surfaces[0]->clip_rect.width
970 != set[i].target->streams[0]->src.width
971 || set[i].surfaces[0]->clip_rect.height
972 != set[i].target->streams[0]->src.height)
973 return false;
974 if (set[i].surfaces[0]->format
975 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
976 return false;
977 }
978
979 return true;
980 }
981
982 enum dc_status dce112_validate_with_context(
983 const struct core_dc *dc,
984 const struct dc_validation_set set[],
985 int set_count,
986 struct validate_context *context)
987 {
988 struct dc_context *dc_ctx = dc->ctx;
989 enum dc_status result = DC_ERROR_UNEXPECTED;
990 int i;
991
992 if (!dce112_validate_surface_sets(set, set_count))
993 return DC_FAIL_SURFACE_VALIDATE;
994
995 context->res_ctx.pool = dc->res_pool;
996
997 for (i = 0; i < set_count; i++) {
998 context->targets[i] = DC_TARGET_TO_CORE(set[i].target);
999 dc_target_retain(&context->targets[i]->public);
1000 context->target_count++;
1001 }
1002
1003 result = resource_map_pool_resources(dc, context);
1004
1005 if (result == DC_OK)
1006 result = resource_map_phy_clock_resources(dc, context);
1007
1008 if (!resource_validate_attach_surfaces(
1009 set, set_count, dc->current_context, context)) {
1010 DC_ERROR("Failed to attach surface to target!\n");
1011 return DC_FAIL_ATTACH_SURFACES;
1012 }
1013
1014 if (result == DC_OK)
1015 result = validate_mapped_resource(dc, context);
1016
1017 if (result == DC_OK)
1018 result = resource_build_scaling_params_for_context(dc, context);
1019
1020 if (result == DC_OK)
1021 result = dce112_validate_bandwidth(dc, context);
1022
1023 return result;
1024 }
1025
1026 enum dc_status dce112_validate_guaranteed(
1027 const struct core_dc *dc,
1028 const struct dc_target *dc_target,
1029 struct validate_context *context)
1030 {
1031 enum dc_status result = DC_ERROR_UNEXPECTED;
1032
1033 context->res_ctx.pool = dc->res_pool;
1034
1035 context->targets[0] = DC_TARGET_TO_CORE(dc_target);
1036 dc_target_retain(&context->targets[0]->public);
1037 context->target_count++;
1038
1039 result = resource_map_pool_resources(dc, context);
1040
1041 if (result == DC_OK)
1042 result = resource_map_phy_clock_resources(dc, context);
1043
1044 if (result == DC_OK)
1045 result = validate_mapped_resource(dc, context);
1046
1047 if (result == DC_OK) {
1048 validate_guaranteed_copy_target(
1049 context, dc->public.caps.max_targets);
1050 result = resource_build_scaling_params_for_context(dc, context);
1051 }
1052
1053 if (result == DC_OK)
1054 result = dce112_validate_bandwidth(dc, context);
1055
1056 return result;
1057 }
1058
1059 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1060 {
1061 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1062
1063 destruct(dce110_pool);
1064 dm_free(dce110_pool);
1065 *pool = NULL;
1066 }
1067
1068 static const struct resource_funcs dce112_res_pool_funcs = {
1069 .destroy = dce112_destroy_resource_pool,
1070 .link_enc_create = dce112_link_encoder_create,
1071 .validate_with_context = dce112_validate_with_context,
1072 .validate_guaranteed = dce112_validate_guaranteed,
1073 .validate_bandwidth = dce112_validate_bandwidth
1074 };
1075
1076 static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
1077 {
1078 struct dm_pp_clock_levels_with_latency eng_clks = {0};
1079 struct dm_pp_clock_levels_with_latency mem_clks = {0};
1080 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1081 struct dm_pp_clock_levels clks = {0};
1082
1083 /*do system clock TODO PPLIB: after PPLIB implement,
1084 * then remove old way
1085 */
1086 if (!dm_pp_get_clock_levels_by_type_with_latency(
1087 dc->ctx,
1088 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1089 &eng_clks)) {
1090
1091 /* This is only for temporary */
1092 dm_pp_get_clock_levels_by_type(
1093 dc->ctx,
1094 DM_PP_CLOCK_TYPE_ENGINE_CLK,
1095 &clks);
1096 /* convert all the clock fro kHz to fix point mHz */
1097 dc->bw_vbios.high_sclk = bw_frc_to_fixed(
1098 clks.clocks_in_khz[clks.num_levels-1], 1000);
1099 dc->bw_vbios.mid1_sclk = bw_frc_to_fixed(
1100 clks.clocks_in_khz[clks.num_levels/8], 1000);
1101 dc->bw_vbios.mid2_sclk = bw_frc_to_fixed(
1102 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1103 dc->bw_vbios.mid3_sclk = bw_frc_to_fixed(
1104 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1105 dc->bw_vbios.mid4_sclk = bw_frc_to_fixed(
1106 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1107 dc->bw_vbios.mid5_sclk = bw_frc_to_fixed(
1108 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1109 dc->bw_vbios.mid6_sclk = bw_frc_to_fixed(
1110 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1111 dc->bw_vbios.low_sclk = bw_frc_to_fixed(
1112 clks.clocks_in_khz[0], 1000);
1113
1114 /*do memory clock*/
1115 dm_pp_get_clock_levels_by_type(
1116 dc->ctx,
1117 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1118 &clks);
1119
1120 dc->bw_vbios.low_yclk = bw_frc_to_fixed(
1121 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1122 dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
1123 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1124 1000);
1125 dc->bw_vbios.high_yclk = bw_frc_to_fixed(
1126 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1127 1000);
1128
1129 return;
1130 }
1131
1132 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1133 dc->bw_vbios.high_sclk = bw_frc_to_fixed(
1134 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1135 dc->bw_vbios.mid1_sclk = bw_frc_to_fixed(
1136 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1137 dc->bw_vbios.mid2_sclk = bw_frc_to_fixed(
1138 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1139 dc->bw_vbios.mid3_sclk = bw_frc_to_fixed(
1140 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1141 dc->bw_vbios.mid4_sclk = bw_frc_to_fixed(
1142 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1143 dc->bw_vbios.mid5_sclk = bw_frc_to_fixed(
1144 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1145 dc->bw_vbios.mid6_sclk = bw_frc_to_fixed(
1146 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1147 dc->bw_vbios.low_sclk = bw_frc_to_fixed(
1148 eng_clks.data[0].clocks_in_khz, 1000);
1149
1150 /*do memory clock*/
1151 dm_pp_get_clock_levels_by_type_with_latency(
1152 dc->ctx,
1153 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1154 &mem_clks);
1155
1156 /* we don't need to call PPLIB for validation clock since they
1157 * also give us the highest sclk and highest mclk (UMA clock).
1158 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1159 * YCLK = UMACLK*m_memoryTypeMultiplier
1160 */
1161 dc->bw_vbios.low_yclk = bw_frc_to_fixed(
1162 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
1163 dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
1164 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1165 1000);
1166 dc->bw_vbios.high_yclk = bw_frc_to_fixed(
1167 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1168 1000);
1169
1170 /* Now notify PPLib/SMU about which Watermarks sets they should select
1171 * depending on DPM state they are in. And update BW MGR GFX Engine and
1172 * Memory clock member variables for Watermarks calculations for each
1173 * Watermark Set
1174 */
1175 clk_ranges.num_wm_sets = 4;
1176 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1177 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1178 eng_clks.data[0].clocks_in_khz;
1179 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1180 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1181 clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
1182 mem_clks.data[0].clocks_in_khz;
1183 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1184 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1185
1186 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1187 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1188 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1189 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1190 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1191 clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
1192 mem_clks.data[0].clocks_in_khz;
1193 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1194 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1195
1196 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1197 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1198 eng_clks.data[0].clocks_in_khz;
1199 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1200 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1201 clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
1202 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1203 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1204 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1205
1206 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1207 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1208 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1209 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1210 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1211 clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
1212 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1213 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1214 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1215
1216 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1217 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1218 }
1219
1220 const struct resource_caps *dce112_resource_cap(
1221 struct hw_asic_id *asic_id)
1222 {
1223 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev))
1224 return &polaris_11_resource_cap;
1225 else
1226 return &polaris_10_resource_cap;
1227 }
1228
1229 static bool construct(
1230 uint8_t num_virtual_links,
1231 struct core_dc *dc,
1232 struct dce110_resource_pool *pool)
1233 {
1234 unsigned int i;
1235 struct dc_context *ctx = dc->ctx;
1236 struct dm_pp_static_clock_info static_clk_info = {0};
1237
1238 ctx->dc_bios->regs = &bios_regs;
1239
1240 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1241 pool->base.funcs = &dce112_res_pool_funcs;
1242
1243 /*************************************************
1244 * Resource + asic cap harcoding *
1245 *************************************************/
1246 pool->base.underlay_pipe_index = -1;
1247 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1248 dc->public.caps.max_downscale_ratio = 200;
1249 dc->public.caps.i2c_speed_in_khz = 100;
1250
1251 /*************************************************
1252 * Create resources *
1253 *************************************************/
1254
1255 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1256 dce112_clock_source_create(
1257 ctx, ctx->dc_bios,
1258 CLOCK_SOURCE_COMBO_PHY_PLL0,
1259 &clk_src_regs[0], false);
1260 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1261 dce112_clock_source_create(
1262 ctx, ctx->dc_bios,
1263 CLOCK_SOURCE_COMBO_PHY_PLL1,
1264 &clk_src_regs[1], false);
1265 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1266 dce112_clock_source_create(
1267 ctx, ctx->dc_bios,
1268 CLOCK_SOURCE_COMBO_PHY_PLL2,
1269 &clk_src_regs[2], false);
1270 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1271 dce112_clock_source_create(
1272 ctx, ctx->dc_bios,
1273 CLOCK_SOURCE_COMBO_PHY_PLL3,
1274 &clk_src_regs[3], false);
1275 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1276 dce112_clock_source_create(
1277 ctx, ctx->dc_bios,
1278 CLOCK_SOURCE_COMBO_PHY_PLL4,
1279 &clk_src_regs[4], false);
1280 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1281 dce112_clock_source_create(
1282 ctx, ctx->dc_bios,
1283 CLOCK_SOURCE_COMBO_PHY_PLL5,
1284 &clk_src_regs[5], false);
1285 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1286
1287 pool->base.dp_clock_source = dce112_clock_source_create(
1288 ctx, ctx->dc_bios,
1289 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1290
1291
1292 for (i = 0; i < pool->base.clk_src_count; i++) {
1293 if (pool->base.clock_sources[i] == NULL) {
1294 dm_error("DC: failed to create clock sources!\n");
1295 BREAK_TO_DEBUGGER();
1296 goto res_create_fail;
1297 }
1298 }
1299
1300 pool->base.display_clock = dal_display_clock_dce112_create(
1301 ctx);
1302
1303 if (pool->base.display_clock == NULL) {
1304 dm_error("DC: failed to create display clock!\n");
1305 BREAK_TO_DEBUGGER();
1306 goto res_create_fail;
1307 }
1308
1309
1310 /* get static clock information for PPLIB or firmware, save
1311 * max_clock_state
1312 */
1313 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
1314 enum clocks_state max_clocks_state =
1315 dce110_resource_convert_clock_state_pp_to_dc(
1316 static_clk_info.max_clocks_state);
1317
1318 pool->base.display_clock->funcs->store_max_clocks_state(
1319 pool->base.display_clock, max_clocks_state);
1320 }
1321
1322 {
1323 struct irq_service_init_data init_data;
1324 init_data.ctx = dc->ctx;
1325 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1326 if (!pool->base.irqs)
1327 goto res_create_fail;
1328 }
1329
1330 for (i = 0; i < pool->base.pipe_count; i++) {
1331 pool->base.timing_generators[i] =
1332 dce112_timing_generator_create(
1333 ctx,
1334 i,
1335 &dce112_tg_offsets[i]);
1336 if (pool->base.timing_generators[i] == NULL) {
1337 BREAK_TO_DEBUGGER();
1338 dm_error("DC: failed to create tg!\n");
1339 goto res_create_fail;
1340 }
1341
1342 pool->base.mis[i] = dce112_mem_input_create(
1343 ctx,
1344 i,
1345 &dce112_mi_reg_offsets[i]);
1346 if (pool->base.mis[i] == NULL) {
1347 BREAK_TO_DEBUGGER();
1348 dm_error(
1349 "DC: failed to create memory input!\n");
1350 goto res_create_fail;
1351 }
1352
1353 pool->base.ipps[i] = dce112_ipp_create(
1354 ctx,
1355 i,
1356 &ipp_reg_offsets[i]);
1357 if (pool->base.ipps[i] == NULL) {
1358 BREAK_TO_DEBUGGER();
1359 dm_error(
1360 "DC:failed to create input pixel processor!\n");
1361 goto res_create_fail;
1362 }
1363
1364 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1365 if (pool->base.transforms[i] == NULL) {
1366 BREAK_TO_DEBUGGER();
1367 dm_error(
1368 "DC: failed to create transform!\n");
1369 goto res_create_fail;
1370 }
1371
1372 pool->base.opps[i] = dce112_opp_create(
1373 ctx,
1374 i,
1375 &dce112_opp_reg_offsets[i]);
1376 if (pool->base.opps[i] == NULL) {
1377 BREAK_TO_DEBUGGER();
1378 dm_error(
1379 "DC:failed to create output pixel processor!\n");
1380 goto res_create_fail;
1381 }
1382 }
1383
1384 if (!resource_construct(num_virtual_links, dc, &pool->base,
1385 &res_create_funcs))
1386 goto res_create_fail;
1387
1388 /* Create hardware sequencer */
1389 if (!dce112_hw_sequencer_construct(dc))
1390 goto res_create_fail;
1391
1392 bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_POLARIS11);
1393
1394 bw_calcs_data_update_from_pplib(dc);
1395
1396 return true;
1397
1398 res_create_fail:
1399 destruct(pool);
1400 return false;
1401 }
1402
1403 struct resource_pool *dce112_create_resource_pool(
1404 uint8_t num_virtual_links,
1405 struct core_dc *dc)
1406 {
1407 struct dce110_resource_pool *pool =
1408 dm_alloc(sizeof(struct dce110_resource_pool));
1409
1410 if (!pool)
1411 return NULL;
1412
1413 if (construct(num_virtual_links, dc, pool))
1414 return &pool->base;
1415
1416 BREAK_TO_DEBUGGER();
1417 return NULL;
1418 }
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