2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "dce112/dce112_mem_input.h"
37 #include "irq/dce110/irq_service_dce110.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce110/dce110_ipp.h"
44 #include "dce/dce_clocks.h"
45 #include "dce/dce_clock_source.h"
47 #include "dce/dce_hwseq.h"
48 #include "dce112/dce112_hw_sequencer.h"
49 #include "dce/dce_abm.h"
50 #include "dce/dce_dmcu.h"
52 #include "reg_helper.h"
54 #include "dce/dce_11_2_d.h"
55 #include "dce/dce_11_2_sh_mask.h"
57 #ifndef mmDP_DPHY_INTERNAL_CTRL
58 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
59 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
60 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
61 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
62 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
63 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
64 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
65 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
66 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
67 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
70 #ifndef mmBIOS_SCRATCH_2
71 #define mmBIOS_SCRATCH_2 0x05CB
72 #define mmBIOS_SCRATCH_6 0x05CF
75 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
76 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
77 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
78 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
79 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
80 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
81 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
82 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
83 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
86 #ifndef mmDP_DPHY_FAST_TRAINING
87 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
88 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
89 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
90 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
91 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
92 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
93 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
94 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
97 enum dce112_clk_src_array_id
{
108 static const struct dce110_timing_generator_offsets dce112_tg_offsets
[] = {
110 .crtc
= (mmCRTC0_CRTC_CONTROL
- mmCRTC_CONTROL
),
111 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
114 .crtc
= (mmCRTC1_CRTC_CONTROL
- mmCRTC_CONTROL
),
115 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
118 .crtc
= (mmCRTC2_CRTC_CONTROL
- mmCRTC_CONTROL
),
119 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
122 .crtc
= (mmCRTC3_CRTC_CONTROL
- mmCRTC_CONTROL
),
123 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
126 .crtc
= (mmCRTC4_CRTC_CONTROL
- mmCRTC_CONTROL
),
127 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
130 .crtc
= (mmCRTC5_CRTC_CONTROL
- mmCRTC_CONTROL
),
131 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
135 static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets
[] = {
137 .dcp
= (mmDCP0_GRPH_CONTROL
- mmGRPH_CONTROL
),
138 .dmif
= (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
139 - mmDPG_WATERMARK_MASK_CONTROL
),
140 .pipe
= (mmPIPE0_DMIF_BUFFER_CONTROL
141 - mmPIPE0_DMIF_BUFFER_CONTROL
),
144 .dcp
= (mmDCP1_GRPH_CONTROL
- mmGRPH_CONTROL
),
145 .dmif
= (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
146 - mmDPG_WATERMARK_MASK_CONTROL
),
147 .pipe
= (mmPIPE1_DMIF_BUFFER_CONTROL
148 - mmPIPE0_DMIF_BUFFER_CONTROL
),
151 .dcp
= (mmDCP2_GRPH_CONTROL
- mmGRPH_CONTROL
),
152 .dmif
= (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
153 - mmDPG_WATERMARK_MASK_CONTROL
),
154 .pipe
= (mmPIPE2_DMIF_BUFFER_CONTROL
155 - mmPIPE0_DMIF_BUFFER_CONTROL
),
158 .dcp
= (mmDCP3_GRPH_CONTROL
- mmGRPH_CONTROL
),
159 .dmif
= (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
160 - mmDPG_WATERMARK_MASK_CONTROL
),
161 .pipe
= (mmPIPE3_DMIF_BUFFER_CONTROL
162 - mmPIPE0_DMIF_BUFFER_CONTROL
),
165 .dcp
= (mmDCP4_GRPH_CONTROL
- mmGRPH_CONTROL
),
166 .dmif
= (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
167 - mmDPG_WATERMARK_MASK_CONTROL
),
168 .pipe
= (mmPIPE4_DMIF_BUFFER_CONTROL
169 - mmPIPE0_DMIF_BUFFER_CONTROL
),
172 .dcp
= (mmDCP5_GRPH_CONTROL
- mmGRPH_CONTROL
),
173 .dmif
= (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
174 - mmDPG_WATERMARK_MASK_CONTROL
),
175 .pipe
= (mmPIPE5_DMIF_BUFFER_CONTROL
176 - mmPIPE0_DMIF_BUFFER_CONTROL
),
180 static const struct dce110_ipp_reg_offsets ipp_reg_offsets
[] = {
182 .dcp_offset
= (mmDCP0_CUR_CONTROL
- mmCUR_CONTROL
),
185 .dcp_offset
= (mmDCP1_CUR_CONTROL
- mmCUR_CONTROL
),
188 .dcp_offset
= (mmDCP2_CUR_CONTROL
- mmCUR_CONTROL
),
191 .dcp_offset
= (mmDCP3_CUR_CONTROL
- mmCUR_CONTROL
),
194 .dcp_offset
= (mmDCP4_CUR_CONTROL
- mmCUR_CONTROL
),
197 .dcp_offset
= (mmDCP5_CUR_CONTROL
- mmCUR_CONTROL
),
202 /* set register offset */
203 #define SR(reg_name)\
204 .reg_name = mm ## reg_name
206 /* set register offset with instance */
207 #define SRI(reg_name, block, id)\
208 .reg_name = mm ## block ## id ## _ ## reg_name
211 static const struct dce_disp_clk_registers disp_clk_regs
= {
212 CLK_COMMON_REG_LIST_DCE_BASE()
215 static const struct dce_disp_clk_shift disp_clk_shift
= {
216 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT
)
219 static const struct dce_disp_clk_mask disp_clk_mask
= {
220 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK
)
223 static const struct dce_dmcu_registers dmcu_regs
= {
224 DMCU_DCE110_COMMON_REG_LIST()
227 static const struct dce_dmcu_shift dmcu_shift
= {
228 DMCU_MASK_SH_LIST_DCE110(__SHIFT
)
231 static const struct dce_dmcu_mask dmcu_mask
= {
232 DMCU_MASK_SH_LIST_DCE110(_MASK
)
235 static const struct dce_abm_registers abm_regs
= {
236 ABM_DCE110_COMMON_REG_LIST()
239 static const struct dce_abm_shift abm_shift
= {
240 ABM_MASK_SH_LIST_DCE110(__SHIFT
)
243 static const struct dce_abm_mask abm_mask
= {
244 ABM_MASK_SH_LIST_DCE110(_MASK
)
247 #define transform_regs(id)\
249 XFM_COMMON_REG_LIST_DCE110(id)\
252 static const struct dce_transform_registers xfm_regs
[] = {
261 static const struct dce_transform_shift xfm_shift
= {
262 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT
)
265 static const struct dce_transform_mask xfm_mask
= {
266 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK
)
269 #define aux_regs(id)\
274 static const struct dce110_link_enc_aux_registers link_enc_aux_regs
[] = {
283 #define hpd_regs(id)\
288 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs
[] = {
297 #define link_regs(id)\
299 LE_DCE110_REG_LIST(id)\
302 static const struct dce110_link_enc_registers link_enc_regs
[] = {
312 #define stream_enc_regs(id)\
314 SE_COMMON_REG_LIST(id),\
318 static const struct dce110_stream_enc_registers stream_enc_regs
[] = {
327 static const struct dce_stream_encoder_shift se_shift
= {
328 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT
)
331 static const struct dce_stream_encoder_mask se_mask
= {
332 SE_COMMON_MASK_SH_LIST_DCE112(_MASK
)
335 #define opp_regs(id)\
337 OPP_DCE_112_REG_LIST(id),\
340 static const struct dce_opp_registers opp_regs
[] = {
349 static const struct dce_opp_shift opp_shift
= {
350 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT
)
353 static const struct dce_opp_mask opp_mask
= {
354 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK
)
357 #define audio_regs(id)\
359 AUD_COMMON_REG_LIST(id)\
362 static const struct dce_audio_registers audio_regs
[] = {
371 static const struct dce_audio_shift audio_shift
= {
372 AUD_COMMON_MASK_SH_LIST(__SHIFT
)
375 static const struct dce_aduio_mask audio_mask
= {
376 AUD_COMMON_MASK_SH_LIST(_MASK
)
379 #define clk_src_regs(index, id)\
381 CS_COMMON_REG_LIST_DCE_112(id),\
384 static const struct dce110_clk_src_regs clk_src_regs
[] = {
393 static const struct dce110_clk_src_shift cs_shift
= {
394 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT
)
397 static const struct dce110_clk_src_mask cs_mask
= {
398 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK
)
401 static const struct bios_registers bios_regs
= {
402 .BIOS_SCRATCH_6
= mmBIOS_SCRATCH_6
405 static const struct resource_caps polaris_10_resource_cap
= {
406 .num_timing_generator
= 6,
408 .num_stream_encoder
= 6,
409 .num_pll
= 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
412 static const struct resource_caps polaris_11_resource_cap
= {
413 .num_timing_generator
= 5,
415 .num_stream_encoder
= 5,
416 .num_pll
= 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
420 #define REG(reg) mm ## reg
422 #ifndef mmCC_DC_HDMI_STRAPS
423 #define mmCC_DC_HDMI_STRAPS 0x4819
424 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
425 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
426 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
427 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
430 static void read_dce_straps(
431 struct dc_context
*ctx
,
432 struct resource_straps
*straps
)
434 REG_GET_2(CC_DC_HDMI_STRAPS
,
435 HDMI_DISABLE
, &straps
->hdmi_disable
,
436 AUDIO_STREAM_NUMBER
, &straps
->audio_stream_number
);
438 REG_GET(DC_PINSTRAPS
, DC_PINSTRAPS_AUDIO
, &straps
->dc_pinstraps_audio
);
441 static struct audio
*create_audio(
442 struct dc_context
*ctx
, unsigned int inst
)
444 return dce_audio_create(ctx
, inst
,
445 &audio_regs
[inst
], &audio_shift
, &audio_mask
);
449 static struct timing_generator
*dce112_timing_generator_create(
450 struct dc_context
*ctx
,
452 const struct dce110_timing_generator_offsets
*offsets
)
454 struct dce110_timing_generator
*tg110
=
455 dm_alloc(sizeof(struct dce110_timing_generator
));
460 if (dce110_timing_generator_construct(tg110
, ctx
, instance
, offsets
))
468 static struct stream_encoder
*dce112_stream_encoder_create(
469 enum engine_id eng_id
,
470 struct dc_context
*ctx
)
472 struct dce110_stream_encoder
*enc110
=
473 dm_alloc(sizeof(struct dce110_stream_encoder
));
478 if (dce110_stream_encoder_construct(
479 enc110
, ctx
, ctx
->dc_bios
, eng_id
,
480 &stream_enc_regs
[eng_id
], &se_shift
, &se_mask
))
481 return &enc110
->base
;
488 #define SRII(reg_name, block, id)\
489 .reg_name[id] = mm ## block ## id ## _ ## reg_name
491 static const struct dce_hwseq_registers hwseq_reg
= {
492 HWSEQ_DCE112_REG_LIST()
495 static const struct dce_hwseq_shift hwseq_shift
= {
496 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT
)
499 static const struct dce_hwseq_mask hwseq_mask
= {
500 HWSEQ_DCE112_MASK_SH_LIST(_MASK
)
503 static struct dce_hwseq
*dce112_hwseq_create(
504 struct dc_context
*ctx
)
506 struct dce_hwseq
*hws
= dm_alloc(sizeof(struct dce_hwseq
));
510 hws
->regs
= &hwseq_reg
;
511 hws
->shifts
= &hwseq_shift
;
512 hws
->masks
= &hwseq_mask
;
517 static const struct resource_create_funcs res_create_funcs
= {
518 .read_dce_straps
= read_dce_straps
,
519 .create_audio
= create_audio
,
520 .create_stream_encoder
= dce112_stream_encoder_create
,
521 .create_hwseq
= dce112_hwseq_create
,
524 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
525 static const struct dce_mem_input_registers mi_regs
[] = {
534 static const struct dce_mem_input_shift mi_shifts
= {
535 MI_DCE11_2_MASK_SH_LIST(__SHIFT
)
538 static const struct dce_mem_input_mask mi_masks
= {
539 MI_DCE11_2_MASK_SH_LIST(_MASK
)
542 static struct mem_input
*dce112_mem_input_create(
543 struct dc_context
*ctx
,
545 const struct dce110_mem_input_reg_offsets
*offset
)
547 struct dce110_mem_input
*mem_input110
=
548 dm_alloc(sizeof(struct dce110_mem_input
));
553 if (dce112_mem_input_construct(mem_input110
, ctx
, inst
, offset
)) {
554 struct mem_input
*mi
= &mem_input110
->base
;
556 mi
->regs
= &mi_regs
[inst
];
557 mi
->shifts
= &mi_shifts
;
558 mi
->masks
= &mi_masks
;
563 dm_free(mem_input110
);
567 static void dce112_transform_destroy(struct transform
**xfm
)
569 dm_free(TO_DCE_TRANSFORM(*xfm
));
573 static struct transform
*dce112_transform_create(
574 struct dc_context
*ctx
,
577 struct dce_transform
*transform
=
578 dm_alloc(sizeof(struct dce_transform
));
583 if (dce_transform_construct(transform
, ctx
, inst
,
584 &xfm_regs
[inst
], &xfm_shift
, &xfm_mask
)) {
585 transform
->lb_memory_size
= 0x1404; /*5124*/
586 return &transform
->base
;
594 static const struct encoder_feature_support link_enc_feature
= {
595 .max_hdmi_deep_color
= COLOR_DEPTH_121212
,
596 .max_hdmi_pixel_clock
= 600000,
597 .ycbcr420_supported
= true,
598 .flags
.bits
.IS_HBR2_CAPABLE
= true,
599 .flags
.bits
.IS_HBR3_CAPABLE
= true,
600 .flags
.bits
.IS_TPS3_CAPABLE
= true,
601 .flags
.bits
.IS_TPS4_CAPABLE
= true,
602 .flags
.bits
.IS_YCBCR_CAPABLE
= true
605 struct link_encoder
*dce112_link_encoder_create(
606 const struct encoder_init_data
*enc_init_data
)
608 struct dce110_link_encoder
*enc110
=
609 dm_alloc(sizeof(struct dce110_link_encoder
));
614 if (dce110_link_encoder_construct(
618 &link_enc_regs
[enc_init_data
->transmitter
],
619 &link_enc_aux_regs
[enc_init_data
->channel
- 1],
620 &link_enc_hpd_regs
[enc_init_data
->hpd_source
])) {
622 return &enc110
->base
;
630 struct input_pixel_processor
*dce112_ipp_create(
631 struct dc_context
*ctx
,
633 const struct dce110_ipp_reg_offsets
*offset
)
635 struct dce110_ipp
*ipp
=
636 dm_alloc(sizeof(struct dce110_ipp
));
641 if (dce110_ipp_construct(ipp
, ctx
, inst
, offset
))
649 void dce112_ipp_destroy(struct input_pixel_processor
**ipp
)
651 dm_free(TO_DCE110_IPP(*ipp
));
655 struct output_pixel_processor
*dce112_opp_create(
656 struct dc_context
*ctx
,
659 struct dce110_opp
*opp
=
660 dm_alloc(sizeof(struct dce110_opp
));
665 if (dce110_opp_construct(opp
,
666 ctx
, inst
, &opp_regs
[inst
], &opp_shift
, &opp_mask
))
674 struct clock_source
*dce112_clock_source_create(
675 struct dc_context
*ctx
,
676 struct dc_bios
*bios
,
677 enum clock_source_id id
,
678 const struct dce110_clk_src_regs
*regs
,
681 struct dce110_clk_src
*clk_src
=
682 dm_alloc(sizeof(struct dce110_clk_src
));
687 if (dce110_clk_src_construct(clk_src
, ctx
, bios
, id
,
688 regs
, &cs_shift
, &cs_mask
)) {
689 clk_src
->base
.dp_clk_src
= dp_clk_src
;
690 return &clk_src
->base
;
697 void dce112_clock_source_destroy(struct clock_source
**clk_src
)
699 dm_free(TO_DCE110_CLK_SRC(*clk_src
));
703 static void destruct(struct dce110_resource_pool
*pool
)
707 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
708 if (pool
->base
.opps
[i
] != NULL
)
709 dce110_opp_destroy(&pool
->base
.opps
[i
]);
711 if (pool
->base
.transforms
[i
] != NULL
)
712 dce112_transform_destroy(&pool
->base
.transforms
[i
]);
714 if (pool
->base
.ipps
[i
] != NULL
)
715 dce112_ipp_destroy(&pool
->base
.ipps
[i
]);
717 if (pool
->base
.mis
[i
] != NULL
) {
718 dm_free(TO_DCE110_MEM_INPUT(pool
->base
.mis
[i
]));
719 pool
->base
.mis
[i
] = NULL
;
722 if (pool
->base
.timing_generators
[i
] != NULL
) {
723 dm_free(DCE110TG_FROM_TG(pool
->base
.timing_generators
[i
]));
724 pool
->base
.timing_generators
[i
] = NULL
;
728 for (i
= 0; i
< pool
->base
.stream_enc_count
; i
++) {
729 if (pool
->base
.stream_enc
[i
] != NULL
)
730 dm_free(DCE110STRENC_FROM_STRENC(pool
->base
.stream_enc
[i
]));
733 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
734 if (pool
->base
.clock_sources
[i
] != NULL
) {
735 dce112_clock_source_destroy(&pool
->base
.clock_sources
[i
]);
739 if (pool
->base
.dp_clock_source
!= NULL
)
740 dce112_clock_source_destroy(&pool
->base
.dp_clock_source
);
742 for (i
= 0; i
< pool
->base
.audio_count
; i
++) {
743 if (pool
->base
.audios
[i
] != NULL
) {
744 dce_aud_destroy(&pool
->base
.audios
[i
]);
748 if (pool
->base
.abm
!= NULL
)
749 dce_abm_destroy(&pool
->base
.abm
);
751 if (pool
->base
.dmcu
!= NULL
)
752 dce_dmcu_destroy(&pool
->base
.dmcu
);
754 if (pool
->base
.display_clock
!= NULL
)
755 dce_disp_clk_destroy(&pool
->base
.display_clock
);
757 if (pool
->base
.irqs
!= NULL
) {
758 dal_irq_service_destroy(&pool
->base
.irqs
);
762 static struct clock_source
*find_matching_pll(struct resource_context
*res_ctx
,
763 const struct core_stream
*const stream
)
765 switch (stream
->sink
->link
->link_enc
->transmitter
) {
766 case TRANSMITTER_UNIPHY_A
:
767 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL0
];
768 case TRANSMITTER_UNIPHY_B
:
769 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL1
];
770 case TRANSMITTER_UNIPHY_C
:
771 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL2
];
772 case TRANSMITTER_UNIPHY_D
:
773 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL3
];
774 case TRANSMITTER_UNIPHY_E
:
775 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL4
];
776 case TRANSMITTER_UNIPHY_F
:
777 return res_ctx
->pool
->clock_sources
[DCE112_CLK_SRC_PLL5
];
785 static enum dc_status
validate_mapped_resource(
786 const struct core_dc
*dc
,
787 struct validate_context
*context
)
789 enum dc_status status
= DC_OK
;
792 for (i
= 0; i
< context
->stream_count
; i
++) {
793 struct core_stream
*stream
= context
->streams
[i
];
794 struct core_link
*link
= stream
->sink
->link
;
796 if (resource_is_stream_unchanged(dc
->current_context
, stream
))
799 for (j
= 0; j
< MAX_PIPES
; j
++) {
800 struct pipe_ctx
*pipe_ctx
=
801 &context
->res_ctx
.pipe_ctx
[j
];
803 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
806 if (!pipe_ctx
->tg
->funcs
->validate_timing(
807 pipe_ctx
->tg
, &stream
->public.timing
))
808 return DC_FAIL_CONTROLLER_VALIDATE
;
810 status
= dce110_resource_build_pipe_hw_param(pipe_ctx
);
815 if (!link
->link_enc
->funcs
->validate_output_with_stream(
818 return DC_FAIL_ENC_VALIDATE
;
820 /* TODO: validate audio ASIC caps, encoder */
822 status
= dc_link_validate_mode_timing(stream
,
824 &stream
->public.timing
);
829 resource_build_info_frame(pipe_ctx
);
831 /* do not need to validate non root pipes */
839 bool dce112_validate_bandwidth(
840 const struct core_dc
*dc
,
841 struct validate_context
*context
)
846 dc
->ctx
->logger
, LOG_BANDWIDTH_CALCS
,
854 context
->res_ctx
.pipe_ctx
,
855 context
->res_ctx
.pool
->pipe_count
,
856 &context
->bw_results
))
858 context
->dispclk_khz
= context
->bw_results
.dispclk_khz
;
861 dm_logger_write(dc
->ctx
->logger
, LOG_BANDWIDTH_VALIDATION
,
862 "%s: Bandwidth validation failed!",
865 if (memcmp(&dc
->current_context
->bw_results
,
866 &context
->bw_results
, sizeof(context
->bw_results
))) {
867 struct log_entry log_entry
;
871 LOG_BANDWIDTH_CALCS
);
872 dm_logger_append(&log_entry
, "%s: finish,\n"
873 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
874 "stutMark_b: %d stutMark_a: %d\n",
876 context
->bw_results
.nbp_state_change_wm_ns
[0].b_mark
,
877 context
->bw_results
.nbp_state_change_wm_ns
[0].a_mark
,
878 context
->bw_results
.urgent_wm_ns
[0].b_mark
,
879 context
->bw_results
.urgent_wm_ns
[0].a_mark
,
880 context
->bw_results
.stutter_exit_wm_ns
[0].b_mark
,
881 context
->bw_results
.stutter_exit_wm_ns
[0].a_mark
);
882 dm_logger_append(&log_entry
,
883 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
884 "stutMark_b: %d stutMark_a: %d\n",
885 context
->bw_results
.nbp_state_change_wm_ns
[1].b_mark
,
886 context
->bw_results
.nbp_state_change_wm_ns
[1].a_mark
,
887 context
->bw_results
.urgent_wm_ns
[1].b_mark
,
888 context
->bw_results
.urgent_wm_ns
[1].a_mark
,
889 context
->bw_results
.stutter_exit_wm_ns
[1].b_mark
,
890 context
->bw_results
.stutter_exit_wm_ns
[1].a_mark
);
891 dm_logger_append(&log_entry
,
892 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
893 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
894 context
->bw_results
.nbp_state_change_wm_ns
[2].b_mark
,
895 context
->bw_results
.nbp_state_change_wm_ns
[2].a_mark
,
896 context
->bw_results
.urgent_wm_ns
[2].b_mark
,
897 context
->bw_results
.urgent_wm_ns
[2].a_mark
,
898 context
->bw_results
.stutter_exit_wm_ns
[2].b_mark
,
899 context
->bw_results
.stutter_exit_wm_ns
[2].a_mark
,
900 context
->bw_results
.stutter_mode_enable
);
901 dm_logger_append(&log_entry
,
902 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
903 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
904 context
->bw_results
.cpuc_state_change_enable
,
905 context
->bw_results
.cpup_state_change_enable
,
906 context
->bw_results
.nbp_state_change_enable
,
907 context
->bw_results
.all_displays_in_sync
,
908 context
->bw_results
.dispclk_khz
,
909 context
->bw_results
.required_sclk
,
910 context
->bw_results
.required_sclk_deep_sleep
,
911 context
->bw_results
.required_yclk
,
912 context
->bw_results
.blackout_recovery_time_us
);
913 dm_logger_close(&log_entry
);
918 enum dc_status
resource_map_phy_clock_resources(
919 const struct core_dc
*dc
,
920 struct validate_context
*context
)
924 /* acquire new resources */
925 for (i
= 0; i
< context
->stream_count
; i
++) {
926 struct core_stream
*stream
= context
->streams
[i
];
928 if (resource_is_stream_unchanged(dc
->current_context
, stream
))
931 for (j
= 0; j
< MAX_PIPES
; j
++) {
932 struct pipe_ctx
*pipe_ctx
=
933 &context
->res_ctx
.pipe_ctx
[j
];
935 if (context
->res_ctx
.pipe_ctx
[j
].stream
!= stream
)
938 if (dc_is_dp_signal(pipe_ctx
->stream
->signal
)
939 || pipe_ctx
->stream
->signal
== SIGNAL_TYPE_VIRTUAL
)
940 pipe_ctx
->clock_source
=
941 context
->res_ctx
.pool
->dp_clock_source
;
943 pipe_ctx
->clock_source
=
944 find_matching_pll(&context
->res_ctx
,
947 if (pipe_ctx
->clock_source
== NULL
)
948 return DC_NO_CLOCK_SOURCE_RESOURCE
;
950 resource_reference_clock_source(
952 pipe_ctx
->clock_source
);
954 /* only one cs per stream regardless of mpo */
962 static bool dce112_validate_surface_sets(
963 const struct dc_validation_set set
[],
968 for (i
= 0; i
< set_count
; i
++) {
969 if (set
[i
].surface_count
== 0)
972 if (set
[i
].surface_count
> 1)
975 if (set
[i
].surfaces
[0]->format
976 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
983 enum dc_status
dce112_validate_with_context(
984 const struct core_dc
*dc
,
985 const struct dc_validation_set set
[],
987 struct validate_context
*context
)
989 struct dc_context
*dc_ctx
= dc
->ctx
;
990 enum dc_status result
= DC_ERROR_UNEXPECTED
;
993 if (!dce112_validate_surface_sets(set
, set_count
))
994 return DC_FAIL_SURFACE_VALIDATE
;
996 context
->res_ctx
.pool
= dc
->res_pool
;
998 for (i
= 0; i
< set_count
; i
++) {
999 context
->streams
[i
] = DC_STREAM_TO_CORE(set
[i
].stream
);
1000 dc_stream_retain(&context
->streams
[i
]->public);
1001 context
->stream_count
++;
1004 result
= resource_map_pool_resources(dc
, context
);
1006 if (result
== DC_OK
)
1007 result
= resource_map_phy_clock_resources(dc
, context
);
1009 if (!resource_validate_attach_surfaces(
1010 set
, set_count
, dc
->current_context
, context
)) {
1011 DC_ERROR("Failed to attach surface to stream!\n");
1012 return DC_FAIL_ATTACH_SURFACES
;
1015 if (result
== DC_OK
)
1016 result
= validate_mapped_resource(dc
, context
);
1018 if (result
== DC_OK
)
1019 result
= resource_build_scaling_params_for_context(dc
, context
);
1021 if (result
== DC_OK
)
1022 if (!dce112_validate_bandwidth(dc
, context
))
1023 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
1028 enum dc_status
dce112_validate_guaranteed(
1029 const struct core_dc
*dc
,
1030 const struct dc_stream
*dc_stream
,
1031 struct validate_context
*context
)
1033 enum dc_status result
= DC_ERROR_UNEXPECTED
;
1035 context
->res_ctx
.pool
= dc
->res_pool
;
1037 context
->streams
[0] = DC_STREAM_TO_CORE(dc_stream
);
1038 dc_stream_retain(&context
->streams
[0]->public);
1039 context
->stream_count
++;
1041 result
= resource_map_pool_resources(dc
, context
);
1043 if (result
== DC_OK
)
1044 result
= resource_map_phy_clock_resources(dc
, context
);
1046 if (result
== DC_OK
)
1047 result
= validate_mapped_resource(dc
, context
);
1049 if (result
== DC_OK
) {
1050 validate_guaranteed_copy_streams(
1051 context
, dc
->public.caps
.max_streams
);
1052 result
= resource_build_scaling_params_for_context(dc
, context
);
1055 if (result
== DC_OK
)
1056 if (!dce112_validate_bandwidth(dc
, context
))
1057 result
= DC_FAIL_BANDWIDTH_VALIDATE
;
1062 static void dce112_destroy_resource_pool(struct resource_pool
**pool
)
1064 struct dce110_resource_pool
*dce110_pool
= TO_DCE110_RES_POOL(*pool
);
1066 destruct(dce110_pool
);
1067 dm_free(dce110_pool
);
1071 static const struct resource_funcs dce112_res_pool_funcs
= {
1072 .destroy
= dce112_destroy_resource_pool
,
1073 .link_enc_create
= dce112_link_encoder_create
,
1074 .validate_with_context
= dce112_validate_with_context
,
1075 .validate_guaranteed
= dce112_validate_guaranteed
,
1076 .validate_bandwidth
= dce112_validate_bandwidth
1079 static void bw_calcs_data_update_from_pplib(struct core_dc
*dc
)
1081 struct dm_pp_clock_levels_with_latency eng_clks
= {0};
1082 struct dm_pp_clock_levels_with_latency mem_clks
= {0};
1083 struct dm_pp_wm_sets_with_clock_ranges clk_ranges
= {0};
1084 struct dm_pp_clock_levels clks
= {0};
1086 /*do system clock TODO PPLIB: after PPLIB implement,
1087 * then remove old way
1089 if (!dm_pp_get_clock_levels_by_type_with_latency(
1091 DM_PP_CLOCK_TYPE_ENGINE_CLK
,
1094 /* This is only for temporary */
1095 dm_pp_get_clock_levels_by_type(
1097 DM_PP_CLOCK_TYPE_ENGINE_CLK
,
1099 /* convert all the clock fro kHz to fix point mHz */
1100 dc
->bw_vbios
.high_sclk
= bw_frc_to_fixed(
1101 clks
.clocks_in_khz
[clks
.num_levels
-1], 1000);
1102 dc
->bw_vbios
.mid1_sclk
= bw_frc_to_fixed(
1103 clks
.clocks_in_khz
[clks
.num_levels
/8], 1000);
1104 dc
->bw_vbios
.mid2_sclk
= bw_frc_to_fixed(
1105 clks
.clocks_in_khz
[clks
.num_levels
*2/8], 1000);
1106 dc
->bw_vbios
.mid3_sclk
= bw_frc_to_fixed(
1107 clks
.clocks_in_khz
[clks
.num_levels
*3/8], 1000);
1108 dc
->bw_vbios
.mid4_sclk
= bw_frc_to_fixed(
1109 clks
.clocks_in_khz
[clks
.num_levels
*4/8], 1000);
1110 dc
->bw_vbios
.mid5_sclk
= bw_frc_to_fixed(
1111 clks
.clocks_in_khz
[clks
.num_levels
*5/8], 1000);
1112 dc
->bw_vbios
.mid6_sclk
= bw_frc_to_fixed(
1113 clks
.clocks_in_khz
[clks
.num_levels
*6/8], 1000);
1114 dc
->bw_vbios
.low_sclk
= bw_frc_to_fixed(
1115 clks
.clocks_in_khz
[0], 1000);
1118 dm_pp_get_clock_levels_by_type(
1120 DM_PP_CLOCK_TYPE_MEMORY_CLK
,
1123 dc
->bw_vbios
.low_yclk
= bw_frc_to_fixed(
1124 clks
.clocks_in_khz
[0] * MEMORY_TYPE_MULTIPLIER
, 1000);
1125 dc
->bw_vbios
.mid_yclk
= bw_frc_to_fixed(
1126 clks
.clocks_in_khz
[clks
.num_levels
>>1] * MEMORY_TYPE_MULTIPLIER
,
1128 dc
->bw_vbios
.high_yclk
= bw_frc_to_fixed(
1129 clks
.clocks_in_khz
[clks
.num_levels
-1] * MEMORY_TYPE_MULTIPLIER
,
1135 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
1136 dc
->bw_vbios
.high_sclk
= bw_frc_to_fixed(
1137 eng_clks
.data
[eng_clks
.num_levels
-1].clocks_in_khz
, 1000);
1138 dc
->bw_vbios
.mid1_sclk
= bw_frc_to_fixed(
1139 eng_clks
.data
[eng_clks
.num_levels
/8].clocks_in_khz
, 1000);
1140 dc
->bw_vbios
.mid2_sclk
= bw_frc_to_fixed(
1141 eng_clks
.data
[eng_clks
.num_levels
*2/8].clocks_in_khz
, 1000);
1142 dc
->bw_vbios
.mid3_sclk
= bw_frc_to_fixed(
1143 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
, 1000);
1144 dc
->bw_vbios
.mid4_sclk
= bw_frc_to_fixed(
1145 eng_clks
.data
[eng_clks
.num_levels
*4/8].clocks_in_khz
, 1000);
1146 dc
->bw_vbios
.mid5_sclk
= bw_frc_to_fixed(
1147 eng_clks
.data
[eng_clks
.num_levels
*5/8].clocks_in_khz
, 1000);
1148 dc
->bw_vbios
.mid6_sclk
= bw_frc_to_fixed(
1149 eng_clks
.data
[eng_clks
.num_levels
*6/8].clocks_in_khz
, 1000);
1150 dc
->bw_vbios
.low_sclk
= bw_frc_to_fixed(
1151 eng_clks
.data
[0].clocks_in_khz
, 1000);
1154 dm_pp_get_clock_levels_by_type_with_latency(
1156 DM_PP_CLOCK_TYPE_MEMORY_CLK
,
1159 /* we don't need to call PPLIB for validation clock since they
1160 * also give us the highest sclk and highest mclk (UMA clock).
1161 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
1162 * YCLK = UMACLK*m_memoryTypeMultiplier
1164 dc
->bw_vbios
.low_yclk
= bw_frc_to_fixed(
1165 mem_clks
.data
[0].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
, 1000);
1166 dc
->bw_vbios
.mid_yclk
= bw_frc_to_fixed(
1167 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
,
1169 dc
->bw_vbios
.high_yclk
= bw_frc_to_fixed(
1170 mem_clks
.data
[mem_clks
.num_levels
-1].clocks_in_khz
* MEMORY_TYPE_MULTIPLIER
,
1173 /* Now notify PPLib/SMU about which Watermarks sets they should select
1174 * depending on DPM state they are in. And update BW MGR GFX Engine and
1175 * Memory clock member variables for Watermarks calculations for each
1178 clk_ranges
.num_wm_sets
= 4;
1179 clk_ranges
.wm_clk_ranges
[0].wm_set_id
= WM_SET_A
;
1180 clk_ranges
.wm_clk_ranges
[0].wm_min_eng_clk_in_khz
=
1181 eng_clks
.data
[0].clocks_in_khz
;
1182 clk_ranges
.wm_clk_ranges
[0].wm_max_eng_clk_in_khz
=
1183 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
- 1;
1184 clk_ranges
.wm_clk_ranges
[0].wm_min_memg_clk_in_khz
=
1185 mem_clks
.data
[0].clocks_in_khz
;
1186 clk_ranges
.wm_clk_ranges
[0].wm_max_mem_clk_in_khz
=
1187 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
- 1;
1189 clk_ranges
.wm_clk_ranges
[1].wm_set_id
= WM_SET_B
;
1190 clk_ranges
.wm_clk_ranges
[1].wm_min_eng_clk_in_khz
=
1191 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
;
1192 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1193 clk_ranges
.wm_clk_ranges
[1].wm_max_eng_clk_in_khz
= 5000000;
1194 clk_ranges
.wm_clk_ranges
[1].wm_min_memg_clk_in_khz
=
1195 mem_clks
.data
[0].clocks_in_khz
;
1196 clk_ranges
.wm_clk_ranges
[1].wm_max_mem_clk_in_khz
=
1197 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
- 1;
1199 clk_ranges
.wm_clk_ranges
[2].wm_set_id
= WM_SET_C
;
1200 clk_ranges
.wm_clk_ranges
[2].wm_min_eng_clk_in_khz
=
1201 eng_clks
.data
[0].clocks_in_khz
;
1202 clk_ranges
.wm_clk_ranges
[2].wm_max_eng_clk_in_khz
=
1203 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
- 1;
1204 clk_ranges
.wm_clk_ranges
[2].wm_min_memg_clk_in_khz
=
1205 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
;
1206 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1207 clk_ranges
.wm_clk_ranges
[2].wm_max_mem_clk_in_khz
= 5000000;
1209 clk_ranges
.wm_clk_ranges
[3].wm_set_id
= WM_SET_D
;
1210 clk_ranges
.wm_clk_ranges
[3].wm_min_eng_clk_in_khz
=
1211 eng_clks
.data
[eng_clks
.num_levels
*3/8].clocks_in_khz
;
1212 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1213 clk_ranges
.wm_clk_ranges
[3].wm_max_eng_clk_in_khz
= 5000000;
1214 clk_ranges
.wm_clk_ranges
[3].wm_min_memg_clk_in_khz
=
1215 mem_clks
.data
[mem_clks
.num_levels
>>1].clocks_in_khz
;
1216 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1217 clk_ranges
.wm_clk_ranges
[3].wm_max_mem_clk_in_khz
= 5000000;
1219 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1220 dm_pp_notify_wm_clock_changes(dc
->ctx
, &clk_ranges
);
1223 const struct resource_caps
*dce112_resource_cap(
1224 struct hw_asic_id
*asic_id
)
1226 if (ASIC_REV_IS_POLARIS11_M(asic_id
->hw_internal_rev
) ||
1227 ASIC_REV_IS_POLARIS12_V(asic_id
->hw_internal_rev
))
1228 return &polaris_11_resource_cap
;
1230 return &polaris_10_resource_cap
;
1233 static bool construct(
1234 uint8_t num_virtual_links
,
1236 struct dce110_resource_pool
*pool
)
1239 struct dc_context
*ctx
= dc
->ctx
;
1240 struct dm_pp_static_clock_info static_clk_info
= {0};
1242 ctx
->dc_bios
->regs
= &bios_regs
;
1244 pool
->base
.res_cap
= dce112_resource_cap(&ctx
->asic_id
);
1245 pool
->base
.funcs
= &dce112_res_pool_funcs
;
1247 /*************************************************
1248 * Resource + asic cap harcoding *
1249 *************************************************/
1250 pool
->base
.underlay_pipe_index
= NO_UNDERLAY_PIPE
;
1251 pool
->base
.pipe_count
= pool
->base
.res_cap
->num_timing_generator
;
1252 dc
->public.caps
.max_downscale_ratio
= 200;
1253 dc
->public.caps
.i2c_speed_in_khz
= 100;
1254 dc
->public.caps
.max_cursor_size
= 128;
1256 /*************************************************
1257 * Create resources *
1258 *************************************************/
1260 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL0
] =
1261 dce112_clock_source_create(
1263 CLOCK_SOURCE_COMBO_PHY_PLL0
,
1264 &clk_src_regs
[0], false);
1265 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL1
] =
1266 dce112_clock_source_create(
1268 CLOCK_SOURCE_COMBO_PHY_PLL1
,
1269 &clk_src_regs
[1], false);
1270 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL2
] =
1271 dce112_clock_source_create(
1273 CLOCK_SOURCE_COMBO_PHY_PLL2
,
1274 &clk_src_regs
[2], false);
1275 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL3
] =
1276 dce112_clock_source_create(
1278 CLOCK_SOURCE_COMBO_PHY_PLL3
,
1279 &clk_src_regs
[3], false);
1280 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL4
] =
1281 dce112_clock_source_create(
1283 CLOCK_SOURCE_COMBO_PHY_PLL4
,
1284 &clk_src_regs
[4], false);
1285 pool
->base
.clock_sources
[DCE112_CLK_SRC_PLL5
] =
1286 dce112_clock_source_create(
1288 CLOCK_SOURCE_COMBO_PHY_PLL5
,
1289 &clk_src_regs
[5], false);
1290 pool
->base
.clk_src_count
= DCE112_CLK_SRC_TOTAL
;
1292 pool
->base
.dp_clock_source
= dce112_clock_source_create(
1294 CLOCK_SOURCE_ID_DP_DTO
, &clk_src_regs
[0], true);
1297 for (i
= 0; i
< pool
->base
.clk_src_count
; i
++) {
1298 if (pool
->base
.clock_sources
[i
] == NULL
) {
1299 dm_error("DC: failed to create clock sources!\n");
1300 BREAK_TO_DEBUGGER();
1301 goto res_create_fail
;
1305 pool
->base
.display_clock
= dce112_disp_clk_create(ctx
,
1309 if (pool
->base
.display_clock
== NULL
) {
1310 dm_error("DC: failed to create display clock!\n");
1311 BREAK_TO_DEBUGGER();
1312 goto res_create_fail
;
1315 pool
->base
.dmcu
= dce_dmcu_create(ctx
,
1319 if (pool
->base
.dmcu
== NULL
) {
1320 dm_error("DC: failed to create dmcu!\n");
1321 BREAK_TO_DEBUGGER();
1322 goto res_create_fail
;
1325 pool
->base
.abm
= dce_abm_create(ctx
,
1329 if (pool
->base
.abm
== NULL
) {
1330 dm_error("DC: failed to create abm!\n");
1331 BREAK_TO_DEBUGGER();
1332 goto res_create_fail
;
1335 /* get static clock information for PPLIB or firmware, save
1338 if (dm_pp_get_static_clocks(ctx
, &static_clk_info
))
1339 pool
->base
.display_clock
->max_clks_state
=
1340 static_clk_info
.max_clocks_state
;
1343 struct irq_service_init_data init_data
;
1344 init_data
.ctx
= dc
->ctx
;
1345 pool
->base
.irqs
= dal_irq_service_dce110_create(&init_data
);
1346 if (!pool
->base
.irqs
)
1347 goto res_create_fail
;
1350 for (i
= 0; i
< pool
->base
.pipe_count
; i
++) {
1351 pool
->base
.timing_generators
[i
] =
1352 dce112_timing_generator_create(
1355 &dce112_tg_offsets
[i
]);
1356 if (pool
->base
.timing_generators
[i
] == NULL
) {
1357 BREAK_TO_DEBUGGER();
1358 dm_error("DC: failed to create tg!\n");
1359 goto res_create_fail
;
1362 pool
->base
.mis
[i
] = dce112_mem_input_create(
1365 &dce112_mi_reg_offsets
[i
]);
1366 if (pool
->base
.mis
[i
] == NULL
) {
1367 BREAK_TO_DEBUGGER();
1369 "DC: failed to create memory input!\n");
1370 goto res_create_fail
;
1373 pool
->base
.ipps
[i
] = dce112_ipp_create(
1376 &ipp_reg_offsets
[i
]);
1377 if (pool
->base
.ipps
[i
] == NULL
) {
1378 BREAK_TO_DEBUGGER();
1380 "DC:failed to create input pixel processor!\n");
1381 goto res_create_fail
;
1384 pool
->base
.transforms
[i
] = dce112_transform_create(ctx
, i
);
1385 if (pool
->base
.transforms
[i
] == NULL
) {
1386 BREAK_TO_DEBUGGER();
1388 "DC: failed to create transform!\n");
1389 goto res_create_fail
;
1392 pool
->base
.opps
[i
] = dce112_opp_create(
1395 if (pool
->base
.opps
[i
] == NULL
) {
1396 BREAK_TO_DEBUGGER();
1398 "DC:failed to create output pixel processor!\n");
1399 goto res_create_fail
;
1403 if (!resource_construct(num_virtual_links
, dc
, &pool
->base
,
1405 goto res_create_fail
;
1407 dc
->public.caps
.max_surfaces
= pool
->base
.pipe_count
;
1409 /* Create hardware sequencer */
1410 if (!dce112_hw_sequencer_construct(dc
))
1411 goto res_create_fail
;
1413 bw_calcs_init(&dc
->bw_dceip
, &dc
->bw_vbios
, dc
->ctx
->asic_id
);
1415 bw_calcs_data_update_from_pplib(dc
);
1424 struct resource_pool
*dce112_create_resource_pool(
1425 uint8_t num_virtual_links
,
1428 struct dce110_resource_pool
*pool
=
1429 dm_alloc(sizeof(struct dce110_resource_pool
));
1434 if (construct(num_virtual_links
, dc
, pool
))
1437 BREAK_TO_DEBUGGER();