drivers/gpu/drm/amd/display/dc/dce80/dce80_opp.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 /* include DCE8 register header files */
  29 #include "dce/dce_8_0_d.h"
  30 #include "dce/dce_8_0_sh_mask.h"
  31
  32 #include "dce80_opp.h"
  33
  34 #define FROM_OPP(opp)\
  35         container_of(opp, struct dce80_opp, base)
  36
  37 enum {
  38         MAX_LUT_ENTRY = 256,
  39         MAX_NUMBER_OF_ENTRIES = 256
  40 };
  41
  42 static const struct dce80_opp_reg_offsets reg_offsets[] = {
  43 {
  44         .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  45         .crtc_offset = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL -
  46                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  47         .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  48 },
  49 {       .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  50         .crtc_offset = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL -
  51                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  52         .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  53 },
  54 {       .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  55         .crtc_offset = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL -
  56                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  57         .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  58 },
  59 {
  60         .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  61         .crtc_offset = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL -
  62                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  63         .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  64 },
  65 {
  66         .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  67         .crtc_offset = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL -
  68                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  69         .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  70 },
  71 {
  72         .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
  73         .crtc_offset = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL -
  74                                         mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
  75         .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  76 }
  77 };
  78
  79 static const struct opp_funcs funcs = {
  80                 .opp_power_on_regamma_lut = dce80_opp_power_on_regamma_lut,
  81                 .opp_set_csc_adjustment = dce80_opp_set_csc_adjustment,
  82                 .opp_set_csc_default = dce80_opp_set_csc_default,
  83                 .opp_set_dyn_expansion = dce80_opp_set_dyn_expansion,
  84                 .opp_program_regamma_pwl = dce80_opp_program_regamma_pwl,
  85                 .opp_set_regamma_mode = dce80_opp_set_regamma_mode,
  86                 .opp_destroy = dce80_opp_destroy,
  87                 .opp_program_fmt = dce110_opp_program_fmt,
  88 };
  89
  90 /*****************************************/
  91 /* Constructor, Destructor               */
  92 /*****************************************/
  93
  94 bool dce80_opp_construct(struct dce80_opp *opp80,
  95         struct dc_context *ctx,
  96         uint32_t inst)
  97 {
  98         if (inst >= ARRAY_SIZE(reg_offsets))
  99                 return false;
 100
 101         opp80->base.funcs = &funcs;
 102
 103         opp80->base.ctx = ctx;
 104
 105         opp80->base.inst = inst;
 106
 107         opp80->offsets = reg_offsets[inst];
 108
 109         return true;
 110 }
 111
 112 void dce80_opp_destroy(struct output_pixel_processor **opp)
 113 {
 114         dm_free(FROM_OPP(*opp));
 115         *opp = NULL;
 116 }
 117
 118 struct output_pixel_processor *dce80_opp_create(
 119         struct dc_context *ctx,
 120         uint32_t inst)
 121 {
 122         struct dce80_opp *opp =
 123                 dm_alloc(sizeof(struct dce80_opp));
 124
 125         if (!opp)
 126                 return NULL;
 127
 128         if (dce80_opp_construct(opp,
 129                         ctx, inst))
 130                 return &opp->base;
 131
 132         BREAK_TO_DEBUGGER();
 133         dm_free(opp);
 134         return NULL;
 135 }
 136