2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
26 #include "dce_calcs.h"
27 #include "reg_helper.h"
28 #include "basics/conversion.h"
29 #include "dcn10_hubp.h"
38 #define FN(reg_name, field_name) \
39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
41 void hubp1_set_blank(struct hubp
*hubp
, bool blank
)
43 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
44 uint32_t blank_en
= blank
? 1 : 0;
46 REG_UPDATE_2(DCHUBP_CNTL
,
47 HUBP_BLANK_EN
, blank_en
,
48 HUBP_TTU_DISABLE
, blank_en
);
51 uint32_t reg_val
= REG_READ(DCHUBP_CNTL
);
54 /* init sequence workaround: in case HUBP is
55 * power gated, this wait would timeout.
57 * we just wrote reg_val to non-0, if it stay 0
58 * it means HUBP is gated
61 HUBP_NO_OUTSTANDING_REQ
, 1,
70 static void hubp1_disconnect(struct hubp
*hubp
)
72 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
74 REG_UPDATE(DCHUBP_CNTL
,
77 REG_UPDATE(CURSOR_CONTROL
,
81 static void hubp1_disable_control(struct hubp
*hubp
, bool disable_hubp
)
83 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
84 uint32_t disable
= disable_hubp
? 1 : 0;
86 REG_UPDATE(DCHUBP_CNTL
,
87 HUBP_DISABLE
, disable
);
90 static unsigned int hubp1_get_underflow_status(struct hubp
*hubp
)
92 uint32_t hubp_underflow
= 0;
93 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
96 HUBP_UNDERFLOW_STATUS
,
99 return hubp_underflow
;
103 void hubp1_clear_underflow(struct hubp
*hubp
)
105 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
107 REG_UPDATE(DCHUBP_CNTL
, HUBP_UNDERFLOW_CLEAR
, 1);
110 static void hubp1_set_hubp_blank_en(struct hubp
*hubp
, bool blank
)
112 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
113 uint32_t blank_en
= blank
? 1 : 0;
115 REG_UPDATE(DCHUBP_CNTL
, HUBP_BLANK_EN
, blank_en
);
118 static void hubp1_vready_workaround(struct hubp
*hubp
,
119 struct _vcs_dpi_display_pipe_dest_params_st
*pipe_dest
)
122 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
124 /* set HBUBREQ_DEBUG_DB[12] = 1 */
125 value
= REG_READ(HUBPREQ_DEBUG_DB
);
127 /* hack mode disable */
131 if ((pipe_dest
->vstartup_start
- 2*(pipe_dest
->vready_offset
+pipe_dest
->vupdate_width
132 + pipe_dest
->vupdate_offset
) / pipe_dest
->htotal
) <= pipe_dest
->vblank_end
) {
133 /* if (eco_fix_needed(otg_global_sync_timing)
134 * set HBUBREQ_DEBUG_DB[12] = 1 */
138 REG_WRITE(HUBPREQ_DEBUG_DB
, value
);
141 void hubp1_program_tiling(
143 const union dc_tiling_info
*info
,
144 const enum surface_pixel_format pixel_format
)
146 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
148 REG_UPDATE_6(DCSURF_ADDR_CONFIG
,
149 NUM_PIPES
, log_2(info
->gfx9
.num_pipes
),
150 NUM_BANKS
, log_2(info
->gfx9
.num_banks
),
151 PIPE_INTERLEAVE
, info
->gfx9
.pipe_interleave
,
152 NUM_SE
, log_2(info
->gfx9
.num_shader_engines
),
153 NUM_RB_PER_SE
, log_2(info
->gfx9
.num_rb_per_se
),
154 MAX_COMPRESSED_FRAGS
, log_2(info
->gfx9
.max_compressed_frags
));
156 REG_UPDATE_4(DCSURF_TILING_CONFIG
,
157 SW_MODE
, info
->gfx9
.swizzle
,
158 META_LINEAR
, info
->gfx9
.meta_linear
,
159 RB_ALIGNED
, info
->gfx9
.rb_aligned
,
160 PIPE_ALIGNED
, info
->gfx9
.pipe_aligned
);
163 void hubp1_program_size(
165 enum surface_pixel_format format
,
166 const union plane_size
*plane_size
,
167 struct dc_plane_dcc_param
*dcc
)
169 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
170 uint32_t pitch
, meta_pitch
, pitch_c
, meta_pitch_c
;
172 /* Program data and meta surface pitch (calculation from addrlib)
175 if (format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
&& format
< SURFACE_PIXEL_FORMAT_SUBSAMPLE_END
) {
176 ASSERT(plane_size
->video
.chroma_pitch
!= 0);
177 /* Chroma pitch zero can cause system hang! */
179 pitch
= plane_size
->video
.luma_pitch
- 1;
180 meta_pitch
= dcc
->video
.meta_pitch_l
- 1;
181 pitch_c
= plane_size
->video
.chroma_pitch
- 1;
182 meta_pitch_c
= dcc
->video
.meta_pitch_c
- 1;
184 pitch
= plane_size
->grph
.surface_pitch
- 1;
185 meta_pitch
= dcc
->grph
.meta_pitch
- 1;
195 REG_UPDATE_2(DCSURF_SURFACE_PITCH
,
196 PITCH
, pitch
, META_PITCH
, meta_pitch
);
198 if (format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
)
199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C
,
200 PITCH_C
, pitch_c
, META_PITCH_C
, meta_pitch_c
);
203 void hubp1_program_rotation(
205 enum dc_rotation_angle rotation
,
206 bool horizontal_mirror
)
208 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
212 if (horizontal_mirror
)
217 /* Program rotation angle and horz mirror - no mirror */
218 if (rotation
== ROTATION_ANGLE_0
)
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG
,
221 H_MIRROR_EN
, mirror
);
222 else if (rotation
== ROTATION_ANGLE_90
)
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG
,
225 H_MIRROR_EN
, mirror
);
226 else if (rotation
== ROTATION_ANGLE_180
)
227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG
,
229 H_MIRROR_EN
, mirror
);
230 else if (rotation
== ROTATION_ANGLE_270
)
231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG
,
233 H_MIRROR_EN
, mirror
);
236 void hubp1_program_pixel_format(
238 enum surface_pixel_format format
)
240 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
241 uint32_t red_bar
= 3;
242 uint32_t blue_bar
= 2;
244 /* swap for ABGR format */
245 if (format
== SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
246 || format
== SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
247 || format
== SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
248 || format
== SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
) {
253 REG_UPDATE_2(HUBPRET_CONTROL
,
254 CROSSBAR_SRC_CB_B
, blue_bar
,
255 CROSSBAR_SRC_CR_R
, red_bar
);
257 /* Mapping is same as ipp programming (cnvc) */
260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555
:
261 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
262 SURFACE_PIXEL_FORMAT
, 1);
264 case SURFACE_PIXEL_FORMAT_GRPH_RGB565
:
265 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
266 SURFACE_PIXEL_FORMAT
, 3);
268 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888
:
269 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
:
270 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
271 SURFACE_PIXEL_FORMAT
, 8);
273 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010
:
274 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
:
275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
:
276 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
277 SURFACE_PIXEL_FORMAT
, 10);
279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
:
280 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
281 SURFACE_PIXEL_FORMAT
, 22);
283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F
:
284 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
:/*we use crossbar already*/
285 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
286 SURFACE_PIXEL_FORMAT
, 24);
289 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr
:
290 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
291 SURFACE_PIXEL_FORMAT
, 65);
293 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb
:
294 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
295 SURFACE_PIXEL_FORMAT
, 64);
297 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr
:
298 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
299 SURFACE_PIXEL_FORMAT
, 67);
301 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb
:
302 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
303 SURFACE_PIXEL_FORMAT
, 66);
305 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888
:
306 REG_UPDATE(DCSURF_SURFACE_CONFIG
,
307 SURFACE_PIXEL_FORMAT
, 12);
314 /* don't see the need of program the xbar in DCN 1.0 */
317 bool hubp1_program_surface_flip_and_addr(
319 const struct dc_plane_address
*address
,
322 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
326 REG_UPDATE(DCSURF_FLIP_CONTROL
,
327 SURFACE_FLIP_TYPE
, flip_immediate
);
330 if (address
->type
== PLN_ADDR_TYPE_GRPH_STEREO
) {
331 REG_UPDATE(DCSURF_FLIP_CONTROL
, SURFACE_FLIP_MODE_FOR_STEREOSYNC
, 0x1);
332 REG_UPDATE(DCSURF_FLIP_CONTROL
, SURFACE_FLIP_IN_STEREOSYNC
, 0x1);
335 // turn off stereo if not in stereo
336 REG_UPDATE(DCSURF_FLIP_CONTROL
, SURFACE_FLIP_MODE_FOR_STEREOSYNC
, 0x0);
337 REG_UPDATE(DCSURF_FLIP_CONTROL
, SURFACE_FLIP_IN_STEREOSYNC
, 0x0);
342 /* HW automatically latch rest of address register on write to
343 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
345 * program high first and then the low addr, order matters!
347 switch (address
->type
) {
348 case PLN_ADDR_TYPE_GRAPHICS
:
349 /* DCN1.0 does not support const color
350 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
351 * base on address->grph.dcc_const_color
352 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
353 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
356 if (address
->grph
.addr
.quad_part
== 0)
359 REG_UPDATE_2(DCSURF_SURFACE_CONTROL
,
360 PRIMARY_SURFACE_TMZ
, address
->tmz_surface
,
361 PRIMARY_META_SURFACE_TMZ
, address
->tmz_surface
);
363 if (address
->grph
.meta_addr
.quad_part
!= 0) {
364 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
, 0,
365 PRIMARY_META_SURFACE_ADDRESS_HIGH
,
366 address
->grph
.meta_addr
.high_part
);
368 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS
, 0,
369 PRIMARY_META_SURFACE_ADDRESS
,
370 address
->grph
.meta_addr
.low_part
);
373 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
, 0,
374 PRIMARY_SURFACE_ADDRESS_HIGH
,
375 address
->grph
.addr
.high_part
);
377 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS
, 0,
378 PRIMARY_SURFACE_ADDRESS
,
379 address
->grph
.addr
.low_part
);
381 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
:
382 if (address
->video_progressive
.luma_addr
.quad_part
== 0
383 || address
->video_progressive
.chroma_addr
.quad_part
== 0)
386 REG_UPDATE_4(DCSURF_SURFACE_CONTROL
,
387 PRIMARY_SURFACE_TMZ
, address
->tmz_surface
,
388 PRIMARY_SURFACE_TMZ_C
, address
->tmz_surface
,
389 PRIMARY_META_SURFACE_TMZ
, address
->tmz_surface
,
390 PRIMARY_META_SURFACE_TMZ_C
, address
->tmz_surface
);
392 if (address
->video_progressive
.luma_meta_addr
.quad_part
!= 0) {
393 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
, 0,
394 PRIMARY_META_SURFACE_ADDRESS_HIGH_C
,
395 address
->video_progressive
.chroma_meta_addr
.high_part
);
397 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
, 0,
398 PRIMARY_META_SURFACE_ADDRESS_C
,
399 address
->video_progressive
.chroma_meta_addr
.low_part
);
401 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
, 0,
402 PRIMARY_META_SURFACE_ADDRESS_HIGH
,
403 address
->video_progressive
.luma_meta_addr
.high_part
);
405 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS
, 0,
406 PRIMARY_META_SURFACE_ADDRESS
,
407 address
->video_progressive
.luma_meta_addr
.low_part
);
410 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
, 0,
411 PRIMARY_SURFACE_ADDRESS_HIGH_C
,
412 address
->video_progressive
.chroma_addr
.high_part
);
414 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C
, 0,
415 PRIMARY_SURFACE_ADDRESS_C
,
416 address
->video_progressive
.chroma_addr
.low_part
);
418 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
, 0,
419 PRIMARY_SURFACE_ADDRESS_HIGH
,
420 address
->video_progressive
.luma_addr
.high_part
);
422 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS
, 0,
423 PRIMARY_SURFACE_ADDRESS
,
424 address
->video_progressive
.luma_addr
.low_part
);
426 case PLN_ADDR_TYPE_GRPH_STEREO
:
427 if (address
->grph_stereo
.left_addr
.quad_part
== 0)
429 if (address
->grph_stereo
.right_addr
.quad_part
== 0)
432 REG_UPDATE_8(DCSURF_SURFACE_CONTROL
,
433 PRIMARY_SURFACE_TMZ
, address
->tmz_surface
,
434 PRIMARY_SURFACE_TMZ_C
, address
->tmz_surface
,
435 PRIMARY_META_SURFACE_TMZ
, address
->tmz_surface
,
436 PRIMARY_META_SURFACE_TMZ_C
, address
->tmz_surface
,
437 SECONDARY_SURFACE_TMZ
, address
->tmz_surface
,
438 SECONDARY_SURFACE_TMZ_C
, address
->tmz_surface
,
439 SECONDARY_META_SURFACE_TMZ
, address
->tmz_surface
,
440 SECONDARY_META_SURFACE_TMZ_C
, address
->tmz_surface
);
442 if (address
->grph_stereo
.right_meta_addr
.quad_part
!= 0) {
444 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
, 0,
445 SECONDARY_META_SURFACE_ADDRESS_HIGH
,
446 address
->grph_stereo
.right_meta_addr
.high_part
);
448 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS
, 0,
449 SECONDARY_META_SURFACE_ADDRESS
,
450 address
->grph_stereo
.right_meta_addr
.low_part
);
452 if (address
->grph_stereo
.left_meta_addr
.quad_part
!= 0) {
454 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
, 0,
455 PRIMARY_META_SURFACE_ADDRESS_HIGH
,
456 address
->grph_stereo
.left_meta_addr
.high_part
);
458 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS
, 0,
459 PRIMARY_META_SURFACE_ADDRESS
,
460 address
->grph_stereo
.left_meta_addr
.low_part
);
463 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
, 0,
464 SECONDARY_SURFACE_ADDRESS_HIGH
,
465 address
->grph_stereo
.right_addr
.high_part
);
467 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS
, 0,
468 SECONDARY_SURFACE_ADDRESS
,
469 address
->grph_stereo
.right_addr
.low_part
);
471 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
, 0,
472 PRIMARY_SURFACE_ADDRESS_HIGH
,
473 address
->grph_stereo
.left_addr
.high_part
);
475 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS
, 0,
476 PRIMARY_SURFACE_ADDRESS
,
477 address
->grph_stereo
.left_addr
.low_part
);
484 hubp
->request_address
= *address
;
489 void hubp1_dcc_control(struct hubp
*hubp
, bool enable
,
490 bool independent_64b_blks
)
492 uint32_t dcc_en
= enable
? 1 : 0;
493 uint32_t dcc_ind_64b_blk
= independent_64b_blks
? 1 : 0;
494 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
496 REG_UPDATE_4(DCSURF_SURFACE_CONTROL
,
497 PRIMARY_SURFACE_DCC_EN
, dcc_en
,
498 PRIMARY_SURFACE_DCC_IND_64B_BLK
, dcc_ind_64b_blk
,
499 SECONDARY_SURFACE_DCC_EN
, dcc_en
,
500 SECONDARY_SURFACE_DCC_IND_64B_BLK
, dcc_ind_64b_blk
);
503 void hubp1_program_surface_config(
505 enum surface_pixel_format format
,
506 union dc_tiling_info
*tiling_info
,
507 union plane_size
*plane_size
,
508 enum dc_rotation_angle rotation
,
509 struct dc_plane_dcc_param
*dcc
,
510 bool horizontal_mirror
,
511 unsigned int compat_level
)
513 hubp1_dcc_control(hubp
, dcc
->enable
, dcc
->grph
.independent_64b_blks
);
514 hubp1_program_tiling(hubp
, tiling_info
, format
);
515 hubp1_program_size(hubp
, format
, plane_size
, dcc
);
516 hubp1_program_rotation(hubp
, rotation
, horizontal_mirror
);
517 hubp1_program_pixel_format(hubp
, format
);
520 void hubp1_program_requestor(
522 struct _vcs_dpi_display_rq_regs_st
*rq_regs
)
524 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
526 REG_UPDATE(HUBPRET_CONTROL
,
527 DET_BUF_PLANE1_BASE_ADDRESS
, rq_regs
->plane1_base_address
);
528 REG_SET_4(DCN_EXPANSION_MODE
, 0,
529 DRQ_EXPANSION_MODE
, rq_regs
->drq_expansion_mode
,
530 PRQ_EXPANSION_MODE
, rq_regs
->prq_expansion_mode
,
531 MRQ_EXPANSION_MODE
, rq_regs
->mrq_expansion_mode
,
532 CRQ_EXPANSION_MODE
, rq_regs
->crq_expansion_mode
);
533 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG
, 0,
534 CHUNK_SIZE
, rq_regs
->rq_regs_l
.chunk_size
,
535 MIN_CHUNK_SIZE
, rq_regs
->rq_regs_l
.min_chunk_size
,
536 META_CHUNK_SIZE
, rq_regs
->rq_regs_l
.meta_chunk_size
,
537 MIN_META_CHUNK_SIZE
, rq_regs
->rq_regs_l
.min_meta_chunk_size
,
538 DPTE_GROUP_SIZE
, rq_regs
->rq_regs_l
.dpte_group_size
,
539 MPTE_GROUP_SIZE
, rq_regs
->rq_regs_l
.mpte_group_size
,
540 SWATH_HEIGHT
, rq_regs
->rq_regs_l
.swath_height
,
541 PTE_ROW_HEIGHT_LINEAR
, rq_regs
->rq_regs_l
.pte_row_height_linear
);
542 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C
, 0,
543 CHUNK_SIZE_C
, rq_regs
->rq_regs_c
.chunk_size
,
544 MIN_CHUNK_SIZE_C
, rq_regs
->rq_regs_c
.min_chunk_size
,
545 META_CHUNK_SIZE_C
, rq_regs
->rq_regs_c
.meta_chunk_size
,
546 MIN_META_CHUNK_SIZE_C
, rq_regs
->rq_regs_c
.min_meta_chunk_size
,
547 DPTE_GROUP_SIZE_C
, rq_regs
->rq_regs_c
.dpte_group_size
,
548 MPTE_GROUP_SIZE_C
, rq_regs
->rq_regs_c
.mpte_group_size
,
549 SWATH_HEIGHT_C
, rq_regs
->rq_regs_c
.swath_height
,
550 PTE_ROW_HEIGHT_LINEAR_C
, rq_regs
->rq_regs_c
.pte_row_height_linear
);
554 void hubp1_program_deadline(
556 struct _vcs_dpi_display_dlg_regs_st
*dlg_attr
,
557 struct _vcs_dpi_display_ttu_regs_st
*ttu_attr
)
559 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
562 REG_SET_2(BLANK_OFFSET_0
, 0,
563 REFCYC_H_BLANK_END
, dlg_attr
->refcyc_h_blank_end
,
564 DLG_V_BLANK_END
, dlg_attr
->dlg_vblank_end
);
566 REG_SET(BLANK_OFFSET_1
, 0,
567 MIN_DST_Y_NEXT_START
, dlg_attr
->min_dst_y_next_start
);
569 REG_SET(DST_DIMENSIONS
, 0,
570 REFCYC_PER_HTOTAL
, dlg_attr
->refcyc_per_htotal
);
572 REG_SET_2(DST_AFTER_SCALER
, 0,
573 REFCYC_X_AFTER_SCALER
, dlg_attr
->refcyc_x_after_scaler
,
574 DST_Y_AFTER_SCALER
, dlg_attr
->dst_y_after_scaler
);
576 REG_SET(REF_FREQ_TO_PIX_FREQ
, 0,
577 REF_FREQ_TO_PIX_FREQ
, dlg_attr
->ref_freq_to_pix_freq
);
579 /* DLG - Per luma/chroma */
580 REG_SET(VBLANK_PARAMETERS_1
, 0,
581 REFCYC_PER_PTE_GROUP_VBLANK_L
, dlg_attr
->refcyc_per_pte_group_vblank_l
);
583 if (REG(NOM_PARAMETERS_0
))
584 REG_SET(NOM_PARAMETERS_0
, 0,
585 DST_Y_PER_PTE_ROW_NOM_L
, dlg_attr
->dst_y_per_pte_row_nom_l
);
587 if (REG(NOM_PARAMETERS_1
))
588 REG_SET(NOM_PARAMETERS_1
, 0,
589 REFCYC_PER_PTE_GROUP_NOM_L
, dlg_attr
->refcyc_per_pte_group_nom_l
);
591 REG_SET(NOM_PARAMETERS_4
, 0,
592 DST_Y_PER_META_ROW_NOM_L
, dlg_attr
->dst_y_per_meta_row_nom_l
);
594 REG_SET(NOM_PARAMETERS_5
, 0,
595 REFCYC_PER_META_CHUNK_NOM_L
, dlg_attr
->refcyc_per_meta_chunk_nom_l
);
597 REG_SET_2(PER_LINE_DELIVERY
, 0,
598 REFCYC_PER_LINE_DELIVERY_L
, dlg_attr
->refcyc_per_line_delivery_l
,
599 REFCYC_PER_LINE_DELIVERY_C
, dlg_attr
->refcyc_per_line_delivery_c
);
601 REG_SET(VBLANK_PARAMETERS_2
, 0,
602 REFCYC_PER_PTE_GROUP_VBLANK_C
, dlg_attr
->refcyc_per_pte_group_vblank_c
);
604 if (REG(NOM_PARAMETERS_2
))
605 REG_SET(NOM_PARAMETERS_2
, 0,
606 DST_Y_PER_PTE_ROW_NOM_C
, dlg_attr
->dst_y_per_pte_row_nom_c
);
608 if (REG(NOM_PARAMETERS_3
))
609 REG_SET(NOM_PARAMETERS_3
, 0,
610 REFCYC_PER_PTE_GROUP_NOM_C
, dlg_attr
->refcyc_per_pte_group_nom_c
);
612 REG_SET(NOM_PARAMETERS_6
, 0,
613 DST_Y_PER_META_ROW_NOM_C
, dlg_attr
->dst_y_per_meta_row_nom_c
);
615 REG_SET(NOM_PARAMETERS_7
, 0,
616 REFCYC_PER_META_CHUNK_NOM_C
, dlg_attr
->refcyc_per_meta_chunk_nom_c
);
619 REG_SET_2(DCN_TTU_QOS_WM
, 0,
620 QoS_LEVEL_LOW_WM
, ttu_attr
->qos_level_low_wm
,
621 QoS_LEVEL_HIGH_WM
, ttu_attr
->qos_level_high_wm
);
623 /* TTU - per luma/chroma */
624 /* Assumed surf0 is luma and 1 is chroma */
626 REG_SET_3(DCN_SURF0_TTU_CNTL0
, 0,
627 REFCYC_PER_REQ_DELIVERY
, ttu_attr
->refcyc_per_req_delivery_l
,
628 QoS_LEVEL_FIXED
, ttu_attr
->qos_level_fixed_l
,
629 QoS_RAMP_DISABLE
, ttu_attr
->qos_ramp_disable_l
);
631 REG_SET_3(DCN_SURF1_TTU_CNTL0
, 0,
632 REFCYC_PER_REQ_DELIVERY
, ttu_attr
->refcyc_per_req_delivery_c
,
633 QoS_LEVEL_FIXED
, ttu_attr
->qos_level_fixed_c
,
634 QoS_RAMP_DISABLE
, ttu_attr
->qos_ramp_disable_c
);
636 REG_SET_3(DCN_CUR0_TTU_CNTL0
, 0,
637 REFCYC_PER_REQ_DELIVERY
, ttu_attr
->refcyc_per_req_delivery_cur0
,
638 QoS_LEVEL_FIXED
, ttu_attr
->qos_level_fixed_cur0
,
639 QoS_RAMP_DISABLE
, ttu_attr
->qos_ramp_disable_cur0
);
642 static void hubp1_setup(
644 struct _vcs_dpi_display_dlg_regs_st
*dlg_attr
,
645 struct _vcs_dpi_display_ttu_regs_st
*ttu_attr
,
646 struct _vcs_dpi_display_rq_regs_st
*rq_regs
,
647 struct _vcs_dpi_display_pipe_dest_params_st
*pipe_dest
)
649 /* otg is locked when this func is called. Register are double buffered.
650 * disable the requestors is not needed
652 hubp1_program_requestor(hubp
, rq_regs
);
653 hubp1_program_deadline(hubp
, dlg_attr
, ttu_attr
);
654 hubp1_vready_workaround(hubp
, pipe_dest
);
657 static void hubp1_setup_interdependent(
659 struct _vcs_dpi_display_dlg_regs_st
*dlg_attr
,
660 struct _vcs_dpi_display_ttu_regs_st
*ttu_attr
)
662 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
664 REG_SET_2(PREFETCH_SETTINS
, 0,
665 DST_Y_PREFETCH
, dlg_attr
->dst_y_prefetch
,
666 VRATIO_PREFETCH
, dlg_attr
->vratio_prefetch
);
668 REG_SET(PREFETCH_SETTINS_C
, 0,
669 VRATIO_PREFETCH_C
, dlg_attr
->vratio_prefetch_c
);
671 REG_SET_2(VBLANK_PARAMETERS_0
, 0,
672 DST_Y_PER_VM_VBLANK
, dlg_attr
->dst_y_per_vm_vblank
,
673 DST_Y_PER_ROW_VBLANK
, dlg_attr
->dst_y_per_row_vblank
);
675 REG_SET(VBLANK_PARAMETERS_3
, 0,
676 REFCYC_PER_META_CHUNK_VBLANK_L
, dlg_attr
->refcyc_per_meta_chunk_vblank_l
);
678 REG_SET(VBLANK_PARAMETERS_4
, 0,
679 REFCYC_PER_META_CHUNK_VBLANK_C
, dlg_attr
->refcyc_per_meta_chunk_vblank_c
);
681 REG_SET_2(PER_LINE_DELIVERY_PRE
, 0,
682 REFCYC_PER_LINE_DELIVERY_PRE_L
, dlg_attr
->refcyc_per_line_delivery_pre_l
,
683 REFCYC_PER_LINE_DELIVERY_PRE_C
, dlg_attr
->refcyc_per_line_delivery_pre_c
);
685 REG_SET(DCN_SURF0_TTU_CNTL1
, 0,
686 REFCYC_PER_REQ_DELIVERY_PRE
,
687 ttu_attr
->refcyc_per_req_delivery_pre_l
);
688 REG_SET(DCN_SURF1_TTU_CNTL1
, 0,
689 REFCYC_PER_REQ_DELIVERY_PRE
,
690 ttu_attr
->refcyc_per_req_delivery_pre_c
);
691 REG_SET(DCN_CUR0_TTU_CNTL1
, 0,
692 REFCYC_PER_REQ_DELIVERY_PRE
, ttu_attr
->refcyc_per_req_delivery_pre_cur0
);
694 REG_SET_2(DCN_GLOBAL_TTU_CNTL
, 0,
695 MIN_TTU_VBLANK
, ttu_attr
->min_ttu_vblank
,
696 QoS_LEVEL_FLIP
, ttu_attr
->qos_level_flip
);
699 bool hubp1_is_flip_pending(struct hubp
*hubp
)
701 uint32_t flip_pending
= 0;
702 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
703 struct dc_plane_address earliest_inuse_address
;
705 REG_GET(DCSURF_FLIP_CONTROL
,
706 SURFACE_FLIP_PENDING
, &flip_pending
);
708 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE
,
709 SURFACE_EARLIEST_INUSE_ADDRESS
, &earliest_inuse_address
.grph
.addr
.low_part
);
711 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH
,
712 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
, &earliest_inuse_address
.grph
.addr
.high_part
);
717 if (earliest_inuse_address
.grph
.addr
.quad_part
!= hubp
->request_address
.grph
.addr
.quad_part
)
723 uint32_t aperture_default_system
= 1;
724 uint32_t context0_default_system
; /* = 0;*/
726 static void hubp1_set_vm_system_aperture_settings(struct hubp
*hubp
,
727 struct vm_system_aperture_param
*apt
)
729 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
730 PHYSICAL_ADDRESS_LOC mc_vm_apt_default
;
731 PHYSICAL_ADDRESS_LOC mc_vm_apt_low
;
732 PHYSICAL_ADDRESS_LOC mc_vm_apt_high
;
734 mc_vm_apt_default
.quad_part
= apt
->sys_default
.quad_part
>> 12;
735 mc_vm_apt_low
.quad_part
= apt
->sys_low
.quad_part
>> 12;
736 mc_vm_apt_high
.quad_part
= apt
->sys_high
.quad_part
>> 12;
738 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
, 0,
739 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM
, aperture_default_system
, /* 1 = system physical memory */
740 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
, mc_vm_apt_default
.high_part
);
741 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
, 0,
742 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
, mc_vm_apt_default
.low_part
);
744 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB
, 0,
745 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB
, mc_vm_apt_low
.high_part
);
746 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB
, 0,
747 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB
, mc_vm_apt_low
.low_part
);
749 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB
, 0,
750 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB
, mc_vm_apt_high
.high_part
);
751 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB
, 0,
752 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB
, mc_vm_apt_high
.low_part
);
755 static void hubp1_set_vm_context0_settings(struct hubp
*hubp
,
756 const struct vm_context0_param
*vm0
)
758 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
760 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
, 0,
761 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
, vm0
->pte_base
.high_part
);
762 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
, 0,
763 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
, vm0
->pte_base
.low_part
);
766 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
, 0,
767 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
, vm0
->pte_start
.high_part
);
768 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
, 0,
769 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
, vm0
->pte_start
.low_part
);
772 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
, 0,
773 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
, vm0
->pte_end
.high_part
);
774 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
, 0,
775 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
, vm0
->pte_end
.low_part
);
778 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
, 0,
779 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
, vm0
->fault_default
.high_part
,
780 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM
, context0_default_system
);
781 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
, 0,
782 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
, vm0
->fault_default
.low_part
);
784 /* control: enable VM PTE*/
785 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL
, 0,
787 SYSTEM_ACCESS_MODE
, 3);
790 void min_set_viewport(
792 const struct rect
*viewport
,
793 const struct rect
*viewport_c
)
795 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
797 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION
, 0,
798 PRI_VIEWPORT_WIDTH
, viewport
->width
,
799 PRI_VIEWPORT_HEIGHT
, viewport
->height
);
801 REG_SET_2(DCSURF_PRI_VIEWPORT_START
, 0,
802 PRI_VIEWPORT_X_START
, viewport
->x
,
803 PRI_VIEWPORT_Y_START
, viewport
->y
);
806 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION
, 0,
807 SEC_VIEWPORT_WIDTH
, viewport
->width
,
808 SEC_VIEWPORT_HEIGHT
, viewport
->height
);
810 REG_SET_2(DCSURF_SEC_VIEWPORT_START
, 0,
811 SEC_VIEWPORT_X_START
, viewport
->x
,
812 SEC_VIEWPORT_Y_START
, viewport
->y
);
814 /* DC supports NV12 only at the moment */
815 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C
, 0,
816 PRI_VIEWPORT_WIDTH_C
, viewport_c
->width
,
817 PRI_VIEWPORT_HEIGHT_C
, viewport_c
->height
);
819 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C
, 0,
820 PRI_VIEWPORT_X_START_C
, viewport_c
->x
,
821 PRI_VIEWPORT_Y_START_C
, viewport_c
->y
);
824 void hubp1_read_state(struct hubp
*hubp
)
826 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
827 struct dcn_hubp_state
*s
= &hubp1
->state
;
828 struct _vcs_dpi_display_dlg_regs_st
*dlg_attr
= &s
->dlg_attr
;
829 struct _vcs_dpi_display_ttu_regs_st
*ttu_attr
= &s
->ttu_attr
;
830 struct _vcs_dpi_display_rq_regs_st
*rq_regs
= &s
->rq_regs
;
833 REG_GET(HUBPRET_CONTROL
,
834 DET_BUF_PLANE1_BASE_ADDRESS
, &rq_regs
->plane1_base_address
);
835 REG_GET_4(DCN_EXPANSION_MODE
,
836 DRQ_EXPANSION_MODE
, &rq_regs
->drq_expansion_mode
,
837 PRQ_EXPANSION_MODE
, &rq_regs
->prq_expansion_mode
,
838 MRQ_EXPANSION_MODE
, &rq_regs
->mrq_expansion_mode
,
839 CRQ_EXPANSION_MODE
, &rq_regs
->crq_expansion_mode
);
840 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG
,
841 CHUNK_SIZE
, &rq_regs
->rq_regs_l
.chunk_size
,
842 MIN_CHUNK_SIZE
, &rq_regs
->rq_regs_l
.min_chunk_size
,
843 META_CHUNK_SIZE
, &rq_regs
->rq_regs_l
.meta_chunk_size
,
844 MIN_META_CHUNK_SIZE
, &rq_regs
->rq_regs_l
.min_meta_chunk_size
,
845 DPTE_GROUP_SIZE
, &rq_regs
->rq_regs_l
.dpte_group_size
,
846 MPTE_GROUP_SIZE
, &rq_regs
->rq_regs_l
.mpte_group_size
,
847 SWATH_HEIGHT
, &rq_regs
->rq_regs_l
.swath_height
,
848 PTE_ROW_HEIGHT_LINEAR
, &rq_regs
->rq_regs_l
.pte_row_height_linear
);
849 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C
,
850 CHUNK_SIZE_C
, &rq_regs
->rq_regs_c
.chunk_size
,
851 MIN_CHUNK_SIZE_C
, &rq_regs
->rq_regs_c
.min_chunk_size
,
852 META_CHUNK_SIZE_C
, &rq_regs
->rq_regs_c
.meta_chunk_size
,
853 MIN_META_CHUNK_SIZE_C
, &rq_regs
->rq_regs_c
.min_meta_chunk_size
,
854 DPTE_GROUP_SIZE_C
, &rq_regs
->rq_regs_c
.dpte_group_size
,
855 MPTE_GROUP_SIZE_C
, &rq_regs
->rq_regs_c
.mpte_group_size
,
856 SWATH_HEIGHT_C
, &rq_regs
->rq_regs_c
.swath_height
,
857 PTE_ROW_HEIGHT_LINEAR_C
, &rq_regs
->rq_regs_c
.pte_row_height_linear
);
860 REG_GET_2(BLANK_OFFSET_0
,
861 REFCYC_H_BLANK_END
, &dlg_attr
->refcyc_h_blank_end
,
862 DLG_V_BLANK_END
, &dlg_attr
->dlg_vblank_end
);
864 REG_GET(BLANK_OFFSET_1
,
865 MIN_DST_Y_NEXT_START
, &dlg_attr
->min_dst_y_next_start
);
867 REG_GET(DST_DIMENSIONS
,
868 REFCYC_PER_HTOTAL
, &dlg_attr
->refcyc_per_htotal
);
870 REG_GET_2(DST_AFTER_SCALER
,
871 REFCYC_X_AFTER_SCALER
, &dlg_attr
->refcyc_x_after_scaler
,
872 DST_Y_AFTER_SCALER
, &dlg_attr
->dst_y_after_scaler
);
874 if (REG(PREFETCH_SETTINS
))
875 REG_GET_2(PREFETCH_SETTINS
,
876 DST_Y_PREFETCH
, &dlg_attr
->dst_y_prefetch
,
877 VRATIO_PREFETCH
, &dlg_attr
->vratio_prefetch
);
879 REG_GET_2(PREFETCH_SETTINGS
,
880 DST_Y_PREFETCH
, &dlg_attr
->dst_y_prefetch
,
881 VRATIO_PREFETCH
, &dlg_attr
->vratio_prefetch
);
883 REG_GET_2(VBLANK_PARAMETERS_0
,
884 DST_Y_PER_VM_VBLANK
, &dlg_attr
->dst_y_per_vm_vblank
,
885 DST_Y_PER_ROW_VBLANK
, &dlg_attr
->dst_y_per_row_vblank
);
887 REG_GET(REF_FREQ_TO_PIX_FREQ
,
888 REF_FREQ_TO_PIX_FREQ
, &dlg_attr
->ref_freq_to_pix_freq
);
890 /* DLG - Per luma/chroma */
891 REG_GET(VBLANK_PARAMETERS_1
,
892 REFCYC_PER_PTE_GROUP_VBLANK_L
, &dlg_attr
->refcyc_per_pte_group_vblank_l
);
894 REG_GET(VBLANK_PARAMETERS_3
,
895 REFCYC_PER_META_CHUNK_VBLANK_L
, &dlg_attr
->refcyc_per_meta_chunk_vblank_l
);
897 if (REG(NOM_PARAMETERS_0
))
898 REG_GET(NOM_PARAMETERS_0
,
899 DST_Y_PER_PTE_ROW_NOM_L
, &dlg_attr
->dst_y_per_pte_row_nom_l
);
901 if (REG(NOM_PARAMETERS_1
))
902 REG_GET(NOM_PARAMETERS_1
,
903 REFCYC_PER_PTE_GROUP_NOM_L
, &dlg_attr
->refcyc_per_pte_group_nom_l
);
905 REG_GET(NOM_PARAMETERS_4
,
906 DST_Y_PER_META_ROW_NOM_L
, &dlg_attr
->dst_y_per_meta_row_nom_l
);
908 REG_GET(NOM_PARAMETERS_5
,
909 REFCYC_PER_META_CHUNK_NOM_L
, &dlg_attr
->refcyc_per_meta_chunk_nom_l
);
911 REG_GET_2(PER_LINE_DELIVERY_PRE
,
912 REFCYC_PER_LINE_DELIVERY_PRE_L
, &dlg_attr
->refcyc_per_line_delivery_pre_l
,
913 REFCYC_PER_LINE_DELIVERY_PRE_C
, &dlg_attr
->refcyc_per_line_delivery_pre_c
);
915 REG_GET_2(PER_LINE_DELIVERY
,
916 REFCYC_PER_LINE_DELIVERY_L
, &dlg_attr
->refcyc_per_line_delivery_l
,
917 REFCYC_PER_LINE_DELIVERY_C
, &dlg_attr
->refcyc_per_line_delivery_c
);
919 if (REG(PREFETCH_SETTINS_C
))
920 REG_GET(PREFETCH_SETTINS_C
,
921 VRATIO_PREFETCH_C
, &dlg_attr
->vratio_prefetch_c
);
923 REG_GET(PREFETCH_SETTINGS_C
,
924 VRATIO_PREFETCH_C
, &dlg_attr
->vratio_prefetch_c
);
926 REG_GET(VBLANK_PARAMETERS_2
,
927 REFCYC_PER_PTE_GROUP_VBLANK_C
, &dlg_attr
->refcyc_per_pte_group_vblank_c
);
929 REG_GET(VBLANK_PARAMETERS_4
,
930 REFCYC_PER_META_CHUNK_VBLANK_C
, &dlg_attr
->refcyc_per_meta_chunk_vblank_c
);
932 if (REG(NOM_PARAMETERS_2
))
933 REG_GET(NOM_PARAMETERS_2
,
934 DST_Y_PER_PTE_ROW_NOM_C
, &dlg_attr
->dst_y_per_pte_row_nom_c
);
936 if (REG(NOM_PARAMETERS_3
))
937 REG_GET(NOM_PARAMETERS_3
,
938 REFCYC_PER_PTE_GROUP_NOM_C
, &dlg_attr
->refcyc_per_pte_group_nom_c
);
940 REG_GET(NOM_PARAMETERS_6
,
941 DST_Y_PER_META_ROW_NOM_C
, &dlg_attr
->dst_y_per_meta_row_nom_c
);
943 REG_GET(NOM_PARAMETERS_7
,
944 REFCYC_PER_META_CHUNK_NOM_C
, &dlg_attr
->refcyc_per_meta_chunk_nom_c
);
947 REG_GET_2(DCN_TTU_QOS_WM
,
948 QoS_LEVEL_LOW_WM
, &ttu_attr
->qos_level_low_wm
,
949 QoS_LEVEL_HIGH_WM
, &ttu_attr
->qos_level_high_wm
);
951 REG_GET_2(DCN_GLOBAL_TTU_CNTL
,
952 MIN_TTU_VBLANK
, &ttu_attr
->min_ttu_vblank
,
953 QoS_LEVEL_FLIP
, &ttu_attr
->qos_level_flip
);
955 /* TTU - per luma/chroma */
956 /* Assumed surf0 is luma and 1 is chroma */
958 REG_GET_3(DCN_SURF0_TTU_CNTL0
,
959 REFCYC_PER_REQ_DELIVERY
, &ttu_attr
->refcyc_per_req_delivery_l
,
960 QoS_LEVEL_FIXED
, &ttu_attr
->qos_level_fixed_l
,
961 QoS_RAMP_DISABLE
, &ttu_attr
->qos_ramp_disable_l
);
963 REG_GET(DCN_SURF0_TTU_CNTL1
,
964 REFCYC_PER_REQ_DELIVERY_PRE
,
965 &ttu_attr
->refcyc_per_req_delivery_pre_l
);
967 REG_GET_3(DCN_SURF1_TTU_CNTL0
,
968 REFCYC_PER_REQ_DELIVERY
, &ttu_attr
->refcyc_per_req_delivery_c
,
969 QoS_LEVEL_FIXED
, &ttu_attr
->qos_level_fixed_c
,
970 QoS_RAMP_DISABLE
, &ttu_attr
->qos_ramp_disable_c
);
972 REG_GET(DCN_SURF1_TTU_CNTL1
,
973 REFCYC_PER_REQ_DELIVERY_PRE
,
974 &ttu_attr
->refcyc_per_req_delivery_pre_c
);
977 REG_GET(DCSURF_SURFACE_CONFIG
,
978 SURFACE_PIXEL_FORMAT
, &s
->pixel_format
);
980 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH
,
981 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
, &s
->inuse_addr_hi
);
983 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE
,
984 SURFACE_EARLIEST_INUSE_ADDRESS
, &s
->inuse_addr_lo
);
986 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION
,
987 PRI_VIEWPORT_WIDTH
, &s
->viewport_width
,
988 PRI_VIEWPORT_HEIGHT
, &s
->viewport_height
);
990 REG_GET_2(DCSURF_SURFACE_CONFIG
,
991 ROTATION_ANGLE
, &s
->rotation_angle
,
992 H_MIRROR_EN
, &s
->h_mirror_en
);
994 REG_GET(DCSURF_TILING_CONFIG
,
995 SW_MODE
, &s
->sw_mode
);
997 REG_GET(DCSURF_SURFACE_CONTROL
,
998 PRIMARY_SURFACE_DCC_EN
, &s
->dcc_en
);
1000 REG_GET_3(DCHUBP_CNTL
,
1001 HUBP_BLANK_EN
, &s
->blank_en
,
1002 HUBP_TTU_DISABLE
, &s
->ttu_disable
,
1003 HUBP_UNDERFLOW_STATUS
, &s
->underflow_status
);
1005 REG_GET(DCN_GLOBAL_TTU_CNTL
,
1006 MIN_TTU_VBLANK
, &s
->min_ttu_vblank
);
1008 REG_GET_2(DCN_TTU_QOS_WM
,
1009 QoS_LEVEL_LOW_WM
, &s
->qos_level_low_wm
,
1010 QoS_LEVEL_HIGH_WM
, &s
->qos_level_high_wm
);
1013 enum cursor_pitch
hubp1_get_cursor_pitch(unsigned int pitch
)
1015 enum cursor_pitch hw_pitch
;
1019 hw_pitch
= CURSOR_PITCH_64_PIXELS
;
1022 hw_pitch
= CURSOR_PITCH_128_PIXELS
;
1025 hw_pitch
= CURSOR_PITCH_256_PIXELS
;
1028 DC_ERR("Invalid cursor pitch of %d. "
1029 "Only 64/128/256 is supported on DCN.\n", pitch
);
1030 hw_pitch
= CURSOR_PITCH_64_PIXELS
;
1036 static enum cursor_lines_per_chunk
hubp1_get_lines_per_chunk(
1037 unsigned int cur_width
,
1038 enum dc_cursor_color_format format
)
1040 enum cursor_lines_per_chunk line_per_chunk
;
1042 if (format
== CURSOR_MODE_MONO
)
1043 /* impl B. expansion in CUR Buffer reader */
1044 line_per_chunk
= CURSOR_LINE_PER_CHUNK_16
;
1045 else if (cur_width
<= 32)
1046 line_per_chunk
= CURSOR_LINE_PER_CHUNK_16
;
1047 else if (cur_width
<= 64)
1048 line_per_chunk
= CURSOR_LINE_PER_CHUNK_8
;
1049 else if (cur_width
<= 128)
1050 line_per_chunk
= CURSOR_LINE_PER_CHUNK_4
;
1052 line_per_chunk
= CURSOR_LINE_PER_CHUNK_2
;
1054 return line_per_chunk
;
1057 void hubp1_cursor_set_attributes(
1059 const struct dc_cursor_attributes
*attr
)
1061 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
1062 enum cursor_pitch hw_pitch
= hubp1_get_cursor_pitch(attr
->pitch
);
1063 enum cursor_lines_per_chunk lpc
= hubp1_get_lines_per_chunk(
1064 attr
->width
, attr
->color_format
);
1066 hubp
->curs_attr
= *attr
;
1068 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH
,
1069 CURSOR_SURFACE_ADDRESS_HIGH
, attr
->address
.high_part
);
1070 REG_UPDATE(CURSOR_SURFACE_ADDRESS
,
1071 CURSOR_SURFACE_ADDRESS
, attr
->address
.low_part
);
1073 REG_UPDATE_2(CURSOR_SIZE
,
1074 CURSOR_WIDTH
, attr
->width
,
1075 CURSOR_HEIGHT
, attr
->height
);
1077 REG_UPDATE_3(CURSOR_CONTROL
,
1078 CURSOR_MODE
, attr
->color_format
,
1079 CURSOR_PITCH
, hw_pitch
,
1080 CURSOR_LINES_PER_CHUNK
, lpc
);
1082 REG_SET_2(CURSOR_SETTINS
, 0,
1083 /* no shift of the cursor HDL schedule */
1084 CURSOR0_DST_Y_OFFSET
, 0,
1085 /* used to shift the cursor chunk request deadline */
1086 CURSOR0_CHUNK_HDL_ADJUST
, 3);
1089 void hubp1_cursor_set_position(
1091 const struct dc_cursor_position
*pos
,
1092 const struct dc_cursor_mi_param
*param
)
1094 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
1095 int src_x_offset
= pos
->x
- pos
->x_hotspot
- param
->viewport
.x
;
1096 int src_y_offset
= pos
->y
- pos
->y_hotspot
- param
->viewport
.y
;
1097 int x_hotspot
= pos
->x_hotspot
;
1098 int y_hotspot
= pos
->y_hotspot
;
1099 uint32_t dst_x_offset
;
1100 uint32_t cur_en
= pos
->enable
? 1 : 0;
1103 * Guard aganst cursor_set_position() from being called with invalid
1106 * TODO: Look at combining cursor_set_position() and
1107 * cursor_set_attributes() into cursor_update()
1109 if (hubp
->curs_attr
.address
.quad_part
== 0)
1112 if (param
->rotation
== ROTATION_ANGLE_90
|| param
->rotation
== ROTATION_ANGLE_270
) {
1113 src_x_offset
= pos
->y
- pos
->y_hotspot
- param
->viewport
.x
;
1114 y_hotspot
= pos
->x_hotspot
;
1115 x_hotspot
= pos
->y_hotspot
;
1118 if (param
->mirror
) {
1119 x_hotspot
= param
->viewport
.width
- x_hotspot
;
1120 src_x_offset
= param
->viewport
.x
+ param
->viewport
.width
- src_x_offset
;
1123 dst_x_offset
= (src_x_offset
>= 0) ? src_x_offset
: 0;
1124 dst_x_offset
*= param
->ref_clk_khz
;
1125 dst_x_offset
/= param
->pixel_clk_khz
;
1127 ASSERT(param
->h_scale_ratio
.value
);
1129 if (param
->h_scale_ratio
.value
)
1130 dst_x_offset
= dc_fixpt_floor(dc_fixpt_div(
1131 dc_fixpt_from_int(dst_x_offset
),
1132 param
->h_scale_ratio
));
1134 if (src_x_offset
>= (int)param
->viewport
.width
)
1135 cur_en
= 0; /* not visible beyond right edge*/
1137 if (src_x_offset
+ (int)hubp
->curs_attr
.width
<= 0)
1138 cur_en
= 0; /* not visible beyond left edge*/
1140 if (src_y_offset
>= (int)param
->viewport
.height
)
1141 cur_en
= 0; /* not visible beyond bottom edge*/
1143 if (src_y_offset
+ (int)hubp
->curs_attr
.height
<= 0)
1144 cur_en
= 0; /* not visible beyond top edge*/
1146 if (cur_en
&& REG_READ(CURSOR_SURFACE_ADDRESS
) == 0)
1147 hubp
->funcs
->set_cursor_attributes(hubp
, &hubp
->curs_attr
);
1149 REG_UPDATE(CURSOR_CONTROL
,
1150 CURSOR_ENABLE
, cur_en
);
1152 REG_SET_2(CURSOR_POSITION
, 0,
1153 CURSOR_X_POSITION
, pos
->x
,
1154 CURSOR_Y_POSITION
, pos
->y
);
1156 REG_SET_2(CURSOR_HOT_SPOT
, 0,
1157 CURSOR_HOT_SPOT_X
, x_hotspot
,
1158 CURSOR_HOT_SPOT_Y
, y_hotspot
);
1160 REG_SET(CURSOR_DST_OFFSET
, 0,
1161 CURSOR_DST_X_OFFSET
, dst_x_offset
);
1162 /* TODO Handle surface pixel formats other than 4:4:4 */
1165 void hubp1_clk_cntl(struct hubp
*hubp
, bool enable
)
1167 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
1168 uint32_t clk_enable
= enable
? 1 : 0;
1170 REG_UPDATE(HUBP_CLK_CNTL
, HUBP_CLOCK_ENABLE
, clk_enable
);
1173 void hubp1_vtg_sel(struct hubp
*hubp
, uint32_t otg_inst
)
1175 struct dcn10_hubp
*hubp1
= TO_DCN10_HUBP(hubp
);
1177 REG_UPDATE(DCHUBP_CNTL
, HUBP_VTG_SEL
, otg_inst
);
1180 static const struct hubp_funcs dcn10_hubp_funcs
= {
1181 .hubp_program_surface_flip_and_addr
=
1182 hubp1_program_surface_flip_and_addr
,
1183 .hubp_program_surface_config
=
1184 hubp1_program_surface_config
,
1185 .hubp_is_flip_pending
= hubp1_is_flip_pending
,
1186 .hubp_setup
= hubp1_setup
,
1187 .hubp_setup_interdependent
= hubp1_setup_interdependent
,
1188 .hubp_set_vm_system_aperture_settings
= hubp1_set_vm_system_aperture_settings
,
1189 .hubp_set_vm_context0_settings
= hubp1_set_vm_context0_settings
,
1190 .set_blank
= hubp1_set_blank
,
1191 .dcc_control
= hubp1_dcc_control
,
1192 .mem_program_viewport
= min_set_viewport
,
1193 .set_hubp_blank_en
= hubp1_set_hubp_blank_en
,
1194 .set_cursor_attributes
= hubp1_cursor_set_attributes
,
1195 .set_cursor_position
= hubp1_cursor_set_position
,
1196 .hubp_disconnect
= hubp1_disconnect
,
1197 .hubp_clk_cntl
= hubp1_clk_cntl
,
1198 .hubp_vtg_sel
= hubp1_vtg_sel
,
1199 .hubp_read_state
= hubp1_read_state
,
1200 .hubp_clear_underflow
= hubp1_clear_underflow
,
1201 .hubp_disable_control
= hubp1_disable_control
,
1202 .hubp_get_underflow_status
= hubp1_get_underflow_status
,
1206 /*****************************************/
1207 /* Constructor, Destructor */
1208 /*****************************************/
1210 void dcn10_hubp_construct(
1211 struct dcn10_hubp
*hubp1
,
1212 struct dc_context
*ctx
,
1214 const struct dcn_mi_registers
*hubp_regs
,
1215 const struct dcn_mi_shift
*hubp_shift
,
1216 const struct dcn_mi_mask
*hubp_mask
)
1218 hubp1
->base
.funcs
= &dcn10_hubp_funcs
;
1219 hubp1
->base
.ctx
= ctx
;
1220 hubp1
->hubp_regs
= hubp_regs
;
1221 hubp1
->hubp_shift
= hubp_shift
;
1222 hubp1
->hubp_mask
= hubp_mask
;
1223 hubp1
->base
.inst
= inst
;
1224 hubp1
->base
.opp_id
= 0xf;
1225 hubp1
->base
.mpcc_id
= 0xf;