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drm/amd/display: move ocsc programming from opp to dpp
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "resource.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
33 #include "abm.h"
34 #include "dcn10/dcn10_dpp.h"
35 #include "dcn10/dcn10_mpc.h"
36 #include "mem_input.h"
37 #include "timing_generator.h"
38 #include "opp.h"
39 #include "ipp.h"
40 #include "mpc.h"
41 #include "raven1/DCN/dcn_1_0_offset.h"
42 #include "raven1/DCN/dcn_1_0_sh_mask.h"
43 #include "vega10/soc15ip.h"
44 #include "reg_helper.h"
45
46 #define CTX \
47 hws->ctx
48 #define REG(reg)\
49 hws->regs->reg
50
51 #undef FN
52 #define FN(reg_name, field_name) \
53 hws->shifts->field_name, hws->masks->field_name
54
55
56 static void verify_allow_pstate_change_high(
57 struct dce_hwseq *hws)
58 {
59 /* pstate latency is ~20us so if we wait over 40us and pstate allow
60 * still not asserted, we are probably stuck and going to hang
61 */
62 static unsigned int pstate_wait_timeout_us = 40;
63 static unsigned int max_sampled_pstate_wait_us; /* data collection */
64 static bool forced_pstate_allow; /* help with revert wa */
65
66 unsigned int debug_index = 0x7;
67 unsigned int debug_data;
68 unsigned int force_allow_pstate = 0x30;
69 unsigned int i;
70
71 if (forced_pstate_allow) {
72 /* we hacked to force pstate allow to prevent hang last time
73 * we verify_allow_pstate_change_high. so disable force
74 * here so we can check status
75 */
76 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, 0);
77 forced_pstate_allow = false;
78 }
79
80 /* description "3-0: Pipe0 cursor0 QOS
81 * 7-4: Pipe1 cursor0 QOS
82 * 11-8: Pipe2 cursor0 QOS
83 * 15-12: Pipe3 cursor0 QOS
84 * 16: Pipe0 Plane0 Allow Pstate Change
85 * 17: Pipe1 Plane0 Allow Pstate Change
86 * 18: Pipe2 Plane0 Allow Pstate Change
87 * 19: Pipe3 Plane0 Allow Pstate Change
88 * 20: Pipe0 Plane1 Allow Pstate Change
89 * 21: Pipe1 Plane1 Allow Pstate Change
90 * 22: Pipe2 Plane1 Allow Pstate Change
91 * 23: Pipe3 Plane1 Allow Pstate Change
92 * 24: Pipe0 cursor0 Allow Pstate Change
93 * 25: Pipe1 cursor0 Allow Pstate Change
94 * 26: Pipe2 cursor0 Allow Pstate Change
95 * 27: Pipe3 cursor0 Allow Pstate Change
96 * 28: WB0 Allow Pstate Change
97 * 29: WB1 Allow Pstate Change
98 * 30: Arbiter's allow_pstate_change
99 * 31: SOC pstate change request
100 */
101
102 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
103
104 for (i = 0; i < pstate_wait_timeout_us; i++) {
105 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
106
107 if (debug_data & (1 << 30))
108 return;
109
110 if (max_sampled_pstate_wait_us < i)
111 max_sampled_pstate_wait_us = i;
112
113 udelay(1);
114 }
115
116 /* force pstate allow to prevent system hang
117 * and break to debugger to investigate
118 */
119 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
120 forced_pstate_allow = true;
121 BREAK_TO_DEBUGGER();
122 }
123
124 static void enable_dppclk(
125 struct dce_hwseq *hws,
126 uint8_t plane_id,
127 uint32_t requested_pix_clk,
128 bool dppclk_div)
129 {
130 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
131 "dppclk_rate_control for pipe %d programed to %d\n",
132 plane_id,
133 dppclk_div);
134
135 if (hws->shifts->DPPCLK_RATE_CONTROL)
136 REG_UPDATE_2(DPP_CONTROL[plane_id],
137 DPPCLK_RATE_CONTROL, dppclk_div,
138 DPP_CLOCK_ENABLE, 1);
139 else
140 REG_UPDATE(DPP_CONTROL[plane_id],
141 DPP_CLOCK_ENABLE, 1);
142 }
143
144 static void enable_power_gating_plane(
145 struct dce_hwseq *hws,
146 bool enable)
147 {
148 bool force_on = 1; /* disable power gating */
149
150 if (enable)
151 force_on = 0;
152
153 /* DCHUBP0/1/2/3 */
154 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
157 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
158
159 /* DPP0/1/2/3 */
160 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
161 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
162 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
163 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
164 }
165
166 static void disable_vga(
167 struct dce_hwseq *hws)
168 {
169 REG_WRITE(D1VGA_CONTROL, 0);
170 REG_WRITE(D2VGA_CONTROL, 0);
171 REG_WRITE(D3VGA_CONTROL, 0);
172 REG_WRITE(D4VGA_CONTROL, 0);
173 }
174
175 static void dpp_pg_control(
176 struct dce_hwseq *hws,
177 unsigned int dpp_inst,
178 bool power_on)
179 {
180 uint32_t power_gate = power_on ? 0 : 1;
181 uint32_t pwr_status = power_on ? 0 : 2;
182
183 if (hws->ctx->dc->debug.disable_dpp_power_gate)
184 return;
185
186 switch (dpp_inst) {
187 case 0: /* DPP0 */
188 REG_UPDATE(DOMAIN1_PG_CONFIG,
189 DOMAIN1_POWER_GATE, power_gate);
190
191 REG_WAIT(DOMAIN1_PG_STATUS,
192 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
193 break;
194 case 1: /* DPP1 */
195 REG_UPDATE(DOMAIN3_PG_CONFIG,
196 DOMAIN3_POWER_GATE, power_gate);
197
198 REG_WAIT(DOMAIN3_PG_STATUS,
199 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
200 break;
201 case 2: /* DPP2 */
202 REG_UPDATE(DOMAIN5_PG_CONFIG,
203 DOMAIN5_POWER_GATE, power_gate);
204
205 REG_WAIT(DOMAIN5_PG_STATUS,
206 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
207 break;
208 case 3: /* DPP3 */
209 REG_UPDATE(DOMAIN7_PG_CONFIG,
210 DOMAIN7_POWER_GATE, power_gate);
211
212 REG_WAIT(DOMAIN7_PG_STATUS,
213 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
214 break;
215 default:
216 BREAK_TO_DEBUGGER();
217 break;
218 }
219 }
220
221 static void hubp_pg_control(
222 struct dce_hwseq *hws,
223 unsigned int hubp_inst,
224 bool power_on)
225 {
226 uint32_t power_gate = power_on ? 0 : 1;
227 uint32_t pwr_status = power_on ? 0 : 2;
228
229 if (hws->ctx->dc->debug.disable_hubp_power_gate)
230 return;
231
232 switch (hubp_inst) {
233 case 0: /* DCHUBP0 */
234 REG_UPDATE(DOMAIN0_PG_CONFIG,
235 DOMAIN0_POWER_GATE, power_gate);
236
237 REG_WAIT(DOMAIN0_PG_STATUS,
238 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
239 break;
240 case 1: /* DCHUBP1 */
241 REG_UPDATE(DOMAIN2_PG_CONFIG,
242 DOMAIN2_POWER_GATE, power_gate);
243
244 REG_WAIT(DOMAIN2_PG_STATUS,
245 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
246 break;
247 case 2: /* DCHUBP2 */
248 REG_UPDATE(DOMAIN4_PG_CONFIG,
249 DOMAIN4_POWER_GATE, power_gate);
250
251 REG_WAIT(DOMAIN4_PG_STATUS,
252 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
253 break;
254 case 3: /* DCHUBP3 */
255 REG_UPDATE(DOMAIN6_PG_CONFIG,
256 DOMAIN6_POWER_GATE, power_gate);
257
258 REG_WAIT(DOMAIN6_PG_STATUS,
259 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
260 break;
261 default:
262 BREAK_TO_DEBUGGER();
263 break;
264 }
265 }
266
267 static void power_on_plane(
268 struct dce_hwseq *hws,
269 int plane_id)
270 {
271 REG_SET(DC_IP_REQUEST_CNTL, 0,
272 IP_REQUEST_EN, 1);
273 dpp_pg_control(hws, plane_id, true);
274 hubp_pg_control(hws, plane_id, true);
275 REG_SET(DC_IP_REQUEST_CNTL, 0,
276 IP_REQUEST_EN, 0);
277 dm_logger_write(hws->ctx->logger, LOG_DC,
278 "Un-gated front end for pipe %d\n", plane_id);
279 }
280
281 static void bios_golden_init(struct core_dc *dc)
282 {
283 struct dc_bios *bp = dc->ctx->dc_bios;
284 int i;
285
286 /* initialize dcn global */
287 bp->funcs->enable_disp_power_gating(bp,
288 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
289
290 for (i = 0; i < dc->res_pool->pipe_count; i++) {
291 /* initialize dcn per pipe */
292 bp->funcs->enable_disp_power_gating(bp,
293 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
294 }
295 }
296
297 static void dcn10_init_hw(struct core_dc *dc)
298 {
299 int i;
300 struct abm *abm = dc->res_pool->abm;
301 struct dce_hwseq *hws = dc->hwseq;
302
303 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
304 REG_WRITE(REFCLK_CNTL, 0);
305 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
306 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
307
308 if (!dc->public.debug.disable_clock_gate) {
309 /* enable all DCN clock gating */
310 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
311
312 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
313
314 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
315 }
316
317 enable_power_gating_plane(dc->hwseq, true);
318 return;
319 }
320 /* end of FPGA. Below if real ASIC */
321
322 bios_golden_init(dc);
323
324 disable_vga(dc->hwseq);
325
326 for (i = 0; i < dc->link_count; i++) {
327 /* Power up AND update implementation according to the
328 * required signal (which may be different from the
329 * default signal on connector).
330 */
331 struct core_link *link = dc->links[i];
332
333 link->link_enc->funcs->hw_init(link->link_enc);
334 }
335
336 for (i = 0; i < dc->res_pool->pipe_count; i++) {
337 struct transform *xfm = dc->res_pool->transforms[i];
338 struct timing_generator *tg = dc->res_pool->timing_generators[i];
339 struct mpcc *mpcc = dc->res_pool->mpcc[i];
340 struct mpcc_cfg mpcc_cfg;
341
342 xfm->funcs->transform_reset(xfm);
343 mpcc_cfg.opp_id = 0xf;
344 mpcc_cfg.top_dpp_id = 0xf;
345 mpcc_cfg.bot_mpcc_id = 0xf;
346 mpcc_cfg.top_of_tree = true;
347 mpcc->funcs->set(mpcc, &mpcc_cfg);
348
349 /* Blank controller using driver code instead of
350 * command table.
351 */
352 tg->funcs->set_blank(tg, true);
353 hwss_wait_for_blank_complete(tg);
354 }
355
356 for (i = 0; i < dc->res_pool->audio_count; i++) {
357 struct audio *audio = dc->res_pool->audios[i];
358
359 audio->funcs->hw_init(audio);
360 }
361
362 if (abm != NULL) {
363 abm->funcs->init_backlight(abm);
364 abm->funcs->abm_init(abm);
365 }
366
367 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
368 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
369
370 if (!dc->public.debug.disable_clock_gate) {
371 /* enable all DCN clock gating */
372 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
373
374 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
375
376 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
377 }
378
379 enable_power_gating_plane(dc->hwseq, true);
380 }
381
382 static enum dc_status dcn10_prog_pixclk_crtc_otg(
383 struct pipe_ctx *pipe_ctx,
384 struct validate_context *context,
385 struct core_dc *dc)
386 {
387 struct core_stream *stream = pipe_ctx->stream;
388 enum dc_color_space color_space;
389 struct tg_color black_color = {0};
390 bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
391 false:true;
392 bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
393
394
395 /* by upper caller loop, pipe0 is parent pipe and be called first.
396 * back end is set up by for pipe0. Other children pipe share back end
397 * with pipe 0. No program is needed.
398 */
399 if (pipe_ctx->top_pipe != NULL)
400 return DC_OK;
401
402 /* TODO check if timing_changed, disable stream if timing changed */
403
404 /* HW program guide assume display already disable
405 * by unplug sequence. OTG assume stop.
406 */
407 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true);
408
409 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
410 pipe_ctx->clock_source,
411 &pipe_ctx->pix_clk_params,
412 &pipe_ctx->pll_settings)) {
413 BREAK_TO_DEBUGGER();
414 return DC_ERROR_UNEXPECTED;
415 }
416 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
417 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
418 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
419 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
420
421 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
422
423 pipe_ctx->tg->funcs->program_timing(
424 pipe_ctx->tg,
425 &stream->public.timing,
426 true);
427
428 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
429 pipe_ctx->opp,
430 enableStereo,
431 rightEyePolarity);
432
433 #if 0 /* move to after enable_crtc */
434 /* TODO: OPP FMT, ABM. etc. should be done here. */
435 /* or FPGA now. instance 0 only. TODO: move to opp.c */
436
437 inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
438
439 pipe_ctx->opp->funcs->opp_program_fmt(
440 pipe_ctx->opp,
441 &stream->bit_depth_params,
442 &stream->clamping);
443 #endif
444 /* program otg blank color */
445 color_space = stream->public.output_color_space;
446 color_space_to_black_color(dc, color_space, &black_color);
447 pipe_ctx->tg->funcs->set_blank_color(
448 pipe_ctx->tg,
449 &black_color);
450
451 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
452 hwss_wait_for_blank_complete(pipe_ctx->tg);
453
454 /* VTG is within DCHUB command block. DCFCLK is always on */
455 if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
456 BREAK_TO_DEBUGGER();
457 return DC_ERROR_UNEXPECTED;
458 }
459
460 /* TODO program crtc source select for non-virtual signal*/
461 /* TODO program FMT */
462 /* TODO setup link_enc */
463 /* TODO set stream attributes */
464 /* TODO program audio */
465 /* TODO enable stream if timing changed */
466 /* TODO unblank stream if DP */
467
468 return DC_OK;
469 }
470
471 static void reset_back_end_for_pipe(
472 struct core_dc *dc,
473 struct pipe_ctx *pipe_ctx,
474 struct validate_context *context)
475 {
476 int i;
477
478 if (pipe_ctx->stream_enc == NULL) {
479 pipe_ctx->stream = NULL;
480 return;
481 }
482
483 /* TODOFPGA break core_link_disable_stream into 2 functions:
484 * disable_stream and disable_link. disable_link will disable PHYPLL
485 * which is used by otg. Move disable_link after disable_crtc
486 */
487 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
488 core_link_disable_stream(pipe_ctx);
489
490 /* by upper caller loop, parent pipe: pipe0, will be reset last.
491 * back end share by all pipes and will be disable only when disable
492 * parent pipe.
493 */
494 if (pipe_ctx->top_pipe == NULL) {
495 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
496
497 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false);
498 }
499
500 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
501 resource_unreference_clock_source(
502 &context->res_ctx, dc->res_pool,
503 &pipe_ctx->clock_source);
504
505 for (i = 0; i < dc->res_pool->pipe_count; i++)
506 if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx)
507 break;
508
509 if (i == dc->res_pool->pipe_count)
510 return;
511
512 pipe_ctx->stream = NULL;
513 dm_logger_write(dc->ctx->logger, LOG_DC,
514 "Reset back end for pipe %d, tg:%d\n",
515 pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
516 }
517
518 static void plane_atomic_stop(
519 struct core_dc *dc,
520 int fe_idx)
521 {
522 struct mpcc_cfg mpcc_cfg;
523 struct mem_input *mi = dc->res_pool->mis[fe_idx];
524 struct transform *xfm = dc->res_pool->transforms[fe_idx];
525 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
526 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
527
528 mi->funcs->dcc_control(mi, false, false);
529
530 mpcc_cfg.opp_id = 0xf;
531 mpcc_cfg.top_dpp_id = 0xf;
532 mpcc_cfg.bot_mpcc_id = 0xf;
533 mpcc_cfg.top_of_tree = tg->inst == mpcc->inst;
534 mpcc->funcs->set(mpcc, &mpcc_cfg);
535
536 xfm->funcs->transform_reset(xfm);
537 }
538
539 static void reset_front_end(
540 struct core_dc *dc,
541 int fe_idx)
542 {
543 struct dce_hwseq *hws = dc->hwseq;
544 struct mem_input *mi = dc->res_pool->mis[fe_idx];
545 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
546 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
547 unsigned int opp_id = mpcc->opp_id;
548
549 /*Already reset*/
550 if (opp_id == 0xf)
551 return;
552
553 tg->funcs->lock(tg);
554
555 plane_atomic_stop(dc, fe_idx);
556
557 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
558 tg->funcs->unlock(tg);
559
560 if (dc->public.debug.sanity_checks)
561 verify_allow_pstate_change_high(dc->hwseq);
562
563 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
564 REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
565 VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
566
567 mpcc->funcs->wait_for_idle(mpcc);
568
569 mi->funcs->set_blank(mi, true);
570
571 if (dc->public.debug.sanity_checks)
572 verify_allow_pstate_change_high(dc->hwseq);
573
574 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
575 HUBP_CLOCK_ENABLE, 0);
576 REG_UPDATE(DPP_CONTROL[fe_idx],
577 DPP_CLOCK_ENABLE, 0);
578
579 if (tg->inst == mpcc->inst)
580 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
581 OPP_PIPE_CLOCK_EN, 0);
582
583 dm_logger_write(dc->ctx->logger, LOG_DC,
584 "Reset front end %d\n",
585 fe_idx);
586
587 if (dc->public.debug.sanity_checks)
588 verify_allow_pstate_change_high(dc->hwseq);
589 }
590
591 static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx)
592 {
593 struct dce_hwseq *hws = dc->hwseq;
594
595 reset_front_end(dc, fe_idx);
596
597 REG_SET(DC_IP_REQUEST_CNTL, 0,
598 IP_REQUEST_EN, 1);
599 dpp_pg_control(hws, fe_idx, false);
600 hubp_pg_control(hws, fe_idx, false);
601 REG_SET(DC_IP_REQUEST_CNTL, 0,
602 IP_REQUEST_EN, 0);
603 dm_logger_write(dc->ctx->logger, LOG_DC,
604 "Power gated front end %d\n", fe_idx);
605
606 if (dc->public.debug.sanity_checks)
607 verify_allow_pstate_change_high(dc->hwseq);
608 }
609
610 static void reset_hw_ctx_wrap(
611 struct core_dc *dc,
612 struct validate_context *context)
613 {
614 int i;
615
616 /* Reset Front End*/
617 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
618 struct pipe_ctx *pipe_ctx_old =
619 &dc->current_context->res_ctx.pipe_ctx[i];
620 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
621
622 /*if (!pipe_ctx_old->stream)
623 continue;*/
624
625 if (!pipe_ctx->stream || !pipe_ctx->surface)
626 dcn10_power_down_fe(dc, i);
627 else if (pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
628 reset_front_end(dc, i);
629 }
630 /* Reset Back End*/
631 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
632 struct pipe_ctx *pipe_ctx_old =
633 &dc->current_context->res_ctx.pipe_ctx[i];
634 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
635
636 if (!pipe_ctx_old->stream)
637 continue;
638
639 if (!pipe_ctx->stream ||
640 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
641 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context);
642 }
643 }
644
645 static bool patch_address_for_sbs_tb_stereo(
646 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
647 {
648 struct core_surface *surface = pipe_ctx->surface;
649 bool sec_split = pipe_ctx->top_pipe &&
650 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
651 if (sec_split && surface->public.address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
652 (pipe_ctx->stream->public.timing.timing_3d_format ==
653 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
654 pipe_ctx->stream->public.timing.timing_3d_format ==
655 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
656 *addr = surface->public.address.grph_stereo.left_addr;
657 surface->public.address.grph_stereo.left_addr =
658 surface->public.address.grph_stereo.right_addr;
659 return true;
660 } else {
661 if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE &&
662 surface->public.address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
663 surface->public.address.type = PLN_ADDR_TYPE_GRPH_STEREO;
664 surface->public.address.grph_stereo.right_addr =
665 surface->public.address.grph_stereo.left_addr;
666 }
667 }
668 return false;
669 }
670
671 static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
672 {
673 bool addr_patched = false;
674 PHYSICAL_ADDRESS_LOC addr;
675 struct core_surface *surface = pipe_ctx->surface;
676
677 if (surface == NULL)
678 return;
679 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
680 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
681 pipe_ctx->mi,
682 &surface->public.address,
683 surface->public.flip_immediate);
684 surface->status.requested_address = surface->public.address;
685 if (addr_patched)
686 pipe_ctx->surface->public.address.grph_stereo.left_addr = addr;
687 }
688
689 static bool dcn10_set_input_transfer_func(
690 struct pipe_ctx *pipe_ctx, const struct core_surface *surface)
691 {
692 struct input_pixel_processor *ipp = pipe_ctx->ipp;
693 const struct dc_transfer_func *tf = NULL;
694 bool result = true;
695
696 if (ipp == NULL)
697 return false;
698
699 if (surface->public.in_transfer_func)
700 tf = surface->public.in_transfer_func;
701
702 if (surface->public.gamma_correction && dce_use_lut(surface))
703 ipp->funcs->ipp_program_input_lut(ipp,
704 surface->public.gamma_correction);
705
706 if (tf == NULL)
707 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
708 else if (tf->type == TF_TYPE_PREDEFINED) {
709 switch (tf->tf) {
710 case TRANSFER_FUNCTION_SRGB:
711 ipp->funcs->ipp_set_degamma(ipp,
712 IPP_DEGAMMA_MODE_HW_sRGB);
713 break;
714 case TRANSFER_FUNCTION_BT709:
715 ipp->funcs->ipp_set_degamma(ipp,
716 IPP_DEGAMMA_MODE_HW_xvYCC);
717 break;
718 case TRANSFER_FUNCTION_LINEAR:
719 ipp->funcs->ipp_set_degamma(ipp,
720 IPP_DEGAMMA_MODE_BYPASS);
721 break;
722 case TRANSFER_FUNCTION_PQ:
723 result = false;
724 break;
725 default:
726 result = false;
727 break;
728 }
729 } else if (tf->type == TF_TYPE_BYPASS) {
730 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
731 } else {
732 /*TF_TYPE_DISTRIBUTED_POINTS*/
733 result = false;
734 }
735
736 return result;
737 }
738 /*modify the method to handle rgb for arr_points*/
739 static bool convert_to_custom_float(
740 struct pwl_result_data *rgb_resulted,
741 struct curve_points *arr_points,
742 uint32_t hw_points_num)
743 {
744 struct custom_float_format fmt;
745
746 struct pwl_result_data *rgb = rgb_resulted;
747
748 uint32_t i = 0;
749
750 fmt.exponenta_bits = 6;
751 fmt.mantissa_bits = 12;
752 fmt.sign = false;
753
754 if (!convert_to_custom_float_format(
755 arr_points[0].x,
756 &fmt,
757 &arr_points[0].custom_float_x)) {
758 BREAK_TO_DEBUGGER();
759 return false;
760 }
761
762 if (!convert_to_custom_float_format(
763 arr_points[0].offset,
764 &fmt,
765 &arr_points[0].custom_float_offset)) {
766 BREAK_TO_DEBUGGER();
767 return false;
768 }
769
770 if (!convert_to_custom_float_format(
771 arr_points[0].slope,
772 &fmt,
773 &arr_points[0].custom_float_slope)) {
774 BREAK_TO_DEBUGGER();
775 return false;
776 }
777
778 fmt.mantissa_bits = 10;
779 fmt.sign = false;
780
781 if (!convert_to_custom_float_format(
782 arr_points[1].x,
783 &fmt,
784 &arr_points[1].custom_float_x)) {
785 BREAK_TO_DEBUGGER();
786 return false;
787 }
788
789 if (!convert_to_custom_float_format(
790 arr_points[1].y,
791 &fmt,
792 &arr_points[1].custom_float_y)) {
793 BREAK_TO_DEBUGGER();
794 return false;
795 }
796
797 if (!convert_to_custom_float_format(
798 arr_points[1].slope,
799 &fmt,
800 &arr_points[1].custom_float_slope)) {
801 BREAK_TO_DEBUGGER();
802 return false;
803 }
804
805 fmt.mantissa_bits = 12;
806 fmt.sign = true;
807
808 while (i != hw_points_num) {
809 if (!convert_to_custom_float_format(
810 rgb->red,
811 &fmt,
812 &rgb->red_reg)) {
813 BREAK_TO_DEBUGGER();
814 return false;
815 }
816
817 if (!convert_to_custom_float_format(
818 rgb->green,
819 &fmt,
820 &rgb->green_reg)) {
821 BREAK_TO_DEBUGGER();
822 return false;
823 }
824
825 if (!convert_to_custom_float_format(
826 rgb->blue,
827 &fmt,
828 &rgb->blue_reg)) {
829 BREAK_TO_DEBUGGER();
830 return false;
831 }
832
833 if (!convert_to_custom_float_format(
834 rgb->delta_red,
835 &fmt,
836 &rgb->delta_red_reg)) {
837 BREAK_TO_DEBUGGER();
838 return false;
839 }
840
841 if (!convert_to_custom_float_format(
842 rgb->delta_green,
843 &fmt,
844 &rgb->delta_green_reg)) {
845 BREAK_TO_DEBUGGER();
846 return false;
847 }
848
849 if (!convert_to_custom_float_format(
850 rgb->delta_blue,
851 &fmt,
852 &rgb->delta_blue_reg)) {
853 BREAK_TO_DEBUGGER();
854 return false;
855 }
856
857 ++rgb;
858 ++i;
859 }
860
861 return true;
862 }
863 #define MAX_REGIONS_NUMBER 34
864 #define MAX_LOW_POINT 25
865 #define NUMBER_SEGMENTS 32
866
867 static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
868 *output_tf, struct pwl_params *regamma_params)
869 {
870 struct curve_points *arr_points;
871 struct pwl_result_data *rgb_resulted;
872 struct pwl_result_data *rgb;
873 struct pwl_result_data *rgb_plus_1;
874 struct fixed31_32 y_r;
875 struct fixed31_32 y_g;
876 struct fixed31_32 y_b;
877 struct fixed31_32 y1_min;
878 struct fixed31_32 y3_max;
879
880 int32_t segment_start, segment_end;
881 int32_t i;
882 uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
883
884 if (output_tf == NULL || regamma_params == NULL ||
885 output_tf->type == TF_TYPE_BYPASS)
886 return false;
887
888 arr_points = regamma_params->arr_points;
889 rgb_resulted = regamma_params->rgb_resulted;
890 hw_points = 0;
891
892 memset(regamma_params, 0, sizeof(struct pwl_params));
893 memset(seg_distr, 0, sizeof(seg_distr));
894
895 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
896 /* 32 segments
897 * segments are from 2^-25 to 2^7
898 */
899 for (i = 0; i < 32 ; i++)
900 seg_distr[i] = 3;
901
902 segment_start = -25;
903 segment_end = 7;
904 } else {
905 /* 10 segments
906 * segment is from 2^-10 to 2^0
907 * There are less than 256 points, for optimization
908 */
909 seg_distr[0] = 3;
910 seg_distr[1] = 4;
911 seg_distr[2] = 4;
912 seg_distr[3] = 4;
913 seg_distr[4] = 4;
914 seg_distr[5] = 4;
915 seg_distr[6] = 4;
916 seg_distr[7] = 4;
917 seg_distr[8] = 5;
918 seg_distr[9] = 5;
919
920 segment_start = -10;
921 segment_end = 0;
922 }
923
924 for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
925 seg_distr[i] = -1;
926
927 for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
928 if (seg_distr[k] != -1)
929 hw_points += (1 << seg_distr[k]);
930 }
931
932 j = 0;
933 for (k = 0; k < (segment_end - segment_start); k++) {
934 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
935 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
936 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
937 if (j == hw_points - 1)
938 break;
939 rgb_resulted[j].red = output_tf->tf_pts.red[i];
940 rgb_resulted[j].green = output_tf->tf_pts.green[i];
941 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
942 j++;
943 }
944 }
945
946 /* last point */
947 start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
948 rgb_resulted[hw_points - 1].red =
949 output_tf->tf_pts.red[start_index];
950 rgb_resulted[hw_points - 1].green =
951 output_tf->tf_pts.green[start_index];
952 rgb_resulted[hw_points - 1].blue =
953 output_tf->tf_pts.blue[start_index];
954
955 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
956 dal_fixed31_32_from_int(segment_start));
957 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
958 dal_fixed31_32_from_int(segment_end));
959 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
960 dal_fixed31_32_from_int(segment_end));
961
962 y_r = rgb_resulted[0].red;
963 y_g = rgb_resulted[0].green;
964 y_b = rgb_resulted[0].blue;
965
966 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
967
968 arr_points[0].y = y1_min;
969 arr_points[0].slope = dal_fixed31_32_div(
970 arr_points[0].y,
971 arr_points[0].x);
972 y_r = rgb_resulted[hw_points - 1].red;
973 y_g = rgb_resulted[hw_points - 1].green;
974 y_b = rgb_resulted[hw_points - 1].blue;
975
976 /* see comment above, m_arrPoints[1].y should be the Y value for the
977 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
978 */
979 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
980
981 arr_points[1].y = y3_max;
982 arr_points[2].y = y3_max;
983
984 arr_points[1].slope = dal_fixed31_32_zero;
985 arr_points[2].slope = dal_fixed31_32_zero;
986
987 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
988 /* for PQ, we want to have a straight line from last HW X point,
989 * and the slope to be such that we hit 1.0 at 10000 nits.
990 */
991 const struct fixed31_32 end_value =
992 dal_fixed31_32_from_int(125);
993
994 arr_points[1].slope = dal_fixed31_32_div(
995 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
996 dal_fixed31_32_sub(end_value, arr_points[1].x));
997 arr_points[2].slope = dal_fixed31_32_div(
998 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
999 dal_fixed31_32_sub(end_value, arr_points[1].x));
1000 }
1001
1002 regamma_params->hw_points_num = hw_points;
1003
1004 i = 1;
1005 for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1006 if (seg_distr[k] != -1) {
1007 regamma_params->arr_curve_points[k].segments_num =
1008 seg_distr[k];
1009 regamma_params->arr_curve_points[i].offset =
1010 regamma_params->arr_curve_points[k].
1011 offset + (1 << seg_distr[k]);
1012 }
1013 i++;
1014 }
1015
1016 if (seg_distr[k] != -1)
1017 regamma_params->arr_curve_points[k].segments_num =
1018 seg_distr[k];
1019
1020 rgb = rgb_resulted;
1021 rgb_plus_1 = rgb_resulted + 1;
1022
1023 i = 1;
1024
1025 while (i != hw_points + 1) {
1026 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1027 rgb_plus_1->red = rgb->red;
1028 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1029 rgb_plus_1->green = rgb->green;
1030 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1031 rgb_plus_1->blue = rgb->blue;
1032
1033 rgb->delta_red = dal_fixed31_32_sub(
1034 rgb_plus_1->red,
1035 rgb->red);
1036 rgb->delta_green = dal_fixed31_32_sub(
1037 rgb_plus_1->green,
1038 rgb->green);
1039 rgb->delta_blue = dal_fixed31_32_sub(
1040 rgb_plus_1->blue,
1041 rgb->blue);
1042
1043 ++rgb_plus_1;
1044 ++rgb;
1045 ++i;
1046 }
1047
1048 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1049
1050 return true;
1051 }
1052
1053 static bool dcn10_set_output_transfer_func(
1054 struct pipe_ctx *pipe_ctx,
1055 const struct core_stream *stream)
1056 {
1057 struct output_pixel_processor *opp = pipe_ctx->opp;
1058
1059 if (opp == NULL)
1060 return false;
1061
1062 opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1063
1064 if (stream->public.out_transfer_func &&
1065 stream->public.out_transfer_func->type ==
1066 TF_TYPE_PREDEFINED &&
1067 stream->public.out_transfer_func->tf ==
1068 TRANSFER_FUNCTION_SRGB) {
1069 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
1070 } else if (dcn10_translate_regamma_to_hw_format(
1071 stream->public.out_transfer_func, &opp->regamma_params)) {
1072 opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params);
1073 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
1074 } else {
1075 opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
1076 }
1077
1078 return true;
1079 }
1080
1081 static void dcn10_pipe_control_lock(
1082 struct core_dc *dc,
1083 struct pipe_ctx *pipe,
1084 bool lock)
1085 {
1086 /* use TG master update lock to lock everything on the TG
1087 * therefore only top pipe need to lock
1088 */
1089 if (pipe->top_pipe)
1090 return;
1091
1092 if (dc->public.debug.sanity_checks)
1093 verify_allow_pstate_change_high(dc->hwseq);
1094
1095 if (lock)
1096 pipe->tg->funcs->lock(pipe->tg);
1097 else
1098 pipe->tg->funcs->unlock(pipe->tg);
1099
1100 if (dc->public.debug.sanity_checks)
1101 verify_allow_pstate_change_high(dc->hwseq);
1102 }
1103
1104 static bool wait_for_reset_trigger_to_occur(
1105 struct dc_context *dc_ctx,
1106 struct timing_generator *tg)
1107 {
1108 bool rc = false;
1109
1110 /* To avoid endless loop we wait at most
1111 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1112 const uint32_t frames_to_wait_on_triggered_reset = 10;
1113 int i;
1114
1115 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1116
1117 if (!tg->funcs->is_counter_moving(tg)) {
1118 DC_ERROR("TG counter is not moving!\n");
1119 break;
1120 }
1121
1122 if (tg->funcs->did_triggered_reset_occur(tg)) {
1123 rc = true;
1124 /* usually occurs at i=1 */
1125 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1126 i);
1127 break;
1128 }
1129
1130 /* Wait for one frame. */
1131 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1132 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1133 }
1134
1135 if (false == rc)
1136 DC_ERROR("GSL: Timeout on reset trigger!\n");
1137
1138 return rc;
1139 }
1140
1141 static void dcn10_enable_timing_synchronization(
1142 struct core_dc *dc,
1143 int group_index,
1144 int group_size,
1145 struct pipe_ctx *grouped_pipes[])
1146 {
1147 struct dc_context *dc_ctx = dc->ctx;
1148 int i;
1149
1150 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1151
1152 for (i = 1; i < group_size; i++)
1153 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
1154 grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst);
1155
1156
1157 DC_SYNC_INFO("Waiting for trigger\n");
1158
1159 /* Need to get only check 1 pipe for having reset as all the others are
1160 * synchronized. Look at last pipe programmed to reset.
1161 */
1162 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg);
1163 for (i = 1; i < group_size; i++)
1164 grouped_pipes[i]->tg->funcs->disable_reset_trigger(
1165 grouped_pipes[i]->tg);
1166
1167 DC_SYNC_INFO("Sync complete\n");
1168 }
1169
1170 static void print_rq_dlg_ttu(
1171 struct core_dc *core_dc,
1172 struct pipe_ctx *pipe_ctx)
1173 {
1174 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1175 "\n============== DML TTU Output parameters [%d] ==============\n"
1176 "qos_level_low_wm: %d, \n"
1177 "qos_level_high_wm: %d, \n"
1178 "min_ttu_vblank: %d, \n"
1179 "qos_level_flip: %d, \n"
1180 "refcyc_per_req_delivery_l: %d, \n"
1181 "qos_level_fixed_l: %d, \n"
1182 "qos_ramp_disable_l: %d, \n"
1183 "refcyc_per_req_delivery_pre_l: %d, \n"
1184 "refcyc_per_req_delivery_c: %d, \n"
1185 "qos_level_fixed_c: %d, \n"
1186 "qos_ramp_disable_c: %d, \n"
1187 "refcyc_per_req_delivery_pre_c: %d\n"
1188 "=============================================================\n",
1189 pipe_ctx->pipe_idx,
1190 pipe_ctx->ttu_regs.qos_level_low_wm,
1191 pipe_ctx->ttu_regs.qos_level_high_wm,
1192 pipe_ctx->ttu_regs.min_ttu_vblank,
1193 pipe_ctx->ttu_regs.qos_level_flip,
1194 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1195 pipe_ctx->ttu_regs.qos_level_fixed_l,
1196 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1197 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1198 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1199 pipe_ctx->ttu_regs.qos_level_fixed_c,
1200 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1201 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1202 );
1203
1204 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1205 "\n============== DML DLG Output parameters [%d] ==============\n"
1206 "refcyc_h_blank_end: %d, \n"
1207 "dlg_vblank_end: %d, \n"
1208 "min_dst_y_next_start: %d, \n"
1209 "refcyc_per_htotal: %d, \n"
1210 "refcyc_x_after_scaler: %d, \n"
1211 "dst_y_after_scaler: %d, \n"
1212 "dst_y_prefetch: %d, \n"
1213 "dst_y_per_vm_vblank: %d, \n"
1214 "dst_y_per_row_vblank: %d, \n"
1215 "ref_freq_to_pix_freq: %d, \n"
1216 "vratio_prefetch: %d, \n"
1217 "refcyc_per_pte_group_vblank_l: %d, \n"
1218 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1219 "dst_y_per_pte_row_nom_l: %d, \n"
1220 "refcyc_per_pte_group_nom_l: %d, \n",
1221 pipe_ctx->pipe_idx,
1222 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1223 pipe_ctx->dlg_regs.dlg_vblank_end,
1224 pipe_ctx->dlg_regs.min_dst_y_next_start,
1225 pipe_ctx->dlg_regs.refcyc_per_htotal,
1226 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1227 pipe_ctx->dlg_regs.dst_y_after_scaler,
1228 pipe_ctx->dlg_regs.dst_y_prefetch,
1229 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1230 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1231 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1232 pipe_ctx->dlg_regs.vratio_prefetch,
1233 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1234 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1235 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1236 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1237 );
1238
1239 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1240 "\ndst_y_per_meta_row_nom_l: %d, \n"
1241 "refcyc_per_meta_chunk_nom_l: %d, \n"
1242 "refcyc_per_line_delivery_pre_l: %d, \n"
1243 "refcyc_per_line_delivery_l: %d, \n"
1244 "vratio_prefetch_c: %d, \n"
1245 "refcyc_per_pte_group_vblank_c: %d, \n"
1246 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1247 "dst_y_per_pte_row_nom_c: %d, \n"
1248 "refcyc_per_pte_group_nom_c: %d, \n"
1249 "dst_y_per_meta_row_nom_c: %d, \n"
1250 "refcyc_per_meta_chunk_nom_c: %d, \n"
1251 "refcyc_per_line_delivery_pre_c: %d, \n"
1252 "refcyc_per_line_delivery_c: %d \n"
1253 "========================================================\n",
1254 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1255 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1256 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1257 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1258 pipe_ctx->dlg_regs.vratio_prefetch_c,
1259 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1260 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1261 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1262 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1263 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1264 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1265 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1266 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1267 );
1268
1269 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1270 "\n============== DML RQ Output parameters [%d] ==============\n"
1271 "chunk_size: %d \n"
1272 "min_chunk_size: %d \n"
1273 "meta_chunk_size: %d \n"
1274 "min_meta_chunk_size: %d \n"
1275 "dpte_group_size: %d \n"
1276 "mpte_group_size: %d \n"
1277 "swath_height: %d \n"
1278 "pte_row_height_linear: %d \n"
1279 "========================================================\n",
1280 pipe_ctx->pipe_idx,
1281 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1282 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1283 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1284 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1285 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1286 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1287 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1288 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1289 );
1290 }
1291
1292 static void dcn10_power_on_fe(
1293 struct core_dc *dc,
1294 struct pipe_ctx *pipe_ctx,
1295 struct validate_context *context)
1296 {
1297 struct dc_surface *dc_surface = &pipe_ctx->surface->public;
1298 struct dce_hwseq *hws = dc->hwseq;
1299
1300 power_on_plane(dc->hwseq,
1301 pipe_ctx->pipe_idx);
1302
1303 /* enable DCFCLK current DCHUB */
1304 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1305 HUBP_CLOCK_ENABLE, 1);
1306
1307 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1308 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
1309 OPP_PIPE_CLOCK_EN, 1);
1310 /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
1311
1312 if (dc_surface) {
1313 dm_logger_write(dc->ctx->logger, LOG_DC,
1314 "Pipe:%d 0x%x: addr hi:0x%x, "
1315 "addr low:0x%x, "
1316 "src: %d, %d, %d,"
1317 " %d; dst: %d, %d, %d, %d;\n",
1318 pipe_ctx->pipe_idx,
1319 dc_surface,
1320 dc_surface->address.grph.addr.high_part,
1321 dc_surface->address.grph.addr.low_part,
1322 dc_surface->src_rect.x,
1323 dc_surface->src_rect.y,
1324 dc_surface->src_rect.width,
1325 dc_surface->src_rect.height,
1326 dc_surface->dst_rect.x,
1327 dc_surface->dst_rect.y,
1328 dc_surface->dst_rect.width,
1329 dc_surface->dst_rect.height);
1330
1331 dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
1332 "Pipe %d: width, height, x, y\n"
1333 "viewport:%d, %d, %d, %d\n"
1334 "recout: %d, %d, %d, %d\n",
1335 pipe_ctx->pipe_idx,
1336 pipe_ctx->scl_data.viewport.width,
1337 pipe_ctx->scl_data.viewport.height,
1338 pipe_ctx->scl_data.viewport.x,
1339 pipe_ctx->scl_data.viewport.y,
1340 pipe_ctx->scl_data.recout.width,
1341 pipe_ctx->scl_data.recout.height,
1342 pipe_ctx->scl_data.recout.x,
1343 pipe_ctx->scl_data.recout.y);
1344 print_rq_dlg_ttu(dc, pipe_ctx);
1345 }
1346 }
1347
1348 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1349 {
1350 struct xfm_grph_csc_adjustment adjust;
1351 memset(&adjust, 0, sizeof(adjust));
1352 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1353
1354
1355 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
1356 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1357 adjust.temperature_matrix[0] =
1358 pipe_ctx->stream->
1359 public.gamut_remap_matrix.matrix[0];
1360 adjust.temperature_matrix[1] =
1361 pipe_ctx->stream->
1362 public.gamut_remap_matrix.matrix[1];
1363 adjust.temperature_matrix[2] =
1364 pipe_ctx->stream->
1365 public.gamut_remap_matrix.matrix[2];
1366 adjust.temperature_matrix[3] =
1367 pipe_ctx->stream->
1368 public.gamut_remap_matrix.matrix[4];
1369 adjust.temperature_matrix[4] =
1370 pipe_ctx->stream->
1371 public.gamut_remap_matrix.matrix[5];
1372 adjust.temperature_matrix[5] =
1373 pipe_ctx->stream->
1374 public.gamut_remap_matrix.matrix[6];
1375 adjust.temperature_matrix[6] =
1376 pipe_ctx->stream->
1377 public.gamut_remap_matrix.matrix[8];
1378 adjust.temperature_matrix[7] =
1379 pipe_ctx->stream->
1380 public.gamut_remap_matrix.matrix[9];
1381 adjust.temperature_matrix[8] =
1382 pipe_ctx->stream->
1383 public.gamut_remap_matrix.matrix[10];
1384 }
1385
1386 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1387 }
1388
1389
1390 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1391 enum dc_color_space colorspace,
1392 uint16_t *matrix)
1393 {
1394 int i;
1395 struct out_csc_color_matrix tbl_entry;
1396
1397 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
1398 == true) {
1399 enum dc_color_space color_space =
1400 pipe_ctx->stream->public.output_color_space;
1401
1402 //uint16_t matrix[12];
1403 for (i = 0; i < 12; i++)
1404 tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i];
1405
1406 tbl_entry.color_space = color_space;
1407 //tbl_entry.regval = matrix;
1408 pipe_ctx->opp->funcs->opp_set_csc_adjustment(pipe_ctx->opp, &tbl_entry);
1409 }
1410 }
1411 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1412 {
1413 if (pipe_ctx->surface->public.visible)
1414 return true;
1415 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1416 return true;
1417 return false;
1418 }
1419
1420 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1421 {
1422 if (pipe_ctx->surface->public.visible)
1423 return true;
1424 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1425 return true;
1426 return false;
1427 }
1428
1429 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1430 {
1431 if (pipe_ctx->surface->public.visible)
1432 return true;
1433 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1434 return true;
1435 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1436 return true;
1437 return false;
1438 }
1439
1440 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1441 {
1442 switch (output_color_space) {
1443 case COLOR_SPACE_SRGB:
1444 case COLOR_SPACE_SRGB_LIMITED:
1445 case COLOR_SPACE_2020_RGB_FULLRANGE:
1446 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1447 case COLOR_SPACE_ADOBERGB:
1448 return true;
1449 case COLOR_SPACE_YCBCR601:
1450 case COLOR_SPACE_YCBCR709:
1451 case COLOR_SPACE_YCBCR601_LIMITED:
1452 case COLOR_SPACE_YCBCR709_LIMITED:
1453 case COLOR_SPACE_2020_YCBCR:
1454 return false;
1455 default:
1456 /* Add a case to switch */
1457 BREAK_TO_DEBUGGER();
1458 return false;
1459 }
1460 }
1461
1462 static void dcn10_get_surface_visual_confirm_color(
1463 const struct pipe_ctx *pipe_ctx,
1464 struct tg_color *color)
1465 {
1466 uint32_t color_value = MAX_TG_COLOR_VALUE;
1467
1468 switch (pipe_ctx->scl_data.format) {
1469 case PIXEL_FORMAT_ARGB8888:
1470 /* set boarder color to red */
1471 color->color_r_cr = color_value;
1472 break;
1473
1474 case PIXEL_FORMAT_ARGB2101010:
1475 /* set boarder color to blue */
1476 color->color_b_cb = color_value;
1477 break;
1478 case PIXEL_FORMAT_420BPP8:
1479 /* set boarder color to green */
1480 color->color_g_y = color_value;
1481 break;
1482 case PIXEL_FORMAT_420BPP10:
1483 /* set boarder color to yellow */
1484 color->color_g_y = color_value;
1485 color->color_r_cr = color_value;
1486 break;
1487 case PIXEL_FORMAT_FP16:
1488 /* set boarder color to white */
1489 color->color_r_cr = color_value;
1490 color->color_b_cb = color_value;
1491 color->color_g_y = color_value;
1492 break;
1493 default:
1494 break;
1495 }
1496 }
1497
1498 static void update_dchubp_dpp(
1499 struct core_dc *dc,
1500 struct pipe_ctx *pipe_ctx,
1501 struct validate_context *context)
1502 {
1503 struct dce_hwseq *hws = dc->hwseq;
1504 struct mem_input *mi = pipe_ctx->mi;
1505 struct input_pixel_processor *ipp = pipe_ctx->ipp;
1506 struct core_surface *surface = pipe_ctx->surface;
1507 union plane_size size = surface->public.plane_size;
1508 struct default_adjustment ocsc = {0};
1509 struct tg_color black_color = {0};
1510 struct mpcc_cfg mpcc_cfg;
1511 bool per_pixel_alpha = surface->public.per_pixel_alpha && pipe_ctx->bottom_pipe;
1512
1513 /* TODO: proper fix once fpga works */
1514 /* depends on DML calculation, DPP clock value may change dynamically */
1515 enable_dppclk(
1516 dc->hwseq,
1517 pipe_ctx->pipe_idx,
1518 pipe_ctx->pix_clk_params.requested_pix_clk,
1519 context->bw.dcn.calc_clk.dppclk_div);
1520 dc->current_context->bw.dcn.cur_clk.dppclk_div =
1521 context->bw.dcn.calc_clk.dppclk_div;
1522 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1523
1524 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1525 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1526 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1527 */
1528 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->tg->inst);
1529
1530 update_plane_addr(dc, pipe_ctx);
1531
1532 mi->funcs->mem_input_setup(
1533 mi,
1534 &pipe_ctx->dlg_regs,
1535 &pipe_ctx->ttu_regs,
1536 &pipe_ctx->rq_regs,
1537 &pipe_ctx->pipe_dlg_param);
1538
1539 size.grph.surface_size = pipe_ctx->scl_data.viewport;
1540
1541 if (dc->public.config.gpu_vm_support)
1542 mi->funcs->mem_input_program_pte_vm(
1543 pipe_ctx->mi,
1544 surface->public.format,
1545 &surface->public.tiling_info,
1546 surface->public.rotation);
1547
1548 ipp->funcs->ipp_setup(ipp,
1549 surface->public.format,
1550 1,
1551 IPP_OUTPUT_FORMAT_12_BIT_FIX);
1552
1553 pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha;
1554 mpcc_cfg.top_dpp_id = pipe_ctx->pipe_idx;
1555 if (pipe_ctx->bottom_pipe)
1556 mpcc_cfg.bot_mpcc_id = pipe_ctx->bottom_pipe->mpcc->inst;
1557 else
1558 mpcc_cfg.bot_mpcc_id = 0xf;
1559 mpcc_cfg.opp_id = pipe_ctx->tg->inst;
1560 mpcc_cfg.top_of_tree = pipe_ctx->pipe_idx == pipe_ctx->tg->inst;
1561 mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
1562 /* DCN1.0 has output CM before MPC which seems to screw with
1563 * pre-multiplied alpha.
1564 */
1565 mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
1566 pipe_ctx->stream->public.output_color_space)
1567 && per_pixel_alpha;
1568 pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg);
1569
1570 if (dc->public.debug.surface_visual_confirm) {
1571 dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color);
1572 } else {
1573 color_space_to_black_color(
1574 dc, pipe_ctx->stream->public.output_color_space,
1575 &black_color);
1576 }
1577 pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color);
1578
1579 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1580 /* scaler configuration */
1581 pipe_ctx->xfm->funcs->transform_set_scaler(
1582 pipe_ctx->xfm, &pipe_ctx->scl_data);
1583 mi->funcs->mem_program_viewport(mi,
1584 &pipe_ctx->scl_data.viewport, &pipe_ctx->scl_data.viewport_c);
1585
1586 /*gamut remap*/
1587 program_gamut_remap(pipe_ctx);
1588
1589 /*TODO add adjustments parameters*/
1590 ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
1591 pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc);
1592
1593 mi->funcs->mem_input_program_surface_config(
1594 mi,
1595 surface->public.format,
1596 &surface->public.tiling_info,
1597 &size,
1598 surface->public.rotation,
1599 &surface->public.dcc,
1600 surface->public.horizontal_mirror);
1601
1602 mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
1603 }
1604
1605 static void program_all_pipe_in_tree(
1606 struct core_dc *dc,
1607 struct pipe_ctx *pipe_ctx,
1608 struct validate_context *context)
1609 {
1610 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1611
1612 if (pipe_ctx->top_pipe == NULL) {
1613
1614 /* lock otg_master_update to process all pipes associated with
1615 * this OTG. this is done only one time.
1616 */
1617 /* watermark is for all pipes */
1618 pipe_ctx->mi->funcs->program_watermarks(
1619 pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
1620
1621 if (dc->public.debug.sanity_checks) {
1622 /* pstate stuck check after watermark update */
1623 verify_allow_pstate_change_high(dc->hwseq);
1624 }
1625
1626 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
1627
1628 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1629 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1630 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1631 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1632 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
1633
1634 pipe_ctx->tg->funcs->program_global_sync(
1635 pipe_ctx->tg);
1636 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
1637 }
1638
1639 if (pipe_ctx->surface != NULL) {
1640 dcn10_power_on_fe(dc, pipe_ctx, context);
1641 update_dchubp_dpp(dc, pipe_ctx, context);
1642 }
1643
1644 if (dc->public.debug.sanity_checks) {
1645 /* pstate stuck check after each pipe is programmed */
1646 verify_allow_pstate_change_high(dc->hwseq);
1647 }
1648
1649 if (pipe_ctx->bottom_pipe != NULL)
1650 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1651 }
1652
1653 static void dcn10_pplib_apply_display_requirements(
1654 struct core_dc *dc,
1655 struct validate_context *context)
1656 {
1657 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1658
1659 pp_display_cfg->all_displays_in_sync = false;/*todo*/
1660 pp_display_cfg->nb_pstate_switch_disable = false;
1661 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1662 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
1663 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1664 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
1665 pp_display_cfg->avail_mclk_switch_time_us =
1666 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
1667 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
1668 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
1669 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
1670 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
1671 dce110_fill_display_configs(context, pp_display_cfg);
1672
1673 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
1674 struct dm_pp_display_configuration)) != 0)
1675 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
1676
1677 dc->prev_display_config = *pp_display_cfg;
1678 }
1679
1680 static void dcn10_apply_ctx_for_surface(
1681 struct core_dc *dc,
1682 struct core_surface *surface,
1683 struct validate_context *context)
1684 {
1685 int i, be_idx;
1686
1687 if (dc->public.debug.sanity_checks)
1688 verify_allow_pstate_change_high(dc->hwseq);
1689
1690 if (!surface)
1691 return;
1692
1693 for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++)
1694 if (surface == context->res_ctx.pipe_ctx[be_idx].surface)
1695 break;
1696
1697 /* reset unused mpcc */
1698 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1699 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1700 struct pipe_ctx *old_pipe_ctx =
1701 &dc->current_context->res_ctx.pipe_ctx[i];
1702
1703 if (!pipe_ctx->surface && !old_pipe_ctx->surface)
1704 continue;
1705
1706 /*
1707 * Powergate reused pipes that are not powergated
1708 * fairly hacky right now, using opp_id as indicator
1709 */
1710
1711 if (pipe_ctx->surface && !old_pipe_ctx->surface) {
1712 if (pipe_ctx->mpcc->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) {
1713 dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
1714 /*
1715 * power down fe will unlock when calling reset, need
1716 * to lock it back here. Messy, need rework.
1717 */
1718 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
1719 }
1720 }
1721
1722
1723 if ((!pipe_ctx->surface && old_pipe_ctx->surface)
1724 || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
1725 struct mpcc_cfg mpcc_cfg;
1726 int opp_id_cached = old_pipe_ctx->mpcc->opp_id;
1727
1728 if (old_pipe_ctx->tg->inst != be_idx)
1729 continue;
1730
1731 if (!old_pipe_ctx->top_pipe) {
1732 ASSERT(0);
1733 continue;
1734 }
1735
1736 /* reset mpc */
1737 mpcc_cfg.opp_id = 0xf;
1738 mpcc_cfg.top_dpp_id = 0xf;
1739 mpcc_cfg.bot_mpcc_id = 0xf;
1740 mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
1741 old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg);
1742 old_pipe_ctx->top_pipe->opp->mpcc_disconnect_pending[old_pipe_ctx->mpcc->inst] = true;
1743
1744 if (dc->public.debug.sanity_checks)
1745 verify_allow_pstate_change_high(dc->hwseq);
1746
1747 /*
1748 * the mpcc is the only thing that keeps track of the mpcc
1749 * mapping for reset front end right now. Might need some
1750 * rework.
1751 */
1752 old_pipe_ctx->mpcc->opp_id = opp_id_cached;
1753
1754 old_pipe_ctx->top_pipe = NULL;
1755 old_pipe_ctx->bottom_pipe = NULL;
1756 old_pipe_ctx->surface = NULL;
1757
1758 dm_logger_write(dc->ctx->logger, LOG_DC,
1759 "Reset mpcc for pipe %d\n",
1760 old_pipe_ctx->pipe_idx);
1761 }
1762 }
1763
1764 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1765 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1766
1767 if (pipe_ctx->surface != surface)
1768 continue;
1769
1770 /* looking for top pipe to program */
1771 if (!pipe_ctx->top_pipe)
1772 program_all_pipe_in_tree(dc, pipe_ctx, context);
1773 }
1774
1775 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1776 "\n============== Watermark parameters ==============\n"
1777 "a.urgent_ns: %d \n"
1778 "a.cstate_enter_plus_exit: %d \n"
1779 "a.cstate_exit: %d \n"
1780 "a.pstate_change: %d \n"
1781 "a.pte_meta_urgent: %d \n"
1782 "b.urgent_ns: %d \n"
1783 "b.cstate_enter_plus_exit: %d \n"
1784 "b.cstate_exit: %d \n"
1785 "b.pstate_change: %d \n"
1786 "b.pte_meta_urgent: %d \n",
1787 context->bw.dcn.watermarks.a.urgent_ns,
1788 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
1789 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
1790 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
1791 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
1792 context->bw.dcn.watermarks.b.urgent_ns,
1793 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
1794 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
1795 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
1796 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
1797 );
1798 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1799 "\nc.urgent_ns: %d \n"
1800 "c.cstate_enter_plus_exit: %d \n"
1801 "c.cstate_exit: %d \n"
1802 "c.pstate_change: %d \n"
1803 "c.pte_meta_urgent: %d \n"
1804 "d.urgent_ns: %d \n"
1805 "d.cstate_enter_plus_exit: %d \n"
1806 "d.cstate_exit: %d \n"
1807 "d.pstate_change: %d \n"
1808 "d.pte_meta_urgent: %d \n"
1809 "========================================================\n",
1810 context->bw.dcn.watermarks.c.urgent_ns,
1811 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
1812 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
1813 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
1814 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
1815 context->bw.dcn.watermarks.d.urgent_ns,
1816 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
1817 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
1818 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
1819 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
1820 );
1821
1822 if (dc->public.debug.sanity_checks)
1823 verify_allow_pstate_change_high(dc->hwseq);
1824 }
1825
1826 static void dcn10_set_bandwidth(
1827 struct core_dc *dc,
1828 struct validate_context *context,
1829 bool decrease_allowed)
1830 {
1831 struct dm_pp_clock_for_voltage_req clock;
1832
1833 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1834 return;
1835
1836 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
1837 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
1838 dc->res_pool->display_clock->funcs->set_clock(
1839 dc->res_pool->display_clock,
1840 context->bw.dcn.calc_clk.dispclk_khz);
1841 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
1842 context->bw.dcn.calc_clk.dispclk_khz;
1843 }
1844 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
1845 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
1846 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
1847 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
1848 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1849 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1850 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
1851 }
1852 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
1853 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
1854 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
1855 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
1856 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
1857 dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
1858 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
1859 }
1860 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
1861 > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
1862 dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
1863 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
1864 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
1865 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
1866 }
1867 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
1868 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
1869 < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {
1870 dc->current_context->bw.dcn.calc_clk.dram_ccm_us =
1871 context->bw.dcn.calc_clk.dram_ccm_us;
1872 context->bw.dcn.cur_clk.dram_ccm_us =
1873 context->bw.dcn.calc_clk.dram_ccm_us;
1874 }
1875 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
1876 < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) {
1877 dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us =
1878 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
1879 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
1880 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
1881 }
1882 dcn10_pplib_apply_display_requirements(dc, context);
1883
1884 /* need to fix this function. not doing the right thing here */
1885 }
1886
1887 static void set_drr(struct pipe_ctx **pipe_ctx,
1888 int num_pipes, int vmin, int vmax)
1889 {
1890 int i = 0;
1891 struct drr_params params = {0};
1892
1893 params.vertical_total_max = vmax;
1894 params.vertical_total_min = vmin;
1895
1896 /* TODO: If multiple pipes are to be supported, you need
1897 * some GSL stuff
1898 */
1899 for (i = 0; i < num_pipes; i++) {
1900 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
1901 }
1902 }
1903
1904 static void get_position(struct pipe_ctx **pipe_ctx,
1905 int num_pipes,
1906 struct crtc_position *position)
1907 {
1908 int i = 0;
1909
1910 /* TODO: handle pipes > 1
1911 */
1912 for (i = 0; i < num_pipes; i++)
1913 pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
1914 }
1915
1916 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1917 int num_pipes, const struct dc_static_screen_events *events)
1918 {
1919 unsigned int i;
1920 unsigned int value = 0;
1921
1922 if (events->surface_update)
1923 value |= 0x80;
1924 if (events->cursor_update)
1925 value |= 0x2;
1926
1927 for (i = 0; i < num_pipes; i++)
1928 pipe_ctx[i]->tg->funcs->
1929 set_static_screen_control(pipe_ctx[i]->tg, value);
1930 }
1931
1932 static void set_plane_config(
1933 const struct core_dc *dc,
1934 struct pipe_ctx *pipe_ctx,
1935 struct resource_context *res_ctx)
1936 {
1937 /* TODO */
1938 program_gamut_remap(pipe_ctx);
1939 }
1940
1941 static void dcn10_config_stereo_parameters(
1942 struct core_stream *stream, struct crtc_stereo_flags *flags)
1943 {
1944 enum view_3d_format view_format = stream->public.view_format;
1945 enum dc_timing_3d_format timing_3d_format =\
1946 stream->public.timing.timing_3d_format;
1947 bool non_stereo_timing = false;
1948
1949 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
1950 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1951 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
1952 non_stereo_timing = true;
1953
1954 if (non_stereo_timing == false &&
1955 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
1956
1957 flags->PROGRAM_STEREO = 1;
1958 flags->PROGRAM_POLARITY = 1;
1959 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
1960 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
1961 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
1962 enum display_dongle_type dongle = \
1963 stream->sink->link->public.ddc->dongle_type;
1964 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
1965 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
1966 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
1967 flags->DISABLE_STEREO_DP_SYNC = 1;
1968 }
1969 flags->RIGHT_EYE_POLARITY =\
1970 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
1971 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1972 flags->FRAME_PACKED = 1;
1973 }
1974
1975 return;
1976 }
1977
1978 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
1979 {
1980 struct crtc_stereo_flags flags = { 0 };
1981 struct core_stream *stream = pipe_ctx->stream;
1982
1983 dcn10_config_stereo_parameters(stream, &flags);
1984
1985 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
1986 pipe_ctx->opp,
1987 flags.PROGRAM_STEREO == 1 ? true:false,
1988 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
1989
1990 pipe_ctx->tg->funcs->program_stereo(
1991 pipe_ctx->tg,
1992 &stream->public.timing,
1993 &flags);
1994
1995 return;
1996 }
1997
1998 static void dcn10_log_hw_state(struct core_dc *dc)
1999 {
2000 struct dc_context *dc_ctx = dc->ctx;
2001 struct dce_hwseq *hws = dc->hwseq;
2002
2003 DTN_INFO("%s: Hello World", __func__);
2004
2005 if (REG(MPC_CRC_RESULT_GB))
2006 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
2007 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
2008 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
2009 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
2010 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
2011 /* todo: add meaningful register reads and print out HW state
2012 *
2013 */
2014 }
2015
2016 static void dcn10_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx)
2017 {
2018 int i;
2019 for (i = 0; i < MAX_PIPES; i++) {
2020 if (!pipe_ctx->opp || !pipe_ctx->mpcc)
2021 continue;
2022
2023 if (pipe_ctx->opp->mpcc_disconnect_pending[i]) {
2024 pipe_ctx->mpcc->funcs->wait_for_idle(res_pool->mpcc[i]);
2025 pipe_ctx->opp->mpcc_disconnect_pending[i] = false;
2026 }
2027 }
2028 }
2029
2030 static bool dcn10_dummy_display_power_gating(
2031 struct core_dc *dc,
2032 uint8_t controller_id,
2033 struct dc_bios *dcb,
2034 enum pipe_gating_control power_gating)
2035 {
2036 return true;
2037 }
2038
2039 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2040 {
2041 struct core_surface *surface = pipe_ctx->surface;
2042 struct timing_generator *tg = pipe_ctx->tg;
2043
2044 if (surface->ctx->dc->debug.sanity_checks) {
2045 struct core_dc *dc = DC_TO_CORE(surface->ctx->dc);
2046
2047 verify_allow_pstate_change_high(dc->hwseq);
2048 }
2049
2050 if (surface == NULL)
2051 return;
2052
2053 surface->status.is_flip_pending =
2054 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
2055 pipe_ctx->mi);
2056
2057 /* DCN we read INUSE address in MI, do we still need this wa? */
2058 if (surface->status.is_flip_pending &&
2059 !surface->public.visible) {
2060 pipe_ctx->mi->current_address =
2061 pipe_ctx->mi->request_address;
2062 BREAK_TO_DEBUGGER();
2063 }
2064
2065 surface->status.current_address = pipe_ctx->mi->current_address;
2066 if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2067 tg->funcs->is_stereo_left_eye) {
2068 surface->status.is_right_eye =
2069 !tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
2070 }
2071 }
2072
2073 static const struct hw_sequencer_funcs dcn10_funcs = {
2074 .program_gamut_remap = program_gamut_remap,
2075 .program_csc_matrix = program_csc_matrix,
2076 .init_hw = dcn10_init_hw,
2077 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2078 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2079 .set_plane_config = set_plane_config,
2080 .update_plane_addr = update_plane_addr,
2081 .update_pending_status = dcn10_update_pending_status,
2082 .set_input_transfer_func = dcn10_set_input_transfer_func,
2083 .set_output_transfer_func = dcn10_set_output_transfer_func,
2084 .power_down = dce110_power_down,
2085 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2086 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2087 .update_info_frame = dce110_update_info_frame,
2088 .enable_stream = dce110_enable_stream,
2089 .disable_stream = dce110_disable_stream,
2090 .unblank_stream = dce110_unblank_stream,
2091 .enable_display_power_gating = dcn10_dummy_display_power_gating,
2092 .power_down_front_end = dcn10_power_down_fe,
2093 .power_on_front_end = dcn10_power_on_fe,
2094 .pipe_control_lock = dcn10_pipe_control_lock,
2095 .set_bandwidth = dcn10_set_bandwidth,
2096 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2097 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2098 .set_drr = set_drr,
2099 .get_position = get_position,
2100 .set_static_screen_control = set_static_screen_control,
2101 .setup_stereo = dcn10_setup_stereo,
2102 .set_avmute = dce110_set_avmute,
2103 .log_hw_state = dcn10_log_hw_state,
2104 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect
2105 };
2106
2107
2108 void dcn10_hw_sequencer_construct(struct core_dc *dc)
2109 {
2110 dc->hwss = dcn10_funcs;
2111 }
2112
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