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drm/amd/display: separate plane disable sequence
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_hw_sequencer.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "resource.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
33 #include "abm.h"
34 #include "dcn10/dcn10_dpp.h"
35 #include "dcn10/dcn10_mpc.h"
36 #include "mem_input.h"
37 #include "timing_generator.h"
38 #include "opp.h"
39 #include "ipp.h"
40 #include "mpc.h"
41 #include "raven1/DCN/dcn_1_0_offset.h"
42 #include "raven1/DCN/dcn_1_0_sh_mask.h"
43 #include "vega10/soc15ip.h"
44 #include "reg_helper.h"
45
46 #define CTX \
47 hws->ctx
48 #define REG(reg)\
49 hws->regs->reg
50
51 #undef FN
52 #define FN(reg_name, field_name) \
53 hws->shifts->field_name, hws->masks->field_name
54
55
56 static void verify_allow_pstate_change_high(
57 struct dce_hwseq *hws)
58 {
59 /* pstate latency is ~20us so if we wait over 40us and pstate allow
60 * still not asserted, we are probably stuck and going to hang
61 */
62 static unsigned int pstate_wait_timeout_us = 40;
63 static unsigned int max_sampled_pstate_wait_us; /* data collection */
64 static bool forced_pstate_allow; /* help with revert wa */
65
66 unsigned int debug_index = 0x7;
67 unsigned int debug_data;
68 unsigned int force_allow_pstate = 0x30;
69 unsigned int i;
70
71 if (forced_pstate_allow) {
72 /* we hacked to force pstate allow to prevent hang last time
73 * we verify_allow_pstate_change_high. so disable force
74 * here so we can check status
75 */
76 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, 0);
77 forced_pstate_allow = false;
78 }
79
80 /* description "3-0: Pipe0 cursor0 QOS
81 * 7-4: Pipe1 cursor0 QOS
82 * 11-8: Pipe2 cursor0 QOS
83 * 15-12: Pipe3 cursor0 QOS
84 * 16: Pipe0 Plane0 Allow Pstate Change
85 * 17: Pipe1 Plane0 Allow Pstate Change
86 * 18: Pipe2 Plane0 Allow Pstate Change
87 * 19: Pipe3 Plane0 Allow Pstate Change
88 * 20: Pipe0 Plane1 Allow Pstate Change
89 * 21: Pipe1 Plane1 Allow Pstate Change
90 * 22: Pipe2 Plane1 Allow Pstate Change
91 * 23: Pipe3 Plane1 Allow Pstate Change
92 * 24: Pipe0 cursor0 Allow Pstate Change
93 * 25: Pipe1 cursor0 Allow Pstate Change
94 * 26: Pipe2 cursor0 Allow Pstate Change
95 * 27: Pipe3 cursor0 Allow Pstate Change
96 * 28: WB0 Allow Pstate Change
97 * 29: WB1 Allow Pstate Change
98 * 30: Arbiter's allow_pstate_change
99 * 31: SOC pstate change request
100 */
101
102 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
103
104 for (i = 0; i < pstate_wait_timeout_us; i++) {
105 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
106
107 if (debug_data & (1 << 30))
108 return;
109
110 if (max_sampled_pstate_wait_us < i)
111 max_sampled_pstate_wait_us = i;
112
113 udelay(1);
114 }
115
116 /* force pstate allow to prevent system hang
117 * and break to debugger to investigate
118 */
119 REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
120 forced_pstate_allow = true;
121 BREAK_TO_DEBUGGER();
122 }
123
124 static void enable_dppclk(
125 struct dce_hwseq *hws,
126 uint8_t plane_id,
127 uint32_t requested_pix_clk,
128 bool dppclk_div)
129 {
130 dm_logger_write(hws->ctx->logger, LOG_SURFACE,
131 "dppclk_rate_control for pipe %d programed to %d\n",
132 plane_id,
133 dppclk_div);
134
135 if (hws->shifts->DPPCLK_RATE_CONTROL)
136 REG_UPDATE_2(DPP_CONTROL[plane_id],
137 DPPCLK_RATE_CONTROL, dppclk_div,
138 DPP_CLOCK_ENABLE, 1);
139 else
140 REG_UPDATE(DPP_CONTROL[plane_id],
141 DPP_CLOCK_ENABLE, 1);
142 }
143
144 static void enable_power_gating_plane(
145 struct dce_hwseq *hws,
146 bool enable)
147 {
148 bool force_on = 1; /* disable power gating */
149
150 if (enable)
151 force_on = 0;
152
153 /* DCHUBP0/1/2/3 */
154 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
157 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
158
159 /* DPP0/1/2/3 */
160 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
161 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
162 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
163 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
164 }
165
166 static void disable_vga(
167 struct dce_hwseq *hws)
168 {
169 REG_WRITE(D1VGA_CONTROL, 0);
170 REG_WRITE(D2VGA_CONTROL, 0);
171 REG_WRITE(D3VGA_CONTROL, 0);
172 REG_WRITE(D4VGA_CONTROL, 0);
173 }
174
175 static void dpp_pg_control(
176 struct dce_hwseq *hws,
177 unsigned int dpp_inst,
178 bool power_on)
179 {
180 uint32_t power_gate = power_on ? 0 : 1;
181 uint32_t pwr_status = power_on ? 0 : 2;
182
183 if (hws->ctx->dc->debug.disable_dpp_power_gate)
184 return;
185
186 switch (dpp_inst) {
187 case 0: /* DPP0 */
188 REG_UPDATE(DOMAIN1_PG_CONFIG,
189 DOMAIN1_POWER_GATE, power_gate);
190
191 REG_WAIT(DOMAIN1_PG_STATUS,
192 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
193 break;
194 case 1: /* DPP1 */
195 REG_UPDATE(DOMAIN3_PG_CONFIG,
196 DOMAIN3_POWER_GATE, power_gate);
197
198 REG_WAIT(DOMAIN3_PG_STATUS,
199 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
200 break;
201 case 2: /* DPP2 */
202 REG_UPDATE(DOMAIN5_PG_CONFIG,
203 DOMAIN5_POWER_GATE, power_gate);
204
205 REG_WAIT(DOMAIN5_PG_STATUS,
206 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
207 break;
208 case 3: /* DPP3 */
209 REG_UPDATE(DOMAIN7_PG_CONFIG,
210 DOMAIN7_POWER_GATE, power_gate);
211
212 REG_WAIT(DOMAIN7_PG_STATUS,
213 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
214 break;
215 default:
216 BREAK_TO_DEBUGGER();
217 break;
218 }
219 }
220
221 static uint32_t convert_and_clamp(
222 uint32_t wm_ns,
223 uint32_t refclk_mhz,
224 uint32_t clamp_value)
225 {
226 uint32_t ret_val = 0;
227 ret_val = wm_ns * refclk_mhz;
228 ret_val /= 1000;
229
230 if (ret_val > clamp_value)
231 ret_val = clamp_value;
232
233 return ret_val;
234 }
235
236 static void program_watermarks(
237 struct dce_hwseq *hws,
238 struct dcn_watermark_set *watermarks,
239 unsigned int refclk_mhz)
240 {
241 uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
242 /*
243 * Need to clamp to max of the register values (i.e. no wrap)
244 * for dcn1, all wm registers are 21-bit wide
245 */
246 uint32_t prog_wm_value;
247
248 /* Repeat for water mark set A, B, C and D. */
249 /* clock state A */
250 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
251 refclk_mhz, 0x1fffff);
252 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
253
254 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
255 "URGENCY_WATERMARK_A calculated =%d\n"
256 "HW register value = 0x%x\n",
257 watermarks->a.urgent_ns, prog_wm_value);
258
259 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
260 refclk_mhz, 0x1fffff);
261 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
262 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
263 "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
264 "HW register value = 0x%x\n",
265 watermarks->a.pte_meta_urgent_ns, prog_wm_value);
266
267
268 prog_wm_value = convert_and_clamp(
269 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
270 refclk_mhz, 0x1fffff);
271
272 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
273 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
274 "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
275 "HW register value = 0x%x\n",
276 watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
277
278
279 prog_wm_value = convert_and_clamp(
280 watermarks->a.cstate_pstate.cstate_exit_ns,
281 refclk_mhz, 0x1fffff);
282 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
283 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
284 "SR_EXIT_WATERMARK_A calculated =%d\n"
285 "HW register value = 0x%x\n",
286 watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
287
288
289 prog_wm_value = convert_and_clamp(
290 watermarks->a.cstate_pstate.pstate_change_ns,
291 refclk_mhz, 0x1fffff);
292 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
293 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
294 "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
295 "HW register value = 0x%x\n\n",
296 watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
297
298
299 /* clock state B */
300 prog_wm_value = convert_and_clamp(
301 watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
302 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
303 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
304 "URGENCY_WATERMARK_B calculated =%d\n"
305 "HW register value = 0x%x\n",
306 watermarks->b.urgent_ns, prog_wm_value);
307
308
309 prog_wm_value = convert_and_clamp(
310 watermarks->b.pte_meta_urgent_ns,
311 refclk_mhz, 0x1fffff);
312 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
313 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
314 "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
315 "HW register value = 0x%x\n",
316 watermarks->b.pte_meta_urgent_ns, prog_wm_value);
317
318
319 prog_wm_value = convert_and_clamp(
320 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
321 refclk_mhz, 0x1fffff);
322 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
323 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
324 "SR_ENTER_WATERMARK_B calculated =%d\n"
325 "HW register value = 0x%x\n",
326 watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
327
328
329 prog_wm_value = convert_and_clamp(
330 watermarks->b.cstate_pstate.cstate_exit_ns,
331 refclk_mhz, 0x1fffff);
332 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
333 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
334 "SR_EXIT_WATERMARK_B calculated =%d\n"
335 "HW register value = 0x%x\n",
336 watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
337
338 prog_wm_value = convert_and_clamp(
339 watermarks->b.cstate_pstate.pstate_change_ns,
340 refclk_mhz, 0x1fffff);
341 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
342 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
343 "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
344 "HW register value = 0x%x\n",
345 watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
346
347 /* clock state C */
348 prog_wm_value = convert_and_clamp(
349 watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
350 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
351 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
352 "URGENCY_WATERMARK_C calculated =%d\n"
353 "HW register value = 0x%x\n",
354 watermarks->c.urgent_ns, prog_wm_value);
355
356
357 prog_wm_value = convert_and_clamp(
358 watermarks->c.pte_meta_urgent_ns,
359 refclk_mhz, 0x1fffff);
360 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
361 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
362 "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
363 "HW register value = 0x%x\n",
364 watermarks->c.pte_meta_urgent_ns, prog_wm_value);
365
366
367 prog_wm_value = convert_and_clamp(
368 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
369 refclk_mhz, 0x1fffff);
370 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
371 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
372 "SR_ENTER_WATERMARK_C calculated =%d\n"
373 "HW register value = 0x%x\n",
374 watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
375
376
377 prog_wm_value = convert_and_clamp(
378 watermarks->c.cstate_pstate.cstate_exit_ns,
379 refclk_mhz, 0x1fffff);
380 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
381 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
382 "SR_EXIT_WATERMARK_C calculated =%d\n"
383 "HW register value = 0x%x\n",
384 watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
385
386
387 prog_wm_value = convert_and_clamp(
388 watermarks->c.cstate_pstate.pstate_change_ns,
389 refclk_mhz, 0x1fffff);
390 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
391 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
392 "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
393 "HW register value = 0x%x\n",
394 watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
395
396 /* clock state D */
397 prog_wm_value = convert_and_clamp(
398 watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
399 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
400 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
401 "URGENCY_WATERMARK_D calculated =%d\n"
402 "HW register value = 0x%x\n",
403 watermarks->d.urgent_ns, prog_wm_value);
404
405 prog_wm_value = convert_and_clamp(
406 watermarks->d.pte_meta_urgent_ns,
407 refclk_mhz, 0x1fffff);
408 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
409 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
410 "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
411 "HW register value = 0x%x\n",
412 watermarks->d.pte_meta_urgent_ns, prog_wm_value);
413
414
415 prog_wm_value = convert_and_clamp(
416 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
417 refclk_mhz, 0x1fffff);
418 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
419 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
420 "SR_ENTER_WATERMARK_D calculated =%d\n"
421 "HW register value = 0x%x\n",
422 watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
423
424
425 prog_wm_value = convert_and_clamp(
426 watermarks->d.cstate_pstate.cstate_exit_ns,
427 refclk_mhz, 0x1fffff);
428 REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
429 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
430 "SR_EXIT_WATERMARK_D calculated =%d\n"
431 "HW register value = 0x%x\n",
432 watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
433
434
435 prog_wm_value = convert_and_clamp(
436 watermarks->d.cstate_pstate.pstate_change_ns,
437 refclk_mhz, 0x1fffff);
438 REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
439 dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
440 "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
441 "HW register value = 0x%x\n\n",
442 watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
443
444 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
445 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
446 REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
447 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
448 REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
449 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
450 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
451 DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
452
453 REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
454 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
455 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
456
457 #if 0
458 REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
459 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
460 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
461 #endif
462 }
463
464
465 static void dcn10_update_dchub(
466 struct dce_hwseq *hws,
467 struct dchub_init_data *dh_data)
468 {
469 /* TODO: port code from dal2 */
470 switch (dh_data->fb_mode) {
471 case FRAME_BUFFER_MODE_ZFB_ONLY:
472 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
473 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
474 SDPIF_FB_TOP, 0);
475
476 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
477 SDPIF_FB_BASE, 0x0FFFF);
478
479 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
480 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
481
482 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
483 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
484
485 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
486 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
487 dh_data->zfb_size_in_byte - 1) >> 22);
488 break;
489 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
490 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
491
492 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
493 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
494
495 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
496 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
497
498 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
499 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
500 dh_data->zfb_size_in_byte - 1) >> 22);
501 break;
502 case FRAME_BUFFER_MODE_LOCAL_ONLY:
503 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
504 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
505 SDPIF_AGP_BASE, 0);
506
507 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
508 SDPIF_AGP_BOT, 0X03FFFF);
509
510 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
511 SDPIF_AGP_TOP, 0);
512 break;
513 default:
514 break;
515 }
516
517 dh_data->dchub_initialzied = true;
518 dh_data->dchub_info_valid = false;
519 }
520
521 static void hubp_pg_control(
522 struct dce_hwseq *hws,
523 unsigned int hubp_inst,
524 bool power_on)
525 {
526 uint32_t power_gate = power_on ? 0 : 1;
527 uint32_t pwr_status = power_on ? 0 : 2;
528
529 if (hws->ctx->dc->debug.disable_hubp_power_gate)
530 return;
531
532 switch (hubp_inst) {
533 case 0: /* DCHUBP0 */
534 REG_UPDATE(DOMAIN0_PG_CONFIG,
535 DOMAIN0_POWER_GATE, power_gate);
536
537 REG_WAIT(DOMAIN0_PG_STATUS,
538 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
539 break;
540 case 1: /* DCHUBP1 */
541 REG_UPDATE(DOMAIN2_PG_CONFIG,
542 DOMAIN2_POWER_GATE, power_gate);
543
544 REG_WAIT(DOMAIN2_PG_STATUS,
545 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
546 break;
547 case 2: /* DCHUBP2 */
548 REG_UPDATE(DOMAIN4_PG_CONFIG,
549 DOMAIN4_POWER_GATE, power_gate);
550
551 REG_WAIT(DOMAIN4_PG_STATUS,
552 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
553 break;
554 case 3: /* DCHUBP3 */
555 REG_UPDATE(DOMAIN6_PG_CONFIG,
556 DOMAIN6_POWER_GATE, power_gate);
557
558 REG_WAIT(DOMAIN6_PG_STATUS,
559 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);
560 break;
561 default:
562 BREAK_TO_DEBUGGER();
563 break;
564 }
565 }
566
567 static void power_on_plane(
568 struct dce_hwseq *hws,
569 int plane_id)
570 {
571 REG_SET(DC_IP_REQUEST_CNTL, 0,
572 IP_REQUEST_EN, 1);
573 dpp_pg_control(hws, plane_id, true);
574 hubp_pg_control(hws, plane_id, true);
575 REG_SET(DC_IP_REQUEST_CNTL, 0,
576 IP_REQUEST_EN, 0);
577 dm_logger_write(hws->ctx->logger, LOG_DC,
578 "Un-gated front end for pipe %d\n", plane_id);
579 }
580
581 static void bios_golden_init(struct core_dc *dc)
582 {
583 struct dc_bios *bp = dc->ctx->dc_bios;
584 int i;
585
586 /* initialize dcn global */
587 bp->funcs->enable_disp_power_gating(bp,
588 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
589
590 for (i = 0; i < dc->res_pool->pipe_count; i++) {
591 /* initialize dcn per pipe */
592 bp->funcs->enable_disp_power_gating(bp,
593 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
594 }
595 }
596
597 static void dcn10_init_hw(struct core_dc *dc)
598 {
599 int i;
600 struct abm *abm = dc->res_pool->abm;
601 struct dce_hwseq *hws = dc->hwseq;
602
603 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
604 REG_WRITE(REFCLK_CNTL, 0);
605 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
606 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
607
608 if (!dc->public.debug.disable_clock_gate) {
609 /* enable all DCN clock gating */
610 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
611
612 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
613
614 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
615 }
616
617 enable_power_gating_plane(dc->hwseq, true);
618 return;
619 }
620 /* end of FPGA. Below if real ASIC */
621
622 bios_golden_init(dc);
623
624 disable_vga(dc->hwseq);
625
626 for (i = 0; i < dc->link_count; i++) {
627 /* Power up AND update implementation according to the
628 * required signal (which may be different from the
629 * default signal on connector).
630 */
631 struct dc_link *link = dc->links[i];
632
633 link->link_enc->funcs->hw_init(link->link_enc);
634 }
635
636 for (i = 0; i < dc->res_pool->pipe_count; i++) {
637 struct transform *xfm = dc->res_pool->transforms[i];
638 struct timing_generator *tg = dc->res_pool->timing_generators[i];
639 struct mpcc *mpcc = dc->res_pool->mpcc[i];
640 struct mpcc_cfg mpcc_cfg;
641
642 xfm->funcs->transform_reset(xfm);
643 mpcc_cfg.opp_id = 0xf;
644 mpcc_cfg.top_dpp_id = 0xf;
645 mpcc_cfg.bot_mpcc_id = 0xf;
646 mpcc_cfg.top_of_tree = true;
647 mpcc->funcs->set(mpcc, &mpcc_cfg);
648
649 /* Blank controller using driver code instead of
650 * command table.
651 */
652 tg->funcs->set_blank(tg, true);
653 hwss_wait_for_blank_complete(tg);
654 }
655
656 for (i = 0; i < dc->res_pool->audio_count; i++) {
657 struct audio *audio = dc->res_pool->audios[i];
658
659 audio->funcs->hw_init(audio);
660 }
661
662 if (abm != NULL) {
663 abm->funcs->init_backlight(abm);
664 abm->funcs->abm_init(abm);
665 }
666
667 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
668 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
669
670 if (!dc->public.debug.disable_clock_gate) {
671 /* enable all DCN clock gating */
672 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
673
674 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
675
676 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
677 }
678
679 enable_power_gating_plane(dc->hwseq, true);
680 }
681
682 static enum dc_status dcn10_prog_pixclk_crtc_otg(
683 struct pipe_ctx *pipe_ctx,
684 struct validate_context *context,
685 struct core_dc *dc)
686 {
687 struct core_stream *stream = pipe_ctx->stream;
688 enum dc_color_space color_space;
689 struct tg_color black_color = {0};
690 bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
691 false:true;
692 bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
693
694
695 /* by upper caller loop, pipe0 is parent pipe and be called first.
696 * back end is set up by for pipe0. Other children pipe share back end
697 * with pipe 0. No program is needed.
698 */
699 if (pipe_ctx->top_pipe != NULL)
700 return DC_OK;
701
702 /* TODO check if timing_changed, disable stream if timing changed */
703
704 /* HW program guide assume display already disable
705 * by unplug sequence. OTG assume stop.
706 */
707 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true);
708
709 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
710 pipe_ctx->clock_source,
711 &pipe_ctx->pix_clk_params,
712 &pipe_ctx->pll_settings)) {
713 BREAK_TO_DEBUGGER();
714 return DC_ERROR_UNEXPECTED;
715 }
716 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
717 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
718 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
719 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
720
721 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
722
723 pipe_ctx->tg->funcs->program_timing(
724 pipe_ctx->tg,
725 &stream->public.timing,
726 true);
727
728 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
729 pipe_ctx->opp,
730 enableStereo,
731 rightEyePolarity);
732
733 #if 0 /* move to after enable_crtc */
734 /* TODO: OPP FMT, ABM. etc. should be done here. */
735 /* or FPGA now. instance 0 only. TODO: move to opp.c */
736
737 inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
738
739 pipe_ctx->opp->funcs->opp_program_fmt(
740 pipe_ctx->opp,
741 &stream->bit_depth_params,
742 &stream->clamping);
743 #endif
744 /* program otg blank color */
745 color_space = stream->public.output_color_space;
746 color_space_to_black_color(dc, color_space, &black_color);
747 pipe_ctx->tg->funcs->set_blank_color(
748 pipe_ctx->tg,
749 &black_color);
750
751 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
752 hwss_wait_for_blank_complete(pipe_ctx->tg);
753
754 /* VTG is within DCHUB command block. DCFCLK is always on */
755 if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
756 BREAK_TO_DEBUGGER();
757 return DC_ERROR_UNEXPECTED;
758 }
759
760 /* TODO program crtc source select for non-virtual signal*/
761 /* TODO program FMT */
762 /* TODO setup link_enc */
763 /* TODO set stream attributes */
764 /* TODO program audio */
765 /* TODO enable stream if timing changed */
766 /* TODO unblank stream if DP */
767
768 return DC_OK;
769 }
770
771 static void reset_back_end_for_pipe(
772 struct core_dc *dc,
773 struct pipe_ctx *pipe_ctx,
774 struct validate_context *context)
775 {
776 int i;
777
778 if (pipe_ctx->stream_enc == NULL) {
779 pipe_ctx->stream = NULL;
780 return;
781 }
782
783 /* TODOFPGA break core_link_disable_stream into 2 functions:
784 * disable_stream and disable_link. disable_link will disable PHYPLL
785 * which is used by otg. Move disable_link after disable_crtc
786 */
787 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
788 core_link_disable_stream(pipe_ctx);
789
790 /* by upper caller loop, parent pipe: pipe0, will be reset last.
791 * back end share by all pipes and will be disable only when disable
792 * parent pipe.
793 */
794 if (pipe_ctx->top_pipe == NULL) {
795 pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
796
797 pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false);
798 }
799
800 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
801 resource_unreference_clock_source(
802 &context->res_ctx, dc->res_pool,
803 &pipe_ctx->clock_source);
804
805 for (i = 0; i < dc->res_pool->pipe_count; i++)
806 if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx)
807 break;
808
809 if (i == dc->res_pool->pipe_count)
810 return;
811
812 pipe_ctx->stream = NULL;
813 dm_logger_write(dc->ctx->logger, LOG_DC,
814 "Reset back end for pipe %d, tg:%d\n",
815 pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
816 }
817
818 /* trigger HW to start disconnect plane from stream on the next vsync */
819 static void plane_atomic_disconnect(struct core_dc *dc,
820 int fe_idx)
821 {
822 struct mpcc_cfg mpcc_cfg;
823 struct mem_input *mi = dc->res_pool->mis[fe_idx];
824 struct transform *xfm = dc->res_pool->transforms[fe_idx];
825 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
826 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
827 unsigned int opp_id = mpcc->opp_id;
828 int opp_id_cached = mpcc->opp_id;
829
830 /*Already reset*/
831 if (opp_id == 0xf)
832 return;
833
834 mi->funcs->dcc_control(mi, false, false);
835
836 mpcc_cfg.opp_id = 0xf;
837 mpcc_cfg.top_dpp_id = 0xf;
838 mpcc_cfg.bot_mpcc_id = 0xf;
839 mpcc_cfg.top_of_tree = tg->inst == mpcc->inst;
840 mpcc->funcs->set(mpcc, &mpcc_cfg);
841
842 /* Hack to preserve old opp_id for plane_atomic_disable
843 * to find the correct otg */
844 mpcc->opp_id = opp_id_cached;
845
846 /* todo:call remove pipe from tree */
847 /* flag mpcc idle pending */
848
849 xfm->funcs->transform_reset(xfm);
850 }
851
852 /* disable HW used by plane.
853 * note: cannot disable until disconnect is complete */
854 static void plane_atomic_disable(struct core_dc *dc,
855 int fe_idx)
856 {
857 struct dce_hwseq *hws = dc->hwseq;
858 struct mem_input *mi = dc->res_pool->mis[fe_idx];
859 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
860 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
861 unsigned int opp_id = mpcc->opp_id;
862
863 if (opp_id == 0xf)
864 return;
865
866 mpcc->funcs->wait_for_idle(mpcc);
867
868 mi->funcs->set_blank(mi, true);
869
870 if (dc->public.debug.sanity_checks)
871 verify_allow_pstate_change_high(dc->hwseq);
872
873 REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
874 HUBP_CLOCK_ENABLE, 0);
875 REG_UPDATE(DPP_CONTROL[fe_idx],
876 DPP_CLOCK_ENABLE, 0);
877
878 if (tg->inst == mpcc->inst)
879 REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
880 OPP_PIPE_CLOCK_EN, 0);
881
882 mpcc->opp_id = 0xf;
883
884 if (dc->public.debug.sanity_checks)
885 verify_allow_pstate_change_high(dc->hwseq);
886 }
887
888 /* kill power to plane hw
889 * note: cannot power down until plane is disable
890 static void plane_atomic_power_down()
891 {
892
893 }
894 */
895
896 static void reset_front_end(
897 struct core_dc *dc,
898 int fe_idx)
899 {
900 struct dce_hwseq *hws = dc->hwseq;
901 struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
902 struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
903 unsigned int opp_id = mpcc->opp_id;
904
905 /*Already reset*/
906 if (opp_id == 0xf)
907 return;
908
909 tg->funcs->lock(tg);
910
911 plane_atomic_disconnect(dc, fe_idx);
912
913 REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
914 tg->funcs->unlock(tg);
915
916 if (dc->public.debug.sanity_checks)
917 verify_allow_pstate_change_high(dc->hwseq);
918
919 if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
920 REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
921 VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
922
923 plane_atomic_disable(dc, fe_idx);
924
925 dm_logger_write(dc->ctx->logger, LOG_DC,
926 "Reset front end %d\n",
927 fe_idx);
928 }
929
930 static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx)
931 {
932 struct dce_hwseq *hws = dc->hwseq;
933
934 reset_front_end(dc, fe_idx);
935
936 REG_SET(DC_IP_REQUEST_CNTL, 0,
937 IP_REQUEST_EN, 1);
938 dpp_pg_control(hws, fe_idx, false);
939 hubp_pg_control(hws, fe_idx, false);
940 REG_SET(DC_IP_REQUEST_CNTL, 0,
941 IP_REQUEST_EN, 0);
942 dm_logger_write(dc->ctx->logger, LOG_DC,
943 "Power gated front end %d\n", fe_idx);
944
945 if (dc->public.debug.sanity_checks)
946 verify_allow_pstate_change_high(dc->hwseq);
947 }
948
949 static void reset_hw_ctx_wrap(
950 struct core_dc *dc,
951 struct validate_context *context)
952 {
953 int i;
954
955 /* Reset Front End*/
956 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
957 struct pipe_ctx *pipe_ctx_old =
958 &dc->current_context->res_ctx.pipe_ctx[i];
959 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
960
961 /*if (!pipe_ctx_old->stream)
962 continue;*/
963
964 if (!pipe_ctx->stream || !pipe_ctx->surface)
965 dcn10_power_down_fe(dc, i);
966 else if (pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
967 reset_front_end(dc, i);
968 }
969 /* Reset Back End*/
970 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
971 struct pipe_ctx *pipe_ctx_old =
972 &dc->current_context->res_ctx.pipe_ctx[i];
973 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
974
975 if (!pipe_ctx_old->stream)
976 continue;
977
978 if (!pipe_ctx->stream ||
979 pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
980 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context);
981 }
982 }
983
984 static bool patch_address_for_sbs_tb_stereo(
985 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
986 {
987 struct dc_surface *surface = pipe_ctx->surface;
988 bool sec_split = pipe_ctx->top_pipe &&
989 pipe_ctx->top_pipe->surface == pipe_ctx->surface;
990 if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
991 (pipe_ctx->stream->public.timing.timing_3d_format ==
992 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
993 pipe_ctx->stream->public.timing.timing_3d_format ==
994 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
995 *addr = surface->address.grph_stereo.left_addr;
996 surface->address.grph_stereo.left_addr =
997 surface->address.grph_stereo.right_addr;
998 return true;
999 } else {
1000 if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE &&
1001 surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1002 surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1003 surface->address.grph_stereo.right_addr =
1004 surface->address.grph_stereo.left_addr;
1005 }
1006 }
1007 return false;
1008 }
1009
1010 static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
1011 {
1012 bool addr_patched = false;
1013 PHYSICAL_ADDRESS_LOC addr;
1014 struct dc_surface *surface = pipe_ctx->surface;
1015
1016 if (surface == NULL)
1017 return;
1018 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1019 pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
1020 pipe_ctx->mi,
1021 &surface->address,
1022 surface->flip_immediate);
1023 surface->status.requested_address = surface->address;
1024 if (addr_patched)
1025 pipe_ctx->surface->address.grph_stereo.left_addr = addr;
1026 }
1027
1028 static bool dcn10_set_input_transfer_func(
1029 struct pipe_ctx *pipe_ctx, const struct dc_surface *surface)
1030 {
1031 struct input_pixel_processor *ipp = pipe_ctx->ipp;
1032 const struct dc_transfer_func *tf = NULL;
1033 bool result = true;
1034
1035 if (ipp == NULL)
1036 return false;
1037
1038 if (surface->in_transfer_func)
1039 tf = surface->in_transfer_func;
1040
1041 if (surface->gamma_correction && dce_use_lut(surface))
1042 ipp->funcs->ipp_program_input_lut(ipp,
1043 surface->gamma_correction);
1044
1045 if (tf == NULL)
1046 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
1047 else if (tf->type == TF_TYPE_PREDEFINED) {
1048 switch (tf->tf) {
1049 case TRANSFER_FUNCTION_SRGB:
1050 ipp->funcs->ipp_set_degamma(ipp,
1051 IPP_DEGAMMA_MODE_HW_sRGB);
1052 break;
1053 case TRANSFER_FUNCTION_BT709:
1054 ipp->funcs->ipp_set_degamma(ipp,
1055 IPP_DEGAMMA_MODE_HW_xvYCC);
1056 break;
1057 case TRANSFER_FUNCTION_LINEAR:
1058 ipp->funcs->ipp_set_degamma(ipp,
1059 IPP_DEGAMMA_MODE_BYPASS);
1060 break;
1061 case TRANSFER_FUNCTION_PQ:
1062 result = false;
1063 break;
1064 default:
1065 result = false;
1066 break;
1067 }
1068 } else if (tf->type == TF_TYPE_BYPASS) {
1069 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
1070 } else {
1071 /*TF_TYPE_DISTRIBUTED_POINTS*/
1072 result = false;
1073 }
1074
1075 return result;
1076 }
1077 /*modify the method to handle rgb for arr_points*/
1078 static bool convert_to_custom_float(
1079 struct pwl_result_data *rgb_resulted,
1080 struct curve_points *arr_points,
1081 uint32_t hw_points_num)
1082 {
1083 struct custom_float_format fmt;
1084
1085 struct pwl_result_data *rgb = rgb_resulted;
1086
1087 uint32_t i = 0;
1088
1089 fmt.exponenta_bits = 6;
1090 fmt.mantissa_bits = 12;
1091 fmt.sign = false;
1092
1093 if (!convert_to_custom_float_format(
1094 arr_points[0].x,
1095 &fmt,
1096 &arr_points[0].custom_float_x)) {
1097 BREAK_TO_DEBUGGER();
1098 return false;
1099 }
1100
1101 if (!convert_to_custom_float_format(
1102 arr_points[0].offset,
1103 &fmt,
1104 &arr_points[0].custom_float_offset)) {
1105 BREAK_TO_DEBUGGER();
1106 return false;
1107 }
1108
1109 if (!convert_to_custom_float_format(
1110 arr_points[0].slope,
1111 &fmt,
1112 &arr_points[0].custom_float_slope)) {
1113 BREAK_TO_DEBUGGER();
1114 return false;
1115 }
1116
1117 fmt.mantissa_bits = 10;
1118 fmt.sign = false;
1119
1120 if (!convert_to_custom_float_format(
1121 arr_points[1].x,
1122 &fmt,
1123 &arr_points[1].custom_float_x)) {
1124 BREAK_TO_DEBUGGER();
1125 return false;
1126 }
1127
1128 if (!convert_to_custom_float_format(
1129 arr_points[1].y,
1130 &fmt,
1131 &arr_points[1].custom_float_y)) {
1132 BREAK_TO_DEBUGGER();
1133 return false;
1134 }
1135
1136 if (!convert_to_custom_float_format(
1137 arr_points[1].slope,
1138 &fmt,
1139 &arr_points[1].custom_float_slope)) {
1140 BREAK_TO_DEBUGGER();
1141 return false;
1142 }
1143
1144 fmt.mantissa_bits = 12;
1145 fmt.sign = true;
1146
1147 while (i != hw_points_num) {
1148 if (!convert_to_custom_float_format(
1149 rgb->red,
1150 &fmt,
1151 &rgb->red_reg)) {
1152 BREAK_TO_DEBUGGER();
1153 return false;
1154 }
1155
1156 if (!convert_to_custom_float_format(
1157 rgb->green,
1158 &fmt,
1159 &rgb->green_reg)) {
1160 BREAK_TO_DEBUGGER();
1161 return false;
1162 }
1163
1164 if (!convert_to_custom_float_format(
1165 rgb->blue,
1166 &fmt,
1167 &rgb->blue_reg)) {
1168 BREAK_TO_DEBUGGER();
1169 return false;
1170 }
1171
1172 if (!convert_to_custom_float_format(
1173 rgb->delta_red,
1174 &fmt,
1175 &rgb->delta_red_reg)) {
1176 BREAK_TO_DEBUGGER();
1177 return false;
1178 }
1179
1180 if (!convert_to_custom_float_format(
1181 rgb->delta_green,
1182 &fmt,
1183 &rgb->delta_green_reg)) {
1184 BREAK_TO_DEBUGGER();
1185 return false;
1186 }
1187
1188 if (!convert_to_custom_float_format(
1189 rgb->delta_blue,
1190 &fmt,
1191 &rgb->delta_blue_reg)) {
1192 BREAK_TO_DEBUGGER();
1193 return false;
1194 }
1195
1196 ++rgb;
1197 ++i;
1198 }
1199
1200 return true;
1201 }
1202 #define MAX_REGIONS_NUMBER 34
1203 #define MAX_LOW_POINT 25
1204 #define NUMBER_SEGMENTS 32
1205
1206 static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
1207 *output_tf, struct pwl_params *regamma_params)
1208 {
1209 struct curve_points *arr_points;
1210 struct pwl_result_data *rgb_resulted;
1211 struct pwl_result_data *rgb;
1212 struct pwl_result_data *rgb_plus_1;
1213 struct fixed31_32 y_r;
1214 struct fixed31_32 y_g;
1215 struct fixed31_32 y_b;
1216 struct fixed31_32 y1_min;
1217 struct fixed31_32 y3_max;
1218
1219 int32_t segment_start, segment_end;
1220 int32_t i;
1221 uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
1222
1223 if (output_tf == NULL || regamma_params == NULL ||
1224 output_tf->type == TF_TYPE_BYPASS)
1225 return false;
1226
1227 arr_points = regamma_params->arr_points;
1228 rgb_resulted = regamma_params->rgb_resulted;
1229 hw_points = 0;
1230
1231 memset(regamma_params, 0, sizeof(struct pwl_params));
1232 memset(seg_distr, 0, sizeof(seg_distr));
1233
1234 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1235 /* 32 segments
1236 * segments are from 2^-25 to 2^7
1237 */
1238 for (i = 0; i < 32 ; i++)
1239 seg_distr[i] = 3;
1240
1241 segment_start = -25;
1242 segment_end = 7;
1243 } else {
1244 /* 10 segments
1245 * segment is from 2^-10 to 2^0
1246 * There are less than 256 points, for optimization
1247 */
1248 seg_distr[0] = 3;
1249 seg_distr[1] = 4;
1250 seg_distr[2] = 4;
1251 seg_distr[3] = 4;
1252 seg_distr[4] = 4;
1253 seg_distr[5] = 4;
1254 seg_distr[6] = 4;
1255 seg_distr[7] = 4;
1256 seg_distr[8] = 5;
1257 seg_distr[9] = 5;
1258
1259 segment_start = -10;
1260 segment_end = 0;
1261 }
1262
1263 for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
1264 seg_distr[i] = -1;
1265
1266 for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
1267 if (seg_distr[k] != -1)
1268 hw_points += (1 << seg_distr[k]);
1269 }
1270
1271 j = 0;
1272 for (k = 0; k < (segment_end - segment_start); k++) {
1273 increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
1274 start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1275 for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
1276 if (j == hw_points - 1)
1277 break;
1278 rgb_resulted[j].red = output_tf->tf_pts.red[i];
1279 rgb_resulted[j].green = output_tf->tf_pts.green[i];
1280 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
1281 j++;
1282 }
1283 }
1284
1285 /* last point */
1286 start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
1287 rgb_resulted[hw_points - 1].red =
1288 output_tf->tf_pts.red[start_index];
1289 rgb_resulted[hw_points - 1].green =
1290 output_tf->tf_pts.green[start_index];
1291 rgb_resulted[hw_points - 1].blue =
1292 output_tf->tf_pts.blue[start_index];
1293
1294 arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1295 dal_fixed31_32_from_int(segment_start));
1296 arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1297 dal_fixed31_32_from_int(segment_end));
1298 arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
1299 dal_fixed31_32_from_int(segment_end));
1300
1301 y_r = rgb_resulted[0].red;
1302 y_g = rgb_resulted[0].green;
1303 y_b = rgb_resulted[0].blue;
1304
1305 y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
1306
1307 arr_points[0].y = y1_min;
1308 arr_points[0].slope = dal_fixed31_32_div(
1309 arr_points[0].y,
1310 arr_points[0].x);
1311 y_r = rgb_resulted[hw_points - 1].red;
1312 y_g = rgb_resulted[hw_points - 1].green;
1313 y_b = rgb_resulted[hw_points - 1].blue;
1314
1315 /* see comment above, m_arrPoints[1].y should be the Y value for the
1316 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
1317 */
1318 y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
1319
1320 arr_points[1].y = y3_max;
1321 arr_points[2].y = y3_max;
1322
1323 arr_points[1].slope = dal_fixed31_32_zero;
1324 arr_points[2].slope = dal_fixed31_32_zero;
1325
1326 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
1327 /* for PQ, we want to have a straight line from last HW X point,
1328 * and the slope to be such that we hit 1.0 at 10000 nits.
1329 */
1330 const struct fixed31_32 end_value =
1331 dal_fixed31_32_from_int(125);
1332
1333 arr_points[1].slope = dal_fixed31_32_div(
1334 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1335 dal_fixed31_32_sub(end_value, arr_points[1].x));
1336 arr_points[2].slope = dal_fixed31_32_div(
1337 dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
1338 dal_fixed31_32_sub(end_value, arr_points[1].x));
1339 }
1340
1341 regamma_params->hw_points_num = hw_points;
1342
1343 i = 1;
1344 for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
1345 if (seg_distr[k] != -1) {
1346 regamma_params->arr_curve_points[k].segments_num =
1347 seg_distr[k];
1348 regamma_params->arr_curve_points[i].offset =
1349 regamma_params->arr_curve_points[k].
1350 offset + (1 << seg_distr[k]);
1351 }
1352 i++;
1353 }
1354
1355 if (seg_distr[k] != -1)
1356 regamma_params->arr_curve_points[k].segments_num =
1357 seg_distr[k];
1358
1359 rgb = rgb_resulted;
1360 rgb_plus_1 = rgb_resulted + 1;
1361
1362 i = 1;
1363
1364 while (i != hw_points + 1) {
1365 if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
1366 rgb_plus_1->red = rgb->red;
1367 if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
1368 rgb_plus_1->green = rgb->green;
1369 if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
1370 rgb_plus_1->blue = rgb->blue;
1371
1372 rgb->delta_red = dal_fixed31_32_sub(
1373 rgb_plus_1->red,
1374 rgb->red);
1375 rgb->delta_green = dal_fixed31_32_sub(
1376 rgb_plus_1->green,
1377 rgb->green);
1378 rgb->delta_blue = dal_fixed31_32_sub(
1379 rgb_plus_1->blue,
1380 rgb->blue);
1381
1382 ++rgb_plus_1;
1383 ++rgb;
1384 ++i;
1385 }
1386
1387 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
1388
1389 return true;
1390 }
1391
1392 static bool dcn10_set_output_transfer_func(
1393 struct pipe_ctx *pipe_ctx,
1394 const struct core_stream *stream)
1395 {
1396 struct transform *xfm = pipe_ctx->xfm;
1397
1398 if (xfm == NULL)
1399 return false;
1400
1401 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1402
1403 if (stream->public.out_transfer_func &&
1404 stream->public.out_transfer_func->type ==
1405 TF_TYPE_PREDEFINED &&
1406 stream->public.out_transfer_func->tf ==
1407 TRANSFER_FUNCTION_SRGB) {
1408 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
1409 } else if (dcn10_translate_regamma_to_hw_format(
1410 stream->public.out_transfer_func, &xfm->regamma_params)) {
1411 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
1412 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
1413 } else {
1414 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
1415 }
1416
1417 return true;
1418 }
1419
1420 static void dcn10_pipe_control_lock(
1421 struct core_dc *dc,
1422 struct pipe_ctx *pipe,
1423 bool lock)
1424 {
1425 /* use TG master update lock to lock everything on the TG
1426 * therefore only top pipe need to lock
1427 */
1428 if (pipe->top_pipe)
1429 return;
1430
1431 if (dc->public.debug.sanity_checks)
1432 verify_allow_pstate_change_high(dc->hwseq);
1433
1434 if (lock)
1435 pipe->tg->funcs->lock(pipe->tg);
1436 else
1437 pipe->tg->funcs->unlock(pipe->tg);
1438
1439 if (dc->public.debug.sanity_checks)
1440 verify_allow_pstate_change_high(dc->hwseq);
1441 }
1442
1443 static bool wait_for_reset_trigger_to_occur(
1444 struct dc_context *dc_ctx,
1445 struct timing_generator *tg)
1446 {
1447 bool rc = false;
1448
1449 /* To avoid endless loop we wait at most
1450 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1451 const uint32_t frames_to_wait_on_triggered_reset = 10;
1452 int i;
1453
1454 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1455
1456 if (!tg->funcs->is_counter_moving(tg)) {
1457 DC_ERROR("TG counter is not moving!\n");
1458 break;
1459 }
1460
1461 if (tg->funcs->did_triggered_reset_occur(tg)) {
1462 rc = true;
1463 /* usually occurs at i=1 */
1464 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1465 i);
1466 break;
1467 }
1468
1469 /* Wait for one frame. */
1470 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1471 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1472 }
1473
1474 if (false == rc)
1475 DC_ERROR("GSL: Timeout on reset trigger!\n");
1476
1477 return rc;
1478 }
1479
1480 static void dcn10_enable_timing_synchronization(
1481 struct core_dc *dc,
1482 int group_index,
1483 int group_size,
1484 struct pipe_ctx *grouped_pipes[])
1485 {
1486 struct dc_context *dc_ctx = dc->ctx;
1487 int i;
1488
1489 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1490
1491 for (i = 1; i < group_size; i++)
1492 grouped_pipes[i]->tg->funcs->enable_reset_trigger(
1493 grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst);
1494
1495
1496 DC_SYNC_INFO("Waiting for trigger\n");
1497
1498 /* Need to get only check 1 pipe for having reset as all the others are
1499 * synchronized. Look at last pipe programmed to reset.
1500 */
1501 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg);
1502 for (i = 1; i < group_size; i++)
1503 grouped_pipes[i]->tg->funcs->disable_reset_trigger(
1504 grouped_pipes[i]->tg);
1505
1506 DC_SYNC_INFO("Sync complete\n");
1507 }
1508
1509 static void print_rq_dlg_ttu(
1510 struct core_dc *core_dc,
1511 struct pipe_ctx *pipe_ctx)
1512 {
1513 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1514 "\n============== DML TTU Output parameters [%d] ==============\n"
1515 "qos_level_low_wm: %d, \n"
1516 "qos_level_high_wm: %d, \n"
1517 "min_ttu_vblank: %d, \n"
1518 "qos_level_flip: %d, \n"
1519 "refcyc_per_req_delivery_l: %d, \n"
1520 "qos_level_fixed_l: %d, \n"
1521 "qos_ramp_disable_l: %d, \n"
1522 "refcyc_per_req_delivery_pre_l: %d, \n"
1523 "refcyc_per_req_delivery_c: %d, \n"
1524 "qos_level_fixed_c: %d, \n"
1525 "qos_ramp_disable_c: %d, \n"
1526 "refcyc_per_req_delivery_pre_c: %d\n"
1527 "=============================================================\n",
1528 pipe_ctx->pipe_idx,
1529 pipe_ctx->ttu_regs.qos_level_low_wm,
1530 pipe_ctx->ttu_regs.qos_level_high_wm,
1531 pipe_ctx->ttu_regs.min_ttu_vblank,
1532 pipe_ctx->ttu_regs.qos_level_flip,
1533 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1534 pipe_ctx->ttu_regs.qos_level_fixed_l,
1535 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1536 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1537 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1538 pipe_ctx->ttu_regs.qos_level_fixed_c,
1539 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1540 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1541 );
1542
1543 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1544 "\n============== DML DLG Output parameters [%d] ==============\n"
1545 "refcyc_h_blank_end: %d, \n"
1546 "dlg_vblank_end: %d, \n"
1547 "min_dst_y_next_start: %d, \n"
1548 "refcyc_per_htotal: %d, \n"
1549 "refcyc_x_after_scaler: %d, \n"
1550 "dst_y_after_scaler: %d, \n"
1551 "dst_y_prefetch: %d, \n"
1552 "dst_y_per_vm_vblank: %d, \n"
1553 "dst_y_per_row_vblank: %d, \n"
1554 "ref_freq_to_pix_freq: %d, \n"
1555 "vratio_prefetch: %d, \n"
1556 "refcyc_per_pte_group_vblank_l: %d, \n"
1557 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1558 "dst_y_per_pte_row_nom_l: %d, \n"
1559 "refcyc_per_pte_group_nom_l: %d, \n",
1560 pipe_ctx->pipe_idx,
1561 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1562 pipe_ctx->dlg_regs.dlg_vblank_end,
1563 pipe_ctx->dlg_regs.min_dst_y_next_start,
1564 pipe_ctx->dlg_regs.refcyc_per_htotal,
1565 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1566 pipe_ctx->dlg_regs.dst_y_after_scaler,
1567 pipe_ctx->dlg_regs.dst_y_prefetch,
1568 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1569 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1570 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1571 pipe_ctx->dlg_regs.vratio_prefetch,
1572 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1573 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1574 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1575 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1576 );
1577
1578 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1579 "\ndst_y_per_meta_row_nom_l: %d, \n"
1580 "refcyc_per_meta_chunk_nom_l: %d, \n"
1581 "refcyc_per_line_delivery_pre_l: %d, \n"
1582 "refcyc_per_line_delivery_l: %d, \n"
1583 "vratio_prefetch_c: %d, \n"
1584 "refcyc_per_pte_group_vblank_c: %d, \n"
1585 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1586 "dst_y_per_pte_row_nom_c: %d, \n"
1587 "refcyc_per_pte_group_nom_c: %d, \n"
1588 "dst_y_per_meta_row_nom_c: %d, \n"
1589 "refcyc_per_meta_chunk_nom_c: %d, \n"
1590 "refcyc_per_line_delivery_pre_c: %d, \n"
1591 "refcyc_per_line_delivery_c: %d \n"
1592 "========================================================\n",
1593 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1594 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1595 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1596 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1597 pipe_ctx->dlg_regs.vratio_prefetch_c,
1598 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1599 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1600 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1601 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1602 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1603 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1604 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1605 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1606 );
1607
1608 dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
1609 "\n============== DML RQ Output parameters [%d] ==============\n"
1610 "chunk_size: %d \n"
1611 "min_chunk_size: %d \n"
1612 "meta_chunk_size: %d \n"
1613 "min_meta_chunk_size: %d \n"
1614 "dpte_group_size: %d \n"
1615 "mpte_group_size: %d \n"
1616 "swath_height: %d \n"
1617 "pte_row_height_linear: %d \n"
1618 "========================================================\n",
1619 pipe_ctx->pipe_idx,
1620 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1621 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1622 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1623 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1624 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1625 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1626 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1627 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1628 );
1629 }
1630
1631 static void dcn10_power_on_fe(
1632 struct core_dc *dc,
1633 struct pipe_ctx *pipe_ctx,
1634 struct validate_context *context)
1635 {
1636 struct dc_surface *dc_surface = pipe_ctx->surface;
1637 struct dce_hwseq *hws = dc->hwseq;
1638
1639 power_on_plane(dc->hwseq,
1640 pipe_ctx->pipe_idx);
1641
1642 /* enable DCFCLK current DCHUB */
1643 REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
1644 HUBP_CLOCK_ENABLE, 1);
1645
1646 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1647 REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
1648 OPP_PIPE_CLOCK_EN, 1);
1649 /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
1650
1651 if (dc_surface) {
1652 dm_logger_write(dc->ctx->logger, LOG_DC,
1653 "Pipe:%d 0x%x: addr hi:0x%x, "
1654 "addr low:0x%x, "
1655 "src: %d, %d, %d,"
1656 " %d; dst: %d, %d, %d, %d;\n",
1657 pipe_ctx->pipe_idx,
1658 dc_surface,
1659 dc_surface->address.grph.addr.high_part,
1660 dc_surface->address.grph.addr.low_part,
1661 dc_surface->src_rect.x,
1662 dc_surface->src_rect.y,
1663 dc_surface->src_rect.width,
1664 dc_surface->src_rect.height,
1665 dc_surface->dst_rect.x,
1666 dc_surface->dst_rect.y,
1667 dc_surface->dst_rect.width,
1668 dc_surface->dst_rect.height);
1669
1670 dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
1671 "Pipe %d: width, height, x, y\n"
1672 "viewport:%d, %d, %d, %d\n"
1673 "recout: %d, %d, %d, %d\n",
1674 pipe_ctx->pipe_idx,
1675 pipe_ctx->scl_data.viewport.width,
1676 pipe_ctx->scl_data.viewport.height,
1677 pipe_ctx->scl_data.viewport.x,
1678 pipe_ctx->scl_data.viewport.y,
1679 pipe_ctx->scl_data.recout.width,
1680 pipe_ctx->scl_data.recout.height,
1681 pipe_ctx->scl_data.recout.x,
1682 pipe_ctx->scl_data.recout.y);
1683 print_rq_dlg_ttu(dc, pipe_ctx);
1684 }
1685 }
1686
1687 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1688 {
1689 struct xfm_grph_csc_adjustment adjust;
1690 memset(&adjust, 0, sizeof(adjust));
1691 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1692
1693
1694 if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
1695 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1696 adjust.temperature_matrix[0] =
1697 pipe_ctx->stream->
1698 public.gamut_remap_matrix.matrix[0];
1699 adjust.temperature_matrix[1] =
1700 pipe_ctx->stream->
1701 public.gamut_remap_matrix.matrix[1];
1702 adjust.temperature_matrix[2] =
1703 pipe_ctx->stream->
1704 public.gamut_remap_matrix.matrix[2];
1705 adjust.temperature_matrix[3] =
1706 pipe_ctx->stream->
1707 public.gamut_remap_matrix.matrix[4];
1708 adjust.temperature_matrix[4] =
1709 pipe_ctx->stream->
1710 public.gamut_remap_matrix.matrix[5];
1711 adjust.temperature_matrix[5] =
1712 pipe_ctx->stream->
1713 public.gamut_remap_matrix.matrix[6];
1714 adjust.temperature_matrix[6] =
1715 pipe_ctx->stream->
1716 public.gamut_remap_matrix.matrix[8];
1717 adjust.temperature_matrix[7] =
1718 pipe_ctx->stream->
1719 public.gamut_remap_matrix.matrix[9];
1720 adjust.temperature_matrix[8] =
1721 pipe_ctx->stream->
1722 public.gamut_remap_matrix.matrix[10];
1723 }
1724
1725 pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
1726 }
1727
1728
1729 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
1730 enum dc_color_space colorspace,
1731 uint16_t *matrix)
1732 {
1733 int i;
1734 struct out_csc_color_matrix tbl_entry;
1735
1736 if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
1737 == true) {
1738 enum dc_color_space color_space =
1739 pipe_ctx->stream->public.output_color_space;
1740
1741 //uint16_t matrix[12];
1742 for (i = 0; i < 12; i++)
1743 tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i];
1744
1745 tbl_entry.color_space = color_space;
1746 //tbl_entry.regval = matrix;
1747 pipe_ctx->opp->funcs->opp_set_csc_adjustment(pipe_ctx->opp, &tbl_entry);
1748 }
1749 }
1750 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1751 {
1752 if (pipe_ctx->surface->visible)
1753 return true;
1754 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1755 return true;
1756 return false;
1757 }
1758
1759 static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1760 {
1761 if (pipe_ctx->surface->visible)
1762 return true;
1763 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1764 return true;
1765 return false;
1766 }
1767
1768 static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1769 {
1770 if (pipe_ctx->surface->visible)
1771 return true;
1772 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1773 return true;
1774 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1775 return true;
1776 return false;
1777 }
1778
1779 static bool is_rgb_cspace(enum dc_color_space output_color_space)
1780 {
1781 switch (output_color_space) {
1782 case COLOR_SPACE_SRGB:
1783 case COLOR_SPACE_SRGB_LIMITED:
1784 case COLOR_SPACE_2020_RGB_FULLRANGE:
1785 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1786 case COLOR_SPACE_ADOBERGB:
1787 return true;
1788 case COLOR_SPACE_YCBCR601:
1789 case COLOR_SPACE_YCBCR709:
1790 case COLOR_SPACE_YCBCR601_LIMITED:
1791 case COLOR_SPACE_YCBCR709_LIMITED:
1792 case COLOR_SPACE_2020_YCBCR:
1793 return false;
1794 default:
1795 /* Add a case to switch */
1796 BREAK_TO_DEBUGGER();
1797 return false;
1798 }
1799 }
1800
1801 static void dcn10_get_surface_visual_confirm_color(
1802 const struct pipe_ctx *pipe_ctx,
1803 struct tg_color *color)
1804 {
1805 uint32_t color_value = MAX_TG_COLOR_VALUE;
1806
1807 switch (pipe_ctx->scl_data.format) {
1808 case PIXEL_FORMAT_ARGB8888:
1809 /* set boarder color to red */
1810 color->color_r_cr = color_value;
1811 break;
1812
1813 case PIXEL_FORMAT_ARGB2101010:
1814 /* set boarder color to blue */
1815 color->color_b_cb = color_value;
1816 break;
1817 case PIXEL_FORMAT_420BPP8:
1818 /* set boarder color to green */
1819 color->color_g_y = color_value;
1820 break;
1821 case PIXEL_FORMAT_420BPP10:
1822 /* set boarder color to yellow */
1823 color->color_g_y = color_value;
1824 color->color_r_cr = color_value;
1825 break;
1826 case PIXEL_FORMAT_FP16:
1827 /* set boarder color to white */
1828 color->color_r_cr = color_value;
1829 color->color_b_cb = color_value;
1830 color->color_g_y = color_value;
1831 break;
1832 default:
1833 break;
1834 }
1835 }
1836
1837 static void update_dchubp_dpp(
1838 struct core_dc *dc,
1839 struct pipe_ctx *pipe_ctx,
1840 struct validate_context *context)
1841 {
1842 struct dce_hwseq *hws = dc->hwseq;
1843 struct mem_input *mi = pipe_ctx->mi;
1844 struct input_pixel_processor *ipp = pipe_ctx->ipp;
1845 struct dc_surface *surface = pipe_ctx->surface;
1846 union plane_size size = surface->plane_size;
1847 struct default_adjustment ocsc = {0};
1848 struct tg_color black_color = {0};
1849 struct mpcc_cfg mpcc_cfg;
1850 bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe;
1851
1852 /* TODO: proper fix once fpga works */
1853 /* depends on DML calculation, DPP clock value may change dynamically */
1854 enable_dppclk(
1855 dc->hwseq,
1856 pipe_ctx->pipe_idx,
1857 pipe_ctx->pix_clk_params.requested_pix_clk,
1858 context->bw.dcn.calc_clk.dppclk_div);
1859 dc->current_context->bw.dcn.cur_clk.dppclk_div =
1860 context->bw.dcn.calc_clk.dppclk_div;
1861 context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
1862
1863 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1864 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1865 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1866 */
1867 REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->tg->inst);
1868
1869 update_plane_addr(dc, pipe_ctx);
1870
1871 mi->funcs->mem_input_setup(
1872 mi,
1873 &pipe_ctx->dlg_regs,
1874 &pipe_ctx->ttu_regs,
1875 &pipe_ctx->rq_regs,
1876 &pipe_ctx->pipe_dlg_param);
1877
1878 size.grph.surface_size = pipe_ctx->scl_data.viewport;
1879
1880 if (dc->public.config.gpu_vm_support)
1881 mi->funcs->mem_input_program_pte_vm(
1882 pipe_ctx->mi,
1883 surface->format,
1884 &surface->tiling_info,
1885 surface->rotation);
1886
1887 ipp->funcs->ipp_setup(ipp,
1888 surface->format,
1889 1,
1890 IPP_OUTPUT_FORMAT_12_BIT_FIX);
1891
1892 pipe_ctx->scl_data.lb_params.alpha_en = per_pixel_alpha;
1893 mpcc_cfg.top_dpp_id = pipe_ctx->pipe_idx;
1894 if (pipe_ctx->bottom_pipe)
1895 mpcc_cfg.bot_mpcc_id = pipe_ctx->bottom_pipe->mpcc->inst;
1896 else
1897 mpcc_cfg.bot_mpcc_id = 0xf;
1898 mpcc_cfg.opp_id = pipe_ctx->tg->inst;
1899 mpcc_cfg.top_of_tree = pipe_ctx->pipe_idx == pipe_ctx->tg->inst;
1900 mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
1901 /* DCN1.0 has output CM before MPC which seems to screw with
1902 * pre-multiplied alpha.
1903 */
1904 mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
1905 pipe_ctx->stream->public.output_color_space)
1906 && per_pixel_alpha;
1907 pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg);
1908
1909 if (dc->public.debug.surface_visual_confirm) {
1910 dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color);
1911 } else {
1912 color_space_to_black_color(
1913 dc, pipe_ctx->stream->public.output_color_space,
1914 &black_color);
1915 }
1916 pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color);
1917
1918 pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1919 /* scaler configuration */
1920 pipe_ctx->xfm->funcs->transform_set_scaler(
1921 pipe_ctx->xfm, &pipe_ctx->scl_data);
1922 mi->funcs->mem_program_viewport(mi,
1923 &pipe_ctx->scl_data.viewport, &pipe_ctx->scl_data.viewport_c);
1924
1925 /*gamut remap*/
1926 program_gamut_remap(pipe_ctx);
1927
1928 /*TODO add adjustments parameters*/
1929 ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
1930 pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc);
1931
1932 mi->funcs->mem_input_program_surface_config(
1933 mi,
1934 surface->format,
1935 &surface->tiling_info,
1936 &size,
1937 surface->rotation,
1938 &surface->dcc,
1939 surface->horizontal_mirror);
1940
1941 mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
1942 }
1943
1944 static void program_all_pipe_in_tree(
1945 struct core_dc *dc,
1946 struct pipe_ctx *pipe_ctx,
1947 struct validate_context *context)
1948 {
1949 unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
1950
1951 if (pipe_ctx->top_pipe == NULL) {
1952
1953 /* lock otg_master_update to process all pipes associated with
1954 * this OTG. this is done only one time.
1955 */
1956 /* watermark is for all pipes */
1957 program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
1958
1959 if (dc->public.debug.sanity_checks) {
1960 /* pstate stuck check after watermark update */
1961 verify_allow_pstate_change_high(dc->hwseq);
1962 }
1963
1964 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
1965
1966 pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
1967 pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
1968 pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
1969 pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
1970 pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
1971
1972 pipe_ctx->tg->funcs->program_global_sync(
1973 pipe_ctx->tg);
1974 pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
1975 }
1976
1977 if (pipe_ctx->surface != NULL) {
1978 dcn10_power_on_fe(dc, pipe_ctx, context);
1979 update_dchubp_dpp(dc, pipe_ctx, context);
1980 }
1981
1982 if (dc->public.debug.sanity_checks) {
1983 /* pstate stuck check after each pipe is programmed */
1984 verify_allow_pstate_change_high(dc->hwseq);
1985 }
1986
1987 if (pipe_ctx->bottom_pipe != NULL)
1988 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
1989 }
1990
1991 static void dcn10_pplib_apply_display_requirements(
1992 struct core_dc *dc,
1993 struct validate_context *context)
1994 {
1995 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
1996
1997 pp_display_cfg->all_displays_in_sync = false;/*todo*/
1998 pp_display_cfg->nb_pstate_switch_disable = false;
1999 pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2000 pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
2001 pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2002 pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
2003 pp_display_cfg->avail_mclk_switch_time_us =
2004 context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
2005 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
2006 context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
2007 pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
2008 pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
2009 dce110_fill_display_configs(context, pp_display_cfg);
2010
2011 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2012 struct dm_pp_display_configuration)) != 0)
2013 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2014
2015 dc->prev_display_config = *pp_display_cfg;
2016 }
2017
2018 static void dcn10_apply_ctx_for_surface(
2019 struct core_dc *dc,
2020 const struct dc_surface *surface,
2021 struct validate_context *context)
2022 {
2023 int i, be_idx;
2024
2025 if (dc->public.debug.sanity_checks)
2026 verify_allow_pstate_change_high(dc->hwseq);
2027
2028 if (!surface)
2029 return;
2030
2031 for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++)
2032 if (surface == context->res_ctx.pipe_ctx[be_idx].surface)
2033 break;
2034
2035 /* reset unused mpcc */
2036 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2037 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2038 struct pipe_ctx *old_pipe_ctx =
2039 &dc->current_context->res_ctx.pipe_ctx[i];
2040
2041 if (!pipe_ctx->surface && !old_pipe_ctx->surface)
2042 continue;
2043
2044 /*
2045 * Powergate reused pipes that are not powergated
2046 * fairly hacky right now, using opp_id as indicator
2047 */
2048
2049 if (pipe_ctx->surface && !old_pipe_ctx->surface) {
2050 if (pipe_ctx->mpcc->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) {
2051 dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
2052 /*
2053 * power down fe will unlock when calling reset, need
2054 * to lock it back here. Messy, need rework.
2055 */
2056 pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
2057 }
2058 }
2059
2060
2061 if ((!pipe_ctx->surface && old_pipe_ctx->surface)
2062 || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
2063 struct mpcc_cfg mpcc_cfg;
2064 int opp_id_cached = old_pipe_ctx->mpcc->opp_id;
2065
2066 if (old_pipe_ctx->tg->inst != be_idx)
2067 continue;
2068
2069 if (!old_pipe_ctx->top_pipe) {
2070 ASSERT(0);
2071 continue;
2072 }
2073
2074 /* reset mpc */
2075 mpcc_cfg.opp_id = 0xf;
2076 mpcc_cfg.top_dpp_id = 0xf;
2077 mpcc_cfg.bot_mpcc_id = 0xf;
2078 mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
2079 old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg);
2080 old_pipe_ctx->top_pipe->opp->mpcc_disconnect_pending[old_pipe_ctx->mpcc->inst] = true;
2081
2082 if (dc->public.debug.sanity_checks)
2083 verify_allow_pstate_change_high(dc->hwseq);
2084
2085 /*
2086 * the mpcc is the only thing that keeps track of the mpcc
2087 * mapping for reset front end right now. Might need some
2088 * rework.
2089 */
2090 old_pipe_ctx->mpcc->opp_id = opp_id_cached;
2091
2092 old_pipe_ctx->top_pipe = NULL;
2093 old_pipe_ctx->bottom_pipe = NULL;
2094 old_pipe_ctx->surface = NULL;
2095
2096 dm_logger_write(dc->ctx->logger, LOG_DC,
2097 "Reset mpcc for pipe %d\n",
2098 old_pipe_ctx->pipe_idx);
2099 }
2100 }
2101
2102 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2103 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2104
2105 if (pipe_ctx->surface != surface)
2106 continue;
2107
2108 /* looking for top pipe to program */
2109 if (!pipe_ctx->top_pipe)
2110 program_all_pipe_in_tree(dc, pipe_ctx, context);
2111 }
2112
2113 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2114 "\n============== Watermark parameters ==============\n"
2115 "a.urgent_ns: %d \n"
2116 "a.cstate_enter_plus_exit: %d \n"
2117 "a.cstate_exit: %d \n"
2118 "a.pstate_change: %d \n"
2119 "a.pte_meta_urgent: %d \n"
2120 "b.urgent_ns: %d \n"
2121 "b.cstate_enter_plus_exit: %d \n"
2122 "b.cstate_exit: %d \n"
2123 "b.pstate_change: %d \n"
2124 "b.pte_meta_urgent: %d \n",
2125 context->bw.dcn.watermarks.a.urgent_ns,
2126 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
2127 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
2128 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
2129 context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
2130 context->bw.dcn.watermarks.b.urgent_ns,
2131 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
2132 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
2133 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
2134 context->bw.dcn.watermarks.b.pte_meta_urgent_ns
2135 );
2136 dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
2137 "\nc.urgent_ns: %d \n"
2138 "c.cstate_enter_plus_exit: %d \n"
2139 "c.cstate_exit: %d \n"
2140 "c.pstate_change: %d \n"
2141 "c.pte_meta_urgent: %d \n"
2142 "d.urgent_ns: %d \n"
2143 "d.cstate_enter_plus_exit: %d \n"
2144 "d.cstate_exit: %d \n"
2145 "d.pstate_change: %d \n"
2146 "d.pte_meta_urgent: %d \n"
2147 "========================================================\n",
2148 context->bw.dcn.watermarks.c.urgent_ns,
2149 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
2150 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
2151 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
2152 context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
2153 context->bw.dcn.watermarks.d.urgent_ns,
2154 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
2155 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
2156 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
2157 context->bw.dcn.watermarks.d.pte_meta_urgent_ns
2158 );
2159
2160 if (dc->public.debug.sanity_checks)
2161 verify_allow_pstate_change_high(dc->hwseq);
2162 }
2163
2164 static void dcn10_set_bandwidth(
2165 struct core_dc *dc,
2166 struct validate_context *context,
2167 bool decrease_allowed)
2168 {
2169 struct dm_pp_clock_for_voltage_req clock;
2170
2171 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2172 return;
2173
2174 if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
2175 > dc->current_context->bw.dcn.cur_clk.dispclk_khz) {
2176 dc->res_pool->display_clock->funcs->set_clock(
2177 dc->res_pool->display_clock,
2178 context->bw.dcn.calc_clk.dispclk_khz);
2179 dc->current_context->bw.dcn.cur_clk.dispclk_khz =
2180 context->bw.dcn.calc_clk.dispclk_khz;
2181 }
2182 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
2183 > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
2184 clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
2185 clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
2186 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
2187 dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
2188 context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
2189 }
2190 if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
2191 > dc->current_context->bw.dcn.cur_clk.fclk_khz) {
2192 clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
2193 clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
2194 dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
2195 dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
2196 context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
2197 }
2198 if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
2199 > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
2200 dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
2201 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2202 context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
2203 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
2204 }
2205 /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
2206 if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
2207 < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {
2208 dc->current_context->bw.dcn.calc_clk.dram_ccm_us =
2209 context->bw.dcn.calc_clk.dram_ccm_us;
2210 context->bw.dcn.cur_clk.dram_ccm_us =
2211 context->bw.dcn.calc_clk.dram_ccm_us;
2212 }
2213 if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
2214 < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) {
2215 dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us =
2216 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2217 context->bw.dcn.cur_clk.min_active_dram_ccm_us =
2218 context->bw.dcn.calc_clk.min_active_dram_ccm_us;
2219 }
2220 dcn10_pplib_apply_display_requirements(dc, context);
2221
2222 /* need to fix this function. not doing the right thing here */
2223 }
2224
2225 static void set_drr(struct pipe_ctx **pipe_ctx,
2226 int num_pipes, int vmin, int vmax)
2227 {
2228 int i = 0;
2229 struct drr_params params = {0};
2230
2231 params.vertical_total_max = vmax;
2232 params.vertical_total_min = vmin;
2233
2234 /* TODO: If multiple pipes are to be supported, you need
2235 * some GSL stuff
2236 */
2237 for (i = 0; i < num_pipes; i++) {
2238 pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
2239 }
2240 }
2241
2242 static void get_position(struct pipe_ctx **pipe_ctx,
2243 int num_pipes,
2244 struct crtc_position *position)
2245 {
2246 int i = 0;
2247
2248 /* TODO: handle pipes > 1
2249 */
2250 for (i = 0; i < num_pipes; i++)
2251 pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
2252 }
2253
2254 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2255 int num_pipes, const struct dc_static_screen_events *events)
2256 {
2257 unsigned int i;
2258 unsigned int value = 0;
2259
2260 if (events->surface_update)
2261 value |= 0x80;
2262 if (events->cursor_update)
2263 value |= 0x2;
2264
2265 for (i = 0; i < num_pipes; i++)
2266 pipe_ctx[i]->tg->funcs->
2267 set_static_screen_control(pipe_ctx[i]->tg, value);
2268 }
2269
2270 static void set_plane_config(
2271 const struct core_dc *dc,
2272 struct pipe_ctx *pipe_ctx,
2273 struct resource_context *res_ctx)
2274 {
2275 /* TODO */
2276 program_gamut_remap(pipe_ctx);
2277 }
2278
2279 static void dcn10_config_stereo_parameters(
2280 struct core_stream *stream, struct crtc_stereo_flags *flags)
2281 {
2282 enum view_3d_format view_format = stream->public.view_format;
2283 enum dc_timing_3d_format timing_3d_format =\
2284 stream->public.timing.timing_3d_format;
2285 bool non_stereo_timing = false;
2286
2287 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2288 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2289 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2290 non_stereo_timing = true;
2291
2292 if (non_stereo_timing == false &&
2293 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2294
2295 flags->PROGRAM_STEREO = 1;
2296 flags->PROGRAM_POLARITY = 1;
2297 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2298 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2299 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2300 enum display_dongle_type dongle = \
2301 stream->sink->link->ddc->dongle_type;
2302 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2303 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2304 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2305 flags->DISABLE_STEREO_DP_SYNC = 1;
2306 }
2307 flags->RIGHT_EYE_POLARITY =\
2308 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
2309 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2310 flags->FRAME_PACKED = 1;
2311 }
2312
2313 return;
2314 }
2315
2316 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
2317 {
2318 struct crtc_stereo_flags flags = { 0 };
2319 struct core_stream *stream = pipe_ctx->stream;
2320
2321 dcn10_config_stereo_parameters(stream, &flags);
2322
2323 pipe_ctx->opp->funcs->opp_set_stereo_polarity(
2324 pipe_ctx->opp,
2325 flags.PROGRAM_STEREO == 1 ? true:false,
2326 stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
2327
2328 pipe_ctx->tg->funcs->program_stereo(
2329 pipe_ctx->tg,
2330 &stream->public.timing,
2331 &flags);
2332
2333 return;
2334 }
2335
2336 static void dcn10_log_hw_state(struct core_dc *dc)
2337 {
2338 struct dc_context *dc_ctx = dc->ctx;
2339 struct dce_hwseq *hws = dc->hwseq;
2340
2341 DTN_INFO("%s: Hello World", __func__);
2342
2343 if (REG(MPC_CRC_RESULT_GB))
2344 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
2345 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
2346 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
2347 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
2348 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
2349 /* todo: add meaningful register reads and print out HW state
2350 *
2351 */
2352 }
2353
2354 static void dcn10_wait_for_mpcc_disconnect(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx)
2355 {
2356 int i;
2357 for (i = 0; i < MAX_PIPES; i++) {
2358 if (!pipe_ctx->opp || !pipe_ctx->mpcc)
2359 continue;
2360
2361 if (pipe_ctx->opp->mpcc_disconnect_pending[i]) {
2362 pipe_ctx->mpcc->funcs->wait_for_idle(res_pool->mpcc[i]);
2363 pipe_ctx->opp->mpcc_disconnect_pending[i] = false;
2364 }
2365 }
2366 }
2367
2368 static bool dcn10_dummy_display_power_gating(
2369 struct core_dc *dc,
2370 uint8_t controller_id,
2371 struct dc_bios *dcb,
2372 enum pipe_gating_control power_gating)
2373 {
2374 return true;
2375 }
2376
2377 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2378 {
2379 struct dc_surface *surface = pipe_ctx->surface;
2380 struct timing_generator *tg = pipe_ctx->tg;
2381
2382 if (surface->ctx->dc->debug.sanity_checks) {
2383 struct core_dc *dc = DC_TO_CORE(surface->ctx->dc);
2384
2385 verify_allow_pstate_change_high(dc->hwseq);
2386 }
2387
2388 if (surface == NULL)
2389 return;
2390
2391 surface->status.is_flip_pending =
2392 pipe_ctx->mi->funcs->mem_input_is_flip_pending(
2393 pipe_ctx->mi);
2394
2395 /* DCN we read INUSE address in MI, do we still need this wa? */
2396 if (surface->status.is_flip_pending &&
2397 !surface->visible) {
2398 pipe_ctx->mi->current_address =
2399 pipe_ctx->mi->request_address;
2400 BREAK_TO_DEBUGGER();
2401 }
2402
2403 surface->status.current_address = pipe_ctx->mi->current_address;
2404 if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2405 tg->funcs->is_stereo_left_eye) {
2406 surface->status.is_right_eye =
2407 !tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
2408 }
2409 }
2410
2411 static const struct hw_sequencer_funcs dcn10_funcs = {
2412 .program_gamut_remap = program_gamut_remap,
2413 .program_csc_matrix = program_csc_matrix,
2414 .init_hw = dcn10_init_hw,
2415 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2416 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2417 .set_plane_config = set_plane_config,
2418 .update_plane_addr = update_plane_addr,
2419 .update_dchub = dcn10_update_dchub,
2420 .update_pending_status = dcn10_update_pending_status,
2421 .set_input_transfer_func = dcn10_set_input_transfer_func,
2422 .set_output_transfer_func = dcn10_set_output_transfer_func,
2423 .power_down = dce110_power_down,
2424 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2425 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2426 .update_info_frame = dce110_update_info_frame,
2427 .enable_stream = dce110_enable_stream,
2428 .disable_stream = dce110_disable_stream,
2429 .unblank_stream = dce110_unblank_stream,
2430 .enable_display_power_gating = dcn10_dummy_display_power_gating,
2431 .power_down_front_end = dcn10_power_down_fe,
2432 .power_on_front_end = dcn10_power_on_fe,
2433 .pipe_control_lock = dcn10_pipe_control_lock,
2434 .set_bandwidth = dcn10_set_bandwidth,
2435 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2436 .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
2437 .set_drr = set_drr,
2438 .get_position = get_position,
2439 .set_static_screen_control = set_static_screen_control,
2440 .setup_stereo = dcn10_setup_stereo,
2441 .set_avmute = dce110_set_avmute,
2442 .log_hw_state = dcn10_log_hw_state,
2443 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect
2444 };
2445
2446
2447 void dcn10_hw_sequencer_construct(struct core_dc *dc)
2448 {
2449 dc->hwss = dcn10_funcs;
2450 }
2451
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