1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __DC_MEM_INPUT_DCN10_H__
26 #define __DC_MEM_INPUT_DCN10_H__
28 #include "mem_input.h"
30 #define TO_DCN10_MEM_INPUT(mi)\
31 container_of(mi, struct dcn10_mem_input, base)
34 #define MI_DCN10_REG_LIST(id)\
35 SRI(DCHUBP_CNTL, HUBP, id),\
36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
37 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
38 SRI(DCSURF_TILING_CONFIG, HUBP, id),\
39 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
40 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
41 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
42 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
43 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
44 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
45 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
46 SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
47 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
48 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
49 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
50 SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
51 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
52 SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
53 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
54 SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
55 SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
56 SRI(HUBPRET_CONTROL, HUBPRET, id),\
57 SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
58 SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
59 SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
60 SRI(BLANK_OFFSET_0, HUBPREQ, id),\
61 SRI(BLANK_OFFSET_1, HUBPREQ, id),\
62 SRI(DST_DIMENSIONS, HUBPREQ, id),\
63 SRI(DST_AFTER_SCALER, HUBPREQ, id),\
64 SRI(PREFETCH_SETTINS, HUBPREQ, id),\
65 SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
66 SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
67 SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
68 SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
69 SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
70 SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
71 SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
72 SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
73 SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
74 SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
75 SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
76 SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
77 SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
78 SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
79 SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
80 SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
81 SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
82 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
83 SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
84 SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
85 SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
86 SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
87 SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
88 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
89 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
90 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
91 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
92 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
93 SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
94 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
95 SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
96 SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
97 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
98 SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
99 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
100 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
101 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
102 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
103 SR(DCHUBBUB_SDPIF_FB_TOP),\
104 SR(DCHUBBUB_SDPIF_FB_BASE),\
105 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
106 SR(DCHUBBUB_SDPIF_AGP_BASE),\
107 SR(DCHUBBUB_SDPIF_AGP_BOT),\
108 SR(DCHUBBUB_SDPIF_AGP_TOP),\
109 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
110 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
111 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
112 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
113 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
114 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
115 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
116 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
117 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
118 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
119 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
120 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
121 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
122 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
123 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
124 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
125 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
126 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
127 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
128 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
129 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
130 SR(DCHUBBUB_ARB_SAT_LEVEL),\
131 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
132 /* todo: get these from GVM instead of reading registers ourselves */\
133 GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
134 GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
135 GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
136 GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
137 GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
138 GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
139 GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
140 GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
141 GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
142 GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
143 GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
144 GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
146 struct dcn_mi_registers
{
147 uint32_t DCHUBP_CNTL
;
148 uint32_t HUBPREQ_DEBUG_DB
;
149 uint32_t DCSURF_ADDR_CONFIG
;
150 uint32_t DCSURF_TILING_CONFIG
;
151 uint32_t DCSURF_SURFACE_PITCH
;
152 uint32_t DCSURF_SURFACE_PITCH_C
;
153 uint32_t DCSURF_SURFACE_CONFIG
;
154 uint32_t DCSURF_FLIP_CONTROL
;
155 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
;
156 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS
;
157 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
;
158 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS
;
159 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
;
160 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS
;
161 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
;
162 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS
;
163 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
;
164 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C
;
165 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
;
166 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
;
167 uint32_t DCSURF_SURFACE_CONTROL
;
168 uint32_t HUBPRET_CONTROL
;
169 uint32_t DCN_EXPANSION_MODE
;
170 uint32_t DCHUBP_REQ_SIZE_CONFIG
;
171 uint32_t DCHUBP_REQ_SIZE_CONFIG_C
;
172 uint32_t BLANK_OFFSET_0
;
173 uint32_t BLANK_OFFSET_1
;
174 uint32_t DST_DIMENSIONS
;
175 uint32_t DST_AFTER_SCALER
;
176 uint32_t PREFETCH_SETTINS
;
177 uint32_t VBLANK_PARAMETERS_0
;
178 uint32_t REF_FREQ_TO_PIX_FREQ
;
179 uint32_t VBLANK_PARAMETERS_1
;
180 uint32_t VBLANK_PARAMETERS_3
;
181 uint32_t NOM_PARAMETERS_0
;
182 uint32_t NOM_PARAMETERS_1
;
183 uint32_t NOM_PARAMETERS_4
;
184 uint32_t NOM_PARAMETERS_5
;
185 uint32_t PER_LINE_DELIVERY_PRE
;
186 uint32_t PER_LINE_DELIVERY
;
187 uint32_t PREFETCH_SETTINS_C
;
188 uint32_t VBLANK_PARAMETERS_2
;
189 uint32_t VBLANK_PARAMETERS_4
;
190 uint32_t NOM_PARAMETERS_2
;
191 uint32_t NOM_PARAMETERS_3
;
192 uint32_t NOM_PARAMETERS_6
;
193 uint32_t NOM_PARAMETERS_7
;
194 uint32_t DCN_TTU_QOS_WM
;
195 uint32_t DCN_GLOBAL_TTU_CNTL
;
196 uint32_t DCN_SURF0_TTU_CNTL0
;
197 uint32_t DCN_SURF0_TTU_CNTL1
;
198 uint32_t DCN_SURF1_TTU_CNTL0
;
199 uint32_t DCN_SURF1_TTU_CNTL1
;
200 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
;
201 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
;
202 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
;
203 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
;
204 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
;
205 uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
;
206 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
;
207 uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
;
208 uint32_t DCN_VM_MX_L1_TLB_CNTL
;
209 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
;
210 uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
;
211 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB
;
212 uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB
;
213 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB
;
214 uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB
;
215 uint32_t DCHUBBUB_SDPIF_FB_TOP
;
216 uint32_t DCHUBBUB_SDPIF_FB_BASE
;
217 uint32_t DCHUBBUB_SDPIF_FB_OFFSET
;
218 uint32_t DCHUBBUB_SDPIF_AGP_BASE
;
219 uint32_t DCHUBBUB_SDPIF_AGP_BOT
;
220 uint32_t DCHUBBUB_SDPIF_AGP_TOP
;
221 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
;
222 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A
;
223 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
;
224 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
;
225 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
;
226 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
;
227 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B
;
228 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
;
229 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
;
230 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
;
231 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
;
232 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C
;
233 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
;
234 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
;
235 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
;
236 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
;
237 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D
;
238 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
;
239 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
;
240 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
;
241 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
;
242 uint32_t DCHUBBUB_ARB_SAT_LEVEL
;
243 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND
;
245 /* GC registers. read only. temporary hack */
246 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
;
247 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
;
248 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
;
249 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
;
250 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
;
251 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
;
252 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
;
253 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
;
254 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
;
255 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
;
256 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR
;
257 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR
;
260 #define MI_SF(reg_name, field_name, post_fix)\
261 .field_name = reg_name ## __ ## field_name ## post_fix
263 #define MI_DCN10_MASK_SH_LIST(mask_sh)\
264 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
265 MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
266 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
267 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
268 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
269 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
270 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
271 MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
272 MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
273 MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
274 MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
275 MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
276 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
277 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
278 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
279 MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
280 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
281 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
282 MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
283 MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
284 MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
285 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
286 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
287 MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
288 MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
289 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
290 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
291 MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
292 MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
293 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
294 MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
295 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
296 MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
297 MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
298 MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
299 MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
300 MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
301 MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
302 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
303 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
304 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
305 MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
306 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
307 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
308 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
309 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
310 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
311 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
312 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
313 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
314 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
315 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
316 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
317 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
318 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
319 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
320 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
321 MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
322 MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
323 MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
324 MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
325 MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
326 MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
327 MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
328 MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
329 MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
330 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
331 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
332 MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
333 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
334 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
335 MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
336 MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
337 MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
338 MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
339 MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
340 MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
341 MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
342 MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
343 MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
344 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
345 MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
346 MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
347 MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
348 MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
349 MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
350 MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
351 MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
352 MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
353 MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
354 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
355 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
356 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
357 MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
358 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
359 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
360 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
361 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
362 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
363 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
364 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
365 MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
366 MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
367 MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
368 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
369 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
370 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
371 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
372 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
373 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
374 MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
375 MI_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh),\
376 MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
377 MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
378 MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\
379 MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\
380 MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
381 MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
382 MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
383 MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
384 MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\
385 /* todo: get these from GVM instead of reading registers ourselves */\
386 MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
387 MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
388 MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
389 MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
390 MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
391 MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
392 MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
393 MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
394 MI_SF(MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
396 #define DCN_MI_REG_FIELD_LIST(type) \
398 type HUBP_TTU_DISABLE;\
401 type PIPE_INTERLEAVE;\
404 type MAX_COMPRESSED_FRAGS;\
413 type ROTATION_ANGLE;\
415 type SURFACE_PIXEL_FORMAT;\
416 type SURFACE_FLIP_TYPE;\
417 type SURFACE_UPDATE_PENDING;\
418 type PRIMARY_SURFACE_ADDRESS_HIGH;\
419 type PRIMARY_SURFACE_ADDRESS;\
420 type SECONDARY_SURFACE_ADDRESS_HIGH;\
421 type SECONDARY_SURFACE_ADDRESS;\
422 type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
423 type PRIMARY_META_SURFACE_ADDRESS;\
424 type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
425 type SECONDARY_META_SURFACE_ADDRESS;\
426 type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
427 type PRIMARY_SURFACE_ADDRESS_C;\
428 type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
429 type PRIMARY_META_SURFACE_ADDRESS_C;\
430 type PRIMARY_SURFACE_DCC_EN;\
431 type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
432 type DET_BUF_PLANE1_BASE_ADDRESS;\
433 type CROSSBAR_SRC_CB_B;\
434 type CROSSBAR_SRC_CR_R;\
435 type DRQ_EXPANSION_MODE;\
436 type PRQ_EXPANSION_MODE;\
437 type MRQ_EXPANSION_MODE;\
438 type CRQ_EXPANSION_MODE;\
440 type MIN_CHUNK_SIZE;\
441 type META_CHUNK_SIZE;\
442 type MIN_META_CHUNK_SIZE;\
443 type DPTE_GROUP_SIZE;\
444 type MPTE_GROUP_SIZE;\
446 type PTE_ROW_HEIGHT_LINEAR;\
448 type MIN_CHUNK_SIZE_C;\
449 type META_CHUNK_SIZE_C;\
450 type MIN_META_CHUNK_SIZE_C;\
451 type DPTE_GROUP_SIZE_C;\
452 type MPTE_GROUP_SIZE_C;\
453 type SWATH_HEIGHT_C;\
454 type PTE_ROW_HEIGHT_LINEAR_C;\
455 type REFCYC_H_BLANK_END;\
456 type DLG_V_BLANK_END;\
457 type MIN_DST_Y_NEXT_START;\
458 type REFCYC_PER_HTOTAL;\
459 type REFCYC_X_AFTER_SCALER;\
460 type DST_Y_AFTER_SCALER;\
461 type DST_Y_PREFETCH;\
462 type VRATIO_PREFETCH;\
463 type DST_Y_PER_VM_VBLANK;\
464 type DST_Y_PER_ROW_VBLANK;\
465 type REF_FREQ_TO_PIX_FREQ;\
466 type REFCYC_PER_PTE_GROUP_VBLANK_L;\
467 type REFCYC_PER_META_CHUNK_VBLANK_L;\
468 type DST_Y_PER_PTE_ROW_NOM_L;\
469 type REFCYC_PER_PTE_GROUP_NOM_L;\
470 type DST_Y_PER_META_ROW_NOM_L;\
471 type REFCYC_PER_META_CHUNK_NOM_L;\
472 type REFCYC_PER_LINE_DELIVERY_PRE_L;\
473 type REFCYC_PER_LINE_DELIVERY_PRE_C;\
474 type REFCYC_PER_LINE_DELIVERY_L;\
475 type REFCYC_PER_LINE_DELIVERY_C;\
476 type VRATIO_PREFETCH_C;\
477 type REFCYC_PER_PTE_GROUP_VBLANK_C;\
478 type REFCYC_PER_META_CHUNK_VBLANK_C;\
479 type DST_Y_PER_PTE_ROW_NOM_C;\
480 type REFCYC_PER_PTE_GROUP_NOM_C;\
481 type DST_Y_PER_META_ROW_NOM_C;\
482 type REFCYC_PER_META_CHUNK_NOM_C;\
483 type QoS_LEVEL_LOW_WM;\
484 type QoS_LEVEL_HIGH_WM;\
485 type MIN_TTU_VBLANK;\
486 type QoS_LEVEL_FLIP;\
487 type REFCYC_PER_REQ_DELIVERY;\
488 type QoS_LEVEL_FIXED;\
489 type QoS_RAMP_DISABLE;\
490 type REFCYC_PER_REQ_DELIVERY_PRE;\
491 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
492 type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
493 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
494 type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
495 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
496 type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
497 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
498 type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
500 type SYSTEM_ACCESS_MODE;\
501 type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
502 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
503 type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
504 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
505 type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
506 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
507 type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
510 type SDPIF_FB_OFFSET;\
511 type SDPIF_AGP_BASE;\
514 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
515 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
516 type DCHUBBUB_ARB_SAT_LEVEL;\
517 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
518 /* todo: get these from GVM instead of reading registers ourselves */\
519 type PAGE_DIRECTORY_ENTRY_HI32;\
520 type PAGE_DIRECTORY_ENTRY_LO32;\
521 type LOGICAL_PAGE_NUMBER_HI4;\
522 type LOGICAL_PAGE_NUMBER_LO32;\
523 type PHYSICAL_PAGE_ADDR_HI4;\
524 type PHYSICAL_PAGE_ADDR_LO32;\
525 type PHYSICAL_PAGE_NUMBER_MSB;\
526 type PHYSICAL_PAGE_NUMBER_LSB;\
529 struct dcn_mi_shift
{
530 DCN_MI_REG_FIELD_LIST(uint8_t);
534 DCN_MI_REG_FIELD_LIST(uint32_t);
537 struct dcn10_mem_input
{
538 struct mem_input base
;
539 const struct dcn_mi_registers
*mi_regs
;
540 const struct dcn_mi_shift
*mi_shift
;
541 const struct dcn_mi_mask
*mi_mask
;
544 bool dcn10_mem_input_construct(
545 struct dcn10_mem_input
*mi
,
546 struct dc_context
*ctx
,
548 const struct dcn_mi_registers
*mi_regs
,
549 const struct dcn_mi_shift
*mi_shift
,
550 const struct dcn_mi_mask
*mi_mask
);
projects / mirror_ubuntu-bionic-kernel.git / blob