drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h

   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24
  25 #ifndef __DC_MEM_INPUT_DCN10_H__
  26 #define __DC_MEM_INPUT_DCN10_H__
  27
  28 #include "mem_input.h"
  29
  30 #define TO_DCN10_MEM_INPUT(mi)\
  31         container_of(mi, struct dcn10_mem_input, base)
  32
  33
  34 #define MI_REG_LIST_DCN(id)\
  35         SRI(DCHUBP_CNTL, HUBP, id),\
  36         SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
  37         SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
  38         SRI(DCSURF_TILING_CONFIG, HUBP, id),\
  39         SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
  40         SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
  41         SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
  42         SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
  43         SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
  44         SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
  45         SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
  46         SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
  47         SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
  48         SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
  49         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  50         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
  51         SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  52         SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
  53         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  54         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
  55         SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  56         SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
  57         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
  58         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
  59         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
  60         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
  61         SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
  62         SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
  63         SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
  64         SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
  65         SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
  66         SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
  67         SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
  68         SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
  69         SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
  70         SRI(HUBPRET_CONTROL, HUBPRET, id),\
  71         SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
  72         SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
  73         SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
  74         SRI(BLANK_OFFSET_0, HUBPREQ, id),\
  75         SRI(BLANK_OFFSET_1, HUBPREQ, id),\
  76         SRI(DST_DIMENSIONS, HUBPREQ, id),\
  77         SRI(DST_AFTER_SCALER, HUBPREQ, id),\
  78         SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
  79         SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
  80         SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
  81         SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
  82         SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
  83         SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
  84         SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
  85         SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
  86         SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
  87         SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
  88         SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
  89         SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
  90         SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
  91         SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
  92         SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
  93         SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
  94         SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
  95         SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
  96         SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
  97         SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
  98         SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
  99         SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
 100         SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
 101
 102 #define MI_REG_LIST_DCN10(id)\
 103         MI_REG_LIST_DCN(id),\
 104         SRI(PREFETCH_SETTINS, HUBPREQ, id),\
 105         SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
 106         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
 107         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
 108         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
 109         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
 110         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
 111         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
 112         SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
 113         SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
 114         SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
 115         SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
 116         SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
 117         SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
 118         SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
 119         SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
 120         SR(DCHUBBUB_SDPIF_FB_BASE),\
 121         SR(DCHUBBUB_SDPIF_FB_OFFSET)
 122
 123 struct dcn_mi_registers {
 124         uint32_t DCHUBP_CNTL;
 125         uint32_t HUBPREQ_DEBUG_DB;
 126         uint32_t DCSURF_ADDR_CONFIG;
 127         uint32_t DCSURF_TILING_CONFIG;
 128         uint32_t DCSURF_SURFACE_PITCH;
 129         uint32_t DCSURF_SURFACE_PITCH_C;
 130         uint32_t DCSURF_SURFACE_CONFIG;
 131         uint32_t DCSURF_FLIP_CONTROL;
 132         uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
 133         uint32_t DCSURF_PRI_VIEWPORT_START;
 134         uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
 135         uint32_t DCSURF_SEC_VIEWPORT_START;
 136         uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
 137         uint32_t DCSURF_PRI_VIEWPORT_START_C;
 138         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
 139         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
 140         uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
 141         uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
 142         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
 143         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
 144         uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
 145         uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
 146         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
 147         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
 148         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
 149         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
 150         uint32_t DCSURF_SURFACE_INUSE;
 151         uint32_t DCSURF_SURFACE_INUSE_HIGH;
 152         uint32_t DCSURF_SURFACE_INUSE_C;
 153         uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
 154         uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
 155         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
 156         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
 157         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
 158         uint32_t DCSURF_SURFACE_CONTROL;
 159         uint32_t HUBPRET_CONTROL;
 160         uint32_t DCN_EXPANSION_MODE;
 161         uint32_t DCHUBP_REQ_SIZE_CONFIG;
 162         uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
 163         uint32_t BLANK_OFFSET_0;
 164         uint32_t BLANK_OFFSET_1;
 165         uint32_t DST_DIMENSIONS;
 166         uint32_t DST_AFTER_SCALER;
 167         uint32_t PREFETCH_SETTINS;
 168         uint32_t PREFETCH_SETTINGS;
 169         uint32_t VBLANK_PARAMETERS_0;
 170         uint32_t REF_FREQ_TO_PIX_FREQ;
 171         uint32_t VBLANK_PARAMETERS_1;
 172         uint32_t VBLANK_PARAMETERS_3;
 173         uint32_t NOM_PARAMETERS_0;
 174         uint32_t NOM_PARAMETERS_1;
 175         uint32_t NOM_PARAMETERS_4;
 176         uint32_t NOM_PARAMETERS_5;
 177         uint32_t PER_LINE_DELIVERY_PRE;
 178         uint32_t PER_LINE_DELIVERY;
 179         uint32_t PREFETCH_SETTINS_C;
 180         uint32_t PREFETCH_SETTINGS_C;
 181         uint32_t VBLANK_PARAMETERS_2;
 182         uint32_t VBLANK_PARAMETERS_4;
 183         uint32_t NOM_PARAMETERS_2;
 184         uint32_t NOM_PARAMETERS_3;
 185         uint32_t NOM_PARAMETERS_6;
 186         uint32_t NOM_PARAMETERS_7;
 187         uint32_t DCN_TTU_QOS_WM;
 188         uint32_t DCN_GLOBAL_TTU_CNTL;
 189         uint32_t DCN_SURF0_TTU_CNTL0;
 190         uint32_t DCN_SURF0_TTU_CNTL1;
 191         uint32_t DCN_SURF1_TTU_CNTL0;
 192         uint32_t DCN_SURF1_TTU_CNTL1;
 193         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
 194         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
 195         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
 196         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
 197         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
 198         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
 199         uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
 200         uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
 201         uint32_t DCN_VM_MX_L1_TLB_CNTL;
 202         uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
 203         uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
 204         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
 205         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
 206         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
 207         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
 208         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
 209         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
 210         uint32_t DCHUBBUB_SDPIF_FB_BASE;
 211         uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
 212         uint32_t DCN_VM_FB_LOCATION_TOP;
 213         uint32_t DCN_VM_FB_LOCATION_BASE;
 214         uint32_t DCN_VM_FB_OFFSET;
 215         uint32_t DCN_VM_AGP_BASE;
 216         uint32_t DCN_VM_AGP_BOT;
 217         uint32_t DCN_VM_AGP_TOP;
 218 };
 219
 220 #define MI_SF(reg_name, field_name, post_fix)\
 221         .field_name = reg_name ## __ ## field_name ## post_fix
 222
 223 #define MI_MASK_SH_LIST_DCN(mask_sh)\
 224         MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
 225         MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
 226         MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
 227         MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
 228         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
 229         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
 230         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
 231         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
 232         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
 233         MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
 234         MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
 235         MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
 236         MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
 237         MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
 238         MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
 239         MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
 240         MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
 241         MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
 242         MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
 243         MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
 244         MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
 245         MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
 246         MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
 247         MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
 248         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
 249         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
 250         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
 251         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
 252         MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
 253         MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
 254         MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
 255         MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
 256         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
 257         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
 258         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
 259         MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
 260         MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 261         MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
 262         MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 263         MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
 264         MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
 265         MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
 266         MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
 267         MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
 268         MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
 269         MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
 270         MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
 271         MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
 272         MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
 273         MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
 274         MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
 275         MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
 276         MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
 277         MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
 278         MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
 279         MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
 280         MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
 281         MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
 282         MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
 283         MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
 284         MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
 285         MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
 286         MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
 287         MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
 288         MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
 289         MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
 290         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
 291         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
 292         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
 293         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
 294         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
 295         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
 296         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
 297         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
 298         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
 299         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
 300         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
 301         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
 302         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
 303         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
 304         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
 305         MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
 306         MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
 307         MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
 308         MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
 309         MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
 310         MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
 311         MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
 312         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
 313         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
 314         MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
 315         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
 316         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
 317         MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
 318         MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
 319         MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
 320         MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
 321         MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
 322         MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
 323         MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
 324         MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
 325         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
 326         MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
 327         MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
 328         MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
 329         MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
 330         MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
 331         MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
 332         MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
 333         MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
 334         MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
 335         MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
 336         MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
 337         MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
 338         MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
 339         MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
 340         MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
 341
 342 #define MI_MASK_SH_LIST_DCN10(mask_sh)\
 343         MI_MASK_SH_LIST_DCN(mask_sh),\
 344         MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
 345         MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
 346         MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
 347         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
 348         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
 349         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
 350         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
 351         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
 352         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
 353         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
 354         MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
 355         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
 356         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
 357         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
 358         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
 359         MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
 360         MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
 361         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
 362         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
 363         MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
 364
 365 #define DCN_MI_REG_FIELD_LIST(type) \
 366         type HUBP_BLANK_EN;\
 367         type HUBP_TTU_DISABLE;\
 368         type HUBP_NO_OUTSTANDING_REQ;\
 369         type HUBP_UNDERFLOW_STATUS;\
 370         type NUM_PIPES;\
 371         type NUM_BANKS;\
 372         type PIPE_INTERLEAVE;\
 373         type NUM_SE;\
 374         type NUM_RB_PER_SE;\
 375         type MAX_COMPRESSED_FRAGS;\
 376         type SW_MODE;\
 377         type META_LINEAR;\
 378         type RB_ALIGNED;\
 379         type PIPE_ALIGNED;\
 380         type PITCH;\
 381         type META_PITCH;\
 382         type PITCH_C;\
 383         type META_PITCH_C;\
 384         type ROTATION_ANGLE;\
 385         type H_MIRROR_EN;\
 386         type SURFACE_PIXEL_FORMAT;\
 387         type SURFACE_FLIP_TYPE;\
 388         type SURFACE_UPDATE_LOCK;\
 389         type SURFACE_FLIP_PENDING;\
 390         type PRI_VIEWPORT_WIDTH; \
 391         type PRI_VIEWPORT_HEIGHT; \
 392         type PRI_VIEWPORT_X_START; \
 393         type PRI_VIEWPORT_Y_START; \
 394         type SEC_VIEWPORT_WIDTH; \
 395         type SEC_VIEWPORT_HEIGHT; \
 396         type SEC_VIEWPORT_X_START; \
 397         type SEC_VIEWPORT_Y_START; \
 398         type PRI_VIEWPORT_WIDTH_C; \
 399         type PRI_VIEWPORT_HEIGHT_C; \
 400         type PRI_VIEWPORT_X_START_C; \
 401         type PRI_VIEWPORT_Y_START_C; \
 402         type PRIMARY_SURFACE_ADDRESS_HIGH;\
 403         type PRIMARY_SURFACE_ADDRESS;\
 404         type SECONDARY_SURFACE_ADDRESS_HIGH;\
 405         type SECONDARY_SURFACE_ADDRESS;\
 406         type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
 407         type PRIMARY_META_SURFACE_ADDRESS;\
 408         type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
 409         type SECONDARY_META_SURFACE_ADDRESS;\
 410         type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
 411         type PRIMARY_SURFACE_ADDRESS_C;\
 412         type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
 413         type PRIMARY_META_SURFACE_ADDRESS_C;\
 414         type SURFACE_INUSE_ADDRESS;\
 415         type SURFACE_INUSE_ADDRESS_HIGH;\
 416         type SURFACE_INUSE_ADDRESS_C;\
 417         type SURFACE_INUSE_ADDRESS_HIGH_C;\
 418         type SURFACE_EARLIEST_INUSE_ADDRESS;\
 419         type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
 420         type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
 421         type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
 422         type PRIMARY_SURFACE_TMZ;\
 423         type PRIMARY_SURFACE_DCC_EN;\
 424         type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
 425         type DET_BUF_PLANE1_BASE_ADDRESS;\
 426         type CROSSBAR_SRC_CB_B;\
 427         type CROSSBAR_SRC_CR_R;\
 428         type DRQ_EXPANSION_MODE;\
 429         type PRQ_EXPANSION_MODE;\
 430         type MRQ_EXPANSION_MODE;\
 431         type CRQ_EXPANSION_MODE;\
 432         type CHUNK_SIZE;\
 433         type MIN_CHUNK_SIZE;\
 434         type META_CHUNK_SIZE;\
 435         type MIN_META_CHUNK_SIZE;\
 436         type DPTE_GROUP_SIZE;\
 437         type MPTE_GROUP_SIZE;\
 438         type SWATH_HEIGHT;\
 439         type PTE_ROW_HEIGHT_LINEAR;\
 440         type CHUNK_SIZE_C;\
 441         type MIN_CHUNK_SIZE_C;\
 442         type META_CHUNK_SIZE_C;\
 443         type MIN_META_CHUNK_SIZE_C;\
 444         type DPTE_GROUP_SIZE_C;\
 445         type MPTE_GROUP_SIZE_C;\
 446         type SWATH_HEIGHT_C;\
 447         type PTE_ROW_HEIGHT_LINEAR_C;\
 448         type REFCYC_H_BLANK_END;\
 449         type DLG_V_BLANK_END;\
 450         type MIN_DST_Y_NEXT_START;\
 451         type REFCYC_PER_HTOTAL;\
 452         type REFCYC_X_AFTER_SCALER;\
 453         type DST_Y_AFTER_SCALER;\
 454         type DST_Y_PREFETCH;\
 455         type VRATIO_PREFETCH;\
 456         type DST_Y_PER_VM_VBLANK;\
 457         type DST_Y_PER_ROW_VBLANK;\
 458         type REF_FREQ_TO_PIX_FREQ;\
 459         type REFCYC_PER_PTE_GROUP_VBLANK_L;\
 460         type REFCYC_PER_META_CHUNK_VBLANK_L;\
 461         type DST_Y_PER_PTE_ROW_NOM_L;\
 462         type REFCYC_PER_PTE_GROUP_NOM_L;\
 463         type DST_Y_PER_META_ROW_NOM_L;\
 464         type REFCYC_PER_META_CHUNK_NOM_L;\
 465         type REFCYC_PER_LINE_DELIVERY_PRE_L;\
 466         type REFCYC_PER_LINE_DELIVERY_PRE_C;\
 467         type REFCYC_PER_LINE_DELIVERY_L;\
 468         type REFCYC_PER_LINE_DELIVERY_C;\
 469         type VRATIO_PREFETCH_C;\
 470         type REFCYC_PER_PTE_GROUP_VBLANK_C;\
 471         type REFCYC_PER_META_CHUNK_VBLANK_C;\
 472         type DST_Y_PER_PTE_ROW_NOM_C;\
 473         type REFCYC_PER_PTE_GROUP_NOM_C;\
 474         type DST_Y_PER_META_ROW_NOM_C;\
 475         type REFCYC_PER_META_CHUNK_NOM_C;\
 476         type QoS_LEVEL_LOW_WM;\
 477         type QoS_LEVEL_HIGH_WM;\
 478         type MIN_TTU_VBLANK;\
 479         type QoS_LEVEL_FLIP;\
 480         type REFCYC_PER_REQ_DELIVERY;\
 481         type QoS_LEVEL_FIXED;\
 482         type QoS_RAMP_DISABLE;\
 483         type REFCYC_PER_REQ_DELIVERY_PRE;\
 484         type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
 485         type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
 486         type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
 487         type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
 488         type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
 489         type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
 490         type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
 491         type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
 492         type ENABLE_L1_TLB;\
 493         type SYSTEM_ACCESS_MODE;\
 494         type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
 495         type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
 496         type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
 497         type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
 498         type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
 499         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
 500         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
 501         type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
 502         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
 503         type SDPIF_FB_TOP;\
 504         type SDPIF_FB_BASE;\
 505         type SDPIF_FB_OFFSET;\
 506         type SDPIF_AGP_BASE;\
 507         type SDPIF_AGP_BOT;\
 508         type SDPIF_AGP_TOP;\
 509         type FB_TOP;\
 510         type FB_BASE;\
 511         type FB_OFFSET;\
 512         type AGP_BASE;\
 513         type AGP_BOT;\
 514         type AGP_TOP;\
 515         /* todo:  get these from GVM instead of reading registers ourselves */\
 516         type PAGE_DIRECTORY_ENTRY_HI32;\
 517         type PAGE_DIRECTORY_ENTRY_LO32;\
 518         type LOGICAL_PAGE_NUMBER_HI4;\
 519         type LOGICAL_PAGE_NUMBER_LO32;\
 520         type PHYSICAL_PAGE_ADDR_HI4;\
 521         type PHYSICAL_PAGE_ADDR_LO32;\
 522         type PHYSICAL_PAGE_NUMBER_MSB;\
 523         type PHYSICAL_PAGE_NUMBER_LSB;\
 524         type LOGICAL_ADDR
 525
 526 struct dcn_mi_shift {
 527         DCN_MI_REG_FIELD_LIST(uint8_t);
 528 };
 529
 530 struct dcn_mi_mask {
 531         DCN_MI_REG_FIELD_LIST(uint32_t);
 532 };
 533
 534 struct dcn10_mem_input {
 535         struct mem_input base;
 536         const struct dcn_mi_registers *mi_regs;
 537         const struct dcn_mi_shift *mi_shift;
 538         const struct dcn_mi_mask *mi_mask;
 539 };
 540
 541 bool dcn10_mem_input_construct(
 542         struct dcn10_mem_input *mi,
 543         struct dc_context *ctx,
 544         uint32_t inst,
 545         const struct dcn_mi_registers *mi_regs,
 546         const struct dcn_mi_shift *mi_shift,
 547         const struct dcn_mi_mask *mi_mask);
 548
 549 struct dcn_hubp_state {
 550         uint32_t pixel_format;
 551         uint32_t inuse_addr_hi;
 552         uint32_t viewport_width;
 553         uint32_t viewport_height;
 554         uint32_t rotation_angle;
 555         uint32_t h_mirror_en;
 556         uint32_t sw_mode;
 557         uint32_t dcc_en;
 558         uint32_t blank_en;
 559         uint32_t underflow_status;
 560         uint32_t ttu_disable;
 561         uint32_t min_ttu_vblank;
 562         uint32_t qos_level_low_wm;
 563         uint32_t qos_level_high_wm;
 564 };
 565 void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
 566                 struct dcn_hubp_state *s);
 567
 568 #endif