drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h

   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24
  25 #ifndef __DC_MPCC_DCN10_H__
  26 #define __DC_MPCC_DCN10_H__
  27
  28 #include "mpc.h"
  29
  30 #define TO_DCN10_MPCC(mpcc_base) \
  31         container_of(mpcc_base, struct dcn10_mpcc, base)
  32
  33 #define MAX_OPP 4
  34
  35 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \
  36         SRII(MUX, MPC_OUT, inst),\
  37         SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst)
  38
  39 #define MPCC_COMMON_REG_LIST_DCN1_0(inst) \
  40         SRI(MPCC_TOP_SEL, MPCC, inst),\
  41         SRI(MPCC_BOT_SEL, MPCC, inst),\
  42         SRI(MPCC_CONTROL, MPCC, inst),\
  43         SRI(MPCC_STATUS, MPCC, inst),\
  44         SRI(MPCC_OPP_ID, MPCC, inst),\
  45         SRI(MPCC_BG_G_Y, MPCC, inst),\
  46         SRI(MPCC_BG_R_CR, MPCC, inst),\
  47         SRI(MPCC_BG_B_CB, MPCC, inst),\
  48         SRI(MPCC_BG_B_CB, MPCC, inst)
  49
  50 struct dcn_mpcc_registers {
  51         uint32_t MPCC_TOP_SEL;
  52         uint32_t MPCC_BOT_SEL;
  53         uint32_t MPCC_CONTROL;
  54         uint32_t MPCC_STATUS;
  55         uint32_t MPCC_OPP_ID;
  56         uint32_t MPCC_BG_G_Y;
  57         uint32_t MPCC_BG_R_CR;
  58         uint32_t MPCC_BG_B_CB;
  59         uint32_t OPP_PIPE_CONTROL[MAX_OPP];
  60         uint32_t MUX[MAX_OPP];
  61 };
  62
  63 #define MPCC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
  64         SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
  65         SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
  66         SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
  67         SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
  68         SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
  69         SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
  70         SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
  71         SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
  72         SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
  73         SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
  74         SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
  75         SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
  76         SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh)
  77
  78 #define MPCC_REG_FIELD_LIST(type) \
  79         type MPCC_TOP_SEL;\
  80         type MPCC_BOT_SEL;\
  81         type MPCC_MODE;\
  82         type MPCC_ALPHA_BLND_MODE;\
  83         type MPCC_ALPHA_MULTIPLIED_MODE;\
  84         type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
  85         type MPCC_IDLE;\
  86         type MPCC_OPP_ID;\
  87         type MPCC_BG_G_Y;\
  88         type MPCC_BG_R_CR;\
  89         type MPCC_BG_B_CB;\
  90         type MPC_OUT_MUX;\
  91         type OPP_PIPE_CLOCK_EN;\
  92
  93 struct dcn_mpcc_shift {
  94         MPCC_REG_FIELD_LIST(uint8_t)
  95 };
  96
  97 struct dcn_mpcc_mask {
  98         MPCC_REG_FIELD_LIST(uint32_t)
  99 };
 100
 101 struct dcn10_mpcc {
 102         struct mpcc base;
 103         const struct dcn_mpcc_registers *mpcc_regs;
 104         const struct dcn_mpcc_shift *mpcc_shift;
 105         const struct dcn_mpcc_mask *mpcc_mask;
 106
 107         int opp_id;
 108 };
 109
 110 void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10,
 111         struct dc_context *ctx,
 112         const struct dcn_mpcc_registers *mpcc_regs,
 113         const struct dcn_mpcc_shift *mpcc_shift,
 114         const struct dcn_mpcc_mask *mpcc_mask,
 115         int inst);
 116
 117 #endif