drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h

   1 /* Copyright 2017 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24 #ifndef __DCN20_DSC_H__
  25 #define __DCN20_DSC_H__
  26
  27 #include "dsc.h"
  28 #include "dsc/dscc_types.h"
  29 #include <drm/drm_dsc.h>
  30
  31 #define TO_DCN20_DSC(dsc)\
  32         container_of(dsc, struct dcn20_dsc, base)
  33
  34 #define DSC_REG_LIST_DCN20(id) \
  35         SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
  36         SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\
  37         SRI(DSCC_CONFIG0, DSCC, id),\
  38         SRI(DSCC_CONFIG1, DSCC, id),\
  39         SRI(DSCC_STATUS, DSCC, id),\
  40         SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\
  41         SRI(DSCC_PPS_CONFIG0, DSCC, id),\
  42         SRI(DSCC_PPS_CONFIG1, DSCC, id),\
  43         SRI(DSCC_PPS_CONFIG2, DSCC, id),\
  44         SRI(DSCC_PPS_CONFIG3, DSCC, id),\
  45         SRI(DSCC_PPS_CONFIG4, DSCC, id),\
  46         SRI(DSCC_PPS_CONFIG5, DSCC, id),\
  47         SRI(DSCC_PPS_CONFIG6, DSCC, id),\
  48         SRI(DSCC_PPS_CONFIG7, DSCC, id),\
  49         SRI(DSCC_PPS_CONFIG8, DSCC, id),\
  50         SRI(DSCC_PPS_CONFIG9, DSCC, id),\
  51         SRI(DSCC_PPS_CONFIG10, DSCC, id),\
  52         SRI(DSCC_PPS_CONFIG11, DSCC, id),\
  53         SRI(DSCC_PPS_CONFIG12, DSCC, id),\
  54         SRI(DSCC_PPS_CONFIG13, DSCC, id),\
  55         SRI(DSCC_PPS_CONFIG14, DSCC, id),\
  56         SRI(DSCC_PPS_CONFIG15, DSCC, id),\
  57         SRI(DSCC_PPS_CONFIG16, DSCC, id),\
  58         SRI(DSCC_PPS_CONFIG17, DSCC, id),\
  59         SRI(DSCC_PPS_CONFIG18, DSCC, id),\
  60         SRI(DSCC_PPS_CONFIG19, DSCC, id),\
  61         SRI(DSCC_PPS_CONFIG20, DSCC, id),\
  62         SRI(DSCC_PPS_CONFIG21, DSCC, id),\
  63         SRI(DSCC_PPS_CONFIG22, DSCC, id),\
  64         SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\
  65         SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\
  66         SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\
  67         SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\
  68         SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\
  69         SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\
  70         SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\
  71         SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\
  72         SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\
  73         SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
  74         SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
  75         SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
  76         SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
  77         SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
  78         SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
  79         SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
  80         SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
  81         SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\
  82         SRI(DSCCIF_CONFIG0, DSCCIF, id),\
  83         SRI(DSCCIF_CONFIG1, DSCCIF, id),\
  84         SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
  85
  86
  87 #define DSC_SF(reg_name, field_name, post_fix)\
  88         .field_name = reg_name ## __ ## field_name ## post_fix
  89
  90 //Used in resolving the corner case with duplicate field name
  91 #define DSC2_SF(reg_name, field_name, post_fix)\
  92         .field_name = reg_name ## _ ## field_name ## post_fix
  93
  94 #define DSC_REG_LIST_SH_MASK_DCN20(mask_sh)\
  95         DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
  96         DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
  97         DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
  98         DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
  99         DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
 100         DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
 101         DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
 102         DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
 103         DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
 104         DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
 105         /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
 106         DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
 107         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
 108         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
 109         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
 110         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
 111         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
 112         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
 113         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
 114         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
 115         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
 116         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
 117         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
 118         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
 119         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 120         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 121         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 122         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 123         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
 124         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
 125         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
 126         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
 127         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 128         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 129         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 130         DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
 131         DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
 132         DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
 133         DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
 134         DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
 135         DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
 136         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
 137         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
 138         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
 139         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
 140         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
 141         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
 142         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
 143         DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
 144         DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
 145         DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
 146         DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
 147         DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
 148         DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
 149         DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
 150         DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
 151         DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
 152         DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
 153         DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
 154         DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
 155         DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
 156         DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
 157         DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
 158         DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
 159         DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
 160         DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
 161         DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \
 162         DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
 163         DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
 164         DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
 165         DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
 166         DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
 167         DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
 168         DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
 169         DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
 170         DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
 171         DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
 172         DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
 173         DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
 174         DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
 175         DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
 176         DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
 177         DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
 178         DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
 179         DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
 180         DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
 181         DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
 182         DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
 183         DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
 184         DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
 185         DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
 186         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
 187         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
 188         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
 189         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
 190         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
 191         DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
 192         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
 193         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
 194         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
 195         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
 196         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
 197         DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
 198         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
 199         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
 200         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
 201         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
 202         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
 203         DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
 204         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
 205         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
 206         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
 207         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
 208         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
 209         DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
 210         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
 211         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
 212         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
 213         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
 214         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
 215         DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
 216         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
 217         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
 218         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
 219         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
 220         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
 221         DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
 222         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
 223         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
 224         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
 225         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
 226         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
 227         DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
 228         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
 229         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \
 230         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \
 231         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \
 232         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \
 233         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \
 234         DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \
 235         DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
 236         DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
 237         DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
 238         DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
 239         DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
 240         DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
 241         DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
 242         DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
 243         DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
 244         DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
 245         DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
 246         DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
 247         DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
 248         DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
 249         DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
 250         DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
 251         DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
 252         DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \
 253         DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \
 254         DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \
 255         DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \
 256         DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
 257         DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
 258         DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
 259         DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
 260         DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
 261         DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
 262         DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \
 263         DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \
 264         DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
 265         DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)
 266
 267
 268
 269 #define DSC_FIELD_LIST_DCN20(type)\
 270         type DSC_CLOCK_EN; \
 271         type DSC_DISPCLK_R_GATE_DIS; \
 272         type DSC_DSCCLK_R_GATE_DIS; \
 273         type DSC_DBG_EN; \
 274         type DSC_TEST_CLOCK_MUX_SEL; \
 275         type ICH_RESET_AT_END_OF_LINE; \
 276         type NUMBER_OF_SLICES_PER_LINE; \
 277         type ALTERNATE_ICH_ENCODING_EN; \
 278         type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
 279         type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
 280         /*type DSCC_DISABLE_ICH;*/ \
 281         type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
 282         type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
 283         type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
 284         type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED; \
 285         type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED; \
 286         type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED; \
 287         type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED; \
 288         type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED; \
 289         type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED; \
 290         type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED; \
 291         type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED; \
 292         type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED; \
 293         type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED; \
 294         type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN; \
 295         type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN; \
 296         type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN; \
 297         type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN; \
 298         type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN; \
 299         type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN; \
 300         type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN; \
 301         type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN; \
 302         type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN; \
 303         type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN; \
 304         type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN; \
 305         type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN; \
 306         type DSC_VERSION_MINOR; \
 307         type DSC_VERSION_MAJOR; \
 308         type PPS_IDENTIFIER; \
 309         type LINEBUF_DEPTH; \
 310         type DSCC_PPS_CONFIG0__BITS_PER_COMPONENT; \
 311         type BITS_PER_PIXEL; \
 312         type VBR_ENABLE; \
 313         type SIMPLE_422; \
 314         type CONVERT_RGB; \
 315         type BLOCK_PRED_ENABLE; \
 316         type NATIVE_422; \
 317         type NATIVE_420; \
 318         type CHUNK_SIZE; \
 319         type PIC_WIDTH; \
 320         type PIC_HEIGHT; \
 321         type SLICE_WIDTH; \
 322         type SLICE_HEIGHT; \
 323         type INITIAL_XMIT_DELAY; \
 324         type INITIAL_DEC_DELAY; \
 325         type INITIAL_SCALE_VALUE; \
 326         type SCALE_INCREMENT_INTERVAL; \
 327         type SCALE_DECREMENT_INTERVAL; \
 328         type FIRST_LINE_BPG_OFFSET; \
 329         type SECOND_LINE_BPG_OFFSET; \
 330         type NFL_BPG_OFFSET; \
 331         type SLICE_BPG_OFFSET; \
 332         type NSL_BPG_OFFSET; \
 333         type SECOND_LINE_OFFSET_ADJ; \
 334         type INITIAL_OFFSET; \
 335         type FINAL_OFFSET; \
 336         type FLATNESS_MIN_QP; \
 337         type FLATNESS_MAX_QP; \
 338         type RC_MODEL_SIZE; \
 339         type RC_EDGE_FACTOR; \
 340         type RC_QUANT_INCR_LIMIT0; \
 341         type RC_QUANT_INCR_LIMIT1; \
 342         type RC_TGT_OFFSET_LO; \
 343         type RC_TGT_OFFSET_HI; \
 344         type RC_BUF_THRESH0; \
 345         type RC_BUF_THRESH1; \
 346         type RC_BUF_THRESH2; \
 347         type RC_BUF_THRESH3; \
 348         type RC_BUF_THRESH4; \
 349         type RC_BUF_THRESH5; \
 350         type RC_BUF_THRESH6; \
 351         type RC_BUF_THRESH7; \
 352         type RC_BUF_THRESH8; \
 353         type RC_BUF_THRESH9; \
 354         type RC_BUF_THRESH10; \
 355         type RC_BUF_THRESH11; \
 356         type RC_BUF_THRESH12; \
 357         type RC_BUF_THRESH13; \
 358         type RANGE_MIN_QP0; \
 359         type RANGE_MAX_QP0; \
 360         type RANGE_BPG_OFFSET0; \
 361         type RANGE_MIN_QP1; \
 362         type RANGE_MAX_QP1; \
 363         type RANGE_BPG_OFFSET1; \
 364         type RANGE_MIN_QP2; \
 365         type RANGE_MAX_QP2; \
 366         type RANGE_BPG_OFFSET2; \
 367         type RANGE_MIN_QP3; \
 368         type RANGE_MAX_QP3; \
 369         type RANGE_BPG_OFFSET3; \
 370         type RANGE_MIN_QP4; \
 371         type RANGE_MAX_QP4; \
 372         type RANGE_BPG_OFFSET4; \
 373         type RANGE_MIN_QP5; \
 374         type RANGE_MAX_QP5; \
 375         type RANGE_BPG_OFFSET5; \
 376         type RANGE_MIN_QP6; \
 377         type RANGE_MAX_QP6; \
 378         type RANGE_BPG_OFFSET6; \
 379         type RANGE_MIN_QP7; \
 380         type RANGE_MAX_QP7; \
 381         type RANGE_BPG_OFFSET7; \
 382         type RANGE_MIN_QP8; \
 383         type RANGE_MAX_QP8; \
 384         type RANGE_BPG_OFFSET8; \
 385         type RANGE_MIN_QP9; \
 386         type RANGE_MAX_QP9; \
 387         type RANGE_BPG_OFFSET9; \
 388         type RANGE_MIN_QP10; \
 389         type RANGE_MAX_QP10; \
 390         type RANGE_BPG_OFFSET10; \
 391         type RANGE_MIN_QP11; \
 392         type RANGE_MAX_QP11; \
 393         type RANGE_BPG_OFFSET11; \
 394         type RANGE_MIN_QP12; \
 395         type RANGE_MAX_QP12; \
 396         type RANGE_BPG_OFFSET12; \
 397         type RANGE_MIN_QP13; \
 398         type RANGE_MAX_QP13; \
 399         type RANGE_BPG_OFFSET13; \
 400         type RANGE_MIN_QP14; \
 401         type RANGE_MAX_QP14; \
 402         type RANGE_BPG_OFFSET14; \
 403         type DSCC_DEFAULT_MEM_LOW_POWER_STATE; \
 404         type DSCC_MEM_PWR_FORCE; \
 405         type DSCC_MEM_PWR_DIS; \
 406         type DSCC_MEM_PWR_STATE; \
 407         type DSCC_NATIVE_422_MEM_PWR_FORCE; \
 408         type DSCC_NATIVE_422_MEM_PWR_DIS; \
 409         type DSCC_NATIVE_422_MEM_PWR_STATE; \
 410         type DSCC_R_Y_SQUARED_ERROR_LOWER; \
 411         type DSCC_R_Y_SQUARED_ERROR_UPPER; \
 412         type DSCC_G_CB_SQUARED_ERROR_LOWER; \
 413         type DSCC_G_CB_SQUARED_ERROR_UPPER; \
 414         type DSCC_B_CR_SQUARED_ERROR_LOWER; \
 415         type DSCC_B_CR_SQUARED_ERROR_UPPER; \
 416         type DSCC_R_Y_MAX_ABS_ERROR; \
 417         type DSCC_G_CB_MAX_ABS_ERROR; \
 418         type DSCC_B_CR_MAX_ABS_ERROR; \
 419         type DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL; \
 420         type DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL; \
 421         type DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL; \
 422         type DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL; \
 423         type DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL; \
 424         type DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; \
 425         type DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; \
 426         type DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; \
 427         type DSCC_UPDATE_PENDING_STATUS; \
 428         type DSCC_UPDATE_TAKEN_STATUS; \
 429         type DSCC_UPDATE_TAKEN_ACK; \
 430         type DSCC_TEST_DEBUG_BUS0_ROTATE; \
 431         type DSCC_TEST_DEBUG_BUS1_ROTATE; \
 432         type DSCC_TEST_DEBUG_BUS2_ROTATE; \
 433         type DSCC_TEST_DEBUG_BUS3_ROTATE; \
 434         type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
 435         type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
 436         type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
 437         type DSCC_RATE_BUFFER3_FULLNESS_LEVEL; \
 438         type DSCC_RATE_CONTROL_BUFFER0_FULLNESS_LEVEL; \
 439         type DSCC_RATE_CONTROL_BUFFER1_FULLNESS_LEVEL; \
 440         type DSCC_RATE_CONTROL_BUFFER2_FULLNESS_LEVEL; \
 441         type DSCC_RATE_CONTROL_BUFFER3_FULLNESS_LEVEL; \
 442         type DSCC_RATE_BUFFER0_INITIAL_XMIT_DELAY_REACHED; \
 443         type DSCC_RATE_BUFFER1_INITIAL_XMIT_DELAY_REACHED; \
 444         type DSCC_RATE_BUFFER2_INITIAL_XMIT_DELAY_REACHED; \
 445         type DSCC_RATE_BUFFER3_INITIAL_XMIT_DELAY_REACHED; \
 446         type INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN; \
 447         type INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN; \
 448         type INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS; \
 449         type INPUT_PIXEL_FORMAT; \
 450         type DSCCIF_CONFIG0__BITS_PER_COMPONENT; \
 451         type DOUBLE_BUFFER_REG_UPDATE_PENDING; \
 452         type DSCCIF_UPDATE_PENDING_STATUS; \
 453         type DSCCIF_UPDATE_TAKEN_STATUS; \
 454         type DSCCIF_UPDATE_TAKEN_ACK; \
 455         type DSCRM_DSC_FORWARD_EN; \
 456         type DSCRM_DSC_OPP_PIPE_SOURCE
 457
 458
 459 struct dcn20_dsc_registers {
 460         uint32_t DSC_TOP_CONTROL;
 461         uint32_t DSC_DEBUG_CONTROL;
 462         uint32_t DSCC_CONFIG0;
 463         uint32_t DSCC_CONFIG1;
 464         uint32_t DSCC_STATUS;
 465         uint32_t DSCC_INTERRUPT_CONTROL_STATUS;
 466         uint32_t DSCC_PPS_CONFIG0;
 467         uint32_t DSCC_PPS_CONFIG1;
 468         uint32_t DSCC_PPS_CONFIG2;
 469         uint32_t DSCC_PPS_CONFIG3;
 470         uint32_t DSCC_PPS_CONFIG4;
 471         uint32_t DSCC_PPS_CONFIG5;
 472         uint32_t DSCC_PPS_CONFIG6;
 473         uint32_t DSCC_PPS_CONFIG7;
 474         uint32_t DSCC_PPS_CONFIG8;
 475         uint32_t DSCC_PPS_CONFIG9;
 476         uint32_t DSCC_PPS_CONFIG10;
 477         uint32_t DSCC_PPS_CONFIG11;
 478         uint32_t DSCC_PPS_CONFIG12;
 479         uint32_t DSCC_PPS_CONFIG13;
 480         uint32_t DSCC_PPS_CONFIG14;
 481         uint32_t DSCC_PPS_CONFIG15;
 482         uint32_t DSCC_PPS_CONFIG16;
 483         uint32_t DSCC_PPS_CONFIG17;
 484         uint32_t DSCC_PPS_CONFIG18;
 485         uint32_t DSCC_PPS_CONFIG19;
 486         uint32_t DSCC_PPS_CONFIG20;
 487         uint32_t DSCC_PPS_CONFIG21;
 488         uint32_t DSCC_PPS_CONFIG22;
 489         uint32_t DSCC_MEM_POWER_CONTROL;
 490         uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;
 491         uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;
 492         uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;
 493         uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;
 494         uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;
 495         uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;
 496         uint32_t DSCC_MAX_ABS_ERROR0;
 497         uint32_t DSCC_MAX_ABS_ERROR1;
 498         uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL;
 499         uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL;
 500         uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL;
 501         uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL;
 502         uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL;
 503         uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
 504         uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
 505         uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
 506         uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;
 507         uint32_t DSCCIF_CONFIG0;
 508         uint32_t DSCCIF_CONFIG1;
 509         uint32_t DSCRM_DSC_FORWARD_CONFIG;
 510 };
 511
 512
 513 struct dcn20_dsc_shift {
 514         DSC_FIELD_LIST_DCN20(uint8_t);
 515 };
 516
 517 struct dcn20_dsc_mask {
 518         DSC_FIELD_LIST_DCN20(uint32_t);
 519 };
 520
 521 /* DSCCIF_CONFIG.INPUT_PIXEL_FORMAT values */
 522 enum dsc_pixel_format {
 523         DSC_PIXFMT_RGB,
 524         DSC_PIXFMT_YCBCR444,
 525         DSC_PIXFMT_SIMPLE_YCBCR422,
 526         DSC_PIXFMT_NATIVE_YCBCR422,
 527         DSC_PIXFMT_NATIVE_YCBCR420,
 528         DSC_PIXFMT_UNKNOWN
 529 };
 530
 531 struct dsc_reg_values {
 532         /* PPS registers */
 533         struct drm_dsc_config pps;
 534
 535         /* Additional registers */
 536         uint32_t dsc_clock_enable;
 537         uint32_t dsc_clock_gating_disable;
 538         uint32_t underflow_recovery_en;
 539         uint32_t underflow_occurred_int_en;
 540         uint32_t underflow_occurred_status;
 541         enum dsc_pixel_format pixel_format;
 542         uint32_t ich_reset_at_eol;
 543         uint32_t alternate_ich_encoding_en;
 544         uint32_t num_slices_h;
 545         uint32_t num_slices_v;
 546         uint32_t rc_buffer_model_size;
 547         uint32_t disable_ich;
 548         uint32_t bpp_x32;
 549         uint32_t dsc_dbg_en;
 550         uint32_t rc_buffer_model_overflow_int_en[4];
 551 };
 552
 553 struct dcn20_dsc {
 554         struct display_stream_compressor base;
 555         const struct dcn20_dsc_registers *dsc_regs;
 556         const struct dcn20_dsc_shift *dsc_shift;
 557         const struct dcn20_dsc_mask *dsc_mask;
 558
 559         struct dsc_reg_values reg_vals;
 560
 561         int max_image_width;
 562 };
 563
 564
 565 void dsc2_construct(struct dcn20_dsc *dsc,
 566                 struct dc_context *ctx,
 567                 int inst,
 568                 const struct dcn20_dsc_registers *dsc_regs,
 569                 const struct dcn20_dsc_shift *dsc_shift,
 570                 const struct dcn20_dsc_mask *dsc_mask);
 571
 572 #endif
 573