drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #if defined(CONFIG_DRM_AMD_DC_DCN)
  26 #include "dm_services.h"
  27 #include "include/gpio_types.h"
  28 #include "../hw_factory.h"
  29
  30
  31 #include "../hw_gpio.h"
  32 #include "../hw_ddc.h"
  33 #include "../hw_hpd.h"
  34 #include "../hw_generic.h"
  35
  36 #include "hw_factory_dcn30.h"
  37
  38
  39 #include "sienna_cichlid_ip_offset.h"
  40 #include "dcn/dcn_3_0_0_offset.h"
  41 #include "dcn/dcn_3_0_0_sh_mask.h"
  42
  43 #include "nbio/nbio_7_4_offset.h"
  44
  45 #include "dpcs/dpcs_3_0_0_offset.h"
  46 #include "dpcs/dpcs_3_0_0_sh_mask.h"
  47
  48 #include "mmhub/mmhub_2_0_0_offset.h"
  49 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  50
  51 #include "reg_helper.h"
  52 #include "../hpd_regs.h"
  53 /* begin *********************
  54  * macros to expend register list macro defined in HW object header file */
  55
  56 /* DCN */
  57 #define block HPD
  58 #define reg_num 0
  59
  60 #undef BASE_INNER
  61 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
  62
  63 #define BASE(seg) BASE_INNER(seg)
  64
  65
  66
  67 #define REG(reg_name)\
  68                 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
  69
  70 #define SF_HPD(reg_name, field_name, post_fix)\
  71         .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
  72
  73 #define REGI(reg_name, block, id)\
  74         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
  75                                 mm ## block ## id ## _ ## reg_name
  76
  77 #define SF(reg_name, field_name, post_fix)\
  78         .field_name = reg_name ## __ ## field_name ## post_fix
  79
  80 /* macros to expend register list macro defined in HW object header file
  81  * end *********************/
  82
  83
  84
  85 #define hpd_regs(id) \
  86 {\
  87         HPD_REG_LIST(id)\
  88 }
  89
  90 static const struct hpd_registers hpd_regs[] = {
  91         hpd_regs(0),
  92         hpd_regs(1),
  93         hpd_regs(2),
  94         hpd_regs(3),
  95         hpd_regs(4),
  96         hpd_regs(5),
  97 };
  98
  99 static const struct hpd_sh_mask hpd_shift = {
 100                 HPD_MASK_SH_LIST(__SHIFT)
 101 };
 102
 103 static const struct hpd_sh_mask hpd_mask = {
 104                 HPD_MASK_SH_LIST(_MASK)
 105 };
 106
 107 #include "../ddc_regs.h"
 108
 109  /* set field name */
 110 #define SF_DDC(reg_name, field_name, post_fix)\
 111         .field_name = reg_name ## __ ## field_name ## post_fix
 112
 113 static const struct ddc_registers ddc_data_regs_dcn[] = {
 114         ddc_data_regs_dcn2(1),
 115         ddc_data_regs_dcn2(2),
 116         ddc_data_regs_dcn2(3),
 117         ddc_data_regs_dcn2(4),
 118         ddc_data_regs_dcn2(5),
 119         ddc_data_regs_dcn2(6),
 120         {
 121                         DDC_GPIO_VGA_REG_LIST(DATA),
 122                         .ddc_setup = 0,
 123                         .phy_aux_cntl = 0,
 124                         .dc_gpio_aux_ctrl_5 = 0
 125         }
 126 };
 127
 128 static const struct ddc_registers ddc_clk_regs_dcn[] = {
 129         ddc_clk_regs_dcn2(1),
 130         ddc_clk_regs_dcn2(2),
 131         ddc_clk_regs_dcn2(3),
 132         ddc_clk_regs_dcn2(4),
 133         ddc_clk_regs_dcn2(5),
 134         ddc_clk_regs_dcn2(6),
 135         {
 136                         DDC_GPIO_VGA_REG_LIST(CLK),
 137                         .ddc_setup = 0,
 138                         .phy_aux_cntl = 0,
 139                         .dc_gpio_aux_ctrl_5 = 0
 140         }
 141 };
 142
 143 static const struct ddc_sh_mask ddc_shift[] = {
 144         DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
 145         DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
 146         DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
 147         DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
 148         DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
 149         DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
 150 };
 151
 152 static const struct ddc_sh_mask ddc_mask[] = {
 153         DDC_MASK_SH_LIST_DCN2(_MASK, 1),
 154         DDC_MASK_SH_LIST_DCN2(_MASK, 2),
 155         DDC_MASK_SH_LIST_DCN2(_MASK, 3),
 156         DDC_MASK_SH_LIST_DCN2(_MASK, 4),
 157         DDC_MASK_SH_LIST_DCN2(_MASK, 5),
 158         DDC_MASK_SH_LIST_DCN2(_MASK, 6)
 159 };
 160
 161 #include "../generic_regs.h"
 162
 163 /* set field name */
 164 #define SF_GENERIC(reg_name, field_name, post_fix)\
 165         .field_name = reg_name ## __ ## field_name ## post_fix
 166
 167 #define generic_regs(id) \
 168 {\
 169         GENERIC_REG_LIST(id)\
 170 }
 171
 172 static const struct generic_registers generic_regs[] = {
 173         generic_regs(A),
 174         generic_regs(B),
 175 };
 176
 177 static const struct generic_sh_mask generic_shift[] = {
 178         GENERIC_MASK_SH_LIST(__SHIFT, A),
 179         GENERIC_MASK_SH_LIST(__SHIFT, B),
 180 };
 181
 182 static const struct generic_sh_mask generic_mask[] = {
 183         GENERIC_MASK_SH_LIST(_MASK, A),
 184         GENERIC_MASK_SH_LIST(_MASK, B),
 185 };
 186
 187 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
 188 {
 189         struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
 190
 191         generic->regs = &generic_regs[en];
 192         generic->shifts = &generic_shift[en];
 193         generic->masks = &generic_mask[en];
 194         generic->base.regs = &generic_regs[en].gpio;
 195 }
 196
 197 static void define_ddc_registers(
 198                 struct hw_gpio_pin *pin,
 199                 uint32_t en)
 200 {
 201         struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
 202
 203         switch (pin->id) {
 204         case GPIO_ID_DDC_DATA:
 205                 ddc->regs = &ddc_data_regs_dcn[en];
 206                 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
 207                 break;
 208         case GPIO_ID_DDC_CLOCK:
 209                 ddc->regs = &ddc_clk_regs_dcn[en];
 210                 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
 211                 break;
 212         default:
 213                 ASSERT_CRITICAL(false);
 214                 return;
 215         }
 216
 217         ddc->shifts = &ddc_shift[en];
 218         ddc->masks = &ddc_mask[en];
 219
 220 }
 221
 222 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
 223 {
 224         struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
 225
 226         hpd->regs = &hpd_regs[en];
 227         hpd->shifts = &hpd_shift;
 228         hpd->masks = &hpd_mask;
 229         hpd->base.regs = &hpd_regs[en].gpio;
 230 }
 231
 232
 233 /* function table */
 234 static const struct hw_factory_funcs funcs = {
 235         .init_ddc_data = dal_hw_ddc_init,
 236         .init_generic = dal_hw_generic_init,
 237         .init_hpd = dal_hw_hpd_init,
 238         .get_ddc_pin = dal_hw_ddc_get_pin,
 239         .get_hpd_pin = dal_hw_hpd_get_pin,
 240         .get_generic_pin = dal_hw_generic_get_pin,
 241         .define_hpd_registers = define_hpd_registers,
 242         .define_ddc_registers = define_ddc_registers,
 243         .define_generic_registers = define_generic_registers
 244 };
 245 /*
 246  * dal_hw_factory_dcn10_init
 247  *
 248  * @brief
 249  * Initialize HW factory function pointers and pin info
 250  *
 251  * @param
 252  * struct hw_factory *factory - [out] struct of function pointers
 253  */
 254 void dal_hw_factory_dcn30_init(struct hw_factory *factory)
 255 {
 256         /*TODO check ASIC CAPs*/
 257         factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
 258         factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
 259         factory->number_of_pins[GPIO_ID_GENERIC] = 4;
 260         factory->number_of_pins[GPIO_ID_HPD] = 6;
 261         factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
 262         factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
 263         factory->number_of_pins[GPIO_ID_SYNC] = 0;
 264         factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
 265
 266         factory->funcs = &funcs;
 267 }
 268
 269 #endif