2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "include/logger_interface.h"
29 * Pre-requisites: headers required by header of this unit
32 #include "include/i2caux_interface.h"
33 #include "../engine.h"
34 #include "../i2c_engine.h"
35 #include "../i2c_hw_engine.h"
36 #include "../i2c_generic_hw_engine.h"
41 #include "i2c_hw_engine_dce110.h"
44 * Post-requisites: headers required by this unit
46 #include "reg_helper.h"
53 DC_I2C_STATUS__DC_I2C_STATUS_IDLE
,
54 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW
,
55 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
58 enum dc_i2c_arbitration
{
59 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL
,
60 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
65 * (timeout implemented in SW by querying status) */
66 I2C_SETUP_TIME_LIMIT
= 255,
67 I2C_HW_BUFFER_SIZE
= 538
72 * Cast pointer to 'struct i2c_hw_engine *'
73 * to pointer 'struct i2c_hw_engine_dce110 *'
75 #define FROM_I2C_HW_ENGINE(ptr) \
76 container_of((ptr), struct i2c_hw_engine_dce110, base)
79 * Cast pointer to 'struct i2c_engine *'
80 * to pointer to 'struct i2c_hw_engine_dce110 *'
82 #define FROM_I2C_ENGINE(ptr) \
83 FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
87 * Cast pointer to 'struct engine *'
88 * to 'pointer to struct i2c_hw_engine_dce110 *'
90 #define FROM_ENGINE(ptr) \
91 FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
94 hw_engine->base.base.base.ctx
96 #define REG(reg_name)\
97 (hw_engine->regs->reg_name)
100 #define FN(reg_name, field_name) \
101 hw_engine->i2c_shift->field_name, hw_engine->i2c_mask->field_name
103 #include "reg_helper.h"
105 static void disable_i2c_hw_engine(
106 struct i2c_hw_engine_dce110
*hw_engine
)
108 REG_UPDATE_N(SETUP
, 1, FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_ENABLE
), 0);
111 static void release_engine(
112 struct engine
*engine
)
114 struct i2c_hw_engine_dce110
*hw_engine
= FROM_ENGINE(engine
);
116 struct i2c_engine
*base
= NULL
;
119 base
= &hw_engine
->base
.base
;
121 /* Restore original HW engine speed */
123 base
->funcs
->set_speed(base
, hw_engine
->base
.original_speed
);
126 REG_UPDATE(DC_I2C_ARBITRATION
, DC_I2C_SW_DONE_USING_I2C_REG
, 1);
128 /* Reset HW engine */
130 uint32_t i2c_sw_status
= 0;
131 REG_GET(DC_I2C_SW_STATUS
, DC_I2C_SW_STATUS
, &i2c_sw_status
);
132 /* if used by SW, safe to reset */
133 safe_to_reset
= (i2c_sw_status
== 1);
139 DC_I2C_SOFT_RESET
, 1,
140 DC_I2C_SW_STATUS_RESET
, 1);
142 REG_UPDATE(DC_I2C_CONTROL
, DC_I2C_SW_STATUS_RESET
, 1);
144 /* HW I2c engine - clock gating feature */
145 if (!hw_engine
->engine_keep_power_up_count
)
146 disable_i2c_hw_engine(hw_engine
);
149 static bool setup_engine(
150 struct i2c_engine
*i2c_engine
)
152 struct i2c_hw_engine_dce110
*hw_engine
= FROM_I2C_ENGINE(i2c_engine
);
154 /* Program pin select */
158 DC_I2C_SOFT_RESET
, 0,
159 DC_I2C_SEND_RESET
, 0,
160 DC_I2C_SW_STATUS_RESET
, 1,
161 DC_I2C_TRANSACTION_COUNT
, 0,
162 DC_I2C_DDC_SELECT
, hw_engine
->engine_id
);
164 /* Program time limit */
167 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_TIME_LIMIT
), I2C_SETUP_TIME_LIMIT
,
168 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_ENABLE
), 1);
170 /* Program HW priority
171 * set to High - interrupt software I2C at any time
172 * Enable restart of SW I2C that was interrupted by HW
173 * disable queuing of software while I2C is in use by HW */
176 DC_I2C_NO_QUEUED_SW_GO
, 0,
177 DC_I2C_SW_PRIORITY
, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL
);
182 static uint32_t get_speed(
183 const struct i2c_engine
*i2c_engine
)
185 const struct i2c_hw_engine_dce110
*hw_engine
= FROM_I2C_ENGINE(i2c_engine
);
186 uint32_t pre_scale
= 0;
188 REG_GET(SPEED
, DC_I2C_DDC1_PRESCALE
, &pre_scale
);
190 /* [anaumov] it seems following is unnecessary */
191 /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
193 hw_engine
->reference_frequency
/ pre_scale
:
194 hw_engine
->base
.default_speed
;
197 static void set_speed(
198 struct i2c_engine
*i2c_engine
,
201 struct i2c_hw_engine_dce110
*hw_engine
= FROM_I2C_ENGINE(i2c_engine
);
204 if (hw_engine
->i2c_mask
->DC_I2C_DDC1_START_STOP_TIMING_CNTL
)
207 FN(DC_I2C_DDC1_SPEED
, DC_I2C_DDC1_PRESCALE
), hw_engine
->reference_frequency
/ speed
,
208 FN(DC_I2C_DDC1_SPEED
, DC_I2C_DDC1_THRESHOLD
), 2,
209 FN(DC_I2C_DDC1_SPEED
, DC_I2C_DDC1_START_STOP_TIMING_CNTL
), speed
> 50 ? 2:1);
213 FN(DC_I2C_DDC1_SPEED
, DC_I2C_DDC1_PRESCALE
), hw_engine
->reference_frequency
/ speed
,
214 FN(DC_I2C_DDC1_SPEED
, DC_I2C_DDC1_THRESHOLD
), 2);
218 static inline void reset_hw_engine(struct engine
*engine
)
220 struct i2c_hw_engine_dce110
*hw_engine
= FROM_ENGINE(engine
);
224 DC_I2C_SW_STATUS_RESET
, 1,
225 DC_I2C_SW_STATUS_RESET
, 1);
228 static bool is_hw_busy(struct engine
*engine
)
230 struct i2c_hw_engine_dce110
*hw_engine
= FROM_ENGINE(engine
);
231 uint32_t i2c_sw_status
= 0;
233 REG_GET(DC_I2C_SW_STATUS
, DC_I2C_SW_STATUS
, &i2c_sw_status
);
234 if (i2c_sw_status
== DC_I2C_STATUS__DC_I2C_STATUS_IDLE
)
237 reset_hw_engine(engine
);
239 REG_GET(DC_I2C_SW_STATUS
, DC_I2C_SW_STATUS
, &i2c_sw_status
);
240 return i2c_sw_status
!= DC_I2C_STATUS__DC_I2C_STATUS_IDLE
;
244 #define STOP_TRANS_PREDICAT \
245 ((hw_engine->transaction_count == 3) || \
246 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) || \
247 (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ))
249 #define SET_I2C_TRANSACTION(id) \
251 REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5, \
252 FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1, \
253 FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1, \
254 FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0, \
255 FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)), \
256 FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length); \
257 if (STOP_TRANS_PREDICAT) \
258 last_transaction = true; \
262 static bool process_transaction(
263 struct i2c_hw_engine_dce110
*hw_engine
,
264 struct i2c_request_transaction_data
*request
)
266 uint32_t length
= request
->length
;
267 uint8_t *buffer
= request
->data
;
270 bool last_transaction
= false;
272 struct dc_context
*ctx
= NULL
;
274 ctx
= hw_engine
->base
.base
.base
.ctx
;
278 switch (hw_engine
->transaction_count
) {
280 SET_I2C_TRANSACTION(0);
283 SET_I2C_TRANSACTION(1);
286 SET_I2C_TRANSACTION(2);
289 SET_I2C_TRANSACTION(3);
297 /* Write the I2C address and I2C data
298 * into the hardware circular buffer, one byte per entry.
299 * As an example, the 7-bit I2C slave address for CRT monitor
300 * for reading DDC/EDID information is 0b1010001.
301 * For an I2C send operation, the LSB must be programmed to 0;
302 * for I2C receive operation, the LSB must be programmed to 1. */
303 if (hw_engine
->transaction_count
== 0) {
304 value
= REG_SET_4(DC_I2C_DATA
, 0,
305 DC_I2C_DATA_RW
, false,
306 DC_I2C_DATA
, request
->address
,
308 DC_I2C_INDEX_WRITE
, 1);
309 hw_engine
->buffer_used_write
= 0;
311 value
= REG_SET_2(DC_I2C_DATA
, 0,
312 DC_I2C_DATA_RW
, false,
313 DC_I2C_DATA
, request
->address
);
315 hw_engine
->buffer_used_write
++;
317 if (!(request
->action
& I2CAUX_TRANSACTION_ACTION_I2C_READ
)) {
319 REG_SET_2(DC_I2C_DATA
, value
,
320 DC_I2C_INDEX_WRITE
, 0,
321 DC_I2C_DATA
, *buffer
++);
322 hw_engine
->buffer_used_write
++;
327 ++hw_engine
->transaction_count
;
328 hw_engine
->buffer_used_bytes
+= length
+ 1;
330 return last_transaction
;
333 static void execute_transaction(
334 struct i2c_hw_engine_dce110
*hw_engine
)
336 REG_UPDATE_N(SETUP
, 5,
337 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_DATA_DRIVE_EN
), 0,
338 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_CLK_DRIVE_EN
), 0,
339 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_DATA_DRIVE_SEL
), 0,
340 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY
), 0,
341 FN(DC_I2C_DDC1_SETUP
, DC_I2C_DDC1_INTRA_BYTE_DELAY
), 0);
344 REG_UPDATE_5(DC_I2C_CONTROL
,
345 DC_I2C_SOFT_RESET
, 0,
346 DC_I2C_SW_STATUS_RESET
, 0,
347 DC_I2C_SEND_RESET
, 0,
349 DC_I2C_TRANSACTION_COUNT
, hw_engine
->transaction_count
- 1);
351 /* start I2C transfer */
352 REG_UPDATE(DC_I2C_CONTROL
, DC_I2C_GO
, 1);
354 /* all transactions were executed and HW buffer became empty
355 * (even though it actually happens when status becomes DONE) */
356 hw_engine
->transaction_count
= 0;
357 hw_engine
->buffer_used_bytes
= 0;
360 static void submit_channel_request(
361 struct i2c_engine
*engine
,
362 struct i2c_request_transaction_data
*request
)
364 request
->status
= I2C_CHANNEL_OPERATION_SUCCEEDED
;
366 if (!process_transaction(FROM_I2C_ENGINE(engine
), request
))
369 if (is_hw_busy(&engine
->base
)) {
370 request
->status
= I2C_CHANNEL_OPERATION_ENGINE_BUSY
;
374 execute_transaction(FROM_I2C_ENGINE(engine
));
377 static void process_channel_reply(
378 struct i2c_engine
*engine
,
379 struct i2c_reply_transaction_data
*reply
)
381 uint32_t length
= reply
->length
;
382 uint8_t *buffer
= reply
->data
;
384 struct i2c_hw_engine_dce110
*hw_engine
=
385 FROM_I2C_ENGINE(engine
);
388 REG_SET_3(DC_I2C_DATA
, 0,
389 DC_I2C_INDEX
, hw_engine
->buffer_used_write
,
391 DC_I2C_INDEX_WRITE
, 1);
394 /* after reading the status,
395 * if the I2C operation executed successfully
396 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
397 * should read data bytes from I2C circular data buffer */
401 REG_GET(DC_I2C_DATA
, DC_I2C_DATA
, &i2c_data
);
402 *buffer
++ = i2c_data
;
408 static enum i2c_channel_operation_result
get_channel_status(
409 struct i2c_engine
*i2c_engine
,
410 uint8_t *returned_bytes
)
412 uint32_t i2c_sw_status
= 0;
413 struct i2c_hw_engine_dce110
*hw_engine
= FROM_I2C_ENGINE(i2c_engine
);
415 REG_GET(DC_I2C_SW_STATUS
, DC_I2C_SW_STATUS
, &i2c_sw_status
);
417 if (i2c_sw_status
== DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW
)
418 return I2C_CHANNEL_OPERATION_ENGINE_BUSY
;
419 else if (value
& hw_engine
->i2c_mask
->DC_I2C_SW_STOPPED_ON_NACK
)
420 return I2C_CHANNEL_OPERATION_NO_RESPONSE
;
421 else if (value
& hw_engine
->i2c_mask
->DC_I2C_SW_TIMEOUT
)
422 return I2C_CHANNEL_OPERATION_TIMEOUT
;
423 else if (value
& hw_engine
->i2c_mask
->DC_I2C_SW_ABORTED
)
424 return I2C_CHANNEL_OPERATION_FAILED
;
425 else if (value
& hw_engine
->i2c_mask
->DC_I2C_SW_DONE
)
426 return I2C_CHANNEL_OPERATION_SUCCEEDED
;
429 * this is the case when HW used for communication, I2C_SW_STATUS
432 return I2C_CHANNEL_OPERATION_SUCCEEDED
;
435 static uint32_t get_hw_buffer_available_size(
436 const struct i2c_hw_engine
*engine
)
438 return I2C_HW_BUFFER_SIZE
-
439 FROM_I2C_HW_ENGINE(engine
)->buffer_used_bytes
;
442 static uint32_t get_transaction_timeout(
443 const struct i2c_hw_engine
*engine
,
446 uint32_t speed
= engine
->base
.funcs
->get_speed(&engine
->base
);
448 uint32_t period_timeout
;
449 uint32_t num_of_clock_stretches
;
454 period_timeout
= (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS
) / speed
;
456 num_of_clock_stretches
= 1 + (length
<< 3) + 1;
457 num_of_clock_stretches
+=
458 (FROM_I2C_HW_ENGINE(engine
)->buffer_used_bytes
<< 3) +
459 (FROM_I2C_HW_ENGINE(engine
)->transaction_count
<< 1);
461 return period_timeout
* num_of_clock_stretches
;
465 struct i2c_engine
**i2c_engine
)
467 struct i2c_hw_engine_dce110
*engine_dce110
=
468 FROM_I2C_ENGINE(*i2c_engine
);
470 dal_i2c_hw_engine_destruct(&engine_dce110
->base
);
472 kfree(engine_dce110
);
477 static const struct i2c_engine_funcs i2c_engine_funcs
= {
479 .get_speed
= get_speed
,
480 .set_speed
= set_speed
,
481 .setup_engine
= setup_engine
,
482 .submit_channel_request
= submit_channel_request
,
483 .process_channel_reply
= process_channel_reply
,
484 .get_channel_status
= get_channel_status
,
485 .acquire_engine
= dal_i2c_hw_engine_acquire_engine
,
488 static const struct engine_funcs engine_funcs
= {
489 .release_engine
= release_engine
,
490 .get_engine_type
= dal_i2c_hw_engine_get_engine_type
,
491 .acquire
= dal_i2c_engine_acquire
,
492 .submit_request
= dal_i2c_hw_engine_submit_request
,
495 static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs
= {
496 .get_hw_buffer_available_size
= get_hw_buffer_available_size
,
497 .get_transaction_timeout
= get_transaction_timeout
,
498 .wait_on_operation_result
= dal_i2c_hw_engine_wait_on_operation_result
,
501 static void construct(
502 struct i2c_hw_engine_dce110
*hw_engine
,
503 const struct i2c_hw_engine_dce110_create_arg
*arg
)
505 uint32_t xtal_ref_div
= 0;
507 dal_i2c_hw_engine_construct(&hw_engine
->base
, arg
->ctx
);
509 hw_engine
->base
.base
.base
.funcs
= &engine_funcs
;
510 hw_engine
->base
.base
.funcs
= &i2c_engine_funcs
;
511 hw_engine
->base
.funcs
= &i2c_hw_engine_funcs
;
512 hw_engine
->base
.default_speed
= arg
->default_speed
;
514 hw_engine
->regs
= arg
->regs
;
515 hw_engine
->i2c_shift
= arg
->i2c_shift
;
516 hw_engine
->i2c_mask
= arg
->i2c_mask
;
518 hw_engine
->engine_id
= arg
->engine_id
;
520 hw_engine
->buffer_used_bytes
= 0;
521 hw_engine
->transaction_count
= 0;
522 hw_engine
->engine_keep_power_up_count
= 1;
525 REG_GET(MICROSECOND_TIME_BASE_DIV
, XTAL_REF_DIV
, &xtal_ref_div
);
527 if (xtal_ref_div
== 0) {
529 hw_engine
->base
.base
.base
.ctx
->logger
, LOG_WARNING
,
530 "Invalid base timer divider\n",
535 /*Calculating Reference Clock by divding original frequency by
537 * At upper level, uint32_t reference_frequency =
538 * dal_i2caux_get_reference_clock(as) >> 1
539 * which already divided by 2. So we need x2 to get original
540 * reference clock from ppll_info
542 hw_engine
->reference_frequency
=
543 (arg
->reference_frequency
* 2) / xtal_ref_div
;
546 struct i2c_engine
*dal_i2c_hw_engine_dce110_create(
547 const struct i2c_hw_engine_dce110_create_arg
*arg
)
549 struct i2c_hw_engine_dce110
*engine_dce10
;
552 ASSERT_CRITICAL(false);
555 if (!arg
->reference_frequency
) {
556 ASSERT_CRITICAL(false);
560 engine_dce10
= kzalloc(sizeof(struct i2c_hw_engine_dce110
),
564 ASSERT_CRITICAL(false);
568 construct(engine_dce10
, arg
);
569 return &engine_dce10
->base
.base
;