drivers/gpu/drm/amd/display/dc/inc/core_types.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef _CORE_TYPES_H_
  27 #define _CORE_TYPES_H_
  28
  29 #include "dc.h"
  30 #include "dce_calcs.h"
  31 #include "dcn_calcs.h"
  32 #include "ddc_service_types.h"
  33 #include "dc_bios_types.h"
  34 #include "mem_input.h"
  35 #include "mpc.h"
  36
  37 #define MAX_CLOCK_SOURCES 7
  38
  39 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
  40                 uint32_t controller_id);
  41
  42 #include "grph_object_id.h"
  43 #include "link_encoder.h"
  44 #include "stream_encoder.h"
  45 #include "clock_source.h"
  46 #include "audio.h"
  47 #include "hw_sequencer_types.h"
  48
  49
  50 /************ link *****************/
  51 struct link_init_data {
  52         const struct core_dc *dc;
  53         struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
  54         uint32_t connector_index; /* this will be mapped to the HPD pins */
  55         uint32_t link_index; /* this is mapped to DAL display_index
  56                                 TODO: remove it when DC is complete. */
  57 };
  58
  59 struct dc_link *link_create(const struct link_init_data *init_params);
  60 void link_destroy(struct dc_link **link);
  61
  62 enum dc_status dc_link_validate_mode_timing(
  63                 const struct dc_stream_state *stream,
  64                 struct dc_link *link,
  65                 const struct dc_crtc_timing *timing);
  66
  67 void core_link_resume(struct dc_link *link);
  68
  69 void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
  70
  71 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
  72
  73 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
  74 /********** DAL Core*********************/
  75 #include "display_clock.h"
  76 #include "transform.h"
  77
  78 struct resource_pool;
  79 struct validate_context;
  80 struct resource_context;
  81
  82 struct resource_funcs {
  83         void (*destroy)(struct resource_pool **pool);
  84         struct link_encoder *(*link_enc_create)(
  85                         const struct encoder_init_data *init);
  86         enum dc_status (*validate_with_context)(
  87                                         const struct core_dc *dc,
  88                                         const struct dc_validation_set set[],
  89                                         int set_count,
  90                                         struct validate_context *context,
  91                                         struct validate_context *old_context);
  92
  93         enum dc_status (*validate_guaranteed)(
  94                                         const struct core_dc *dc,
  95                                         struct dc_stream_state *stream,
  96                                         struct validate_context *context);
  97
  98         bool (*validate_bandwidth)(
  99                                         const struct core_dc *dc,
 100                                         struct validate_context *context);
 101
 102         struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
 103                         struct validate_context *context,
 104                         const struct resource_pool *pool,
 105                         struct dc_stream_state *stream);
 106         enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state);
 107 };
 108
 109 struct audio_support{
 110         bool dp_audio;
 111         bool hdmi_audio_on_dongle;
 112         bool hdmi_audio_native;
 113 };
 114
 115 #define NO_UNDERLAY_PIPE -1
 116
 117 struct resource_pool {
 118         struct mem_input *mis[MAX_PIPES];
 119         struct input_pixel_processor *ipps[MAX_PIPES];
 120         struct transform *transforms[MAX_PIPES];
 121         struct output_pixel_processor *opps[MAX_PIPES];
 122         struct timing_generator *timing_generators[MAX_PIPES];
 123         struct stream_encoder *stream_enc[MAX_PIPES * 2];
 124 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 125         struct mpc *mpc;
 126 #endif
 127
 128         unsigned int pipe_count;
 129         unsigned int underlay_pipe_index;
 130         unsigned int stream_enc_count;
 131         unsigned int ref_clock_inKhz;
 132
 133         /*
 134          * reserved clock source for DP
 135          */
 136         struct clock_source *dp_clock_source;
 137
 138         struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
 139         unsigned int clk_src_count;
 140
 141         struct audio *audios[MAX_PIPES];
 142         unsigned int audio_count;
 143         struct audio_support audio_support;
 144
 145         struct display_clock *display_clock;
 146         struct irq_service *irqs;
 147
 148         struct abm *abm;
 149         struct dmcu *dmcu;
 150
 151         const struct resource_funcs *funcs;
 152         const struct resource_caps *res_cap;
 153 };
 154
 155 struct pipe_ctx {
 156         struct dc_plane_state *plane_state;
 157         struct dc_stream_state *stream;
 158
 159         struct mem_input *mi;
 160         struct input_pixel_processor *ipp;
 161         struct transform *xfm;
 162         struct output_pixel_processor *opp;
 163         struct timing_generator *tg;
 164
 165         struct scaler_data scl_data;
 166
 167         struct stream_encoder *stream_enc;
 168         struct display_clock *dis_clk;
 169         struct clock_source *clock_source;
 170
 171         struct audio *audio;
 172
 173         struct pixel_clk_params pix_clk_params;
 174         struct pll_settings pll_settings;
 175
 176         /*fmt*/
 177         struct encoder_info_frame encoder_info_frame;
 178
 179         uint8_t pipe_idx;
 180
 181         struct pipe_ctx *top_pipe;
 182         struct pipe_ctx *bottom_pipe;
 183
 184 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 185         struct _vcs_dpi_display_dlg_regs_st dlg_regs;
 186         struct _vcs_dpi_display_ttu_regs_st ttu_regs;
 187         struct _vcs_dpi_display_rq_regs_st rq_regs;
 188         struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 189 #endif
 190 };
 191
 192 struct resource_context {
 193         struct pipe_ctx pipe_ctx[MAX_PIPES];
 194         bool is_stream_enc_acquired[MAX_PIPES * 2];
 195         bool is_audio_acquired[MAX_PIPES];
 196         uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 197         uint8_t dp_clock_source_ref_count;
 198 };
 199
 200 struct dce_bw_output {
 201         bool cpuc_state_change_enable;
 202         bool cpup_state_change_enable;
 203         bool stutter_mode_enable;
 204         bool nbp_state_change_enable;
 205         bool all_displays_in_sync;
 206         struct dce_watermarks urgent_wm_ns[MAX_PIPES];
 207         struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
 208         struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
 209         int sclk_khz;
 210         int sclk_deep_sleep_khz;
 211         int yclk_khz;
 212         int dispclk_khz;
 213         int blackout_recovery_time_us;
 214 };
 215
 216 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 217 struct dcn_bw_clocks {
 218         int dispclk_khz;
 219         bool dppclk_div;
 220         int dcfclk_khz;
 221         int dcfclk_deep_sleep_khz;
 222         int fclk_khz;
 223         int dram_ccm_us;
 224         int min_active_dram_ccm_us;
 225 };
 226
 227 struct dcn_bw_output {
 228         struct dcn_bw_clocks cur_clk;
 229         struct dcn_bw_clocks calc_clk;
 230         struct dcn_watermark_set watermarks;
 231 };
 232 #endif
 233
 234 union bw_context {
 235 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 236         struct dcn_bw_output dcn;
 237 #endif
 238         struct dce_bw_output dce;
 239 };
 240
 241 struct validate_context {
 242         struct dc_stream_state *streams[MAX_PIPES];
 243         struct dc_stream_status stream_status[MAX_PIPES];
 244         uint8_t stream_count;
 245
 246         struct resource_context res_ctx;
 247
 248         /* The output from BW and WM calculations. */
 249         union bw_context bw;
 250
 251         /* Note: these are big structures, do *not* put on stack! */
 252         struct dm_pp_display_configuration pp_display_cfg;
 253 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 254         struct dcn_bw_internal_vars dcn_bw_vars;
 255 #endif
 256
 257         int ref_count;
 258 };
 259
 260 #endif /* _CORE_TYPES_H_ */