drivers/gpu/drm/amd/include/amd_shared.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __AMD_SHARED_H__
  24 #define __AMD_SHARED_H__
  25
  26 #define AMD_MAX_USEC_TIMEOUT            200000  /* 200 ms */
  27
  28 /*
  29  * Supported ASIC types
  30  */
  31 enum amd_asic_type {
  32         CHIP_TAHITI = 0,
  33         CHIP_PITCAIRN,
  34         CHIP_VERDE,
  35         CHIP_OLAND,
  36         CHIP_HAINAN,
  37         CHIP_BONAIRE,
  38         CHIP_KAVERI,
  39         CHIP_KABINI,
  40         CHIP_HAWAII,
  41         CHIP_MULLINS,
  42         CHIP_TOPAZ,
  43         CHIP_TONGA,
  44         CHIP_FIJI,
  45         CHIP_CARRIZO,
  46         CHIP_STONEY,
  47         CHIP_POLARIS10,
  48         CHIP_POLARIS11,
  49         CHIP_POLARIS12,
  50         CHIP_VEGA10,
  51         CHIP_RAVEN,
  52         CHIP_LAST,
  53 };
  54
  55 /*
  56  * Chip flags
  57  */
  58 enum amd_chip_flags {
  59         AMD_ASIC_MASK = 0x0000ffffUL,
  60         AMD_FLAGS_MASK  = 0xffff0000UL,
  61         AMD_IS_MOBILITY = 0x00010000UL,
  62         AMD_IS_APU      = 0x00020000UL,
  63         AMD_IS_PX       = 0x00040000UL,
  64         AMD_EXP_HW_SUPPORT = 0x00080000UL,
  65 };
  66
  67 enum amd_ip_block_type {
  68         AMD_IP_BLOCK_TYPE_COMMON,
  69         AMD_IP_BLOCK_TYPE_GMC,
  70         AMD_IP_BLOCK_TYPE_IH,
  71         AMD_IP_BLOCK_TYPE_SMC,
  72         AMD_IP_BLOCK_TYPE_PSP,
  73         AMD_IP_BLOCK_TYPE_DCE,
  74         AMD_IP_BLOCK_TYPE_GFX,
  75         AMD_IP_BLOCK_TYPE_SDMA,
  76         AMD_IP_BLOCK_TYPE_UVD,
  77         AMD_IP_BLOCK_TYPE_VCE,
  78         AMD_IP_BLOCK_TYPE_ACP,
  79         AMD_IP_BLOCK_TYPE_VCN
  80 };
  81
  82 enum amd_clockgating_state {
  83         AMD_CG_STATE_GATE = 0,
  84         AMD_CG_STATE_UNGATE,
  85 };
  86
  87 enum amd_dpm_forced_level {
  88         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  89         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  90         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  91         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  92         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  93         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  94         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  95         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  96         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  97 };
  98
  99 enum amd_powergating_state {
 100         AMD_PG_STATE_GATE = 0,
 101         AMD_PG_STATE_UNGATE,
 102 };
 103
 104 struct amd_vce_state {
 105         /* vce clocks */
 106         u32 evclk;
 107         u32 ecclk;
 108         /* gpu clocks */
 109         u32 sclk;
 110         u32 mclk;
 111         u8 clk_idx;
 112         u8 pstate;
 113 };
 114
 115
 116 #define AMD_MAX_VCE_LEVELS 6
 117
 118 enum amd_vce_level {
 119         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
 120         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
 121         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
 122         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
 123         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
 124         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
 125 };
 126
 127 enum amd_pp_profile_type {
 128         AMD_PP_GFX_PROFILE,
 129         AMD_PP_COMPUTE_PROFILE,
 130 };
 131
 132 struct amd_pp_profile {
 133         enum amd_pp_profile_type type;
 134         uint32_t min_sclk;
 135         uint32_t min_mclk;
 136         uint16_t activity_threshold;
 137         uint8_t up_hyst;
 138         uint8_t down_hyst;
 139 };
 140
 141 enum amd_fan_ctrl_mode {
 142         AMD_FAN_CTRL_NONE = 0,
 143         AMD_FAN_CTRL_MANUAL = 1,
 144         AMD_FAN_CTRL_AUTO = 2,
 145 };
 146
 147 /* CG flags */
 148 #define AMD_CG_SUPPORT_GFX_MGCG                 (1 << 0)
 149 #define AMD_CG_SUPPORT_GFX_MGLS                 (1 << 1)
 150 #define AMD_CG_SUPPORT_GFX_CGCG                 (1 << 2)
 151 #define AMD_CG_SUPPORT_GFX_CGLS                 (1 << 3)
 152 #define AMD_CG_SUPPORT_GFX_CGTS                 (1 << 4)
 153 #define AMD_CG_SUPPORT_GFX_CGTS_LS              (1 << 5)
 154 #define AMD_CG_SUPPORT_GFX_CP_LS                (1 << 6)
 155 #define AMD_CG_SUPPORT_GFX_RLC_LS               (1 << 7)
 156 #define AMD_CG_SUPPORT_MC_LS                    (1 << 8)
 157 #define AMD_CG_SUPPORT_MC_MGCG                  (1 << 9)
 158 #define AMD_CG_SUPPORT_SDMA_LS                  (1 << 10)
 159 #define AMD_CG_SUPPORT_SDMA_MGCG                (1 << 11)
 160 #define AMD_CG_SUPPORT_BIF_LS                   (1 << 12)
 161 #define AMD_CG_SUPPORT_UVD_MGCG                 (1 << 13)
 162 #define AMD_CG_SUPPORT_VCE_MGCG                 (1 << 14)
 163 #define AMD_CG_SUPPORT_HDP_LS                   (1 << 15)
 164 #define AMD_CG_SUPPORT_HDP_MGCG                 (1 << 16)
 165 #define AMD_CG_SUPPORT_ROM_MGCG                 (1 << 17)
 166 #define AMD_CG_SUPPORT_DRM_LS                   (1 << 18)
 167 #define AMD_CG_SUPPORT_BIF_MGCG                 (1 << 19)
 168 #define AMD_CG_SUPPORT_GFX_3D_CGCG              (1 << 20)
 169 #define AMD_CG_SUPPORT_GFX_3D_CGLS              (1 << 21)
 170 #define AMD_CG_SUPPORT_DRM_MGCG                 (1 << 22)
 171 #define AMD_CG_SUPPORT_DF_MGCG                  (1 << 23)
 172
 173 /* PG flags */
 174 #define AMD_PG_SUPPORT_GFX_PG                   (1 << 0)
 175 #define AMD_PG_SUPPORT_GFX_SMG                  (1 << 1)
 176 #define AMD_PG_SUPPORT_GFX_DMG                  (1 << 2)
 177 #define AMD_PG_SUPPORT_UVD                      (1 << 3)
 178 #define AMD_PG_SUPPORT_VCE                      (1 << 4)
 179 #define AMD_PG_SUPPORT_CP                       (1 << 5)
 180 #define AMD_PG_SUPPORT_GDS                      (1 << 6)
 181 #define AMD_PG_SUPPORT_RLC_SMU_HS               (1 << 7)
 182 #define AMD_PG_SUPPORT_SDMA                     (1 << 8)
 183 #define AMD_PG_SUPPORT_ACP                      (1 << 9)
 184 #define AMD_PG_SUPPORT_SAMU                     (1 << 10)
 185 #define AMD_PG_SUPPORT_GFX_QUICK_MG             (1 << 11)
 186 #define AMD_PG_SUPPORT_GFX_PIPELINE             (1 << 12)
 187 #define AMD_PG_SUPPORT_MMHUB                    (1 << 13)
 188
 189 enum amd_pm_state_type {
 190         /* not used for dpm */
 191         POWER_STATE_TYPE_DEFAULT,
 192         POWER_STATE_TYPE_POWERSAVE,
 193         /* user selectable states */
 194         POWER_STATE_TYPE_BATTERY,
 195         POWER_STATE_TYPE_BALANCED,
 196         POWER_STATE_TYPE_PERFORMANCE,
 197         /* internal states */
 198         POWER_STATE_TYPE_INTERNAL_UVD,
 199         POWER_STATE_TYPE_INTERNAL_UVD_SD,
 200         POWER_STATE_TYPE_INTERNAL_UVD_HD,
 201         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
 202         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
 203         POWER_STATE_TYPE_INTERNAL_BOOT,
 204         POWER_STATE_TYPE_INTERNAL_THERMAL,
 205         POWER_STATE_TYPE_INTERNAL_ACPI,
 206         POWER_STATE_TYPE_INTERNAL_ULV,
 207         POWER_STATE_TYPE_INTERNAL_3DPERF,
 208 };
 209
 210 struct amd_ip_funcs {
 211         /* Name of IP block */
 212         char *name;
 213         /* sets up early driver state (pre sw_init), does not configure hw - Optional */
 214         int (*early_init)(void *handle);
 215         /* sets up late driver/hw state (post hw_init) - Optional */
 216         int (*late_init)(void *handle);
 217         /* sets up driver state, does not configure hw */
 218         int (*sw_init)(void *handle);
 219         /* tears down driver state, does not configure hw */
 220         int (*sw_fini)(void *handle);
 221         /* sets up the hw state */
 222         int (*hw_init)(void *handle);
 223         /* tears down the hw state */
 224         int (*hw_fini)(void *handle);
 225         void (*late_fini)(void *handle);
 226         /* handles IP specific hw/sw changes for suspend */
 227         int (*suspend)(void *handle);
 228         /* handles IP specific hw/sw changes for resume */
 229         int (*resume)(void *handle);
 230         /* returns current IP block idle status */
 231         bool (*is_idle)(void *handle);
 232         /* poll for idle */
 233         int (*wait_for_idle)(void *handle);
 234         /* check soft reset the IP block */
 235         bool (*check_soft_reset)(void *handle);
 236         /* pre soft reset the IP block */
 237         int (*pre_soft_reset)(void *handle);
 238         /* soft reset the IP block */
 239         int (*soft_reset)(void *handle);
 240         /* post soft reset the IP block */
 241         int (*post_soft_reset)(void *handle);
 242         /* enable/disable cg for the IP block */
 243         int (*set_clockgating_state)(void *handle,
 244                                      enum amd_clockgating_state state);
 245         /* enable/disable pg for the IP block */
 246         int (*set_powergating_state)(void *handle,
 247                                      enum amd_powergating_state state);
 248         /* get current clockgating status */
 249         void (*get_clockgating_state)(void *handle, u32 *flags);
 250 };
 251
 252 #endif /* __AMD_SHARED_H__ */