drivers/gpu/drm/amd/include/amd_shared.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __AMD_SHARED_H__
  24 #define __AMD_SHARED_H__
  25
  26 #define AMD_MAX_USEC_TIMEOUT            200000  /* 200 ms */
  27
  28 /*
  29  * Supported ASIC types
  30  */
  31 enum amd_asic_type {
  32         CHIP_TAHITI = 0,
  33         CHIP_PITCAIRN,
  34         CHIP_VERDE,
  35         CHIP_OLAND,
  36         CHIP_HAINAN,
  37         CHIP_BONAIRE,
  38         CHIP_KAVERI,
  39         CHIP_KABINI,
  40         CHIP_HAWAII,
  41         CHIP_MULLINS,
  42         CHIP_TOPAZ,
  43         CHIP_TONGA,
  44         CHIP_FIJI,
  45         CHIP_CARRIZO,
  46         CHIP_STONEY,
  47         CHIP_POLARIS10,
  48         CHIP_POLARIS11,
  49         CHIP_POLARIS12,
  50         CHIP_LAST,
  51 };
  52
  53 /*
  54  * Chip flags
  55  */
  56 enum amd_chip_flags {
  57         AMD_ASIC_MASK = 0x0000ffffUL,
  58         AMD_FLAGS_MASK  = 0xffff0000UL,
  59         AMD_IS_MOBILITY = 0x00010000UL,
  60         AMD_IS_APU      = 0x00020000UL,
  61         AMD_IS_PX       = 0x00040000UL,
  62         AMD_EXP_HW_SUPPORT = 0x00080000UL,
  63 };
  64
  65 enum amd_ip_block_type {
  66         AMD_IP_BLOCK_TYPE_COMMON,
  67         AMD_IP_BLOCK_TYPE_GMC,
  68         AMD_IP_BLOCK_TYPE_IH,
  69         AMD_IP_BLOCK_TYPE_SMC,
  70         AMD_IP_BLOCK_TYPE_DCE,
  71         AMD_IP_BLOCK_TYPE_GFX,
  72         AMD_IP_BLOCK_TYPE_SDMA,
  73         AMD_IP_BLOCK_TYPE_UVD,
  74         AMD_IP_BLOCK_TYPE_VCE,
  75         AMD_IP_BLOCK_TYPE_ACP,
  76 };
  77
  78 enum amd_clockgating_state {
  79         AMD_CG_STATE_GATE = 0,
  80         AMD_CG_STATE_UNGATE,
  81 };
  82
  83 enum amd_dpm_forced_level {
  84         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  85         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  86         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  87         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  88         AMD_DPM_FORCED_LEVEL_PROFILING = 0x10,
  89 };
  90
  91 enum amd_powergating_state {
  92         AMD_PG_STATE_GATE = 0,
  93         AMD_PG_STATE_UNGATE,
  94 };
  95
  96 struct amd_vce_state {
  97         /* vce clocks */
  98         u32 evclk;
  99         u32 ecclk;
 100         /* gpu clocks */
 101         u32 sclk;
 102         u32 mclk;
 103         u8 clk_idx;
 104         u8 pstate;
 105 };
 106
 107
 108 #define AMD_MAX_VCE_LEVELS 6
 109
 110 enum amd_vce_level {
 111         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
 112         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
 113         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
 114         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
 115         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
 116         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
 117 };
 118
 119 /* CG flags */
 120 #define AMD_CG_SUPPORT_GFX_MGCG                 (1 << 0)
 121 #define AMD_CG_SUPPORT_GFX_MGLS                 (1 << 1)
 122 #define AMD_CG_SUPPORT_GFX_CGCG                 (1 << 2)
 123 #define AMD_CG_SUPPORT_GFX_CGLS                 (1 << 3)
 124 #define AMD_CG_SUPPORT_GFX_CGTS                 (1 << 4)
 125 #define AMD_CG_SUPPORT_GFX_CGTS_LS              (1 << 5)
 126 #define AMD_CG_SUPPORT_GFX_CP_LS                (1 << 6)
 127 #define AMD_CG_SUPPORT_GFX_RLC_LS               (1 << 7)
 128 #define AMD_CG_SUPPORT_MC_LS                    (1 << 8)
 129 #define AMD_CG_SUPPORT_MC_MGCG                  (1 << 9)
 130 #define AMD_CG_SUPPORT_SDMA_LS                  (1 << 10)
 131 #define AMD_CG_SUPPORT_SDMA_MGCG                (1 << 11)
 132 #define AMD_CG_SUPPORT_BIF_LS                   (1 << 12)
 133 #define AMD_CG_SUPPORT_UVD_MGCG                 (1 << 13)
 134 #define AMD_CG_SUPPORT_VCE_MGCG                 (1 << 14)
 135 #define AMD_CG_SUPPORT_HDP_LS                   (1 << 15)
 136 #define AMD_CG_SUPPORT_HDP_MGCG                 (1 << 16)
 137 #define AMD_CG_SUPPORT_ROM_MGCG                 (1 << 17)
 138 #define AMD_CG_SUPPORT_DRM_LS                   (1 << 18)
 139 #define AMD_CG_SUPPORT_BIF_MGCG                 (1 << 19)
 140 #define AMD_CG_SUPPORT_GFX_3D_CGCG              (1 << 20)
 141 #define AMD_CG_SUPPORT_GFX_3D_CGLS              (1 << 21)
 142
 143 /* PG flags */
 144 #define AMD_PG_SUPPORT_GFX_PG                   (1 << 0)
 145 #define AMD_PG_SUPPORT_GFX_SMG                  (1 << 1)
 146 #define AMD_PG_SUPPORT_GFX_DMG                  (1 << 2)
 147 #define AMD_PG_SUPPORT_UVD                      (1 << 3)
 148 #define AMD_PG_SUPPORT_VCE                      (1 << 4)
 149 #define AMD_PG_SUPPORT_CP                       (1 << 5)
 150 #define AMD_PG_SUPPORT_GDS                      (1 << 6)
 151 #define AMD_PG_SUPPORT_RLC_SMU_HS               (1 << 7)
 152 #define AMD_PG_SUPPORT_SDMA                     (1 << 8)
 153 #define AMD_PG_SUPPORT_ACP                      (1 << 9)
 154 #define AMD_PG_SUPPORT_SAMU                     (1 << 10)
 155 #define AMD_PG_SUPPORT_GFX_QUICK_MG             (1 << 11)
 156 #define AMD_PG_SUPPORT_GFX_PIPELINE             (1 << 12)
 157
 158 enum amd_pm_state_type {
 159         /* not used for dpm */
 160         POWER_STATE_TYPE_DEFAULT,
 161         POWER_STATE_TYPE_POWERSAVE,
 162         /* user selectable states */
 163         POWER_STATE_TYPE_BATTERY,
 164         POWER_STATE_TYPE_BALANCED,
 165         POWER_STATE_TYPE_PERFORMANCE,
 166         /* internal states */
 167         POWER_STATE_TYPE_INTERNAL_UVD,
 168         POWER_STATE_TYPE_INTERNAL_UVD_SD,
 169         POWER_STATE_TYPE_INTERNAL_UVD_HD,
 170         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
 171         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
 172         POWER_STATE_TYPE_INTERNAL_BOOT,
 173         POWER_STATE_TYPE_INTERNAL_THERMAL,
 174         POWER_STATE_TYPE_INTERNAL_ACPI,
 175         POWER_STATE_TYPE_INTERNAL_ULV,
 176         POWER_STATE_TYPE_INTERNAL_3DPERF,
 177 };
 178
 179 struct amd_ip_funcs {
 180         /* Name of IP block */
 181         char *name;
 182         /* sets up early driver state (pre sw_init), does not configure hw - Optional */
 183         int (*early_init)(void *handle);
 184         /* sets up late driver/hw state (post hw_init) - Optional */
 185         int (*late_init)(void *handle);
 186         /* sets up driver state, does not configure hw */
 187         int (*sw_init)(void *handle);
 188         /* tears down driver state, does not configure hw */
 189         int (*sw_fini)(void *handle);
 190         /* sets up the hw state */
 191         int (*hw_init)(void *handle);
 192         /* tears down the hw state */
 193         int (*hw_fini)(void *handle);
 194         void (*late_fini)(void *handle);
 195         /* handles IP specific hw/sw changes for suspend */
 196         int (*suspend)(void *handle);
 197         /* handles IP specific hw/sw changes for resume */
 198         int (*resume)(void *handle);
 199         /* returns current IP block idle status */
 200         bool (*is_idle)(void *handle);
 201         /* poll for idle */
 202         int (*wait_for_idle)(void *handle);
 203         /* check soft reset the IP block */
 204         bool (*check_soft_reset)(void *handle);
 205         /* pre soft reset the IP block */
 206         int (*pre_soft_reset)(void *handle);
 207         /* soft reset the IP block */
 208         int (*soft_reset)(void *handle);
 209         /* post soft reset the IP block */
 210         int (*post_soft_reset)(void *handle);
 211         /* enable/disable cg for the IP block */
 212         int (*set_clockgating_state)(void *handle,
 213                                      enum amd_clockgating_state state);
 214         /* enable/disable pg for the IP block */
 215         int (*set_powergating_state)(void *handle,
 216                                      enum amd_powergating_state state);
 217 };
 218
 219 #endif /* __AMD_SHARED_H__ */