drivers/gpu/drm/amd/include/atomfirmware.h

   1 /****************************************************************************\
   2 *
   3 *  File Name      atomfirmware.h
   4 *  Project        This is an interface header file between atombios and OS GPU drivers for SoC15 products
   5 *
   6 *  Description    header file of general definitions for OS nd pre-OS video drivers
   7 *
   8 *  Copyright 2014 Advanced Micro Devices, Inc.
   9 *
  10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
  11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
  12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
  14 * subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in all copies or substantial
  17 * portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25 * OTHER DEALINGS IN THE SOFTWARE.
  26 *
  27 \****************************************************************************/
  28
  29 /*IMPORTANT NOTES
  30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
  31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
  32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
  33 */
  34
  35 #ifndef _ATOMFIRMWARE_H_
  36 #define _ATOMFIRMWARE_H_
  37
  38 enum  atom_bios_header_version_def{
  39   ATOM_MAJOR_VERSION        =0x0003,
  40   ATOM_MINOR_VERSION        =0x0003,
  41 };
  42
  43 #ifdef _H2INC
  44   #ifndef uint32_t
  45     typedef unsigned long uint32_t;
  46   #endif
  47
  48   #ifndef uint16_t
  49     typedef unsigned short uint16_t;
  50   #endif
  51
  52   #ifndef uint8_t
  53     typedef unsigned char uint8_t;
  54   #endif
  55 #endif
  56
  57 enum atom_crtc_def{
  58   ATOM_CRTC1      =0,
  59   ATOM_CRTC2      =1,
  60   ATOM_CRTC3      =2,
  61   ATOM_CRTC4      =3,
  62   ATOM_CRTC5      =4,
  63   ATOM_CRTC6      =5,
  64   ATOM_CRTC_INVALID  =0xff,
  65 };
  66
  67 enum atom_ppll_def{
  68   ATOM_PPLL0          =2,
  69   ATOM_GCK_DFS        =8,
  70   ATOM_FCH_CLK        =9,
  71   ATOM_DP_DTO         =11,
  72   ATOM_COMBOPHY_PLL0  =20,
  73   ATOM_COMBOPHY_PLL1  =21,
  74   ATOM_COMBOPHY_PLL2  =22,
  75   ATOM_COMBOPHY_PLL3  =23,
  76   ATOM_COMBOPHY_PLL4  =24,
  77   ATOM_COMBOPHY_PLL5  =25,
  78   ATOM_PPLL_INVALID   =0xff,
  79 };
  80
  81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
  82 enum atom_dig_def{
  83   ASIC_INT_DIG1_ENCODER_ID  =0x03,
  84   ASIC_INT_DIG2_ENCODER_ID  =0x09,
  85   ASIC_INT_DIG3_ENCODER_ID  =0x0a,
  86   ASIC_INT_DIG4_ENCODER_ID  =0x0b,
  87   ASIC_INT_DIG5_ENCODER_ID  =0x0c,
  88   ASIC_INT_DIG6_ENCODER_ID  =0x0d,
  89   ASIC_INT_DIG7_ENCODER_ID  =0x0e,
  90 };
  91
  92 //ucEncoderMode
  93 enum atom_encode_mode_def
  94 {
  95   ATOM_ENCODER_MODE_DP          =0,
  96   ATOM_ENCODER_MODE_DP_SST      =0,
  97   ATOM_ENCODER_MODE_LVDS        =1,
  98   ATOM_ENCODER_MODE_DVI         =2,
  99   ATOM_ENCODER_MODE_HDMI        =3,
 100   ATOM_ENCODER_MODE_DP_AUDIO    =5,
 101   ATOM_ENCODER_MODE_DP_MST      =5,
 102   ATOM_ENCODER_MODE_CRT         =15,
 103   ATOM_ENCODER_MODE_DVO         =16,
 104 };
 105
 106 enum atom_encoder_refclk_src_def{
 107   ENCODER_REFCLK_SRC_P1PLL      =0,
 108   ENCODER_REFCLK_SRC_P2PLL      =1,
 109   ENCODER_REFCLK_SRC_P3PLL      =2,
 110   ENCODER_REFCLK_SRC_EXTCLK     =3,
 111   ENCODER_REFCLK_SRC_INVALID    =0xff,
 112 };
 113
 114 enum atom_scaler_def{
 115   ATOM_SCALER_DISABLE          =0,  /*scaler bypass mode, auto-center & no replication*/
 116   ATOM_SCALER_CENTER           =1,  //For Fudo, it's bypass and auto-center & auto replication
 117   ATOM_SCALER_EXPANSION        =2,  /*scaler expansion by 2 tap alpha blending mode*/
 118 };
 119
 120 enum atom_operation_def{
 121   ATOM_DISABLE             = 0,
 122   ATOM_ENABLE              = 1,
 123   ATOM_INIT                = 7,
 124   ATOM_GET_STATUS          = 8,
 125 };
 126
 127 enum atom_embedded_display_op_def{
 128   ATOM_LCD_BL_OFF                = 2,
 129   ATOM_LCD_BL_OM                 = 3,
 130   ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
 131   ATOM_LCD_SELFTEST_START        = 5,
 132   ATOM_LCD_SELFTEST_STOP         = 6,
 133 };
 134
 135 enum atom_spread_spectrum_mode{
 136   ATOM_SS_CENTER_OR_DOWN_MODE_MASK  = 0x01,
 137   ATOM_SS_DOWN_SPREAD_MODE          = 0x00,
 138   ATOM_SS_CENTRE_SPREAD_MODE        = 0x01,
 139   ATOM_INT_OR_EXT_SS_MASK           = 0x02,
 140   ATOM_INTERNAL_SS_MASK             = 0x00,
 141   ATOM_EXTERNAL_SS_MASK             = 0x02,
 142 };
 143
 144 /* define panel bit per color  */
 145 enum atom_panel_bit_per_color{
 146   PANEL_BPC_UNDEFINE     =0x00,
 147   PANEL_6BIT_PER_COLOR   =0x01,
 148   PANEL_8BIT_PER_COLOR   =0x02,
 149   PANEL_10BIT_PER_COLOR  =0x03,
 150   PANEL_12BIT_PER_COLOR  =0x04,
 151   PANEL_16BIT_PER_COLOR  =0x05,
 152 };
 153
 154 //ucVoltageType
 155 enum atom_voltage_type
 156 {
 157   VOLTAGE_TYPE_VDDC = 1,
 158   VOLTAGE_TYPE_MVDDC = 2,
 159   VOLTAGE_TYPE_MVDDQ = 3,
 160   VOLTAGE_TYPE_VDDCI = 4,
 161   VOLTAGE_TYPE_VDDGFX = 5,
 162   VOLTAGE_TYPE_PCC = 6,
 163   VOLTAGE_TYPE_MVPP = 7,
 164   VOLTAGE_TYPE_LEDDPM = 8,
 165   VOLTAGE_TYPE_PCC_MVDD = 9,
 166   VOLTAGE_TYPE_PCIE_VDDC = 10,
 167   VOLTAGE_TYPE_PCIE_VDDR = 11,
 168   VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
 169   VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
 170   VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
 171   VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
 172   VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
 173   VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
 174   VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
 175   VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
 176   VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
 177   VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
 178 };
 179
 180 enum atom_dgpu_vram_type{
 181   ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
 182   ATOM_DGPU_VRAM_TYPE_HBM   = 0x60,
 183 };
 184
 185 enum atom_dp_vs_preemph_def{
 186   DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
 187   DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
 188   DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
 189   DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
 190   DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
 191   DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
 192   DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
 193   DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
 194   DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
 195   DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
 196 };
 197
 198
 199 /*
 200 enum atom_string_def{
 201 asic_bus_type_pcie_string = "PCI_EXPRESS",
 202 atom_fire_gl_string       = "FGL",
 203 atom_bios_string          = "ATOM"
 204 };
 205 */
 206
 207 #pragma pack(1)                          /* BIOS data must use byte aligment*/
 208
 209 enum atombios_image_offset{
 210 OFFSET_TO_ATOM_ROM_HEADER_POINTER          =0x00000048,
 211 OFFSET_TO_ATOM_ROM_IMAGE_SIZE              =0x00000002,
 212 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE       =0x94,
 213 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE      =20,  /*including the terminator 0x0!*/
 214 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS   =0x2f,
 215 OFFSET_TO_GET_ATOMBIOS_STRING_START        =0x6e,
 216 };
 217
 218 /****************************************************************************
 219 * Common header for all tables (Data table, Command function).
 220 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
 221 * And the pointer actually points to this header.
 222 ****************************************************************************/
 223
 224 struct atom_common_table_header
 225 {
 226   uint16_t structuresize;
 227   uint8_t  format_revision;   //mainly used for a hw function, when the parser is not backward compatible
 228   uint8_t  content_revision;  //change it when a data table has a structure change, or a hw function has a input/output parameter change
 229 };
 230
 231 /****************************************************************************
 232 * Structure stores the ROM header.
 233 ****************************************************************************/
 234 struct atom_rom_header_v2_2
 235 {
 236   struct atom_common_table_header table_header;
 237   uint8_t  atom_bios_string[4];        //enum atom_string_def atom_bios_string;     //Signature to distinguish between Atombios and non-atombios,
 238   uint16_t bios_segment_address;
 239   uint16_t protectedmodeoffset;
 240   uint16_t configfilenameoffset;
 241   uint16_t crc_block_offset;
 242   uint16_t vbios_bootupmessageoffset;
 243   uint16_t int10_offset;
 244   uint16_t pcibusdevinitcode;
 245   uint16_t iobaseaddress;
 246   uint16_t subsystem_vendor_id;
 247   uint16_t subsystem_id;
 248   uint16_t pci_info_offset;
 249   uint16_t masterhwfunction_offset;      //Offest for SW to get all command function offsets, Don't change the position
 250   uint16_t masterdatatable_offset;       //Offest for SW to get all data table offsets, Don't change the position
 251   uint16_t reserved;
 252   uint32_t pspdirtableoffset;
 253 };
 254
 255 /*==============================hw function portion======================================================================*/
 256
 257
 258 /****************************************************************************
 259 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time
 260 * The real functionality of each function is associated with the parameter structure version when defined
 261 * For all internal cmd function definitions, please reference to atomstruct.h
 262 ****************************************************************************/
 263 struct atom_master_list_of_command_functions_v2_1{
 264   uint16_t asic_init;                   //Function
 265   uint16_t cmd_function1;               //used as an internal one
 266   uint16_t cmd_function2;               //used as an internal one
 267   uint16_t cmd_function3;               //used as an internal one
 268   uint16_t digxencodercontrol;          //Function
 269   uint16_t cmd_function5;               //used as an internal one
 270   uint16_t cmd_function6;               //used as an internal one
 271   uint16_t cmd_function7;               //used as an internal one
 272   uint16_t cmd_function8;               //used as an internal one
 273   uint16_t cmd_function9;               //used as an internal one
 274   uint16_t setengineclock;              //Function
 275   uint16_t setmemoryclock;              //Function
 276   uint16_t setpixelclock;               //Function
 277   uint16_t enabledisppowergating;       //Function
 278   uint16_t cmd_function14;              //used as an internal one
 279   uint16_t cmd_function15;              //used as an internal one
 280   uint16_t cmd_function16;              //used as an internal one
 281   uint16_t cmd_function17;              //used as an internal one
 282   uint16_t cmd_function18;              //used as an internal one
 283   uint16_t cmd_function19;              //used as an internal one
 284   uint16_t cmd_function20;              //used as an internal one
 285   uint16_t cmd_function21;              //used as an internal one
 286   uint16_t cmd_function22;              //used as an internal one
 287   uint16_t cmd_function23;              //used as an internal one
 288   uint16_t cmd_function24;              //used as an internal one
 289   uint16_t cmd_function25;              //used as an internal one
 290   uint16_t cmd_function26;              //used as an internal one
 291   uint16_t cmd_function27;              //used as an internal one
 292   uint16_t cmd_function28;              //used as an internal one
 293   uint16_t cmd_function29;              //used as an internal one
 294   uint16_t cmd_function30;              //used as an internal one
 295   uint16_t cmd_function31;              //used as an internal one
 296   uint16_t cmd_function32;              //used as an internal one
 297   uint16_t cmd_function33;              //used as an internal one
 298   uint16_t blankcrtc;                   //Function
 299   uint16_t enablecrtc;                  //Function
 300   uint16_t cmd_function36;              //used as an internal one
 301   uint16_t cmd_function37;              //used as an internal one
 302   uint16_t cmd_function38;              //used as an internal one
 303   uint16_t cmd_function39;              //used as an internal one
 304   uint16_t cmd_function40;              //used as an internal one
 305   uint16_t getsmuclockinfo;             //Function
 306   uint16_t selectcrtc_source;           //Function
 307   uint16_t cmd_function43;              //used as an internal one
 308   uint16_t cmd_function44;              //used as an internal one
 309   uint16_t cmd_function45;              //used as an internal one
 310   uint16_t setdceclock;                 //Function
 311   uint16_t getmemoryclock;              //Function
 312   uint16_t getengineclock;              //Function
 313   uint16_t setcrtc_usingdtdtiming;      //Function
 314   uint16_t externalencodercontrol;      //Function
 315   uint16_t cmd_function51;              //used as an internal one
 316   uint16_t cmd_function52;              //used as an internal one
 317   uint16_t cmd_function53;              //used as an internal one
 318   uint16_t processi2cchanneltransaction;//Function
 319   uint16_t cmd_function55;              //used as an internal one
 320   uint16_t cmd_function56;              //used as an internal one
 321   uint16_t cmd_function57;              //used as an internal one
 322   uint16_t cmd_function58;              //used as an internal one
 323   uint16_t cmd_function59;              //used as an internal one
 324   uint16_t computegpuclockparam;        //Function
 325   uint16_t cmd_function61;              //used as an internal one
 326   uint16_t cmd_function62;              //used as an internal one
 327   uint16_t dynamicmemorysettings;       //Function function
 328   uint16_t memorytraining;              //Function function
 329   uint16_t cmd_function65;              //used as an internal one
 330   uint16_t cmd_function66;              //used as an internal one
 331   uint16_t setvoltage;                  //Function
 332   uint16_t cmd_function68;              //used as an internal one
 333   uint16_t readefusevalue;              //Function
 334   uint16_t cmd_function70;              //used as an internal one
 335   uint16_t cmd_function71;              //used as an internal one
 336   uint16_t cmd_function72;              //used as an internal one
 337   uint16_t cmd_function73;              //used as an internal one
 338   uint16_t cmd_function74;              //used as an internal one
 339   uint16_t cmd_function75;              //used as an internal one
 340   uint16_t dig1transmittercontrol;      //Function
 341   uint16_t cmd_function77;              //used as an internal one
 342   uint16_t processauxchanneltransaction;//Function
 343   uint16_t cmd_function79;              //used as an internal one
 344   uint16_t getvoltageinfo;              //Function
 345 };
 346
 347 struct atom_master_command_function_v2_1
 348 {
 349   struct atom_common_table_header  table_header;
 350   struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
 351 };
 352
 353 /****************************************************************************
 354 * Structures used in every command function
 355 ****************************************************************************/
 356 struct atom_function_attribute
 357 {
 358   uint16_t  ws_in_bytes:8;            //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 359   uint16_t  ps_in_bytes:7;            //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 360   uint16_t  updated_by_util:1;        //[15]=flag to indicate the function is updated by util
 361 };
 362
 363
 364 /****************************************************************************
 365 * Common header for all hw functions.
 366 * Every function pointed by _master_list_of_hw_function has this common header.
 367 * And the pointer actually points to this header.
 368 ****************************************************************************/
 369 struct atom_rom_hw_function_header
 370 {
 371   struct atom_common_table_header func_header;
 372   struct atom_function_attribute func_attrib;
 373 };
 374
 375
 376 /*==============================sw data table portion======================================================================*/
 377 /****************************************************************************
 378 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
 379 * The real name of each table is given when its data structure version is defined
 380 ****************************************************************************/
 381 struct atom_master_list_of_data_tables_v2_1{
 382   uint16_t utilitypipeline;               /* Offest for the utility to get parser info,Don't change this position!*/
 383   uint16_t multimedia_info;
 384   uint16_t sw_datatable2;
 385   uint16_t sw_datatable3;
 386   uint16_t firmwareinfo;                  /* Shared by various SW components */
 387   uint16_t sw_datatable5;
 388   uint16_t lcd_info;                      /* Shared by various SW components */
 389   uint16_t sw_datatable7;
 390   uint16_t smu_info;
 391   uint16_t sw_datatable9;
 392   uint16_t sw_datatable10;
 393   uint16_t vram_usagebyfirmware;          /* Shared by various SW components */
 394   uint16_t gpio_pin_lut;                  /* Shared by various SW components */
 395   uint16_t sw_datatable13;
 396   uint16_t gfx_info;
 397   uint16_t powerplayinfo;                 /* Shared by various SW components */
 398   uint16_t sw_datatable16;
 399   uint16_t sw_datatable17;
 400   uint16_t sw_datatable18;
 401   uint16_t sw_datatable19;
 402   uint16_t sw_datatable20;
 403   uint16_t sw_datatable21;
 404   uint16_t displayobjectinfo;             /* Shared by various SW components */
 405   uint16_t indirectioaccess;                      /* used as an internal one */
 406   uint16_t umc_info;                      /* Shared by various SW components */
 407   uint16_t sw_datatable25;
 408   uint16_t sw_datatable26;
 409   uint16_t dce_info;                      /* Shared by various SW components */
 410   uint16_t vram_info;                     /* Shared by various SW components */
 411   uint16_t sw_datatable29;
 412   uint16_t integratedsysteminfo;          /* Shared by various SW components */
 413   uint16_t asic_profiling_info;           /* Shared by various SW components */
 414   uint16_t voltageobject_info;            /* shared by various SW components */
 415   uint16_t sw_datatable33;
 416   uint16_t sw_datatable34;
 417 };
 418
 419
 420 struct atom_master_data_table_v2_1
 421 {
 422   struct atom_common_table_header table_header;
 423   struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
 424 };
 425
 426
 427 struct atom_dtd_format
 428 {
 429   uint16_t  pixclk;
 430   uint16_t  h_active;
 431   uint16_t  h_blanking_time;
 432   uint16_t  v_active;
 433   uint16_t  v_blanking_time;
 434   uint16_t  h_sync_offset;
 435   uint16_t  h_sync_width;
 436   uint16_t  v_sync_offset;
 437   uint16_t  v_syncwidth;
 438   uint16_t  reserved;
 439   uint16_t  reserved0;
 440   uint8_t   h_border;
 441   uint8_t   v_border;
 442   uint16_t  miscinfo;
 443   uint8_t   atom_mode_id;
 444   uint8_t   refreshrate;
 445 };
 446
 447 /* atom_dtd_format.modemiscinfo defintion */
 448 enum atom_dtd_format_modemiscinfo{
 449   ATOM_HSYNC_POLARITY    = 0x0002,
 450   ATOM_VSYNC_POLARITY    = 0x0004,
 451   ATOM_H_REPLICATIONBY2  = 0x0010,
 452   ATOM_V_REPLICATIONBY2  = 0x0020,
 453   ATOM_INTERLACE         = 0x0080,
 454   ATOM_COMPOSITESYNC     = 0x0040,
 455 };
 456
 457
 458 /* utilitypipeline
 459  * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
 460  * the location of it can't change
 461 */
 462
 463
 464 /*
 465   ***************************************************************************
 466     Data Table firmwareinfo  structure
 467   ***************************************************************************
 468 */
 469
 470 struct atom_firmware_info_v3_1
 471 {
 472   struct atom_common_table_header table_header;
 473   uint32_t firmware_revision;
 474   uint32_t bootup_sclk_in10khz;
 475   uint32_t bootup_mclk_in10khz;
 476   uint32_t firmware_capability;             // enum atombios_firmware_capability
 477   uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
 478   uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
 479   uint16_t bootup_vddc_mv;
 480   uint16_t bootup_vddci_mv;
 481   uint16_t bootup_mvddc_mv;
 482   uint16_t bootup_vddgfx_mv;
 483   uint8_t  mem_module_id;
 484   uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
 485   uint8_t  reserved1[2];
 486   uint32_t mc_baseaddr_high;
 487   uint32_t mc_baseaddr_low;
 488   uint32_t reserved2[6];
 489 };
 490
 491 /* Total 32bit cap indication */
 492 enum atombios_firmware_capability
 493 {
 494   ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
 495   ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
 496   ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
 497 };
 498
 499 enum atom_cooling_solution_id{
 500   AIR_COOLING    = 0x00,
 501   LIQUID_COOLING = 0x01
 502 };
 503
 504
 505 /*
 506   ***************************************************************************
 507     Data Table lcd_info  structure
 508   ***************************************************************************
 509 */
 510
 511 struct lcd_info_v2_1
 512 {
 513   struct  atom_common_table_header table_header;
 514   struct  atom_dtd_format  lcd_timing;
 515   uint16_t backlight_pwm;
 516   uint16_t special_handle_cap;
 517   uint16_t panel_misc;
 518   uint16_t lvds_max_slink_pclk;
 519   uint16_t lvds_ss_percentage;
 520   uint16_t lvds_ss_rate_10hz;
 521   uint8_t  pwr_on_digon_to_de;          /*all pwr sequence numbers below are in uint of 4ms*/
 522   uint8_t  pwr_on_de_to_vary_bl;
 523   uint8_t  pwr_down_vary_bloff_to_de;
 524   uint8_t  pwr_down_de_to_digoff;
 525   uint8_t  pwr_off_delay;
 526   uint8_t  pwr_on_vary_bl_to_blon;
 527   uint8_t  pwr_down_bloff_to_vary_bloff;
 528   uint8_t  panel_bpc;
 529   uint8_t  dpcd_edp_config_cap;
 530   uint8_t  dpcd_max_link_rate;
 531   uint8_t  dpcd_max_lane_count;
 532   uint8_t  dpcd_max_downspread;
 533   uint8_t  min_allowed_bl_level;
 534   uint8_t  max_allowed_bl_level;
 535   uint8_t  bootup_bl_level;
 536   uint8_t  dplvdsrxid;
 537   uint32_t reserved1[8];
 538 };
 539
 540 /* lcd_info_v2_1.panel_misc defintion */
 541 enum atom_lcd_info_panel_misc{
 542   ATOM_PANEL_MISC_FPDI            =0x0002,
 543 };
 544
 545 //uceDPToLVDSRxId
 546 enum atom_lcd_info_dptolvds_rx_id
 547 {
 548   eDP_TO_LVDS_RX_DISABLE                 = 0x00,       // no eDP->LVDS translator chip
 549   eDP_TO_LVDS_COMMON_ID                  = 0x01,       // common eDP->LVDS translator chip without AMD SW init
 550   eDP_TO_LVDS_REALTEK_ID                 = 0x02,       // Realtek tansaltor which require AMD SW init
 551 };
 552
 553
 554 /*
 555   ***************************************************************************
 556     Data Table gpio_pin_lut  structure
 557   ***************************************************************************
 558 */
 559
 560 struct atom_gpio_pin_assignment
 561 {
 562   uint32_t data_a_reg_index;
 563   uint8_t  gpio_bitshift;
 564   uint8_t  gpio_mask_bitshift;
 565   uint8_t  gpio_id;
 566   uint8_t  reserved;
 567 };
 568
 569 /* atom_gpio_pin_assignment.gpio_id definition */
 570 enum atom_gpio_pin_assignment_gpio_id {
 571   I2C_HW_LANE_MUX        =0x0f, /* only valid when bit7=1 */
 572   I2C_HW_ENGINE_ID_MASK  =0x70, /* only valid when bit7=1 */
 573   I2C_HW_CAP             =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
 574
 575   /* gpio_id pre-define id for multiple usage */
 576   /* GPIO use to control PCIE_VDDC in certain SLT board */
 577   PCIE_VDDC_CONTROL_GPIO_PINID = 56,
 578   /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
 579   PP_AC_DC_SWITCH_GPIO_PINID = 60,
 580   /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
 581   VDDC_VRHOT_GPIO_PINID = 61,
 582   /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
 583   VDDC_PCC_GPIO_PINID = 62,
 584   /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
 585   EFUSE_CUT_ENABLE_GPIO_PINID = 63,
 586   /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
 587   DRAM_SELF_REFRESH_GPIO_PINID = 64,
 588   /* Thermal interrupt output->system thermal chip GPIO pin */
 589   THERMAL_INT_OUTPUT_GPIO_PINID =65,
 590 };
 591
 592
 593 struct atom_gpio_pin_lut_v2_1
 594 {
 595   struct  atom_common_table_header  table_header;
 596   /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut  */
 597   struct  atom_gpio_pin_assignment  gpio_pin[8];
 598 };
 599
 600
 601 /*
 602   ***************************************************************************
 603     Data Table vram_usagebyfirmware  structure
 604   ***************************************************************************
 605 */
 606
 607 struct vram_usagebyfirmware_v2_1
 608 {
 609   struct  atom_common_table_header  table_header;
 610   uint32_t  start_address_in_kb;
 611   uint16_t  used_by_firmware_in_kb;
 612   uint16_t  used_by_driver_in_kb;
 613 };
 614
 615
 616 /*
 617   ***************************************************************************
 618     Data Table displayobjectinfo  structure
 619   ***************************************************************************
 620 */
 621
 622 enum atom_object_record_type_id
 623 {
 624   ATOM_I2C_RECORD_TYPE =1,
 625   ATOM_HPD_INT_RECORD_TYPE =2,
 626   ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
 627   ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
 628   ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
 629   ATOM_ENCODER_CAP_RECORD_TYPE=20,
 630   ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
 631   ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
 632   ATOM_RECORD_END_TYPE  =0xFF,
 633 };
 634
 635 struct atom_common_record_header
 636 {
 637   uint8_t record_type;                      //An emun to indicate the record type
 638   uint8_t record_size;                      //The size of the whole record in byte
 639 };
 640
 641 struct atom_i2c_record
 642 {
 643   struct atom_common_record_header record_header;   //record_type = ATOM_I2C_RECORD_TYPE
 644   uint8_t i2c_id;
 645   uint8_t i2c_slave_addr;                   //The slave address, it's 0 when the record is attached to connector for DDC
 646 };
 647
 648 struct atom_hpd_int_record
 649 {
 650   struct atom_common_record_header record_header;  //record_type = ATOM_HPD_INT_RECORD_TYPE
 651   uint8_t  pin_id;              //Corresponding block in GPIO_PIN_INFO table gives the pin info
 652   uint8_t  plugin_pin_state;
 653 };
 654
 655 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
 656 enum atom_encoder_caps_def
 657 {
 658   ATOM_ENCODER_CAP_RECORD_HBR2                  =0x01,         // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
 659   ATOM_ENCODER_CAP_RECORD_MST_EN                =0x01,         // from SI, this bit means DP MST is enable or not.
 660   ATOM_ENCODER_CAP_RECORD_HBR2_EN               =0x02,         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
 661   ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          =0x04,         // HDMI2.0 6Gbps enable or not.
 662   ATOM_ENCODER_CAP_RECORD_HBR3_EN               =0x08,         // DP1.3 HBR3 is supported by board.
 663 };
 664
 665 struct  atom_encoder_caps_record
 666 {
 667   struct atom_common_record_header record_header;  //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
 668   uint32_t  encodercaps;
 669 };
 670
 671 enum atom_connector_caps_def
 672 {
 673   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY         = 0x01,        //a cap bit to indicate that this non-embedded display connector is an internal display
 674   ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL      = 0x02,        //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
 675 };
 676
 677 struct atom_disp_connector_caps_record
 678 {
 679   struct atom_common_record_header record_header;
 680   uint32_t connectcaps;
 681 };
 682
 683 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
 684 struct atom_gpio_pin_control_pair
 685 {
 686   uint8_t gpio_id;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
 687   uint8_t gpio_pinstate;         // Pin state showing how to set-up the pin
 688 };
 689
 690 struct atom_object_gpio_cntl_record
 691 {
 692   struct atom_common_record_header record_header;
 693   uint8_t flag;                   // Future expnadibility
 694   uint8_t number_of_pins;         // Number of GPIO pins used to control the object
 695   struct atom_gpio_pin_control_pair gpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
 696 };
 697
 698 //Definitions for GPIO pin state
 699 enum atom_gpio_pin_control_pinstate_def
 700 {
 701   GPIO_PIN_TYPE_INPUT             = 0x00,
 702   GPIO_PIN_TYPE_OUTPUT            = 0x10,
 703   GPIO_PIN_TYPE_HW_CONTROL        = 0x20,
 704
 705 //For GPIO_PIN_TYPE_OUTPUT the following is defined
 706   GPIO_PIN_OUTPUT_STATE_MASK      = 0x01,
 707   GPIO_PIN_OUTPUT_STATE_SHIFT     = 0,
 708   GPIO_PIN_STATE_ACTIVE_LOW       = 0x0,
 709   GPIO_PIN_STATE_ACTIVE_HIGH      = 0x1,
 710 };
 711
 712 // Indexes to GPIO array in GLSync record
 713 // GLSync record is for Frame Lock/Gen Lock feature.
 714 enum atom_glsync_record_gpio_index_def
 715 {
 716   ATOM_GPIO_INDEX_GLSYNC_REFCLK    = 0,
 717   ATOM_GPIO_INDEX_GLSYNC_HSYNC     = 1,
 718   ATOM_GPIO_INDEX_GLSYNC_VSYNC     = 2,
 719   ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  = 3,
 720   ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  = 4,
 721   ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
 722   ATOM_GPIO_INDEX_GLSYNC_V_RESET   = 6,
 723   ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
 724   ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  = 8,
 725   ATOM_GPIO_INDEX_GLSYNC_MAX       = 9,
 726 };
 727
 728
 729 struct atom_connector_hpdpin_lut_record     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
 730 {
 731   struct atom_common_record_header record_header;
 732   uint8_t hpd_pin_map[8];
 733 };
 734
 735 struct atom_connector_auxddc_lut_record     //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
 736 {
 737   struct atom_common_record_header record_header;
 738   uint8_t aux_ddc_map[8];
 739 };
 740
 741 struct atom_connector_forced_tmds_cap_record
 742 {
 743   struct atom_common_record_header record_header;
 744   // override TMDS capability on this connector when it operate in TMDS mode.  usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
 745   uint8_t  maxtmdsclkrate_in2_5mhz;
 746   uint8_t  reserved;
 747 };
 748
 749 struct atom_connector_layout_info
 750 {
 751   uint16_t connectorobjid;
 752   uint8_t  connector_type;
 753   uint8_t  position;
 754 };
 755
 756 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
 757 enum atom_connector_layout_info_connector_type_def
 758 {
 759   CONNECTOR_TYPE_DVI_D                 = 1,
 760
 761   CONNECTOR_TYPE_HDMI                  = 4,
 762   CONNECTOR_TYPE_DISPLAY_PORT          = 5,
 763   CONNECTOR_TYPE_MINI_DISPLAY_PORT     = 6,
 764 };
 765
 766 struct  atom_bracket_layout_record
 767 {
 768   struct atom_common_record_header record_header;
 769   uint8_t bracketlen;
 770   uint8_t bracketwidth;
 771   uint8_t conn_num;
 772   uint8_t reserved;
 773   struct atom_connector_layout_info  conn_info[1];
 774 };
 775
 776 enum atom_display_device_tag_def{
 777   ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002,  //an embedded display is either an LVDS or eDP signal type of display
 778   ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
 779   ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
 780   ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
 781   ATOM_DISPLAY_DFP4_SUPPORT            = 0x0400,
 782   ATOM_DISPLAY_DFP5_SUPPORT            = 0x0800,
 783   ATOM_DISPLAY_DFP6_SUPPORT            = 0x0040,
 784   ATOM_DISPLAY_DFPx_SUPPORT            = 0x0ec8,
 785 };
 786
 787 struct atom_display_object_path_v2
 788 {
 789   uint16_t display_objid;                  //Connector Object ID or Misc Object ID
 790   uint16_t disp_recordoffset;
 791   uint16_t encoderobjid;                   //first encoder closer to the connector, could be either an external or intenal encoder
 792   uint16_t extencoderobjid;                //2nd encoder after the first encoder, from the connector point of view;
 793   uint16_t encoder_recordoffset;
 794   uint16_t extencoder_recordoffset;
 795   uint16_t device_tag;                     //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
 796   uint8_t  priority_id;
 797   uint8_t  reserved;
 798 };
 799
 800 struct display_object_info_table_v1_4
 801 {
 802   struct    atom_common_table_header  table_header;
 803   uint16_t  supporteddevices;
 804   uint8_t   number_of_path;
 805   uint8_t   reserved;
 806   struct    atom_display_object_path_v2 display_path[8];   //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
 807 };
 808
 809
 810 /*
 811   ***************************************************************************
 812     Data Table dce_info  structure
 813   ***************************************************************************
 814 */
 815 struct atom_display_controller_info_v4_1
 816 {
 817   struct  atom_common_table_header  table_header;
 818   uint32_t display_caps;
 819   uint32_t bootup_dispclk_10khz;
 820   uint16_t dce_refclk_10khz;
 821   uint16_t i2c_engine_refclk_10khz;
 822   uint16_t dvi_ss_percentage;       // in unit of 0.001%
 823   uint16_t dvi_ss_rate_10hz;
 824   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
 825   uint16_t hdmi_ss_rate_10hz;
 826   uint16_t dp_ss_percentage;        // in unit of 0.001%
 827   uint16_t dp_ss_rate_10hz;
 828   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
 829   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
 830   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
 831   uint8_t  ss_reserved;
 832   uint8_t  hardcode_mode_num;       // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
 833   uint8_t  reserved1[3];
 834   uint16_t dpphy_refclk_10khz;
 835   uint16_t reserved2;
 836   uint8_t  dceip_min_ver;
 837   uint8_t  dceip_max_ver;
 838   uint8_t  max_disp_pipe_num;
 839   uint8_t  max_vbios_active_disp_pipe_num;
 840   uint8_t  max_ppll_num;
 841   uint8_t  max_disp_phy_num;
 842   uint8_t  max_aux_pairs;
 843   uint8_t  remotedisplayconfig;
 844   uint8_t  reserved3[8];
 845 };
 846
 847
 848 struct atom_display_controller_info_v4_2
 849 {
 850   struct  atom_common_table_header  table_header;
 851   uint32_t display_caps;
 852   uint32_t bootup_dispclk_10khz;
 853   uint16_t dce_refclk_10khz;
 854   uint16_t i2c_engine_refclk_10khz;
 855   uint16_t dvi_ss_percentage;       // in unit of 0.001%
 856   uint16_t dvi_ss_rate_10hz;
 857   uint16_t hdmi_ss_percentage;      // in unit of 0.001%
 858   uint16_t hdmi_ss_rate_10hz;
 859   uint16_t dp_ss_percentage;        // in unit of 0.001%
 860   uint16_t dp_ss_rate_10hz;
 861   uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
 862   uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
 863   uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
 864   uint8_t  ss_reserved;
 865   uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
 866   uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
 867   uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
 868   uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
 869   uint16_t dpphy_refclk_10khz;
 870   uint16_t reserved2;
 871   uint8_t  dcnip_min_ver;
 872   uint8_t  dcnip_max_ver;
 873   uint8_t  max_disp_pipe_num;
 874   uint8_t  max_vbios_active_disp_pipe_num;
 875   uint8_t  max_ppll_num;
 876   uint8_t  max_disp_phy_num;
 877   uint8_t  max_aux_pairs;
 878   uint8_t  remotedisplayconfig;
 879   uint8_t  reserved3[8];
 880 };
 881
 882
 883 enum dce_info_caps_def
 884 {
 885   // only for VBIOS
 886   DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED  =0x02,
 887   // only for VBIOS
 888   DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2      =0x04,
 889   // only for VBIOS
 890   DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
 891
 892 };
 893
 894 /*
 895   ***************************************************************************
 896     Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO  structure
 897   ***************************************************************************
 898 */
 899 struct atom_ext_display_path
 900 {
 901   uint16_t  device_tag;                      //A bit vector to show what devices are supported
 902   uint16_t  device_acpi_enum;                //16bit device ACPI id.
 903   uint16_t  connectorobjid;                  //A physical connector for displays to plug in, using object connector definitions
 904   uint8_t   auxddclut_index;                 //An index into external AUX/DDC channel LUT
 905   uint8_t   hpdlut_index;                    //An index into external HPD pin LUT
 906   uint16_t  ext_encoder_objid;               //external encoder object id
 907   uint8_t   channelmapping;                  // if ucChannelMapping=0, using default one to one mapping
 908   uint8_t   chpninvert;                      // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
 909   uint16_t  caps;
 910   uint16_t  reserved;
 911 };
 912
 913 //usCaps
 914 enum ext_display_path_cap_def
 915 {
 916   EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               =0x0001,
 917   EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             =0x0002,
 918   EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK              =0x007C,
 919 };
 920
 921 struct atom_external_display_connection_info
 922 {
 923   struct  atom_common_table_header  table_header;
 924   uint8_t                  guid[16];                                  // a GUID is a 16 byte long string
 925   struct atom_ext_display_path path[7];                               // total of fixed 7 entries.
 926   uint8_t                  checksum;                                  // a simple Checksum of the sum of whole structure equal to 0x0.
 927   uint8_t                  stereopinid;                               // use for eDP panel
 928   uint8_t                  remotedisplayconfig;
 929   uint8_t                  edptolvdsrxid;
 930   uint8_t                  fixdpvoltageswing;                         // usCaps[1]=1, this indicate DP_LANE_SET value
 931   uint8_t                  reserved[3];                               // for potential expansion
 932 };
 933
 934 /*
 935   ***************************************************************************
 936     Data Table integratedsysteminfo  structure
 937   ***************************************************************************
 938 */
 939
 940 struct atom_camera_dphy_timing_param
 941 {
 942   uint8_t  profile_id;       // SENSOR_PROFILES
 943   uint32_t param;
 944 };
 945
 946 struct atom_camera_dphy_elec_param
 947 {
 948   uint16_t param[3];
 949 };
 950
 951 struct atom_camera_module_info
 952 {
 953   uint8_t module_id;                    // 0: Rear, 1: Front right of user, 2: Front left of user
 954   uint8_t module_name[8];
 955   struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
 956 };
 957
 958 struct atom_camera_flashlight_info
 959 {
 960   uint8_t flashlight_id;                // 0: Rear, 1: Front
 961   uint8_t name[8];
 962 };
 963
 964 struct atom_camera_data
 965 {
 966   uint32_t versionCode;
 967   struct atom_camera_module_info cameraInfo[3];      // Assuming 3 camera sensors max
 968   struct atom_camera_flashlight_info flashInfo;      // Assuming 1 flashlight max
 969   struct atom_camera_dphy_elec_param dphy_param;
 970   uint32_t crc_val;         // CRC
 971 };
 972
 973
 974 struct atom_14nm_dpphy_dvihdmi_tuningset
 975 {
 976   uint32_t max_symclk_in10khz;
 977   uint8_t encoder_mode;            //atom_encode_mode_def, =2: DVI, =3: HDMI mode
 978   uint8_t phy_sel;                 //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
 979   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
 980   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
 981   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
 982   uint8_t tx_driver_fifty_ohms;    //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
 983   uint8_t deemph_sel;              //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
 984 };
 985
 986 struct atom_14nm_dpphy_dp_setting{
 987   uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
 988   uint16_t margindeemph;           //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
 989   uint8_t deemph_6db_4;            //COMMON_SELDEEMPH60[31:24]deemph_6db_4
 990   uint8_t boostadj;                //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj  [20]tx_boost_en  [23:22]tx_binary_ron_code_offset
 991 };
 992
 993 struct atom_14nm_dpphy_dp_tuningset{
 994   uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
 995   uint8_t version;
 996   uint16_t table_size;             // size of atom_14nm_dpphy_dp_tuningset
 997   uint16_t reserved;
 998   struct atom_14nm_dpphy_dp_setting dptuning[10];
 999 };
1000
1001 struct atom_14nm_dig_transmitter_info_header_v4_0{
1002   struct  atom_common_table_header  table_header;
1003   uint16_t pcie_phy_tmds_hdmi_macro_settings_offset;     // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1004   uint16_t uniphy_vs_emph_lookup_table_offset;           // offset of UniphyVSEmphLookUpTbl
1005   uint16_t uniphy_xbar_settings_table_offset;            // offset of UniphyXbarSettingsTbl
1006 };
1007
1008 struct atom_14nm_combphy_tmds_vs_set
1009 {
1010   uint8_t sym_clk;
1011   uint8_t dig_mode;
1012   uint8_t phy_sel;
1013   uint16_t common_mar_deemph_nom__margin_deemph_val;
1014   uint8_t common_seldeemph60__deemph_6db_4_val;
1015   uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1016   uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1017   uint8_t margin_deemph_lane0__deemph_sel_val;
1018 };
1019
1020 struct atom_i2c_reg_info {
1021   uint8_t ucI2cRegIndex;
1022   uint8_t ucI2cRegVal;
1023 };
1024
1025 struct atom_hdmi_retimer_redriver_set {
1026   uint8_t HdmiSlvAddr;
1027   uint8_t HdmiRegNum;
1028   uint8_t Hdmi6GRegNum;
1029   struct atom_i2c_reg_info HdmiRegSetting[9];        //For non 6G Hz use
1030   struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];    //For 6G Hz use.
1031 };
1032
1033 struct atom_integrated_system_info_v1_11
1034 {
1035   struct  atom_common_table_header  table_header;
1036   uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1037   uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
1038   uint32_t  system_config;
1039   uint32_t  cpucapinfo;
1040   uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
1041   uint16_t  gpuclk_ss_type;
1042   uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1043   uint16_t  lvds_ss_rate_10hz;
1044   uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1045   uint16_t  hdmi_ss_rate_10hz;
1046   uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1047   uint16_t  dvi_ss_rate_10hz;
1048   uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1049   uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1050   uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1051   uint8_t   memorytype;                       // enum of atom_sys_mem_type
1052   uint8_t   umachannelnumber;                 // number of memory channels
1053   uint8_t   pwr_on_digon_to_de;               /* all pwr sequence numbers below are in uint of 4ms */
1054   uint8_t   pwr_on_de_to_vary_bl;
1055   uint8_t   pwr_down_vary_bloff_to_de;
1056   uint8_t   pwr_down_de_to_digoff;
1057   uint8_t   pwr_off_delay;
1058   uint8_t   pwr_on_vary_bl_to_blon;
1059   uint8_t   pwr_down_bloff_to_vary_bloff;
1060   uint8_t   min_allowed_bl_level;
1061   struct atom_external_display_connection_info extdispconninfo;
1062   struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1063   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1064   struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1065   struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
1066   struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
1067   struct atom_camera_data  camera_info;
1068   struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1069   struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1070   struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1071   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1072   uint32_t  reserved[108];
1073 };
1074
1075
1076 // system_config
1077 enum atom_system_vbiosmisc_def{
1078   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1079 };
1080
1081
1082 // gpucapinfo
1083 enum atom_system_gpucapinf_def{
1084   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
1085 };
1086
1087 //dpphy_override
1088 enum atom_sysinfo_dpphy_override_def{
1089   ATOM_ENABLE_DVI_TUNINGSET   = 0x01,
1090   ATOM_ENABLE_HDMI_TUNINGSET  = 0x02,
1091   ATOM_ENABLE_HDMI6G_TUNINGSET  = 0x04,
1092   ATOM_ENABLE_DP_TUNINGSET  = 0x08,
1093   ATOM_ENABLE_DP_HBR3_TUNINGSET  = 0x10,
1094 };
1095
1096 //lvds_misc
1097 enum atom_sys_info_lvds_misc_def
1098 {
1099   SYS_INFO_LVDS_MISC_888_FPDI_MODE                 =0x01,
1100   SYS_INFO_LVDS_MISC_888_BPC_MODE                  =0x04,
1101   SYS_INFO_LVDS_MISC_OVERRIDE_EN                   =0x08,
1102 };
1103
1104
1105 //memorytype  DMI Type 17 offset 12h - Memory Type
1106 enum atom_dmi_t17_mem_type_def{
1107   OtherMemType = 0x01,                                  ///< Assign 01 to Other
1108   UnknownMemType,                                       ///< Assign 02 to Unknown
1109   DramMemType,                                          ///< Assign 03 to DRAM
1110   EdramMemType,                                         ///< Assign 04 to EDRAM
1111   VramMemType,                                          ///< Assign 05 to VRAM
1112   SramMemType,                                          ///< Assign 06 to SRAM
1113   RamMemType,                                           ///< Assign 07 to RAM
1114   RomMemType,                                           ///< Assign 08 to ROM
1115   FlashMemType,                                         ///< Assign 09 to Flash
1116   EepromMemType,                                        ///< Assign 10 to EEPROM
1117   FepromMemType,                                        ///< Assign 11 to FEPROM
1118   EpromMemType,                                         ///< Assign 12 to EPROM
1119   CdramMemType,                                         ///< Assign 13 to CDRAM
1120   ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
1121   SdramMemType,                                         ///< Assign 15 to SDRAM
1122   SgramMemType,                                         ///< Assign 16 to SGRAM
1123   RdramMemType,                                         ///< Assign 17 to RDRAM
1124   DdrMemType,                                           ///< Assign 18 to DDR
1125   Ddr2MemType,                                          ///< Assign 19 to DDR2
1126   Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
1127   Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
1128   Fbd2MemType,                                          ///< Assign 25 to FBD2
1129   Ddr4MemType,                                          ///< Assign 26 to DDR4
1130   LpDdrMemType,                                         ///< Assign 27 to LPDDR
1131   LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
1132   LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
1133   LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
1134 };
1135
1136
1137 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1138 struct atom_fusion_system_info_v4
1139 {
1140   struct atom_integrated_system_info_v1_11   sysinfo;           // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1141   uint32_t   powerplayinfo[256];                                // Reserve 1024 bytes space for PowerPlayInfoTable
1142 };
1143
1144
1145 /*
1146   ***************************************************************************
1147     Data Table gfx_info  structure
1148   ***************************************************************************
1149 */
1150
1151 struct  atom_gfx_info_v2_2
1152 {
1153   struct  atom_common_table_header  table_header;
1154   uint8_t gfxip_min_ver;
1155   uint8_t gfxip_max_ver;
1156   uint8_t max_shader_engines;
1157   uint8_t max_tile_pipes;
1158   uint8_t max_cu_per_sh;
1159   uint8_t max_sh_per_se;
1160   uint8_t max_backends_per_se;
1161   uint8_t max_texture_channel_caches;
1162   uint32_t regaddr_cp_dma_src_addr;
1163   uint32_t regaddr_cp_dma_src_addr_hi;
1164   uint32_t regaddr_cp_dma_dst_addr;
1165   uint32_t regaddr_cp_dma_dst_addr_hi;
1166   uint32_t regaddr_cp_dma_command;
1167   uint32_t regaddr_cp_status;
1168   uint32_t regaddr_rlc_gpu_clock_32;
1169   uint32_t rlc_gpu_timer_refclk;
1170 };
1171
1172
1173
1174 /*
1175   ***************************************************************************
1176     Data Table smu_info  structure
1177   ***************************************************************************
1178 */
1179 struct atom_smu_info_v3_1
1180 {
1181   struct  atom_common_table_header  table_header;
1182   uint8_t smuip_min_ver;
1183   uint8_t smuip_max_ver;
1184   uint8_t smu_rsd1;
1185   uint8_t gpuclk_ss_mode;           // enum of atom_spread_spectrum_mode
1186   uint16_t sclk_ss_percentage;
1187   uint16_t sclk_ss_rate_10hz;
1188   uint16_t gpuclk_ss_percentage;    // in unit of 0.001%
1189   uint16_t gpuclk_ss_rate_10hz;
1190   uint32_t core_refclk_10khz;
1191   uint8_t  ac_dc_gpio_bit;          // GPIO bit shift in SMU_GPIOPAD_A  configured for AC/DC switching, =0xff means invalid
1192   uint8_t  ac_dc_polarity;          // GPIO polarity for AC/DC switching
1193   uint8_t  vr0hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A  configured for VR0 HOT event, =0xff means invalid
1194   uint8_t  vr0hot_polarity;         // GPIO polarity for VR0 HOT event
1195   uint8_t  vr1hot_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1196   uint8_t  vr1hot_polarity;         // GPIO polarity for VR1 HOT event
1197   uint8_t  fw_ctf_gpio_bit;         // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1198   uint8_t  fw_ctf_polarity;         // GPIO polarity for CTF
1199 };
1200
1201
1202
1203 /*
1204   ***************************************************************************
1205     Data Table asic_profiling_info  structure
1206   ***************************************************************************
1207 */
1208 struct  atom_asic_profiling_info_v4_1
1209 {
1210   struct  atom_common_table_header  table_header;
1211   uint32_t  maxvddc;
1212   uint32_t  minvddc;
1213   uint32_t  avfs_meannsigma_acontant0;
1214   uint32_t  avfs_meannsigma_acontant1;
1215   uint32_t  avfs_meannsigma_acontant2;
1216   uint16_t  avfs_meannsigma_dc_tol_sigma;
1217   uint16_t  avfs_meannsigma_platform_mean;
1218   uint16_t  avfs_meannsigma_platform_sigma;
1219   uint32_t  gb_vdroop_table_cksoff_a0;
1220   uint32_t  gb_vdroop_table_cksoff_a1;
1221   uint32_t  gb_vdroop_table_cksoff_a2;
1222   uint32_t  gb_vdroop_table_ckson_a0;
1223   uint32_t  gb_vdroop_table_ckson_a1;
1224   uint32_t  gb_vdroop_table_ckson_a2;
1225   uint32_t  avfsgb_fuse_table_cksoff_m1;
1226   uint32_t  avfsgb_fuse_table_cksoff_m2;
1227   uint32_t  avfsgb_fuse_table_cksoff_b;
1228   uint32_t  avfsgb_fuse_table_ckson_m1;
1229   uint32_t  avfsgb_fuse_table_ckson_m2;
1230   uint32_t  avfsgb_fuse_table_ckson_b;
1231   uint16_t  max_voltage_0_25mv;
1232   uint8_t   enable_gb_vdroop_table_cksoff;
1233   uint8_t   enable_gb_vdroop_table_ckson;
1234   uint8_t   enable_gb_fuse_table_cksoff;
1235   uint8_t   enable_gb_fuse_table_ckson;
1236   uint16_t  psm_age_comfactor;
1237   uint8_t   enable_apply_avfs_cksoff_voltage;
1238   uint8_t   reserved;
1239   uint32_t  dispclk2gfxclk_a;
1240   uint32_t  dispclk2gfxclk_b;
1241   uint32_t  dispclk2gfxclk_c;
1242   uint32_t  pixclk2gfxclk_a;
1243   uint32_t  pixclk2gfxclk_b;
1244   uint32_t  pixclk2gfxclk_c;
1245   uint32_t  dcefclk2gfxclk_a;
1246   uint32_t  dcefclk2gfxclk_b;
1247   uint32_t  dcefclk2gfxclk_c;
1248   uint32_t  phyclk2gfxclk_a;
1249   uint32_t  phyclk2gfxclk_b;
1250   uint32_t  phyclk2gfxclk_c;
1251 };
1252
1253 struct  atom_asic_profiling_info_v4_2 {
1254         struct  atom_common_table_header  table_header;
1255         uint32_t  maxvddc;
1256         uint32_t  minvddc;
1257         uint32_t  avfs_meannsigma_acontant0;
1258         uint32_t  avfs_meannsigma_acontant1;
1259         uint32_t  avfs_meannsigma_acontant2;
1260         uint16_t  avfs_meannsigma_dc_tol_sigma;
1261         uint16_t  avfs_meannsigma_platform_mean;
1262         uint16_t  avfs_meannsigma_platform_sigma;
1263         uint32_t  gb_vdroop_table_cksoff_a0;
1264         uint32_t  gb_vdroop_table_cksoff_a1;
1265         uint32_t  gb_vdroop_table_cksoff_a2;
1266         uint32_t  gb_vdroop_table_ckson_a0;
1267         uint32_t  gb_vdroop_table_ckson_a1;
1268         uint32_t  gb_vdroop_table_ckson_a2;
1269         uint32_t  avfsgb_fuse_table_cksoff_m1;
1270         uint32_t  avfsgb_fuse_table_cksoff_m2;
1271         uint32_t  avfsgb_fuse_table_cksoff_b;
1272         uint32_t  avfsgb_fuse_table_ckson_m1;
1273         uint32_t  avfsgb_fuse_table_ckson_m2;
1274         uint32_t  avfsgb_fuse_table_ckson_b;
1275         uint16_t  max_voltage_0_25mv;
1276         uint8_t   enable_gb_vdroop_table_cksoff;
1277         uint8_t   enable_gb_vdroop_table_ckson;
1278         uint8_t   enable_gb_fuse_table_cksoff;
1279         uint8_t   enable_gb_fuse_table_ckson;
1280         uint16_t  psm_age_comfactor;
1281         uint8_t   enable_apply_avfs_cksoff_voltage;
1282         uint8_t   reserved;
1283         uint32_t  dispclk2gfxclk_a;
1284         uint32_t  dispclk2gfxclk_b;
1285         uint32_t  dispclk2gfxclk_c;
1286         uint32_t  pixclk2gfxclk_a;
1287         uint32_t  pixclk2gfxclk_b;
1288         uint32_t  pixclk2gfxclk_c;
1289         uint32_t  dcefclk2gfxclk_a;
1290         uint32_t  dcefclk2gfxclk_b;
1291         uint32_t  dcefclk2gfxclk_c;
1292         uint32_t  phyclk2gfxclk_a;
1293         uint32_t  phyclk2gfxclk_b;
1294         uint32_t  phyclk2gfxclk_c;
1295         uint32_t  acg_gb_vdroop_table_a0;
1296         uint32_t  acg_gb_vdroop_table_a1;
1297         uint32_t  acg_gb_vdroop_table_a2;
1298         uint32_t  acg_avfsgb_fuse_table_m1;
1299         uint32_t  acg_avfsgb_fuse_table_m2;
1300         uint32_t  acg_avfsgb_fuse_table_b;
1301         uint8_t   enable_acg_gb_vdroop_table;
1302         uint8_t   enable_acg_gb_fuse_table;
1303         uint32_t  acg_dispclk2gfxclk_a;
1304         uint32_t  acg_dispclk2gfxclk_b;
1305         uint32_t  acg_dispclk2gfxclk_c;
1306         uint32_t  acg_pixclk2gfxclk_a;
1307         uint32_t  acg_pixclk2gfxclk_b;
1308         uint32_t  acg_pixclk2gfxclk_c;
1309         uint32_t  acg_dcefclk2gfxclk_a;
1310         uint32_t  acg_dcefclk2gfxclk_b;
1311         uint32_t  acg_dcefclk2gfxclk_c;
1312         uint32_t  acg_phyclk2gfxclk_a;
1313         uint32_t  acg_phyclk2gfxclk_b;
1314         uint32_t  acg_phyclk2gfxclk_c;
1315 };
1316
1317 /*
1318   ***************************************************************************
1319     Data Table multimedia_info  structure
1320   ***************************************************************************
1321 */
1322 struct atom_multimedia_info_v2_1
1323 {
1324   struct  atom_common_table_header  table_header;
1325   uint8_t uvdip_min_ver;
1326   uint8_t uvdip_max_ver;
1327   uint8_t vceip_min_ver;
1328   uint8_t vceip_max_ver;
1329   uint16_t uvd_enc_max_input_width_pixels;
1330   uint16_t uvd_enc_max_input_height_pixels;
1331   uint16_t vce_enc_max_input_width_pixels;
1332   uint16_t vce_enc_max_input_height_pixels;
1333   uint32_t uvd_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
1334   uint32_t vce_enc_max_bandwidth;           // 16x16 pixels/sec, codec independent
1335 };
1336
1337
1338 /*
1339   ***************************************************************************
1340     Data Table umc_info  structure
1341   ***************************************************************************
1342 */
1343 struct atom_umc_info_v3_1
1344 {
1345   struct  atom_common_table_header  table_header;
1346   uint32_t ucode_version;
1347   uint32_t ucode_rom_startaddr;
1348   uint32_t ucode_length;
1349   uint16_t umc_reg_init_offset;
1350   uint16_t customer_ucode_name_offset;
1351   uint16_t mclk_ss_percentage;
1352   uint16_t mclk_ss_rate_10hz;
1353   uint8_t umcip_min_ver;
1354   uint8_t umcip_max_ver;
1355   uint8_t vram_type;              //enum of atom_dgpu_vram_type
1356   uint8_t umc_config;
1357   uint32_t mem_refclk_10khz;
1358 };
1359
1360
1361 /*
1362   ***************************************************************************
1363     Data Table vram_info  structure
1364   ***************************************************************************
1365 */
1366 struct atom_vram_module_v9
1367 {
1368   // Design Specific Values
1369   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1370   uint32_t  channel_enable;                // for 32 channel ASIC usage
1371   uint32_t  umcch_addrcfg;
1372   uint32_t  umcch_addrsel;
1373   uint32_t  umcch_colsel;
1374   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
1375   uint8_t   ext_memory_id;                 // Current memory module ID
1376   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
1377   uint8_t   channel_num;                   // Number of mem. channels supported in this module
1378   uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1379   uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1380   uint8_t   tunningset_id;                 // MC phy registers set per.
1381   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
1382   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1383   uint16_t  vram_rsd2;                     // reserved
1384   char    dram_pnstring[20];               // part number end with '0'.
1385 };
1386
1387
1388 struct atom_vram_info_header_v2_3
1389 {
1390   struct   atom_common_table_header  table_header;
1391   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1392   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1393   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1394   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
1395   uint16_t dram_data_remap_tbloffset;                    // reserved for now
1396   uint16_t vram_rsd2[3];
1397   uint8_t  vram_module_num;                              // indicate number of VRAM module
1398   uint8_t  vram_rsd1[2];
1399   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1400   struct   atom_vram_module_v9  vram_module[16];         // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1401 };
1402
1403 struct atom_umc_register_addr_info{
1404   uint32_t  umc_register_addr:24;
1405   uint32_t  umc_reg_type_ind:1;
1406   uint32_t  umc_reg_rsvd:7;
1407 };
1408
1409 //atom_umc_register_addr_info.
1410 enum atom_umc_register_addr_info_flag{
1411   b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS  =0x01,
1412 };
1413
1414 union atom_umc_register_addr_info_access
1415 {
1416   struct atom_umc_register_addr_info umc_reg_addr;
1417   uint32_t u32umc_reg_addr;
1418 };
1419
1420 struct atom_umc_reg_setting_id_config{
1421   uint32_t memclockrange:24;
1422   uint32_t mem_blk_id:8;
1423 };
1424
1425 union atom_umc_reg_setting_id_config_access
1426 {
1427   struct atom_umc_reg_setting_id_config umc_id_access;
1428   uint32_t  u32umc_id_access;
1429 };
1430
1431 struct atom_umc_reg_setting_data_block{
1432   union atom_umc_reg_setting_id_config_access  block_id;
1433   uint32_t u32umc_reg_data[1];
1434 };
1435
1436 struct atom_umc_init_reg_block{
1437   uint16_t umc_reg_num;
1438   uint16_t reserved;
1439   union atom_umc_register_addr_info_access umc_reg_list[1];     //for allocation purpose, the real number come from umc_reg_num;
1440   struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1441 };
1442
1443
1444 /*
1445   ***************************************************************************
1446     Data Table voltageobject_info  structure
1447   ***************************************************************************
1448 */
1449 struct  atom_i2c_data_entry
1450 {
1451   uint16_t  i2c_reg_index;               // i2c register address, can be up to 16bit
1452   uint16_t  i2c_reg_data;                // i2c register data, can be up to 16bit
1453 };
1454
1455 struct atom_voltage_object_header_v4{
1456   uint8_t    voltage_type;                           //enum atom_voltage_type
1457   uint8_t    voltage_mode;                           //enum atom_voltage_object_mode
1458   uint16_t   object_size;                            //Size of Object
1459 };
1460
1461 // atom_voltage_object_header_v4.voltage_mode
1462 enum atom_voltage_object_mode
1463 {
1464    VOLTAGE_OBJ_GPIO_LUT              =  0,        //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1465    VOLTAGE_OBJ_VR_I2C_INIT_SEQ       =  3,        //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1466    VOLTAGE_OBJ_PHASE_LUT             =  4,        //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1467    VOLTAGE_OBJ_SVID2                 =  7,        //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1468    VOLTAGE_OBJ_EVV                   =  8,
1469    VOLTAGE_OBJ_MERGED_POWER          =  9,
1470 };
1471
1472 struct  atom_i2c_voltage_object_v4
1473 {
1474    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1475    uint8_t  regulator_id;                        //Indicate Voltage Regulator Id
1476    uint8_t  i2c_id;
1477    uint8_t  i2c_slave_addr;
1478    uint8_t  i2c_control_offset;
1479    uint8_t  i2c_flag;                            // Bit0: 0 - One byte data; 1 - Two byte data
1480    uint8_t  i2c_speed;                           // =0, use default i2c speed, otherwise use it in unit of kHz.
1481    uint8_t  reserved[2];
1482    struct atom_i2c_data_entry i2cdatalut[1];     // end with 0xff
1483 };
1484
1485 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1486 enum atom_i2c_voltage_control_flag
1487 {
1488    VOLTAGE_DATA_ONE_BYTE = 0,
1489    VOLTAGE_DATA_TWO_BYTE = 1,
1490 };
1491
1492
1493 struct atom_voltage_gpio_map_lut
1494 {
1495   uint32_t  voltage_gpio_reg_val;              // The Voltage ID which is used to program GPIO register
1496   uint16_t  voltage_level_mv;                  // The corresponding Voltage Value, in mV
1497 };
1498
1499 struct atom_gpio_voltage_object_v4
1500 {
1501    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1502    uint8_t  gpio_control_id;                     // default is 0 which indicate control through CG VID mode
1503    uint8_t  gpio_entry_num;                      // indiate the entry numbers of Votlage/Gpio value Look up table
1504    uint8_t  phase_delay_us;                      // phase delay in unit of micro second
1505    uint8_t  reserved;
1506    uint32_t gpio_mask_val;                         // GPIO Mask value
1507    struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1508 };
1509
1510 struct  atom_svid2_voltage_object_v4
1511 {
1512    struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_SVID2
1513    uint8_t loadline_psi1;                        // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1514    uint8_t psi0_l_vid_thresd;                    // VR PSI0_L VID threshold
1515    uint8_t psi0_enable;                          //
1516    uint8_t maxvstep;
1517    uint8_t telemetry_offset;
1518    uint8_t telemetry_gain;
1519    uint16_t reserved1;
1520 };
1521
1522 struct atom_merged_voltage_object_v4
1523 {
1524   struct atom_voltage_object_header_v4 header;  // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1525   uint8_t  merged_powerrail_type;               //enum atom_voltage_type
1526   uint8_t  reserved[3];
1527 };
1528
1529 union atom_voltage_object_v4{
1530   struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1531   struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1532   struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1533   struct atom_merged_voltage_object_v4 merged_voltage_obj;
1534 };
1535
1536 struct  atom_voltage_objects_info_v4_1
1537 {
1538   struct atom_common_table_header table_header;
1539   union atom_voltage_object_v4 voltage_object[1];   //Info for Voltage control
1540 };
1541
1542
1543 /*
1544   ***************************************************************************
1545               All Command Function structure definition
1546   ***************************************************************************
1547 */
1548
1549 /*
1550   ***************************************************************************
1551               Structures used by asic_init
1552   ***************************************************************************
1553 */
1554
1555 struct asic_init_engine_parameters
1556 {
1557   uint32_t sclkfreqin10khz:24;
1558   uint32_t engineflag:8;              /* enum atom_asic_init_engine_flag  */
1559 };
1560
1561 struct asic_init_mem_parameters
1562 {
1563   uint32_t mclkfreqin10khz:24;
1564   uint32_t memflag:8;                 /* enum atom_asic_init_mem_flag  */
1565 };
1566
1567 struct asic_init_parameters_v2_1
1568 {
1569   struct asic_init_engine_parameters engineparam;
1570   struct asic_init_mem_parameters memparam;
1571 };
1572
1573 struct asic_init_ps_allocation_v2_1
1574 {
1575   struct asic_init_parameters_v2_1 param;
1576   uint32_t reserved[16];
1577 };
1578
1579
1580 enum atom_asic_init_engine_flag
1581 {
1582   b3NORMAL_ENGINE_INIT = 0,
1583   b3SRIOV_SKIP_ASIC_INIT = 0x02,
1584   b3SRIOV_LOAD_UCODE = 0x40,
1585 };
1586
1587 enum atom_asic_init_mem_flag
1588 {
1589   b3NORMAL_MEM_INIT = 0,
1590   b3DRAM_SELF_REFRESH_EXIT =0x20,
1591 };
1592
1593 /*
1594   ***************************************************************************
1595               Structures used by setengineclock
1596   ***************************************************************************
1597 */
1598
1599 struct set_engine_clock_parameters_v2_1
1600 {
1601   uint32_t sclkfreqin10khz:24;
1602   uint32_t sclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
1603   uint32_t reserved[10];
1604 };
1605
1606 struct set_engine_clock_ps_allocation_v2_1
1607 {
1608   struct set_engine_clock_parameters_v2_1 clockinfo;
1609   uint32_t reserved[10];
1610 };
1611
1612
1613 enum atom_set_engine_mem_clock_flag
1614 {
1615   b3NORMAL_CHANGE_CLOCK = 0,
1616   b3FIRST_TIME_CHANGE_CLOCK = 0x08,
1617   b3STORE_DPM_TRAINGING = 0x40,         //Applicable to memory clock change,when set, it store specific DPM mode training result
1618 };
1619
1620 /*
1621   ***************************************************************************
1622               Structures used by getengineclock
1623   ***************************************************************************
1624 */
1625 struct get_engine_clock_parameter
1626 {
1627   uint32_t sclk_10khz;          // current engine speed in 10KHz unit
1628   uint32_t reserved;
1629 };
1630
1631 /*
1632   ***************************************************************************
1633               Structures used by setmemoryclock
1634   ***************************************************************************
1635 */
1636 struct set_memory_clock_parameters_v2_1
1637 {
1638   uint32_t mclkfreqin10khz:24;
1639   uint32_t mclkflag:8;              /* enum atom_set_engine_mem_clock_flag,  */
1640   uint32_t reserved[10];
1641 };
1642
1643 struct set_memory_clock_ps_allocation_v2_1
1644 {
1645   struct set_memory_clock_parameters_v2_1 clockinfo;
1646   uint32_t reserved[10];
1647 };
1648
1649
1650 /*
1651   ***************************************************************************
1652               Structures used by getmemoryclock
1653   ***************************************************************************
1654 */
1655 struct get_memory_clock_parameter
1656 {
1657   uint32_t mclk_10khz;          // current engine speed in 10KHz unit
1658   uint32_t reserved;
1659 };
1660
1661
1662
1663 /*
1664   ***************************************************************************
1665               Structures used by setvoltage
1666   ***************************************************************************
1667 */
1668
1669 struct set_voltage_parameters_v1_4
1670 {
1671   uint8_t  voltagetype;                /* enum atom_voltage_type */
1672   uint8_t  command;                    /* Indicate action: Set voltage level, enum atom_set_voltage_command */
1673   uint16_t vlevel_mv;                  /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
1674 };
1675
1676 //set_voltage_parameters_v2_1.voltagemode
1677 enum atom_set_voltage_command{
1678   ATOM_SET_VOLTAGE  = 0,
1679   ATOM_INIT_VOLTAGE_REGULATOR = 3,
1680   ATOM_SET_VOLTAGE_PHASE = 4,
1681   ATOM_GET_LEAKAGE_ID    = 8,
1682 };
1683
1684 struct set_voltage_ps_allocation_v1_4
1685 {
1686   struct set_voltage_parameters_v1_4 setvoltageparam;
1687   uint32_t reserved[10];
1688 };
1689
1690
1691 /*
1692   ***************************************************************************
1693               Structures used by computegpuclockparam
1694   ***************************************************************************
1695 */
1696
1697 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
1698 enum atom_gpu_clock_type
1699 {
1700   COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
1701   COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
1702   COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
1703 };
1704
1705 struct compute_gpu_clock_input_parameter_v1_8
1706 {
1707   uint32_t  gpuclock_10khz:24;         //Input= target clock, output = actual clock
1708   uint32_t  gpu_clock_type:8;          //Input indicate clock type: enum atom_gpu_clock_type
1709   uint32_t  reserved[5];
1710 };
1711
1712
1713 struct compute_gpu_clock_output_parameter_v1_8
1714 {
1715   uint32_t  gpuclock_10khz:24;              //Input= target clock, output = actual clock
1716   uint32_t  dfs_did:8;                      //return parameter: DFS divider which is used to program to register directly
1717   uint32_t  pll_fb_mult;                    //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
1718   uint32_t  pll_ss_fbsmult;                 // Spread FB Mult: bit 8:0 int, bit 31:16 frac
1719   uint16_t  pll_ss_slew_frac;
1720   uint8_t   pll_ss_enable;
1721   uint8_t   reserved;
1722   uint32_t  reserved1[2];
1723 };
1724
1725
1726
1727 /*
1728   ***************************************************************************
1729               Structures used by ReadEfuseValue
1730   ***************************************************************************
1731 */
1732
1733 struct read_efuse_input_parameters_v3_1
1734 {
1735   uint16_t efuse_start_index;
1736   uint8_t  reserved;
1737   uint8_t  bitslen;
1738 };
1739
1740 // ReadEfuseValue input/output parameter
1741 union read_efuse_value_parameters_v3_1
1742 {
1743   struct read_efuse_input_parameters_v3_1 efuse_info;
1744   uint32_t efusevalue;
1745 };
1746
1747
1748 /*
1749   ***************************************************************************
1750               Structures used by getsmuclockinfo
1751   ***************************************************************************
1752 */
1753 struct atom_get_smu_clock_info_parameters_v3_1
1754 {
1755   uint8_t syspll_id;          // 0= syspll0, 1=syspll1, 2=syspll2
1756   uint8_t clk_id;             // atom_smu9_syspll0_clock_id  (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1757   uint8_t command;            // enum of atom_get_smu_clock_info_command
1758   uint8_t dfsdid;             // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1759 };
1760
1761 enum atom_get_smu_clock_info_command
1762 {
1763   GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ       = 0,
1764   GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ      = 1,
1765   GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ   = 2,
1766 };
1767
1768 enum atom_smu9_syspll0_clock_id
1769 {
1770   SMU9_SYSPLL0_SMNCLK_ID   = 0,       //  SMNCLK
1771   SMU9_SYSPLL0_SOCCLK_ID   = 1,       //        SOCCLK (FCLK)
1772   SMU9_SYSPLL0_MP0CLK_ID   = 2,       //        MP0CLK
1773   SMU9_SYSPLL0_MP1CLK_ID   = 3,       //        MP1CLK
1774   SMU9_SYSPLL0_LCLK_ID     = 4,       //        LCLK
1775   SMU9_SYSPLL0_DCLK_ID     = 5,       //        DCLK
1776   SMU9_SYSPLL0_VCLK_ID     = 6,       //        VCLK
1777   SMU9_SYSPLL0_ECLK_ID     = 7,       //        ECLK
1778   SMU9_SYSPLL0_DCEFCLK_ID  = 8,       //        DCEFCLK
1779   SMU9_SYSPLL0_DPREFCLK_ID = 10,      //        DPREFCLK
1780   SMU9_SYSPLL0_DISPCLK_ID  = 11,      //        DISPCLK
1781 };
1782
1783 struct  atom_get_smu_clock_info_output_parameters_v3_1
1784 {
1785   union {
1786     uint32_t smu_clock_freq_hz;
1787     uint32_t syspllvcofreq_10khz;
1788     uint32_t sysspllrefclk_10khz;
1789   }atom_smu_outputclkfreq;
1790 };
1791
1792
1793
1794 /*
1795   ***************************************************************************
1796               Structures used by dynamicmemorysettings
1797   ***************************************************************************
1798 */
1799
1800 enum atom_dynamic_memory_setting_command
1801 {
1802   COMPUTE_MEMORY_PLL_PARAM = 1,
1803   COMPUTE_ENGINE_PLL_PARAM = 2,
1804   ADJUST_MC_SETTING_PARAM = 3,
1805 };
1806
1807 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
1808 struct dynamic_mclk_settings_parameters_v2_1
1809 {
1810   uint32_t  mclk_10khz:24;         //Input= target mclk
1811   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
1812   uint32_t  reserved;
1813 };
1814
1815 /* when command = COMPUTE_ENGINE_PLL_PARAM */
1816 struct dynamic_sclk_settings_parameters_v2_1
1817 {
1818   uint32_t  sclk_10khz:24;         //Input= target mclk
1819   uint32_t  command:8;             //command enum of atom_dynamic_memory_setting_command
1820   uint32_t  mclk_10khz;
1821   uint32_t  reserved;
1822 };
1823
1824 union dynamic_memory_settings_parameters_v2_1
1825 {
1826   struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
1827   struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
1828 };
1829
1830
1831
1832 /*
1833   ***************************************************************************
1834               Structures used by memorytraining
1835   ***************************************************************************
1836 */
1837
1838 enum atom_umc6_0_ucode_function_call_enum_id
1839 {
1840   UMC60_UCODE_FUNC_ID_REINIT                 = 0,
1841   UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH      = 1,
1842   UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH       = 2,
1843 };
1844
1845
1846 struct memory_training_parameters_v2_1
1847 {
1848   uint8_t ucode_func_id;
1849   uint8_t ucode_reserved[3];
1850   uint32_t reserved[5];
1851 };
1852
1853
1854 /*
1855   ***************************************************************************
1856               Structures used by setpixelclock
1857   ***************************************************************************
1858 */
1859
1860 struct set_pixel_clock_parameter_v1_7
1861 {
1862     uint32_t pixclk_100hz;               // target the pixel clock to drive the CRTC timing in unit of 100Hz.
1863
1864     uint8_t  pll_id;                     // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
1865     uint8_t  encoderobjid;               // ASIC encoder id defined in objectId.h,
1866                                          // indicate which graphic encoder will be used.
1867     uint8_t  encoder_mode;               // Encoder mode:
1868     uint8_t  miscinfo;                   // enum atom_set_pixel_clock_v1_7_misc_info
1869     uint8_t  crtc_id;                    // enum of atom_crtc_def
1870     uint8_t  deep_color_ratio;           // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1871     uint8_t  reserved1[2];
1872     uint32_t reserved2;
1873 };
1874
1875 //ucMiscInfo
1876 enum atom_set_pixel_clock_v1_7_misc_info
1877 {
1878   PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL         = 0x01,
1879   PIXEL_CLOCK_V7_MISC_PROG_PHYPLL             = 0x02,
1880   PIXEL_CLOCK_V7_MISC_YUV420_MODE             = 0x04,
1881   PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN         = 0x08,
1882   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC             = 0x30,
1883   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN      = 0x00,
1884   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE        = 0x10,
1885   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK       = 0x20,
1886   PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD      = 0x30,
1887   PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE           = 0x40,
1888   PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS            = 0x80,
1889 };
1890
1891 /* deep_color_ratio */
1892 enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1893 {
1894   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS          = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
1895   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4          = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
1896   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2          = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
1897   PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1          = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
1898 };
1899
1900 /*
1901   ***************************************************************************
1902               Structures used by setdceclock
1903   ***************************************************************************
1904 */
1905
1906 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
1907 struct set_dce_clock_parameters_v2_1
1908 {
1909   uint32_t dceclk_10khz;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
1910   uint8_t  dceclktype;                                 // =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK
1911   uint8_t  dceclksrc;                                  // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
1912   uint8_t  dceclkflag;                                 // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
1913   uint8_t  crtc_id;                                    // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
1914 };
1915
1916 //ucDCEClkType
1917 enum atom_set_dce_clock_clock_type
1918 {
1919   DCE_CLOCK_TYPE_DISPCLK                      = 0,
1920   DCE_CLOCK_TYPE_DPREFCLK                     = 1,
1921   DCE_CLOCK_TYPE_PIXELCLK                     = 2,        // used by VBIOS internally, called by SetPixelClock
1922 };
1923
1924 //ucDCEClkFlag when ucDCEClkType == DPREFCLK
1925 enum atom_set_dce_clock_dprefclk_flag
1926 {
1927   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK          = 0x03,
1928   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA      = 0x00,
1929   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK         = 0x01,
1930   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE          = 0x02,
1931   DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN        = 0x03,
1932 };
1933
1934 //ucDCEClkFlag when ucDCEClkType == PIXCLK
1935 enum atom_set_dce_clock_pixclk_flag
1936 {
1937   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK    = 0x03,
1938   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS     = 0x00,      //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
1939   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4     = 0x01,      //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
1940   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2     = 0x02,      //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
1941   DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1     = 0x03,      //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
1942   DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE           = 0x04,
1943 };
1944
1945 struct set_dce_clock_ps_allocation_v2_1
1946 {
1947   struct set_dce_clock_parameters_v2_1 param;
1948   uint32_t ulReserved[2];
1949 };
1950
1951
1952 /****************************************************************************/
1953 // Structures used by BlankCRTC
1954 /****************************************************************************/
1955 struct blank_crtc_parameters
1956 {
1957   uint8_t  crtc_id;                   // enum atom_crtc_def
1958   uint8_t  blanking;                  // enum atom_blank_crtc_command
1959   uint16_t reserved;
1960   uint32_t reserved1;
1961 };
1962
1963 enum atom_blank_crtc_command
1964 {
1965   ATOM_BLANKING         = 1,
1966   ATOM_BLANKING_OFF     = 0,
1967 };
1968
1969 /****************************************************************************/
1970 // Structures used by enablecrtc
1971 /****************************************************************************/
1972 struct enable_crtc_parameters
1973 {
1974   uint8_t crtc_id;                    // enum atom_crtc_def
1975   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
1976   uint8_t padding[2];
1977 };
1978
1979
1980 /****************************************************************************/
1981 // Structure used by EnableDispPowerGating
1982 /****************************************************************************/
1983 struct enable_disp_power_gating_parameters_v2_1
1984 {
1985   uint8_t disp_pipe_id;                // ATOM_CRTC1, ATOM_CRTC2, ...
1986   uint8_t enable;                     // ATOM_ENABLE or ATOM_DISABLE
1987   uint8_t padding[2];
1988 };
1989
1990 struct enable_disp_power_gating_ps_allocation
1991 {
1992   struct enable_disp_power_gating_parameters_v2_1 param;
1993   uint32_t ulReserved[4];
1994 };
1995
1996 /****************************************************************************/
1997 // Structure used in setcrtc_usingdtdtiming
1998 /****************************************************************************/
1999 struct set_crtc_using_dtd_timing_parameters
2000 {
2001   uint16_t  h_size;
2002   uint16_t  h_blanking_time;
2003   uint16_t  v_size;
2004   uint16_t  v_blanking_time;
2005   uint16_t  h_syncoffset;
2006   uint16_t  h_syncwidth;
2007   uint16_t  v_syncoffset;
2008   uint16_t  v_syncwidth;
2009   uint16_t  modemiscinfo;
2010   uint8_t   h_border;
2011   uint8_t   v_border;
2012   uint8_t   crtc_id;                   // enum atom_crtc_def
2013   uint8_t   encoder_mode;                          // atom_encode_mode_def
2014   uint8_t   padding[2];
2015 };
2016
2017
2018 /****************************************************************************/
2019 // Structures used by processi2cchanneltransaction
2020 /****************************************************************************/
2021 struct process_i2c_channel_transaction_parameters
2022 {
2023   uint8_t i2cspeed_khz;
2024   union {
2025     uint8_t regindex;
2026     uint8_t status;                  /* enum atom_process_i2c_flag */
2027   } regind_status;
2028   uint16_t  i2c_data_out;
2029   uint8_t   flag;                    /* enum atom_process_i2c_status */
2030   uint8_t   trans_bytes;
2031   uint8_t   slave_addr;
2032   uint8_t   i2c_id;
2033 };
2034
2035 //ucFlag
2036 enum atom_process_i2c_flag
2037 {
2038   HW_I2C_WRITE          = 1,
2039   HW_I2C_READ           = 0,
2040   I2C_2BYTE_ADDR        = 0x02,
2041   HW_I2C_SMBUS_BYTE_WR  = 0x04,
2042 };
2043
2044 //status
2045 enum atom_process_i2c_status
2046 {
2047   HW_ASSISTED_I2C_STATUS_FAILURE     =2,
2048   HW_ASSISTED_I2C_STATUS_SUCCESS     =1,
2049 };
2050
2051
2052 /****************************************************************************/
2053 // Structures used by processauxchanneltransaction
2054 /****************************************************************************/
2055
2056 struct process_aux_channel_transaction_parameters_v1_2
2057 {
2058   uint16_t aux_request;
2059   uint16_t dataout;
2060   uint8_t  channelid;
2061   union {
2062     uint8_t   reply_status;
2063     uint8_t   aux_delay;
2064   } aux_status_delay;
2065   uint8_t   dataout_len;
2066   uint8_t   hpd_id;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2067 };
2068
2069
2070 /****************************************************************************/
2071 // Structures used by selectcrtc_source
2072 /****************************************************************************/
2073
2074 struct select_crtc_source_parameters_v2_3
2075 {
2076   uint8_t crtc_id;                        // enum atom_crtc_def
2077   uint8_t encoder_id;                     // enum atom_dig_def
2078   uint8_t encode_mode;                    // enum atom_encode_mode_def
2079   uint8_t dst_bpc;                        // enum atom_panel_bit_per_color
2080 };
2081
2082
2083 /****************************************************************************/
2084 // Structures used by digxencodercontrol
2085 /****************************************************************************/
2086
2087 // ucAction:
2088 enum atom_dig_encoder_control_action
2089 {
2090   ATOM_ENCODER_CMD_DISABLE_DIG                  = 0,
2091   ATOM_ENCODER_CMD_ENABLE_DIG                   = 1,
2092   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       = 0x08,
2093   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    = 0x09,
2094   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    = 0x0a,
2095   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    = 0x13,
2096   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    = 0x0b,
2097   ATOM_ENCODER_CMD_DP_VIDEO_OFF                 = 0x0c,
2098   ATOM_ENCODER_CMD_DP_VIDEO_ON                  = 0x0d,
2099   ATOM_ENCODER_CMD_SETUP_PANEL_MODE             = 0x10,
2100   ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4    = 0x14,
2101   ATOM_ENCODER_CMD_STREAM_SETUP                 = 0x0F,
2102   ATOM_ENCODER_CMD_LINK_SETUP                   = 0x11,
2103   ATOM_ENCODER_CMD_ENCODER_BLANK                = 0x12,
2104 };
2105
2106 //define ucPanelMode
2107 enum atom_dig_encoder_control_panelmode
2108 {
2109   DP_PANEL_MODE_DISABLE                        = 0x00,
2110   DP_PANEL_MODE_ENABLE_eDP_MODE                = 0x01,
2111   DP_PANEL_MODE_ENABLE_LVLINK_MODE             = 0x11,
2112 };
2113
2114 //ucDigId
2115 enum atom_dig_encoder_control_v5_digid
2116 {
2117   ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER           = 0x00,
2118   ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER           = 0x01,
2119   ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER           = 0x02,
2120   ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER           = 0x03,
2121   ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER           = 0x04,
2122   ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER           = 0x05,
2123   ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER           = 0x06,
2124   ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER           = 0x07,
2125 };
2126
2127 struct dig_encoder_stream_setup_parameters_v1_5
2128 {
2129   uint8_t digid;            // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2130   uint8_t action;           // =  ATOM_ENOCODER_CMD_STREAM_SETUP
2131   uint8_t digmode;          // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2132   uint8_t lanenum;          // Lane number
2133   uint32_t pclk_10khz;      // Pixel Clock in 10Khz
2134   uint8_t bitpercolor;
2135   uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G  = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2136   uint8_t reserved[2];
2137 };
2138
2139 struct dig_encoder_link_setup_parameters_v1_5
2140 {
2141   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2142   uint8_t action;          // =  ATOM_ENOCODER_CMD_LINK_SETUP
2143   uint8_t digmode;         // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2144   uint8_t lanenum;         // Lane number
2145   uint8_t symclk_10khz;    // Symbol Clock in 10Khz
2146   uint8_t hpd_sel;
2147   uint8_t digfe_sel;       // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2148   uint8_t reserved[2];
2149 };
2150
2151 struct dp_panel_mode_set_parameters_v1_5
2152 {
2153   uint8_t digid;              // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2154   uint8_t action;             // = ATOM_ENCODER_CMD_DPLINK_SETUP
2155   uint8_t panelmode;      // enum atom_dig_encoder_control_panelmode
2156   uint8_t reserved1;
2157   uint32_t reserved2[2];
2158 };
2159
2160 struct dig_encoder_generic_cmd_parameters_v1_5
2161 {
2162   uint8_t digid;           // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2163   uint8_t action;          // = rest of generic encoder command which does not carry any parameters
2164   uint8_t reserved1[2];
2165   uint32_t reserved2[2];
2166 };
2167
2168 union dig_encoder_control_parameters_v1_5
2169 {
2170   struct dig_encoder_generic_cmd_parameters_v1_5  cmd_param;
2171   struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2172   struct dig_encoder_link_setup_parameters_v1_5   link_param;
2173   struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2174 };
2175
2176 /*
2177   ***************************************************************************
2178               Structures used by dig1transmittercontrol
2179   ***************************************************************************
2180 */
2181 struct dig_transmitter_control_parameters_v1_6
2182 {
2183   uint8_t phyid;           // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2184   uint8_t action;          // define as ATOM_TRANSMITER_ACTION_xxx
2185   union {
2186     uint8_t digmode;        // enum atom_encode_mode_def
2187     uint8_t dplaneset;      // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2188   } mode_laneset;
2189   uint8_t  lanenum;        // Lane number 1, 2, 4, 8
2190   uint32_t symclk_10khz;   // Symbol Clock in 10Khz
2191   uint8_t  hpdsel;         // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2192   uint8_t  digfe_sel;      // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2193   uint8_t  connobj_id;     // Connector Object Id defined in ObjectId.h
2194   uint8_t  reserved;
2195   uint32_t reserved1;
2196 };
2197
2198 struct dig_transmitter_control_ps_allocation_v1_6
2199 {
2200   struct dig_transmitter_control_parameters_v1_6 param;
2201   uint32_t reserved[4];
2202 };
2203
2204 //ucAction
2205 enum atom_dig_transmitter_control_action
2206 {
2207   ATOM_TRANSMITTER_ACTION_DISABLE                 = 0,
2208   ATOM_TRANSMITTER_ACTION_ENABLE                  = 1,
2209   ATOM_TRANSMITTER_ACTION_LCD_BLOFF               = 2,
2210   ATOM_TRANSMITTER_ACTION_LCD_BLON                = 3,
2211   ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL   = 4,
2212   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START      = 5,
2213   ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP       = 6,
2214   ATOM_TRANSMITTER_ACTION_INIT                    = 7,
2215   ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          = 8,
2216   ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT           = 9,
2217   ATOM_TRANSMITTER_ACTION_SETUP                   = 10,
2218   ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH            = 11,
2219   ATOM_TRANSMITTER_ACTION_POWER_ON                = 12,
2220   ATOM_TRANSMITTER_ACTION_POWER_OFF               = 13,
2221 };
2222
2223 // digfe_sel
2224 enum atom_dig_transmitter_control_digfe_sel
2225 {
2226   ATOM_TRANMSITTER_V6__DIGA_SEL                   = 0x01,
2227   ATOM_TRANMSITTER_V6__DIGB_SEL                   = 0x02,
2228   ATOM_TRANMSITTER_V6__DIGC_SEL                   = 0x04,
2229   ATOM_TRANMSITTER_V6__DIGD_SEL                   = 0x08,
2230   ATOM_TRANMSITTER_V6__DIGE_SEL                   = 0x10,
2231   ATOM_TRANMSITTER_V6__DIGF_SEL                   = 0x20,
2232   ATOM_TRANMSITTER_V6__DIGG_SEL                   = 0x40,
2233 };
2234
2235
2236 //ucHPDSel
2237 enum atom_dig_transmitter_control_hpd_sel
2238 {
2239   ATOM_TRANSMITTER_V6_NO_HPD_SEL                  = 0x00,
2240   ATOM_TRANSMITTER_V6_HPD1_SEL                    = 0x01,
2241   ATOM_TRANSMITTER_V6_HPD2_SEL                    = 0x02,
2242   ATOM_TRANSMITTER_V6_HPD3_SEL                    = 0x03,
2243   ATOM_TRANSMITTER_V6_HPD4_SEL                    = 0x04,
2244   ATOM_TRANSMITTER_V6_HPD5_SEL                    = 0x05,
2245   ATOM_TRANSMITTER_V6_HPD6_SEL                    = 0x06,
2246 };
2247
2248 // ucDPLaneSet
2249 enum atom_dig_transmitter_control_dplaneset
2250 {
2251   DP_LANE_SET__0DB_0_4V                           = 0x00,
2252   DP_LANE_SET__0DB_0_6V                           = 0x01,
2253   DP_LANE_SET__0DB_0_8V                           = 0x02,
2254   DP_LANE_SET__0DB_1_2V                           = 0x03,
2255   DP_LANE_SET__3_5DB_0_4V                         = 0x08,
2256   DP_LANE_SET__3_5DB_0_6V                         = 0x09,
2257   DP_LANE_SET__3_5DB_0_8V                         = 0x0a,
2258   DP_LANE_SET__6DB_0_4V                           = 0x10,
2259   DP_LANE_SET__6DB_0_6V                           = 0x11,
2260   DP_LANE_SET__9_5DB_0_4V                         = 0x18,
2261 };
2262
2263
2264
2265 /****************************************************************************/
2266 // Structures used by ExternalEncoderControl V2.4
2267 /****************************************************************************/
2268
2269 struct external_encoder_control_parameters_v2_4
2270 {
2271   uint16_t pixelclock_10khz;  // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2272   uint8_t  config;            // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2273   uint8_t  action;            //
2274   uint8_t  encodermode;       // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2275   uint8_t  lanenum;           // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2276   uint8_t  bitpercolor;       // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2277   uint8_t  hpd_id;
2278 };
2279
2280
2281 // ucAction
2282 enum external_encoder_control_action_def
2283 {
2284   EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT           = 0x00,
2285   EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT            = 0x01,
2286   EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT             = 0x07,
2287   EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP            = 0x0f,
2288   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF     = 0x10,
2289   EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING         = 0x11,
2290   EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION        = 0x12,
2291   EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP                = 0x14,
2292 };
2293
2294 // ucConfig
2295 enum external_encoder_control_v2_4_config_def
2296 {
2297   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK          = 0x03,
2298   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ       = 0x00,
2299   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ       = 0x01,
2300   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ       = 0x02,
2301   EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ       = 0x03,
2302   EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS         = 0x70,
2303   EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                 = 0x00,
2304   EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                 = 0x10,
2305   EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                 = 0x20,
2306 };
2307
2308 struct external_encoder_control_ps_allocation_v2_4
2309 {
2310   struct external_encoder_control_parameters_v2_4 sExtEncoder;
2311   uint32_t reserved[2];
2312 };
2313
2314
2315 /*
2316   ***************************************************************************
2317                            AMD ACPI Table
2318
2319   ***************************************************************************
2320 */
2321
2322 struct amd_acpi_description_header{
2323   uint32_t signature;
2324   uint32_t tableLength;      //Length
2325   uint8_t  revision;
2326   uint8_t  checksum;
2327   uint8_t  oemId[6];
2328   uint8_t  oemTableId[8];    //UINT64  OemTableId;
2329   uint32_t oemRevision;
2330   uint32_t creatorId;
2331   uint32_t creatorRevision;
2332 };
2333
2334 struct uefi_acpi_vfct{
2335   struct   amd_acpi_description_header sheader;
2336   uint8_t  tableUUID[16];    //0x24
2337   uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2338   uint32_t lib1Imageoffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2339   uint32_t reserved[4];      //0x3C
2340 };
2341
2342 struct vfct_image_header{
2343   uint32_t  pcibus;          //0x4C
2344   uint32_t  pcidevice;       //0x50
2345   uint32_t  pcifunction;     //0x54
2346   uint16_t  vendorid;        //0x58
2347   uint16_t  deviceid;        //0x5A
2348   uint16_t  ssvid;           //0x5C
2349   uint16_t  ssid;            //0x5E
2350   uint32_t  revision;        //0x60
2351   uint32_t  imagelength;     //0x64
2352 };
2353
2354
2355 struct gop_vbios_content {
2356   struct vfct_image_header vbiosheader;
2357   uint8_t                  vbioscontent[1];
2358 };
2359
2360 struct gop_lib1_content {
2361   struct vfct_image_header lib1header;
2362   uint8_t                  lib1content[1];
2363 };
2364
2365
2366
2367 /*
2368   ***************************************************************************
2369                    Scratch Register definitions
2370   Each number below indicates which scratch regiser request, Active and
2371   Connect all share the same definitions as display_device_tag defines
2372   ***************************************************************************
2373 */
2374
2375 enum scratch_register_def{
2376   ATOM_DEVICE_CONNECT_INFO_DEF      = 0,
2377   ATOM_BL_BRI_LEVEL_INFO_DEF        = 2,
2378   ATOM_ACTIVE_INFO_DEF              = 3,
2379   ATOM_LCD_INFO_DEF                 = 4,
2380   ATOM_DEVICE_REQ_INFO_DEF          = 5,
2381   ATOM_ACC_CHANGE_INFO_DEF          = 6,
2382   ATOM_PRE_OS_MODE_INFO_DEF         = 7,
2383   ATOM_PRE_OS_ASSERTION_DEF      = 8,    //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2384   ATOM_INTERNAL_TIMER_INFO_DEF      = 10,
2385 };
2386
2387 enum scratch_device_connect_info_bit_def{
2388   ATOM_DISPLAY_LCD1_CONNECT           =0x0002,
2389   ATOM_DISPLAY_DFP1_CONNECT           =0x0008,
2390   ATOM_DISPLAY_DFP2_CONNECT           =0x0080,
2391   ATOM_DISPLAY_DFP3_CONNECT           =0x0200,
2392   ATOM_DISPLAY_DFP4_CONNECT           =0x0400,
2393   ATOM_DISPLAY_DFP5_CONNECT           =0x0800,
2394   ATOM_DISPLAY_DFP6_CONNECT           =0x0040,
2395   ATOM_DISPLAY_DFPx_CONNECT           =0x0ec8,
2396   ATOM_CONNECT_INFO_DEVICE_MASK       =0x0fff,
2397 };
2398
2399 enum scratch_bl_bri_level_info_bit_def{
2400   ATOM_CURRENT_BL_LEVEL_SHIFT         =0x8,
2401 #ifndef _H2INC
2402   ATOM_CURRENT_BL_LEVEL_MASK          =0x0000ff00,
2403   ATOM_DEVICE_DPMS_STATE              =0x00010000,
2404 #endif
2405 };
2406
2407 enum scratch_active_info_bits_def{
2408   ATOM_DISPLAY_LCD1_ACTIVE            =0x0002,
2409   ATOM_DISPLAY_DFP1_ACTIVE            =0x0008,
2410   ATOM_DISPLAY_DFP2_ACTIVE            =0x0080,
2411   ATOM_DISPLAY_DFP3_ACTIVE            =0x0200,
2412   ATOM_DISPLAY_DFP4_ACTIVE            =0x0400,
2413   ATOM_DISPLAY_DFP5_ACTIVE            =0x0800,
2414   ATOM_DISPLAY_DFP6_ACTIVE            =0x0040,
2415   ATOM_ACTIVE_INFO_DEVICE_MASK        =0x0fff,
2416 };
2417
2418 enum scratch_device_req_info_bits_def{
2419   ATOM_DISPLAY_LCD1_REQ               =0x0002,
2420   ATOM_DISPLAY_DFP1_REQ               =0x0008,
2421   ATOM_DISPLAY_DFP2_REQ               =0x0080,
2422   ATOM_DISPLAY_DFP3_REQ               =0x0200,
2423   ATOM_DISPLAY_DFP4_REQ               =0x0400,
2424   ATOM_DISPLAY_DFP5_REQ               =0x0800,
2425   ATOM_DISPLAY_DFP6_REQ               =0x0040,
2426   ATOM_REQ_INFO_DEVICE_MASK           =0x0fff,
2427 };
2428
2429 enum scratch_acc_change_info_bitshift_def{
2430   ATOM_ACC_CHANGE_ACC_MODE_SHIFT    =4,
2431   ATOM_ACC_CHANGE_LID_STATUS_SHIFT  =6,
2432 };
2433
2434 enum scratch_acc_change_info_bits_def{
2435   ATOM_ACC_CHANGE_ACC_MODE          =0x00000010,
2436   ATOM_ACC_CHANGE_LID_STATUS        =0x00000040,
2437 };
2438
2439 enum scratch_pre_os_mode_info_bits_def{
2440   ATOM_PRE_OS_MODE_MASK             =0x00000003,
2441   ATOM_PRE_OS_MODE_VGA              =0x00000000,
2442   ATOM_PRE_OS_MODE_VESA             =0x00000001,
2443   ATOM_PRE_OS_MODE_GOP              =0x00000002,
2444   ATOM_PRE_OS_MODE_PIXEL_DEPTH      =0x0000000C,
2445   ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2446   ATOM_PRE_OS_MODE_8BIT_PAL_EN      =0x00000100,
2447   ATOM_ASIC_INIT_COMPLETE           =0x00000200,
2448 #ifndef _H2INC
2449   ATOM_PRE_OS_MODE_NUMBER_MASK      =0xFFFF0000,
2450 #endif
2451 };
2452
2453
2454
2455 /*
2456   ***************************************************************************
2457                        ATOM firmware ID header file
2458               !! Please keep it at end of the atomfirmware.h !!
2459   ***************************************************************************
2460 */
2461 #include "atomfirmwareid.h"
2462 #pragma pack()
2463
2464 #endif
2465