1 /****************************************************************************\
3 * File Name atomfirmware.h
4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
6 * Description header file of general definitions for OS nd pre-OS video drivers
8 * Copyright 2014 Advanced Micro Devices, Inc.
10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11 * and associated documentation files (the "Software"), to deal in the Software without restriction,
12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
27 \****************************************************************************/
30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
35 #ifndef _ATOMFIRMWARE_H_
36 #define _ATOMFIRMWARE_H_
38 enum atom_bios_header_version_def
{
39 ATOM_MAJOR_VERSION
=0x0003,
40 ATOM_MINOR_VERSION
=0x0003,
45 typedef unsigned long uint32_t;
49 typedef unsigned short uint16_t;
53 typedef unsigned char uint8_t;
64 ATOM_CRTC_INVALID
=0xff,
72 ATOM_COMBOPHY_PLL0
=20,
73 ATOM_COMBOPHY_PLL1
=21,
74 ATOM_COMBOPHY_PLL2
=22,
75 ATOM_COMBOPHY_PLL3
=23,
76 ATOM_COMBOPHY_PLL4
=24,
77 ATOM_COMBOPHY_PLL5
=25,
78 ATOM_PPLL_INVALID
=0xff,
81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
83 ASIC_INT_DIG1_ENCODER_ID
=0x03,
84 ASIC_INT_DIG2_ENCODER_ID
=0x09,
85 ASIC_INT_DIG3_ENCODER_ID
=0x0a,
86 ASIC_INT_DIG4_ENCODER_ID
=0x0b,
87 ASIC_INT_DIG5_ENCODER_ID
=0x0c,
88 ASIC_INT_DIG6_ENCODER_ID
=0x0d,
89 ASIC_INT_DIG7_ENCODER_ID
=0x0e,
93 enum atom_encode_mode_def
95 ATOM_ENCODER_MODE_DP
=0,
96 ATOM_ENCODER_MODE_DP_SST
=0,
97 ATOM_ENCODER_MODE_LVDS
=1,
98 ATOM_ENCODER_MODE_DVI
=2,
99 ATOM_ENCODER_MODE_HDMI
=3,
100 ATOM_ENCODER_MODE_DP_AUDIO
=5,
101 ATOM_ENCODER_MODE_DP_MST
=5,
102 ATOM_ENCODER_MODE_CRT
=15,
103 ATOM_ENCODER_MODE_DVO
=16,
106 enum atom_encoder_refclk_src_def
{
107 ENCODER_REFCLK_SRC_P1PLL
=0,
108 ENCODER_REFCLK_SRC_P2PLL
=1,
109 ENCODER_REFCLK_SRC_P3PLL
=2,
110 ENCODER_REFCLK_SRC_EXTCLK
=3,
111 ENCODER_REFCLK_SRC_INVALID
=0xff,
114 enum atom_scaler_def
{
115 ATOM_SCALER_DISABLE
=0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER
=1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION
=2, /*scaler expansion by 2 tap alpha blending mode*/
120 enum atom_operation_def
{
127 enum atom_embedded_display_op_def
{
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL
= 4,
131 ATOM_LCD_SELFTEST_START
= 5,
132 ATOM_LCD_SELFTEST_STOP
= 6,
135 enum atom_spread_spectrum_mode
{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK
= 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE
= 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE
= 0x01,
139 ATOM_INT_OR_EXT_SS_MASK
= 0x02,
140 ATOM_INTERNAL_SS_MASK
= 0x00,
141 ATOM_EXTERNAL_SS_MASK
= 0x02,
144 /* define panel bit per color */
145 enum atom_panel_bit_per_color
{
146 PANEL_BPC_UNDEFINE
=0x00,
147 PANEL_6BIT_PER_COLOR
=0x01,
148 PANEL_8BIT_PER_COLOR
=0x02,
149 PANEL_10BIT_PER_COLOR
=0x03,
150 PANEL_12BIT_PER_COLOR
=0x04,
151 PANEL_16BIT_PER_COLOR
=0x05,
155 enum atom_voltage_type
157 VOLTAGE_TYPE_VDDC
= 1,
158 VOLTAGE_TYPE_MVDDC
= 2,
159 VOLTAGE_TYPE_MVDDQ
= 3,
160 VOLTAGE_TYPE_VDDCI
= 4,
161 VOLTAGE_TYPE_VDDGFX
= 5,
162 VOLTAGE_TYPE_PCC
= 6,
163 VOLTAGE_TYPE_MVPP
= 7,
164 VOLTAGE_TYPE_LEDDPM
= 8,
165 VOLTAGE_TYPE_PCC_MVDD
= 9,
166 VOLTAGE_TYPE_PCIE_VDDC
= 10,
167 VOLTAGE_TYPE_PCIE_VDDR
= 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1
= 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2
= 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3
= 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4
= 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5
= 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6
= 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7
= 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8
= 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9
= 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10
= 0x1A,
180 enum atom_dgpu_vram_type
{
181 ATOM_DGPU_VRAM_TYPE_GDDR5
= 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM
= 0x60,
185 enum atom_dp_vs_preemph_def
{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0
= 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0
= 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0
= 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0
= 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1
= 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1
= 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1
= 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2
= 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2
= 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3
= 0x18,
200 enum atom_string_def{
201 asic_bus_type_pcie_string = "PCI_EXPRESS",
202 atom_fire_gl_string = "FGL",
203 atom_bios_string = "ATOM"
207 #pragma pack(1) /* BIOS data must use byte aligment*/
209 enum atombios_image_offset
{
210 OFFSET_TO_ATOM_ROM_HEADER_POINTER
=0x00000048,
211 OFFSET_TO_ATOM_ROM_IMAGE_SIZE
=0x00000002,
212 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE
=0x94,
213 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE
=20, /*including the terminator 0x0!*/
214 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS
=0x2f,
215 OFFSET_TO_GET_ATOMBIOS_STRING_START
=0x6e,
218 /****************************************************************************
219 * Common header for all tables (Data table, Command function).
220 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
221 * And the pointer actually points to this header.
222 ****************************************************************************/
224 struct atom_common_table_header
226 uint16_t structuresize
;
227 uint8_t format_revision
; //mainly used for a hw function, when the parser is not backward compatible
228 uint8_t content_revision
; //change it when a data table has a structure change, or a hw function has a input/output parameter change
231 /****************************************************************************
232 * Structure stores the ROM header.
233 ****************************************************************************/
234 struct atom_rom_header_v2_2
236 struct atom_common_table_header table_header
;
237 uint8_t atom_bios_string
[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
238 uint16_t bios_segment_address
;
239 uint16_t protectedmodeoffset
;
240 uint16_t configfilenameoffset
;
241 uint16_t crc_block_offset
;
242 uint16_t vbios_bootupmessageoffset
;
243 uint16_t int10_offset
;
244 uint16_t pcibusdevinitcode
;
245 uint16_t iobaseaddress
;
246 uint16_t subsystem_vendor_id
;
247 uint16_t subsystem_id
;
248 uint16_t pci_info_offset
;
249 uint16_t masterhwfunction_offset
; //Offest for SW to get all command function offsets, Don't change the position
250 uint16_t masterdatatable_offset
; //Offest for SW to get all data table offsets, Don't change the position
252 uint32_t pspdirtableoffset
;
255 /*==============================hw function portion======================================================================*/
258 /****************************************************************************
259 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time
260 * The real functionality of each function is associated with the parameter structure version when defined
261 * For all internal cmd function definitions, please reference to atomstruct.h
262 ****************************************************************************/
263 struct atom_master_list_of_command_functions_v2_1
{
264 uint16_t asic_init
; //Function
265 uint16_t cmd_function1
; //used as an internal one
266 uint16_t cmd_function2
; //used as an internal one
267 uint16_t cmd_function3
; //used as an internal one
268 uint16_t digxencodercontrol
; //Function
269 uint16_t cmd_function5
; //used as an internal one
270 uint16_t cmd_function6
; //used as an internal one
271 uint16_t cmd_function7
; //used as an internal one
272 uint16_t cmd_function8
; //used as an internal one
273 uint16_t cmd_function9
; //used as an internal one
274 uint16_t setengineclock
; //Function
275 uint16_t setmemoryclock
; //Function
276 uint16_t setpixelclock
; //Function
277 uint16_t enabledisppowergating
; //Function
278 uint16_t cmd_function14
; //used as an internal one
279 uint16_t cmd_function15
; //used as an internal one
280 uint16_t cmd_function16
; //used as an internal one
281 uint16_t cmd_function17
; //used as an internal one
282 uint16_t cmd_function18
; //used as an internal one
283 uint16_t cmd_function19
; //used as an internal one
284 uint16_t cmd_function20
; //used as an internal one
285 uint16_t cmd_function21
; //used as an internal one
286 uint16_t cmd_function22
; //used as an internal one
287 uint16_t cmd_function23
; //used as an internal one
288 uint16_t cmd_function24
; //used as an internal one
289 uint16_t cmd_function25
; //used as an internal one
290 uint16_t cmd_function26
; //used as an internal one
291 uint16_t cmd_function27
; //used as an internal one
292 uint16_t cmd_function28
; //used as an internal one
293 uint16_t cmd_function29
; //used as an internal one
294 uint16_t cmd_function30
; //used as an internal one
295 uint16_t cmd_function31
; //used as an internal one
296 uint16_t cmd_function32
; //used as an internal one
297 uint16_t cmd_function33
; //used as an internal one
298 uint16_t blankcrtc
; //Function
299 uint16_t enablecrtc
; //Function
300 uint16_t cmd_function36
; //used as an internal one
301 uint16_t cmd_function37
; //used as an internal one
302 uint16_t cmd_function38
; //used as an internal one
303 uint16_t cmd_function39
; //used as an internal one
304 uint16_t cmd_function40
; //used as an internal one
305 uint16_t getsmuclockinfo
; //Function
306 uint16_t selectcrtc_source
; //Function
307 uint16_t cmd_function43
; //used as an internal one
308 uint16_t cmd_function44
; //used as an internal one
309 uint16_t cmd_function45
; //used as an internal one
310 uint16_t setdceclock
; //Function
311 uint16_t getmemoryclock
; //Function
312 uint16_t getengineclock
; //Function
313 uint16_t setcrtc_usingdtdtiming
; //Function
314 uint16_t externalencodercontrol
; //Function
315 uint16_t cmd_function51
; //used as an internal one
316 uint16_t cmd_function52
; //used as an internal one
317 uint16_t cmd_function53
; //used as an internal one
318 uint16_t processi2cchanneltransaction
;//Function
319 uint16_t cmd_function55
; //used as an internal one
320 uint16_t cmd_function56
; //used as an internal one
321 uint16_t cmd_function57
; //used as an internal one
322 uint16_t cmd_function58
; //used as an internal one
323 uint16_t cmd_function59
; //used as an internal one
324 uint16_t computegpuclockparam
; //Function
325 uint16_t cmd_function61
; //used as an internal one
326 uint16_t cmd_function62
; //used as an internal one
327 uint16_t dynamicmemorysettings
; //Function function
328 uint16_t memorytraining
; //Function function
329 uint16_t cmd_function65
; //used as an internal one
330 uint16_t cmd_function66
; //used as an internal one
331 uint16_t setvoltage
; //Function
332 uint16_t cmd_function68
; //used as an internal one
333 uint16_t readefusevalue
; //Function
334 uint16_t cmd_function70
; //used as an internal one
335 uint16_t cmd_function71
; //used as an internal one
336 uint16_t cmd_function72
; //used as an internal one
337 uint16_t cmd_function73
; //used as an internal one
338 uint16_t cmd_function74
; //used as an internal one
339 uint16_t cmd_function75
; //used as an internal one
340 uint16_t dig1transmittercontrol
; //Function
341 uint16_t cmd_function77
; //used as an internal one
342 uint16_t processauxchanneltransaction
;//Function
343 uint16_t cmd_function79
; //used as an internal one
344 uint16_t getvoltageinfo
; //Function
347 struct atom_master_command_function_v2_1
349 struct atom_common_table_header table_header
;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions
;
353 /****************************************************************************
354 * Structures used in every command function
355 ****************************************************************************/
356 struct atom_function_attribute
358 uint16_t ws_in_bytes
:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 uint16_t ps_in_bytes
:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 uint16_t updated_by_util
:1; //[15]=flag to indicate the function is updated by util
364 /****************************************************************************
365 * Common header for all hw functions.
366 * Every function pointed by _master_list_of_hw_function has this common header.
367 * And the pointer actually points to this header.
368 ****************************************************************************/
369 struct atom_rom_hw_function_header
371 struct atom_common_table_header func_header
;
372 struct atom_function_attribute func_attrib
;
376 /*==============================sw data table portion======================================================================*/
377 /****************************************************************************
378 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
379 * The real name of each table is given when its data structure version is defined
380 ****************************************************************************/
381 struct atom_master_list_of_data_tables_v2_1
{
382 uint16_t utilitypipeline
; /* Offest for the utility to get parser info,Don't change this position!*/
383 uint16_t multimedia_info
;
384 uint16_t sw_datatable2
;
385 uint16_t sw_datatable3
;
386 uint16_t firmwareinfo
; /* Shared by various SW components */
387 uint16_t sw_datatable5
;
388 uint16_t lcd_info
; /* Shared by various SW components */
389 uint16_t sw_datatable7
;
391 uint16_t sw_datatable9
;
392 uint16_t sw_datatable10
;
393 uint16_t vram_usagebyfirmware
; /* Shared by various SW components */
394 uint16_t gpio_pin_lut
; /* Shared by various SW components */
395 uint16_t sw_datatable13
;
397 uint16_t powerplayinfo
; /* Shared by various SW components */
398 uint16_t sw_datatable16
;
399 uint16_t sw_datatable17
;
400 uint16_t sw_datatable18
;
401 uint16_t sw_datatable19
;
402 uint16_t sw_datatable20
;
403 uint16_t sw_datatable21
;
404 uint16_t displayobjectinfo
; /* Shared by various SW components */
405 uint16_t indirectioaccess
; /* used as an internal one */
406 uint16_t umc_info
; /* Shared by various SW components */
407 uint16_t sw_datatable25
;
408 uint16_t sw_datatable26
;
409 uint16_t dce_info
; /* Shared by various SW components */
410 uint16_t vram_info
; /* Shared by various SW components */
411 uint16_t sw_datatable29
;
412 uint16_t integratedsysteminfo
; /* Shared by various SW components */
413 uint16_t asic_profiling_info
; /* Shared by various SW components */
414 uint16_t voltageobject_info
; /* shared by various SW components */
415 uint16_t sw_datatable33
;
416 uint16_t sw_datatable34
;
420 struct atom_master_data_table_v2_1
422 struct atom_common_table_header table_header
;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables
;
427 struct atom_dtd_format
431 uint16_t h_blanking_time
;
433 uint16_t v_blanking_time
;
434 uint16_t h_sync_offset
;
435 uint16_t h_sync_width
;
436 uint16_t v_sync_offset
;
437 uint16_t v_syncwidth
;
443 uint8_t atom_mode_id
;
447 /* atom_dtd_format.modemiscinfo defintion */
448 enum atom_dtd_format_modemiscinfo
{
449 ATOM_HSYNC_POLARITY
= 0x0002,
450 ATOM_VSYNC_POLARITY
= 0x0004,
451 ATOM_H_REPLICATIONBY2
= 0x0010,
452 ATOM_V_REPLICATIONBY2
= 0x0020,
453 ATOM_INTERLACE
= 0x0080,
454 ATOM_COMPOSITESYNC
= 0x0040,
459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
460 * the location of it can't change
465 ***************************************************************************
466 Data Table firmwareinfo structure
467 ***************************************************************************
470 struct atom_firmware_info_v3_1
472 struct atom_common_table_header table_header
;
473 uint32_t firmware_revision
;
474 uint32_t bootup_sclk_in10khz
;
475 uint32_t bootup_mclk_in10khz
;
476 uint32_t firmware_capability
; // enum atombios_firmware_capability
477 uint32_t main_call_parser_entry
; /* direct address of main parser call in VBIOS binary. */
478 uint32_t bios_scratch_reg_startaddr
; // 1st bios scratch register dword address
479 uint16_t bootup_vddc_mv
;
480 uint16_t bootup_vddci_mv
;
481 uint16_t bootup_mvddc_mv
;
482 uint16_t bootup_vddgfx_mv
;
483 uint8_t mem_module_id
;
484 uint8_t coolingsolution_id
; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1
[2];
486 uint32_t mc_baseaddr_high
;
487 uint32_t mc_baseaddr_low
;
488 uint32_t reserved2
[6];
491 /* Total 32bit cap indication */
492 enum atombios_firmware_capability
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED
= 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION
= 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT
= 0x00000040,
499 enum atom_cooling_solution_id
{
501 LIQUID_COOLING
= 0x01
506 ***************************************************************************
507 Data Table lcd_info structure
508 ***************************************************************************
513 struct atom_common_table_header table_header
;
514 struct atom_dtd_format lcd_timing
;
515 uint16_t backlight_pwm
;
516 uint16_t special_handle_cap
;
518 uint16_t lvds_max_slink_pclk
;
519 uint16_t lvds_ss_percentage
;
520 uint16_t lvds_ss_rate_10hz
;
521 uint8_t pwr_on_digon_to_de
; /*all pwr sequence numbers below are in uint of 4ms*/
522 uint8_t pwr_on_de_to_vary_bl
;
523 uint8_t pwr_down_vary_bloff_to_de
;
524 uint8_t pwr_down_de_to_digoff
;
525 uint8_t pwr_off_delay
;
526 uint8_t pwr_on_vary_bl_to_blon
;
527 uint8_t pwr_down_bloff_to_vary_bloff
;
529 uint8_t dpcd_edp_config_cap
;
530 uint8_t dpcd_max_link_rate
;
531 uint8_t dpcd_max_lane_count
;
532 uint8_t dpcd_max_downspread
;
533 uint8_t min_allowed_bl_level
;
534 uint8_t max_allowed_bl_level
;
535 uint8_t bootup_bl_level
;
537 uint32_t reserved1
[8];
540 /* lcd_info_v2_1.panel_misc defintion */
541 enum atom_lcd_info_panel_misc
{
542 ATOM_PANEL_MISC_FPDI
=0x0002,
546 enum atom_lcd_info_dptolvds_rx_id
548 eDP_TO_LVDS_RX_DISABLE
= 0x00, // no eDP->LVDS translator chip
549 eDP_TO_LVDS_COMMON_ID
= 0x01, // common eDP->LVDS translator chip without AMD SW init
550 eDP_TO_LVDS_REALTEK_ID
= 0x02, // Realtek tansaltor which require AMD SW init
555 ***************************************************************************
556 Data Table gpio_pin_lut structure
557 ***************************************************************************
560 struct atom_gpio_pin_assignment
562 uint32_t data_a_reg_index
;
563 uint8_t gpio_bitshift
;
564 uint8_t gpio_mask_bitshift
;
569 /* atom_gpio_pin_assignment.gpio_id definition */
570 enum atom_gpio_pin_assignment_gpio_id
{
571 I2C_HW_LANE_MUX
=0x0f, /* only valid when bit7=1 */
572 I2C_HW_ENGINE_ID_MASK
=0x70, /* only valid when bit7=1 */
573 I2C_HW_CAP
=0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
575 /* gpio_id pre-define id for multiple usage */
576 /* GPIO use to control PCIE_VDDC in certain SLT board */
577 PCIE_VDDC_CONTROL_GPIO_PINID
= 56,
578 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
579 PP_AC_DC_SWITCH_GPIO_PINID
= 60,
580 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
581 VDDC_VRHOT_GPIO_PINID
= 61,
582 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
583 VDDC_PCC_GPIO_PINID
= 62,
584 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
585 EFUSE_CUT_ENABLE_GPIO_PINID
= 63,
586 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
587 DRAM_SELF_REFRESH_GPIO_PINID
= 64,
588 /* Thermal interrupt output->system thermal chip GPIO pin */
589 THERMAL_INT_OUTPUT_GPIO_PINID
=65,
593 struct atom_gpio_pin_lut_v2_1
595 struct atom_common_table_header table_header
;
596 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
597 struct atom_gpio_pin_assignment gpio_pin
[8];
602 ***************************************************************************
603 Data Table vram_usagebyfirmware structure
604 ***************************************************************************
607 struct vram_usagebyfirmware_v2_1
609 struct atom_common_table_header table_header
;
610 uint32_t start_address_in_kb
;
611 uint16_t used_by_firmware_in_kb
;
612 uint16_t used_by_driver_in_kb
;
617 ***************************************************************************
618 Data Table displayobjectinfo structure
619 ***************************************************************************
622 enum atom_object_record_type_id
624 ATOM_I2C_RECORD_TYPE
=1,
625 ATOM_HPD_INT_RECORD_TYPE
=2,
626 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
=9,
627 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
=16,
628 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
=17,
629 ATOM_ENCODER_CAP_RECORD_TYPE
=20,
630 ATOM_BRACKET_LAYOUT_RECORD_TYPE
=21,
631 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
=22,
632 ATOM_RECORD_END_TYPE
=0xFF,
635 struct atom_common_record_header
637 uint8_t record_type
; //An emun to indicate the record type
638 uint8_t record_size
; //The size of the whole record in byte
641 struct atom_i2c_record
643 struct atom_common_record_header record_header
; //record_type = ATOM_I2C_RECORD_TYPE
645 uint8_t i2c_slave_addr
; //The slave address, it's 0 when the record is attached to connector for DDC
648 struct atom_hpd_int_record
650 struct atom_common_record_header record_header
; //record_type = ATOM_HPD_INT_RECORD_TYPE
651 uint8_t pin_id
; //Corresponding block in GPIO_PIN_INFO table gives the pin info
652 uint8_t plugin_pin_state
;
655 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
656 enum atom_encoder_caps_def
658 ATOM_ENCODER_CAP_RECORD_HBR2
=0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
659 ATOM_ENCODER_CAP_RECORD_MST_EN
=0x01, // from SI, this bit means DP MST is enable or not.
660 ATOM_ENCODER_CAP_RECORD_HBR2_EN
=0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
661 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN
=0x04, // HDMI2.0 6Gbps enable or not.
662 ATOM_ENCODER_CAP_RECORD_HBR3_EN
=0x08, // DP1.3 HBR3 is supported by board.
665 struct atom_encoder_caps_record
667 struct atom_common_record_header record_header
; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
668 uint32_t encodercaps
;
671 enum atom_connector_caps_def
673 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY
= 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
674 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL
= 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
677 struct atom_disp_connector_caps_record
679 struct atom_common_record_header record_header
;
680 uint32_t connectcaps
;
683 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
684 struct atom_gpio_pin_control_pair
686 uint8_t gpio_id
; // GPIO_ID, find the corresponding ID in GPIO_LUT table
687 uint8_t gpio_pinstate
; // Pin state showing how to set-up the pin
690 struct atom_object_gpio_cntl_record
692 struct atom_common_record_header record_header
;
693 uint8_t flag
; // Future expnadibility
694 uint8_t number_of_pins
; // Number of GPIO pins used to control the object
695 struct atom_gpio_pin_control_pair gpio
[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
698 //Definitions for GPIO pin state
699 enum atom_gpio_pin_control_pinstate_def
701 GPIO_PIN_TYPE_INPUT
= 0x00,
702 GPIO_PIN_TYPE_OUTPUT
= 0x10,
703 GPIO_PIN_TYPE_HW_CONTROL
= 0x20,
705 //For GPIO_PIN_TYPE_OUTPUT the following is defined
706 GPIO_PIN_OUTPUT_STATE_MASK
= 0x01,
707 GPIO_PIN_OUTPUT_STATE_SHIFT
= 0,
708 GPIO_PIN_STATE_ACTIVE_LOW
= 0x0,
709 GPIO_PIN_STATE_ACTIVE_HIGH
= 0x1,
712 // Indexes to GPIO array in GLSync record
713 // GLSync record is for Frame Lock/Gen Lock feature.
714 enum atom_glsync_record_gpio_index_def
716 ATOM_GPIO_INDEX_GLSYNC_REFCLK
= 0,
717 ATOM_GPIO_INDEX_GLSYNC_HSYNC
= 1,
718 ATOM_GPIO_INDEX_GLSYNC_VSYNC
= 2,
719 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ
= 3,
720 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT
= 4,
721 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT
= 5,
722 ATOM_GPIO_INDEX_GLSYNC_V_RESET
= 6,
723 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL
= 7,
724 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL
= 8,
725 ATOM_GPIO_INDEX_GLSYNC_MAX
= 9,
729 struct atom_connector_hpdpin_lut_record
//record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
731 struct atom_common_record_header record_header
;
732 uint8_t hpd_pin_map
[8];
735 struct atom_connector_auxddc_lut_record
//record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
737 struct atom_common_record_header record_header
;
738 uint8_t aux_ddc_map
[8];
741 struct atom_connector_forced_tmds_cap_record
743 struct atom_common_record_header record_header
;
744 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
745 uint8_t maxtmdsclkrate_in2_5mhz
;
749 struct atom_connector_layout_info
751 uint16_t connectorobjid
;
752 uint8_t connector_type
;
756 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
757 enum atom_connector_layout_info_connector_type_def
759 CONNECTOR_TYPE_DVI_D
= 1,
761 CONNECTOR_TYPE_HDMI
= 4,
762 CONNECTOR_TYPE_DISPLAY_PORT
= 5,
763 CONNECTOR_TYPE_MINI_DISPLAY_PORT
= 6,
766 struct atom_bracket_layout_record
768 struct atom_common_record_header record_header
;
770 uint8_t bracketwidth
;
773 struct atom_connector_layout_info conn_info
[1];
776 enum atom_display_device_tag_def
{
777 ATOM_DISPLAY_LCD1_SUPPORT
= 0x0002, //an embedded display is either an LVDS or eDP signal type of display
778 ATOM_DISPLAY_DFP1_SUPPORT
= 0x0008,
779 ATOM_DISPLAY_DFP2_SUPPORT
= 0x0080,
780 ATOM_DISPLAY_DFP3_SUPPORT
= 0x0200,
781 ATOM_DISPLAY_DFP4_SUPPORT
= 0x0400,
782 ATOM_DISPLAY_DFP5_SUPPORT
= 0x0800,
783 ATOM_DISPLAY_DFP6_SUPPORT
= 0x0040,
784 ATOM_DISPLAY_DFPx_SUPPORT
= 0x0ec8,
787 struct atom_display_object_path_v2
789 uint16_t display_objid
; //Connector Object ID or Misc Object ID
790 uint16_t disp_recordoffset
;
791 uint16_t encoderobjid
; //first encoder closer to the connector, could be either an external or intenal encoder
792 uint16_t extencoderobjid
; //2nd encoder after the first encoder, from the connector point of view;
793 uint16_t encoder_recordoffset
;
794 uint16_t extencoder_recordoffset
;
795 uint16_t device_tag
; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
800 struct display_object_info_table_v1_4
802 struct atom_common_table_header table_header
;
803 uint16_t supporteddevices
;
804 uint8_t number_of_path
;
806 struct atom_display_object_path_v2 display_path
[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
811 ***************************************************************************
812 Data Table dce_info structure
813 ***************************************************************************
815 struct atom_display_controller_info_v4_1
817 struct atom_common_table_header table_header
;
818 uint32_t display_caps
;
819 uint32_t bootup_dispclk_10khz
;
820 uint16_t dce_refclk_10khz
;
821 uint16_t i2c_engine_refclk_10khz
;
822 uint16_t dvi_ss_percentage
; // in unit of 0.001%
823 uint16_t dvi_ss_rate_10hz
;
824 uint16_t hdmi_ss_percentage
; // in unit of 0.001%
825 uint16_t hdmi_ss_rate_10hz
;
826 uint16_t dp_ss_percentage
; // in unit of 0.001%
827 uint16_t dp_ss_rate_10hz
;
828 uint8_t dvi_ss_mode
; // enum of atom_spread_spectrum_mode
829 uint8_t hdmi_ss_mode
; // enum of atom_spread_spectrum_mode
830 uint8_t dp_ss_mode
; // enum of atom_spread_spectrum_mode
832 uint8_t hardcode_mode_num
; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
833 uint8_t reserved1
[3];
834 uint16_t dpphy_refclk_10khz
;
836 uint8_t dceip_min_ver
;
837 uint8_t dceip_max_ver
;
838 uint8_t max_disp_pipe_num
;
839 uint8_t max_vbios_active_disp_pipe_num
;
840 uint8_t max_ppll_num
;
841 uint8_t max_disp_phy_num
;
842 uint8_t max_aux_pairs
;
843 uint8_t remotedisplayconfig
;
844 uint8_t reserved3
[8];
848 struct atom_display_controller_info_v4_2
850 struct atom_common_table_header table_header
;
851 uint32_t display_caps
;
852 uint32_t bootup_dispclk_10khz
;
853 uint16_t dce_refclk_10khz
;
854 uint16_t i2c_engine_refclk_10khz
;
855 uint16_t dvi_ss_percentage
; // in unit of 0.001%
856 uint16_t dvi_ss_rate_10hz
;
857 uint16_t hdmi_ss_percentage
; // in unit of 0.001%
858 uint16_t hdmi_ss_rate_10hz
;
859 uint16_t dp_ss_percentage
; // in unit of 0.001%
860 uint16_t dp_ss_rate_10hz
;
861 uint8_t dvi_ss_mode
; // enum of atom_spread_spectrum_mode
862 uint8_t hdmi_ss_mode
; // enum of atom_spread_spectrum_mode
863 uint8_t dp_ss_mode
; // enum of atom_spread_spectrum_mode
865 uint8_t dfp_hardcode_mode_num
; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
866 uint8_t dfp_hardcode_refreshrate
;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
867 uint8_t vga_hardcode_mode_num
; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
868 uint8_t vga_hardcode_refreshrate
;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
869 uint16_t dpphy_refclk_10khz
;
871 uint8_t dcnip_min_ver
;
872 uint8_t dcnip_max_ver
;
873 uint8_t max_disp_pipe_num
;
874 uint8_t max_vbios_active_disp_pipe_num
;
875 uint8_t max_ppll_num
;
876 uint8_t max_disp_phy_num
;
877 uint8_t max_aux_pairs
;
878 uint8_t remotedisplayconfig
;
879 uint8_t reserved3
[8];
883 enum dce_info_caps_def
886 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED
=0x02,
888 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2
=0x04,
890 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING
=0x08,
895 ***************************************************************************
896 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
897 ***************************************************************************
899 struct atom_ext_display_path
901 uint16_t device_tag
; //A bit vector to show what devices are supported
902 uint16_t device_acpi_enum
; //16bit device ACPI id.
903 uint16_t connectorobjid
; //A physical connector for displays to plug in, using object connector definitions
904 uint8_t auxddclut_index
; //An index into external AUX/DDC channel LUT
905 uint8_t hpdlut_index
; //An index into external HPD pin LUT
906 uint16_t ext_encoder_objid
; //external encoder object id
907 uint8_t channelmapping
; // if ucChannelMapping=0, using default one to one mapping
908 uint8_t chpninvert
; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
914 enum ext_display_path_cap_def
916 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE
=0x0001,
917 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN
=0x0002,
918 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK
=0x007C,
921 struct atom_external_display_connection_info
923 struct atom_common_table_header table_header
;
924 uint8_t guid
[16]; // a GUID is a 16 byte long string
925 struct atom_ext_display_path path
[7]; // total of fixed 7 entries.
926 uint8_t checksum
; // a simple Checksum of the sum of whole structure equal to 0x0.
927 uint8_t stereopinid
; // use for eDP panel
928 uint8_t remotedisplayconfig
;
929 uint8_t edptolvdsrxid
;
930 uint8_t fixdpvoltageswing
; // usCaps[1]=1, this indicate DP_LANE_SET value
931 uint8_t reserved
[3]; // for potential expansion
935 ***************************************************************************
936 Data Table integratedsysteminfo structure
937 ***************************************************************************
940 struct atom_camera_dphy_timing_param
942 uint8_t profile_id
; // SENSOR_PROFILES
946 struct atom_camera_dphy_elec_param
951 struct atom_camera_module_info
953 uint8_t module_id
; // 0: Rear, 1: Front right of user, 2: Front left of user
954 uint8_t module_name
[8];
955 struct atom_camera_dphy_timing_param timingparam
[6]; // Exact number is under estimation and confirmation from sensor vendor
958 struct atom_camera_flashlight_info
960 uint8_t flashlight_id
; // 0: Rear, 1: Front
964 struct atom_camera_data
966 uint32_t versionCode
;
967 struct atom_camera_module_info cameraInfo
[3]; // Assuming 3 camera sensors max
968 struct atom_camera_flashlight_info flashInfo
; // Assuming 1 flashlight max
969 struct atom_camera_dphy_elec_param dphy_param
;
970 uint32_t crc_val
; // CRC
974 struct atom_14nm_dpphy_dvihdmi_tuningset
976 uint32_t max_symclk_in10khz
;
977 uint8_t encoder_mode
; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
978 uint8_t phy_sel
; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
979 uint16_t margindeemph
; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
980 uint8_t deemph_6db_4
; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
981 uint8_t boostadj
; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
982 uint8_t tx_driver_fifty_ohms
; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
983 uint8_t deemph_sel
; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
986 struct atom_14nm_dpphy_dp_setting
{
987 uint8_t dp_vs_pemph_level
; //enum of atom_dp_vs_preemph_def
988 uint16_t margindeemph
; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
989 uint8_t deemph_6db_4
; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
990 uint8_t boostadj
; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
993 struct atom_14nm_dpphy_dp_tuningset
{
994 uint8_t phy_sel
; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
996 uint16_t table_size
; // size of atom_14nm_dpphy_dp_tuningset
998 struct atom_14nm_dpphy_dp_setting dptuning
[10];
1001 struct atom_14nm_dig_transmitter_info_header_v4_0
{
1002 struct atom_common_table_header table_header
;
1003 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset
; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1004 uint16_t uniphy_vs_emph_lookup_table_offset
; // offset of UniphyVSEmphLookUpTbl
1005 uint16_t uniphy_xbar_settings_table_offset
; // offset of UniphyXbarSettingsTbl
1008 struct atom_14nm_combphy_tmds_vs_set
1013 uint16_t common_mar_deemph_nom__margin_deemph_val
;
1014 uint8_t common_seldeemph60__deemph_6db_4_val
;
1015 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val
;
1016 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val
;
1017 uint8_t margin_deemph_lane0__deemph_sel_val
;
1020 struct atom_i2c_reg_info
{
1021 uint8_t ucI2cRegIndex
;
1022 uint8_t ucI2cRegVal
;
1025 struct atom_hdmi_retimer_redriver_set
{
1026 uint8_t HdmiSlvAddr
;
1028 uint8_t Hdmi6GRegNum
;
1029 struct atom_i2c_reg_info HdmiRegSetting
[9]; //For non 6G Hz use
1030 struct atom_i2c_reg_info Hdmi6GhzRegSetting
[3]; //For 6G Hz use.
1033 struct atom_integrated_system_info_v1_11
1035 struct atom_common_table_header table_header
;
1036 uint32_t vbios_misc
; //enum of atom_system_vbiosmisc_def
1037 uint32_t gpucapinfo
; //enum of atom_system_gpucapinf_def
1038 uint32_t system_config
;
1039 uint32_t cpucapinfo
;
1040 uint16_t gpuclk_ss_percentage
; //unit of 0.001%, 1000 mean 1%
1041 uint16_t gpuclk_ss_type
;
1042 uint16_t lvds_ss_percentage
; //unit of 0.001%, 1000 mean 1%
1043 uint16_t lvds_ss_rate_10hz
;
1044 uint16_t hdmi_ss_percentage
; //unit of 0.001%, 1000 mean 1%
1045 uint16_t hdmi_ss_rate_10hz
;
1046 uint16_t dvi_ss_percentage
; //unit of 0.001%, 1000 mean 1%
1047 uint16_t dvi_ss_rate_10hz
;
1048 uint16_t dpphy_override
; // bit vector, enum of atom_sysinfo_dpphy_override_def
1049 uint16_t lvds_misc
; // enum of atom_sys_info_lvds_misc_def
1050 uint16_t backlight_pwm_hz
; // pwm frequency in hz
1051 uint8_t memorytype
; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1052 uint8_t umachannelnumber
; // number of memory channels
1053 uint8_t pwr_on_digon_to_de
; /* all pwr sequence numbers below are in uint of 4ms */
1054 uint8_t pwr_on_de_to_vary_bl
;
1055 uint8_t pwr_down_vary_bloff_to_de
;
1056 uint8_t pwr_down_de_to_digoff
;
1057 uint8_t pwr_off_delay
;
1058 uint8_t pwr_on_vary_bl_to_blon
;
1059 uint8_t pwr_down_bloff_to_vary_bloff
;
1060 uint8_t min_allowed_bl_level
;
1061 uint8_t htc_hyst_limit
;
1062 uint8_t htc_tmp_limit
;
1065 struct atom_external_display_connection_info extdispconninfo
;
1066 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset
;
1067 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset
;
1068 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset
;
1069 struct atom_14nm_dpphy_dp_tuningset dp_tuningset
; // rbr 1.62G dp tuning set
1070 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset
; // HBR3 dp tuning set
1071 struct atom_camera_data camera_info
;
1072 struct atom_hdmi_retimer_redriver_set dp0_retimer_set
; //for DP0
1073 struct atom_hdmi_retimer_redriver_set dp1_retimer_set
; //for DP1
1074 struct atom_hdmi_retimer_redriver_set dp2_retimer_set
; //for DP2
1075 struct atom_hdmi_retimer_redriver_set dp3_retimer_set
; //for DP3
1076 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset
; //hbr 2.7G dp tuning set
1077 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset
; //hbr2 5.4G dp turnig set
1078 struct atom_14nm_dpphy_dp_tuningset edp_tuningset
; //edp tuning set
1079 uint32_t reserved
[66];
1084 enum atom_system_vbiosmisc_def
{
1085 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT
= 0x01,
1090 enum atom_system_gpucapinf_def
{
1091 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS
= 0x10,
1095 enum atom_sysinfo_dpphy_override_def
{
1096 ATOM_ENABLE_DVI_TUNINGSET
= 0x01,
1097 ATOM_ENABLE_HDMI_TUNINGSET
= 0x02,
1098 ATOM_ENABLE_HDMI6G_TUNINGSET
= 0x04,
1099 ATOM_ENABLE_DP_TUNINGSET
= 0x08,
1100 ATOM_ENABLE_DP_HBR3_TUNINGSET
= 0x10,
1104 enum atom_sys_info_lvds_misc_def
1106 SYS_INFO_LVDS_MISC_888_FPDI_MODE
=0x01,
1107 SYS_INFO_LVDS_MISC_888_BPC_MODE
=0x04,
1108 SYS_INFO_LVDS_MISC_OVERRIDE_EN
=0x08,
1112 //memorytype DMI Type 17 offset 12h - Memory Type
1113 enum atom_dmi_t17_mem_type_def
{
1114 OtherMemType
= 0x01, ///< Assign 01 to Other
1115 UnknownMemType
, ///< Assign 02 to Unknown
1116 DramMemType
, ///< Assign 03 to DRAM
1117 EdramMemType
, ///< Assign 04 to EDRAM
1118 VramMemType
, ///< Assign 05 to VRAM
1119 SramMemType
, ///< Assign 06 to SRAM
1120 RamMemType
, ///< Assign 07 to RAM
1121 RomMemType
, ///< Assign 08 to ROM
1122 FlashMemType
, ///< Assign 09 to Flash
1123 EepromMemType
, ///< Assign 10 to EEPROM
1124 FepromMemType
, ///< Assign 11 to FEPROM
1125 EpromMemType
, ///< Assign 12 to EPROM
1126 CdramMemType
, ///< Assign 13 to CDRAM
1127 ThreeDramMemType
, ///< Assign 14 to 3DRAM
1128 SdramMemType
, ///< Assign 15 to SDRAM
1129 SgramMemType
, ///< Assign 16 to SGRAM
1130 RdramMemType
, ///< Assign 17 to RDRAM
1131 DdrMemType
, ///< Assign 18 to DDR
1132 Ddr2MemType
, ///< Assign 19 to DDR2
1133 Ddr2FbdimmMemType
, ///< Assign 20 to DDR2 FB-DIMM
1134 Ddr3MemType
= 0x18, ///< Assign 24 to DDR3
1135 Fbd2MemType
, ///< Assign 25 to FBD2
1136 Ddr4MemType
, ///< Assign 26 to DDR4
1137 LpDdrMemType
, ///< Assign 27 to LPDDR
1138 LpDdr2MemType
, ///< Assign 28 to LPDDR2
1139 LpDdr3MemType
, ///< Assign 29 to LPDDR3
1140 LpDdr4MemType
, ///< Assign 30 to LPDDR4
1144 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1145 struct atom_fusion_system_info_v4
1147 struct atom_integrated_system_info_v1_11 sysinfo
; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1148 uint32_t powerplayinfo
[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1153 ***************************************************************************
1154 Data Table gfx_info structure
1155 ***************************************************************************
1158 struct atom_gfx_info_v2_2
1160 struct atom_common_table_header table_header
;
1161 uint8_t gfxip_min_ver
;
1162 uint8_t gfxip_max_ver
;
1163 uint8_t max_shader_engines
;
1164 uint8_t max_tile_pipes
;
1165 uint8_t max_cu_per_sh
;
1166 uint8_t max_sh_per_se
;
1167 uint8_t max_backends_per_se
;
1168 uint8_t max_texture_channel_caches
;
1169 uint32_t regaddr_cp_dma_src_addr
;
1170 uint32_t regaddr_cp_dma_src_addr_hi
;
1171 uint32_t regaddr_cp_dma_dst_addr
;
1172 uint32_t regaddr_cp_dma_dst_addr_hi
;
1173 uint32_t regaddr_cp_dma_command
;
1174 uint32_t regaddr_cp_status
;
1175 uint32_t regaddr_rlc_gpu_clock_32
;
1176 uint32_t rlc_gpu_timer_refclk
;
1182 ***************************************************************************
1183 Data Table smu_info structure
1184 ***************************************************************************
1186 struct atom_smu_info_v3_1
1188 struct atom_common_table_header table_header
;
1189 uint8_t smuip_min_ver
;
1190 uint8_t smuip_max_ver
;
1192 uint8_t gpuclk_ss_mode
; // enum of atom_spread_spectrum_mode
1193 uint16_t sclk_ss_percentage
;
1194 uint16_t sclk_ss_rate_10hz
;
1195 uint16_t gpuclk_ss_percentage
; // in unit of 0.001%
1196 uint16_t gpuclk_ss_rate_10hz
;
1197 uint32_t core_refclk_10khz
;
1198 uint8_t ac_dc_gpio_bit
; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1199 uint8_t ac_dc_polarity
; // GPIO polarity for AC/DC switching
1200 uint8_t vr0hot_gpio_bit
; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1201 uint8_t vr0hot_polarity
; // GPIO polarity for VR0 HOT event
1202 uint8_t vr1hot_gpio_bit
; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1203 uint8_t vr1hot_polarity
; // GPIO polarity for VR1 HOT event
1204 uint8_t fw_ctf_gpio_bit
; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1205 uint8_t fw_ctf_polarity
; // GPIO polarity for CTF
1211 ***************************************************************************
1212 Data Table asic_profiling_info structure
1213 ***************************************************************************
1215 struct atom_asic_profiling_info_v4_1
1217 struct atom_common_table_header table_header
;
1220 uint32_t avfs_meannsigma_acontant0
;
1221 uint32_t avfs_meannsigma_acontant1
;
1222 uint32_t avfs_meannsigma_acontant2
;
1223 uint16_t avfs_meannsigma_dc_tol_sigma
;
1224 uint16_t avfs_meannsigma_platform_mean
;
1225 uint16_t avfs_meannsigma_platform_sigma
;
1226 uint32_t gb_vdroop_table_cksoff_a0
;
1227 uint32_t gb_vdroop_table_cksoff_a1
;
1228 uint32_t gb_vdroop_table_cksoff_a2
;
1229 uint32_t gb_vdroop_table_ckson_a0
;
1230 uint32_t gb_vdroop_table_ckson_a1
;
1231 uint32_t gb_vdroop_table_ckson_a2
;
1232 uint32_t avfsgb_fuse_table_cksoff_m1
;
1233 uint32_t avfsgb_fuse_table_cksoff_m2
;
1234 uint32_t avfsgb_fuse_table_cksoff_b
;
1235 uint32_t avfsgb_fuse_table_ckson_m1
;
1236 uint32_t avfsgb_fuse_table_ckson_m2
;
1237 uint32_t avfsgb_fuse_table_ckson_b
;
1238 uint16_t max_voltage_0_25mv
;
1239 uint8_t enable_gb_vdroop_table_cksoff
;
1240 uint8_t enable_gb_vdroop_table_ckson
;
1241 uint8_t enable_gb_fuse_table_cksoff
;
1242 uint8_t enable_gb_fuse_table_ckson
;
1243 uint16_t psm_age_comfactor
;
1244 uint8_t enable_apply_avfs_cksoff_voltage
;
1246 uint32_t dispclk2gfxclk_a
;
1247 uint32_t dispclk2gfxclk_b
;
1248 uint32_t dispclk2gfxclk_c
;
1249 uint32_t pixclk2gfxclk_a
;
1250 uint32_t pixclk2gfxclk_b
;
1251 uint32_t pixclk2gfxclk_c
;
1252 uint32_t dcefclk2gfxclk_a
;
1253 uint32_t dcefclk2gfxclk_b
;
1254 uint32_t dcefclk2gfxclk_c
;
1255 uint32_t phyclk2gfxclk_a
;
1256 uint32_t phyclk2gfxclk_b
;
1257 uint32_t phyclk2gfxclk_c
;
1260 struct atom_asic_profiling_info_v4_2
{
1261 struct atom_common_table_header table_header
;
1264 uint32_t avfs_meannsigma_acontant0
;
1265 uint32_t avfs_meannsigma_acontant1
;
1266 uint32_t avfs_meannsigma_acontant2
;
1267 uint16_t avfs_meannsigma_dc_tol_sigma
;
1268 uint16_t avfs_meannsigma_platform_mean
;
1269 uint16_t avfs_meannsigma_platform_sigma
;
1270 uint32_t gb_vdroop_table_cksoff_a0
;
1271 uint32_t gb_vdroop_table_cksoff_a1
;
1272 uint32_t gb_vdroop_table_cksoff_a2
;
1273 uint32_t gb_vdroop_table_ckson_a0
;
1274 uint32_t gb_vdroop_table_ckson_a1
;
1275 uint32_t gb_vdroop_table_ckson_a2
;
1276 uint32_t avfsgb_fuse_table_cksoff_m1
;
1277 uint32_t avfsgb_fuse_table_cksoff_m2
;
1278 uint32_t avfsgb_fuse_table_cksoff_b
;
1279 uint32_t avfsgb_fuse_table_ckson_m1
;
1280 uint32_t avfsgb_fuse_table_ckson_m2
;
1281 uint32_t avfsgb_fuse_table_ckson_b
;
1282 uint16_t max_voltage_0_25mv
;
1283 uint8_t enable_gb_vdroop_table_cksoff
;
1284 uint8_t enable_gb_vdroop_table_ckson
;
1285 uint8_t enable_gb_fuse_table_cksoff
;
1286 uint8_t enable_gb_fuse_table_ckson
;
1287 uint16_t psm_age_comfactor
;
1288 uint8_t enable_apply_avfs_cksoff_voltage
;
1290 uint32_t dispclk2gfxclk_a
;
1291 uint32_t dispclk2gfxclk_b
;
1292 uint32_t dispclk2gfxclk_c
;
1293 uint32_t pixclk2gfxclk_a
;
1294 uint32_t pixclk2gfxclk_b
;
1295 uint32_t pixclk2gfxclk_c
;
1296 uint32_t dcefclk2gfxclk_a
;
1297 uint32_t dcefclk2gfxclk_b
;
1298 uint32_t dcefclk2gfxclk_c
;
1299 uint32_t phyclk2gfxclk_a
;
1300 uint32_t phyclk2gfxclk_b
;
1301 uint32_t phyclk2gfxclk_c
;
1302 uint32_t acg_gb_vdroop_table_a0
;
1303 uint32_t acg_gb_vdroop_table_a1
;
1304 uint32_t acg_gb_vdroop_table_a2
;
1305 uint32_t acg_avfsgb_fuse_table_m1
;
1306 uint32_t acg_avfsgb_fuse_table_m2
;
1307 uint32_t acg_avfsgb_fuse_table_b
;
1308 uint8_t enable_acg_gb_vdroop_table
;
1309 uint8_t enable_acg_gb_fuse_table
;
1310 uint32_t acg_dispclk2gfxclk_a
;
1311 uint32_t acg_dispclk2gfxclk_b
;
1312 uint32_t acg_dispclk2gfxclk_c
;
1313 uint32_t acg_pixclk2gfxclk_a
;
1314 uint32_t acg_pixclk2gfxclk_b
;
1315 uint32_t acg_pixclk2gfxclk_c
;
1316 uint32_t acg_dcefclk2gfxclk_a
;
1317 uint32_t acg_dcefclk2gfxclk_b
;
1318 uint32_t acg_dcefclk2gfxclk_c
;
1319 uint32_t acg_phyclk2gfxclk_a
;
1320 uint32_t acg_phyclk2gfxclk_b
;
1321 uint32_t acg_phyclk2gfxclk_c
;
1325 ***************************************************************************
1326 Data Table multimedia_info structure
1327 ***************************************************************************
1329 struct atom_multimedia_info_v2_1
1331 struct atom_common_table_header table_header
;
1332 uint8_t uvdip_min_ver
;
1333 uint8_t uvdip_max_ver
;
1334 uint8_t vceip_min_ver
;
1335 uint8_t vceip_max_ver
;
1336 uint16_t uvd_enc_max_input_width_pixels
;
1337 uint16_t uvd_enc_max_input_height_pixels
;
1338 uint16_t vce_enc_max_input_width_pixels
;
1339 uint16_t vce_enc_max_input_height_pixels
;
1340 uint32_t uvd_enc_max_bandwidth
; // 16x16 pixels/sec, codec independent
1341 uint32_t vce_enc_max_bandwidth
; // 16x16 pixels/sec, codec independent
1346 ***************************************************************************
1347 Data Table umc_info structure
1348 ***************************************************************************
1350 struct atom_umc_info_v3_1
1352 struct atom_common_table_header table_header
;
1353 uint32_t ucode_version
;
1354 uint32_t ucode_rom_startaddr
;
1355 uint32_t ucode_length
;
1356 uint16_t umc_reg_init_offset
;
1357 uint16_t customer_ucode_name_offset
;
1358 uint16_t mclk_ss_percentage
;
1359 uint16_t mclk_ss_rate_10hz
;
1360 uint8_t umcip_min_ver
;
1361 uint8_t umcip_max_ver
;
1362 uint8_t vram_type
; //enum of atom_dgpu_vram_type
1364 uint32_t mem_refclk_10khz
;
1369 ***************************************************************************
1370 Data Table vram_info structure
1371 ***************************************************************************
1373 struct atom_vram_module_v9
1375 // Design Specific Values
1376 uint32_t memory_size
; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1377 uint32_t channel_enable
; // for 32 channel ASIC usage
1378 uint32_t umcch_addrcfg
;
1379 uint32_t umcch_addrsel
;
1380 uint32_t umcch_colsel
;
1381 uint16_t vram_module_size
; // Size of atom_vram_module_v9
1382 uint8_t ext_memory_id
; // Current memory module ID
1383 uint8_t memory_type
; // enum of atom_dgpu_vram_type
1384 uint8_t channel_num
; // Number of mem. channels supported in this module
1385 uint8_t channel_width
; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1386 uint8_t density
; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1387 uint8_t tunningset_id
; // MC phy registers set per.
1388 uint8_t vender_rev_id
; // [7:4] Revision, [3:0] Vendor code
1389 uint8_t refreshrate
; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1390 uint16_t vram_rsd2
; // reserved
1391 char dram_pnstring
[20]; // part number end with '0'.
1395 struct atom_vram_info_header_v2_3
1397 struct atom_common_table_header table_header
;
1398 uint16_t mem_adjust_tbloffset
; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1399 uint16_t mem_clk_patch_tbloffset
; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1400 uint16_t mc_adjust_pertile_tbloffset
; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1401 uint16_t mc_phyinit_tbloffset
; // offset of atom_umc_init_reg_block structure for MC phy init set
1402 uint16_t dram_data_remap_tbloffset
; // reserved for now
1403 uint16_t vram_rsd2
[3];
1404 uint8_t vram_module_num
; // indicate number of VRAM module
1405 uint8_t vram_rsd1
[2];
1406 uint8_t mc_phy_tile_num
; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1407 struct atom_vram_module_v9 vram_module
[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1410 struct atom_umc_register_addr_info
{
1411 uint32_t umc_register_addr
:24;
1412 uint32_t umc_reg_type_ind
:1;
1413 uint32_t umc_reg_rsvd
:7;
1416 //atom_umc_register_addr_info.
1417 enum atom_umc_register_addr_info_flag
{
1418 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS
=0x01,
1421 union atom_umc_register_addr_info_access
1423 struct atom_umc_register_addr_info umc_reg_addr
;
1424 uint32_t u32umc_reg_addr
;
1427 struct atom_umc_reg_setting_id_config
{
1428 uint32_t memclockrange
:24;
1429 uint32_t mem_blk_id
:8;
1432 union atom_umc_reg_setting_id_config_access
1434 struct atom_umc_reg_setting_id_config umc_id_access
;
1435 uint32_t u32umc_id_access
;
1438 struct atom_umc_reg_setting_data_block
{
1439 union atom_umc_reg_setting_id_config_access block_id
;
1440 uint32_t u32umc_reg_data
[1];
1443 struct atom_umc_init_reg_block
{
1444 uint16_t umc_reg_num
;
1446 union atom_umc_register_addr_info_access umc_reg_list
[1]; //for allocation purpose, the real number come from umc_reg_num;
1447 struct atom_umc_reg_setting_data_block umc_reg_setting_list
[1];
1452 ***************************************************************************
1453 Data Table voltageobject_info structure
1454 ***************************************************************************
1456 struct atom_i2c_data_entry
1458 uint16_t i2c_reg_index
; // i2c register address, can be up to 16bit
1459 uint16_t i2c_reg_data
; // i2c register data, can be up to 16bit
1462 struct atom_voltage_object_header_v4
{
1463 uint8_t voltage_type
; //enum atom_voltage_type
1464 uint8_t voltage_mode
; //enum atom_voltage_object_mode
1465 uint16_t object_size
; //Size of Object
1468 // atom_voltage_object_header_v4.voltage_mode
1469 enum atom_voltage_object_mode
1471 VOLTAGE_OBJ_GPIO_LUT
= 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1472 VOLTAGE_OBJ_VR_I2C_INIT_SEQ
= 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1473 VOLTAGE_OBJ_PHASE_LUT
= 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1474 VOLTAGE_OBJ_SVID2
= 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1475 VOLTAGE_OBJ_EVV
= 8,
1476 VOLTAGE_OBJ_MERGED_POWER
= 9,
1479 struct atom_i2c_voltage_object_v4
1481 struct atom_voltage_object_header_v4 header
; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1482 uint8_t regulator_id
; //Indicate Voltage Regulator Id
1484 uint8_t i2c_slave_addr
;
1485 uint8_t i2c_control_offset
;
1486 uint8_t i2c_flag
; // Bit0: 0 - One byte data; 1 - Two byte data
1487 uint8_t i2c_speed
; // =0, use default i2c speed, otherwise use it in unit of kHz.
1488 uint8_t reserved
[2];
1489 struct atom_i2c_data_entry i2cdatalut
[1]; // end with 0xff
1492 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1493 enum atom_i2c_voltage_control_flag
1495 VOLTAGE_DATA_ONE_BYTE
= 0,
1496 VOLTAGE_DATA_TWO_BYTE
= 1,
1500 struct atom_voltage_gpio_map_lut
1502 uint32_t voltage_gpio_reg_val
; // The Voltage ID which is used to program GPIO register
1503 uint16_t voltage_level_mv
; // The corresponding Voltage Value, in mV
1506 struct atom_gpio_voltage_object_v4
1508 struct atom_voltage_object_header_v4 header
; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1509 uint8_t gpio_control_id
; // default is 0 which indicate control through CG VID mode
1510 uint8_t gpio_entry_num
; // indiate the entry numbers of Votlage/Gpio value Look up table
1511 uint8_t phase_delay_us
; // phase delay in unit of micro second
1513 uint32_t gpio_mask_val
; // GPIO Mask value
1514 struct atom_voltage_gpio_map_lut voltage_gpio_lut
[1];
1517 struct atom_svid2_voltage_object_v4
1519 struct atom_voltage_object_header_v4 header
; // voltage mode = VOLTAGE_OBJ_SVID2
1520 uint8_t loadline_psi1
; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1521 uint8_t psi0_l_vid_thresd
; // VR PSI0_L VID threshold
1522 uint8_t psi0_enable
; //
1524 uint8_t telemetry_offset
;
1525 uint8_t telemetry_gain
;
1529 struct atom_merged_voltage_object_v4
1531 struct atom_voltage_object_header_v4 header
; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1532 uint8_t merged_powerrail_type
; //enum atom_voltage_type
1533 uint8_t reserved
[3];
1536 union atom_voltage_object_v4
{
1537 struct atom_gpio_voltage_object_v4 gpio_voltage_obj
;
1538 struct atom_i2c_voltage_object_v4 i2c_voltage_obj
;
1539 struct atom_svid2_voltage_object_v4 svid2_voltage_obj
;
1540 struct atom_merged_voltage_object_v4 merged_voltage_obj
;
1543 struct atom_voltage_objects_info_v4_1
1545 struct atom_common_table_header table_header
;
1546 union atom_voltage_object_v4 voltage_object
[1]; //Info for Voltage control
1551 ***************************************************************************
1552 All Command Function structure definition
1553 ***************************************************************************
1557 ***************************************************************************
1558 Structures used by asic_init
1559 ***************************************************************************
1562 struct asic_init_engine_parameters
1564 uint32_t sclkfreqin10khz
:24;
1565 uint32_t engineflag
:8; /* enum atom_asic_init_engine_flag */
1568 struct asic_init_mem_parameters
1570 uint32_t mclkfreqin10khz
:24;
1571 uint32_t memflag
:8; /* enum atom_asic_init_mem_flag */
1574 struct asic_init_parameters_v2_1
1576 struct asic_init_engine_parameters engineparam
;
1577 struct asic_init_mem_parameters memparam
;
1580 struct asic_init_ps_allocation_v2_1
1582 struct asic_init_parameters_v2_1 param
;
1583 uint32_t reserved
[16];
1587 enum atom_asic_init_engine_flag
1589 b3NORMAL_ENGINE_INIT
= 0,
1590 b3SRIOV_SKIP_ASIC_INIT
= 0x02,
1591 b3SRIOV_LOAD_UCODE
= 0x40,
1594 enum atom_asic_init_mem_flag
1596 b3NORMAL_MEM_INIT
= 0,
1597 b3DRAM_SELF_REFRESH_EXIT
=0x20,
1601 ***************************************************************************
1602 Structures used by setengineclock
1603 ***************************************************************************
1606 struct set_engine_clock_parameters_v2_1
1608 uint32_t sclkfreqin10khz
:24;
1609 uint32_t sclkflag
:8; /* enum atom_set_engine_mem_clock_flag, */
1610 uint32_t reserved
[10];
1613 struct set_engine_clock_ps_allocation_v2_1
1615 struct set_engine_clock_parameters_v2_1 clockinfo
;
1616 uint32_t reserved
[10];
1620 enum atom_set_engine_mem_clock_flag
1622 b3NORMAL_CHANGE_CLOCK
= 0,
1623 b3FIRST_TIME_CHANGE_CLOCK
= 0x08,
1624 b3STORE_DPM_TRAINGING
= 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
1628 ***************************************************************************
1629 Structures used by getengineclock
1630 ***************************************************************************
1632 struct get_engine_clock_parameter
1634 uint32_t sclk_10khz
; // current engine speed in 10KHz unit
1639 ***************************************************************************
1640 Structures used by setmemoryclock
1641 ***************************************************************************
1643 struct set_memory_clock_parameters_v2_1
1645 uint32_t mclkfreqin10khz
:24;
1646 uint32_t mclkflag
:8; /* enum atom_set_engine_mem_clock_flag, */
1647 uint32_t reserved
[10];
1650 struct set_memory_clock_ps_allocation_v2_1
1652 struct set_memory_clock_parameters_v2_1 clockinfo
;
1653 uint32_t reserved
[10];
1658 ***************************************************************************
1659 Structures used by getmemoryclock
1660 ***************************************************************************
1662 struct get_memory_clock_parameter
1664 uint32_t mclk_10khz
; // current engine speed in 10KHz unit
1671 ***************************************************************************
1672 Structures used by setvoltage
1673 ***************************************************************************
1676 struct set_voltage_parameters_v1_4
1678 uint8_t voltagetype
; /* enum atom_voltage_type */
1679 uint8_t command
; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
1680 uint16_t vlevel_mv
; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
1683 //set_voltage_parameters_v2_1.voltagemode
1684 enum atom_set_voltage_command
{
1685 ATOM_SET_VOLTAGE
= 0,
1686 ATOM_INIT_VOLTAGE_REGULATOR
= 3,
1687 ATOM_SET_VOLTAGE_PHASE
= 4,
1688 ATOM_GET_LEAKAGE_ID
= 8,
1691 struct set_voltage_ps_allocation_v1_4
1693 struct set_voltage_parameters_v1_4 setvoltageparam
;
1694 uint32_t reserved
[10];
1699 ***************************************************************************
1700 Structures used by computegpuclockparam
1701 ***************************************************************************
1704 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
1705 enum atom_gpu_clock_type
1707 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
=0x00,
1708 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK
=0x01,
1709 COMPUTE_GPUCLK_INPUT_FLAG_UCLK
=0x02,
1712 struct compute_gpu_clock_input_parameter_v1_8
1714 uint32_t gpuclock_10khz
:24; //Input= target clock, output = actual clock
1715 uint32_t gpu_clock_type
:8; //Input indicate clock type: enum atom_gpu_clock_type
1716 uint32_t reserved
[5];
1720 struct compute_gpu_clock_output_parameter_v1_8
1722 uint32_t gpuclock_10khz
:24; //Input= target clock, output = actual clock
1723 uint32_t dfs_did
:8; //return parameter: DFS divider which is used to program to register directly
1724 uint32_t pll_fb_mult
; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
1725 uint32_t pll_ss_fbsmult
; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
1726 uint16_t pll_ss_slew_frac
;
1727 uint8_t pll_ss_enable
;
1729 uint32_t reserved1
[2];
1735 ***************************************************************************
1736 Structures used by ReadEfuseValue
1737 ***************************************************************************
1740 struct read_efuse_input_parameters_v3_1
1742 uint16_t efuse_start_index
;
1747 // ReadEfuseValue input/output parameter
1748 union read_efuse_value_parameters_v3_1
1750 struct read_efuse_input_parameters_v3_1 efuse_info
;
1751 uint32_t efusevalue
;
1756 ***************************************************************************
1757 Structures used by getsmuclockinfo
1758 ***************************************************************************
1760 struct atom_get_smu_clock_info_parameters_v3_1
1762 uint8_t syspll_id
; // 0= syspll0, 1=syspll1, 2=syspll2
1763 uint8_t clk_id
; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1764 uint8_t command
; // enum of atom_get_smu_clock_info_command
1765 uint8_t dfsdid
; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1768 enum atom_get_smu_clock_info_command
1770 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ
= 0,
1771 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ
= 1,
1772 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ
= 2,
1775 enum atom_smu9_syspll0_clock_id
1777 SMU9_SYSPLL0_SMNCLK_ID
= 0, // SMNCLK
1778 SMU9_SYSPLL0_SOCCLK_ID
= 1, // SOCCLK (FCLK)
1779 SMU9_SYSPLL0_MP0CLK_ID
= 2, // MP0CLK
1780 SMU9_SYSPLL0_MP1CLK_ID
= 3, // MP1CLK
1781 SMU9_SYSPLL0_LCLK_ID
= 4, // LCLK
1782 SMU9_SYSPLL0_DCLK_ID
= 5, // DCLK
1783 SMU9_SYSPLL0_VCLK_ID
= 6, // VCLK
1784 SMU9_SYSPLL0_ECLK_ID
= 7, // ECLK
1785 SMU9_SYSPLL0_DCEFCLK_ID
= 8, // DCEFCLK
1786 SMU9_SYSPLL0_DPREFCLK_ID
= 10, // DPREFCLK
1787 SMU9_SYSPLL0_DISPCLK_ID
= 11, // DISPCLK
1790 struct atom_get_smu_clock_info_output_parameters_v3_1
1793 uint32_t smu_clock_freq_hz
;
1794 uint32_t syspllvcofreq_10khz
;
1795 uint32_t sysspllrefclk_10khz
;
1796 }atom_smu_outputclkfreq
;
1802 ***************************************************************************
1803 Structures used by dynamicmemorysettings
1804 ***************************************************************************
1807 enum atom_dynamic_memory_setting_command
1809 COMPUTE_MEMORY_PLL_PARAM
= 1,
1810 COMPUTE_ENGINE_PLL_PARAM
= 2,
1811 ADJUST_MC_SETTING_PARAM
= 3,
1814 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
1815 struct dynamic_mclk_settings_parameters_v2_1
1817 uint32_t mclk_10khz
:24; //Input= target mclk
1818 uint32_t command
:8; //command enum of atom_dynamic_memory_setting_command
1822 /* when command = COMPUTE_ENGINE_PLL_PARAM */
1823 struct dynamic_sclk_settings_parameters_v2_1
1825 uint32_t sclk_10khz
:24; //Input= target mclk
1826 uint32_t command
:8; //command enum of atom_dynamic_memory_setting_command
1827 uint32_t mclk_10khz
;
1831 union dynamic_memory_settings_parameters_v2_1
1833 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting
;
1834 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting
;
1840 ***************************************************************************
1841 Structures used by memorytraining
1842 ***************************************************************************
1845 enum atom_umc6_0_ucode_function_call_enum_id
1847 UMC60_UCODE_FUNC_ID_REINIT
= 0,
1848 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH
= 1,
1849 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH
= 2,
1853 struct memory_training_parameters_v2_1
1855 uint8_t ucode_func_id
;
1856 uint8_t ucode_reserved
[3];
1857 uint32_t reserved
[5];
1862 ***************************************************************************
1863 Structures used by setpixelclock
1864 ***************************************************************************
1867 struct set_pixel_clock_parameter_v1_7
1869 uint32_t pixclk_100hz
; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
1871 uint8_t pll_id
; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
1872 uint8_t encoderobjid
; // ASIC encoder id defined in objectId.h,
1873 // indicate which graphic encoder will be used.
1874 uint8_t encoder_mode
; // Encoder mode:
1875 uint8_t miscinfo
; // enum atom_set_pixel_clock_v1_7_misc_info
1876 uint8_t crtc_id
; // enum of atom_crtc_def
1877 uint8_t deep_color_ratio
; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1878 uint8_t reserved1
[2];
1883 enum atom_set_pixel_clock_v1_7_misc_info
1885 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL
= 0x01,
1886 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL
= 0x02,
1887 PIXEL_CLOCK_V7_MISC_YUV420_MODE
= 0x04,
1888 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN
= 0x08,
1889 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC
= 0x30,
1890 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN
= 0x00,
1891 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE
= 0x10,
1892 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK
= 0x20,
1893 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD
= 0x30,
1894 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE
= 0x40,
1895 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS
= 0x80,
1898 /* deep_color_ratio */
1899 enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1901 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS
= 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
1902 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4
= 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
1903 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2
= 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
1904 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1
= 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
1908 ***************************************************************************
1909 Structures used by setdceclock
1910 ***************************************************************************
1913 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
1914 struct set_dce_clock_parameters_v2_1
1916 uint32_t dceclk_10khz
; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
1917 uint8_t dceclktype
; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
1918 uint8_t dceclksrc
; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
1919 uint8_t dceclkflag
; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
1920 uint8_t crtc_id
; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
1924 enum atom_set_dce_clock_clock_type
1926 DCE_CLOCK_TYPE_DISPCLK
= 0,
1927 DCE_CLOCK_TYPE_DPREFCLK
= 1,
1928 DCE_CLOCK_TYPE_PIXELCLK
= 2, // used by VBIOS internally, called by SetPixelClock
1931 //ucDCEClkFlag when ucDCEClkType == DPREFCLK
1932 enum atom_set_dce_clock_dprefclk_flag
1934 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK
= 0x03,
1935 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA
= 0x00,
1936 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK
= 0x01,
1937 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE
= 0x02,
1938 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN
= 0x03,
1941 //ucDCEClkFlag when ucDCEClkType == PIXCLK
1942 enum atom_set_dce_clock_pixclk_flag
1944 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK
= 0x03,
1945 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS
= 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
1946 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4
= 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
1947 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2
= 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
1948 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1
= 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
1949 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE
= 0x04,
1952 struct set_dce_clock_ps_allocation_v2_1
1954 struct set_dce_clock_parameters_v2_1 param
;
1955 uint32_t ulReserved
[2];
1959 /****************************************************************************/
1960 // Structures used by BlankCRTC
1961 /****************************************************************************/
1962 struct blank_crtc_parameters
1964 uint8_t crtc_id
; // enum atom_crtc_def
1965 uint8_t blanking
; // enum atom_blank_crtc_command
1970 enum atom_blank_crtc_command
1973 ATOM_BLANKING_OFF
= 0,
1976 /****************************************************************************/
1977 // Structures used by enablecrtc
1978 /****************************************************************************/
1979 struct enable_crtc_parameters
1981 uint8_t crtc_id
; // enum atom_crtc_def
1982 uint8_t enable
; // ATOM_ENABLE or ATOM_DISABLE
1987 /****************************************************************************/
1988 // Structure used by EnableDispPowerGating
1989 /****************************************************************************/
1990 struct enable_disp_power_gating_parameters_v2_1
1992 uint8_t disp_pipe_id
; // ATOM_CRTC1, ATOM_CRTC2, ...
1993 uint8_t enable
; // ATOM_ENABLE or ATOM_DISABLE
1997 struct enable_disp_power_gating_ps_allocation
1999 struct enable_disp_power_gating_parameters_v2_1 param
;
2000 uint32_t ulReserved
[4];
2003 /****************************************************************************/
2004 // Structure used in setcrtc_usingdtdtiming
2005 /****************************************************************************/
2006 struct set_crtc_using_dtd_timing_parameters
2009 uint16_t h_blanking_time
;
2011 uint16_t v_blanking_time
;
2012 uint16_t h_syncoffset
;
2013 uint16_t h_syncwidth
;
2014 uint16_t v_syncoffset
;
2015 uint16_t v_syncwidth
;
2016 uint16_t modemiscinfo
;
2019 uint8_t crtc_id
; // enum atom_crtc_def
2020 uint8_t encoder_mode
; // atom_encode_mode_def
2025 /****************************************************************************/
2026 // Structures used by processi2cchanneltransaction
2027 /****************************************************************************/
2028 struct process_i2c_channel_transaction_parameters
2030 uint8_t i2cspeed_khz
;
2033 uint8_t status
; /* enum atom_process_i2c_flag */
2035 uint16_t i2c_data_out
;
2036 uint8_t flag
; /* enum atom_process_i2c_status */
2037 uint8_t trans_bytes
;
2043 enum atom_process_i2c_flag
2047 I2C_2BYTE_ADDR
= 0x02,
2048 HW_I2C_SMBUS_BYTE_WR
= 0x04,
2052 enum atom_process_i2c_status
2054 HW_ASSISTED_I2C_STATUS_FAILURE
=2,
2055 HW_ASSISTED_I2C_STATUS_SUCCESS
=1,
2059 /****************************************************************************/
2060 // Structures used by processauxchanneltransaction
2061 /****************************************************************************/
2063 struct process_aux_channel_transaction_parameters_v1_2
2065 uint16_t aux_request
;
2069 uint8_t reply_status
;
2072 uint8_t dataout_len
;
2073 uint8_t hpd_id
; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2077 /****************************************************************************/
2078 // Structures used by selectcrtc_source
2079 /****************************************************************************/
2081 struct select_crtc_source_parameters_v2_3
2083 uint8_t crtc_id
; // enum atom_crtc_def
2084 uint8_t encoder_id
; // enum atom_dig_def
2085 uint8_t encode_mode
; // enum atom_encode_mode_def
2086 uint8_t dst_bpc
; // enum atom_panel_bit_per_color
2090 /****************************************************************************/
2091 // Structures used by digxencodercontrol
2092 /****************************************************************************/
2095 enum atom_dig_encoder_control_action
2097 ATOM_ENCODER_CMD_DISABLE_DIG
= 0,
2098 ATOM_ENCODER_CMD_ENABLE_DIG
= 1,
2099 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
= 0x08,
2100 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
= 0x09,
2101 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
= 0x0a,
2102 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
= 0x13,
2103 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
= 0x0b,
2104 ATOM_ENCODER_CMD_DP_VIDEO_OFF
= 0x0c,
2105 ATOM_ENCODER_CMD_DP_VIDEO_ON
= 0x0d,
2106 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
= 0x10,
2107 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4
= 0x14,
2108 ATOM_ENCODER_CMD_STREAM_SETUP
= 0x0F,
2109 ATOM_ENCODER_CMD_LINK_SETUP
= 0x11,
2110 ATOM_ENCODER_CMD_ENCODER_BLANK
= 0x12,
2113 //define ucPanelMode
2114 enum atom_dig_encoder_control_panelmode
2116 DP_PANEL_MODE_DISABLE
= 0x00,
2117 DP_PANEL_MODE_ENABLE_eDP_MODE
= 0x01,
2118 DP_PANEL_MODE_ENABLE_LVLINK_MODE
= 0x11,
2122 enum atom_dig_encoder_control_v5_digid
2124 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER
= 0x00,
2125 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER
= 0x01,
2126 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER
= 0x02,
2127 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER
= 0x03,
2128 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER
= 0x04,
2129 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER
= 0x05,
2130 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER
= 0x06,
2131 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER
= 0x07,
2134 struct dig_encoder_stream_setup_parameters_v1_5
2136 uint8_t digid
; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2137 uint8_t action
; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2138 uint8_t digmode
; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2139 uint8_t lanenum
; // Lane number
2140 uint32_t pclk_10khz
; // Pixel Clock in 10Khz
2141 uint8_t bitpercolor
;
2142 uint8_t dplinkrate_270mhz
;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2143 uint8_t reserved
[2];
2146 struct dig_encoder_link_setup_parameters_v1_5
2148 uint8_t digid
; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2149 uint8_t action
; // = ATOM_ENOCODER_CMD_LINK_SETUP
2150 uint8_t digmode
; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2151 uint8_t lanenum
; // Lane number
2152 uint8_t symclk_10khz
; // Symbol Clock in 10Khz
2154 uint8_t digfe_sel
; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2155 uint8_t reserved
[2];
2158 struct dp_panel_mode_set_parameters_v1_5
2160 uint8_t digid
; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2161 uint8_t action
; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2162 uint8_t panelmode
; // enum atom_dig_encoder_control_panelmode
2164 uint32_t reserved2
[2];
2167 struct dig_encoder_generic_cmd_parameters_v1_5
2169 uint8_t digid
; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2170 uint8_t action
; // = rest of generic encoder command which does not carry any parameters
2171 uint8_t reserved1
[2];
2172 uint32_t reserved2
[2];
2175 union dig_encoder_control_parameters_v1_5
2177 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param
;
2178 struct dig_encoder_stream_setup_parameters_v1_5 stream_param
;
2179 struct dig_encoder_link_setup_parameters_v1_5 link_param
;
2180 struct dp_panel_mode_set_parameters_v1_5 dppanel_param
;
2184 ***************************************************************************
2185 Structures used by dig1transmittercontrol
2186 ***************************************************************************
2188 struct dig_transmitter_control_parameters_v1_6
2190 uint8_t phyid
; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2191 uint8_t action
; // define as ATOM_TRANSMITER_ACTION_xxx
2193 uint8_t digmode
; // enum atom_encode_mode_def
2194 uint8_t dplaneset
; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2196 uint8_t lanenum
; // Lane number 1, 2, 4, 8
2197 uint32_t symclk_10khz
; // Symbol Clock in 10Khz
2198 uint8_t hpdsel
; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2199 uint8_t digfe_sel
; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2200 uint8_t connobj_id
; // Connector Object Id defined in ObjectId.h
2205 struct dig_transmitter_control_ps_allocation_v1_6
2207 struct dig_transmitter_control_parameters_v1_6 param
;
2208 uint32_t reserved
[4];
2212 enum atom_dig_transmitter_control_action
2214 ATOM_TRANSMITTER_ACTION_DISABLE
= 0,
2215 ATOM_TRANSMITTER_ACTION_ENABLE
= 1,
2216 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
= 2,
2217 ATOM_TRANSMITTER_ACTION_LCD_BLON
= 3,
2218 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
= 4,
2219 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START
= 5,
2220 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP
= 6,
2221 ATOM_TRANSMITTER_ACTION_INIT
= 7,
2222 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
= 8,
2223 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
= 9,
2224 ATOM_TRANSMITTER_ACTION_SETUP
= 10,
2225 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
= 11,
2226 ATOM_TRANSMITTER_ACTION_POWER_ON
= 12,
2227 ATOM_TRANSMITTER_ACTION_POWER_OFF
= 13,
2231 enum atom_dig_transmitter_control_digfe_sel
2233 ATOM_TRANMSITTER_V6__DIGA_SEL
= 0x01,
2234 ATOM_TRANMSITTER_V6__DIGB_SEL
= 0x02,
2235 ATOM_TRANMSITTER_V6__DIGC_SEL
= 0x04,
2236 ATOM_TRANMSITTER_V6__DIGD_SEL
= 0x08,
2237 ATOM_TRANMSITTER_V6__DIGE_SEL
= 0x10,
2238 ATOM_TRANMSITTER_V6__DIGF_SEL
= 0x20,
2239 ATOM_TRANMSITTER_V6__DIGG_SEL
= 0x40,
2244 enum atom_dig_transmitter_control_hpd_sel
2246 ATOM_TRANSMITTER_V6_NO_HPD_SEL
= 0x00,
2247 ATOM_TRANSMITTER_V6_HPD1_SEL
= 0x01,
2248 ATOM_TRANSMITTER_V6_HPD2_SEL
= 0x02,
2249 ATOM_TRANSMITTER_V6_HPD3_SEL
= 0x03,
2250 ATOM_TRANSMITTER_V6_HPD4_SEL
= 0x04,
2251 ATOM_TRANSMITTER_V6_HPD5_SEL
= 0x05,
2252 ATOM_TRANSMITTER_V6_HPD6_SEL
= 0x06,
2256 enum atom_dig_transmitter_control_dplaneset
2258 DP_LANE_SET__0DB_0_4V
= 0x00,
2259 DP_LANE_SET__0DB_0_6V
= 0x01,
2260 DP_LANE_SET__0DB_0_8V
= 0x02,
2261 DP_LANE_SET__0DB_1_2V
= 0x03,
2262 DP_LANE_SET__3_5DB_0_4V
= 0x08,
2263 DP_LANE_SET__3_5DB_0_6V
= 0x09,
2264 DP_LANE_SET__3_5DB_0_8V
= 0x0a,
2265 DP_LANE_SET__6DB_0_4V
= 0x10,
2266 DP_LANE_SET__6DB_0_6V
= 0x11,
2267 DP_LANE_SET__9_5DB_0_4V
= 0x18,
2272 /****************************************************************************/
2273 // Structures used by ExternalEncoderControl V2.4
2274 /****************************************************************************/
2276 struct external_encoder_control_parameters_v2_4
2278 uint16_t pixelclock_10khz
; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2279 uint8_t config
; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2281 uint8_t encodermode
; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2282 uint8_t lanenum
; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2283 uint8_t bitpercolor
; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2289 enum external_encoder_control_action_def
2291 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT
= 0x00,
2292 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT
= 0x01,
2293 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
= 0x07,
2294 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
= 0x0f,
2295 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF
= 0x10,
2296 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING
= 0x11,
2297 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
= 0x12,
2298 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
= 0x14,
2302 enum external_encoder_control_v2_4_config_def
2304 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK
= 0x03,
2305 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ
= 0x00,
2306 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
= 0x01,
2307 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
= 0x02,
2308 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ
= 0x03,
2309 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS
= 0x70,
2310 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
= 0x00,
2311 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
= 0x10,
2312 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
= 0x20,
2315 struct external_encoder_control_ps_allocation_v2_4
2317 struct external_encoder_control_parameters_v2_4 sExtEncoder
;
2318 uint32_t reserved
[2];
2323 ***************************************************************************
2326 ***************************************************************************
2329 struct amd_acpi_description_header
{
2331 uint32_t tableLength
; //Length
2335 uint8_t oemTableId
[8]; //UINT64 OemTableId;
2336 uint32_t oemRevision
;
2338 uint32_t creatorRevision
;
2341 struct uefi_acpi_vfct
{
2342 struct amd_acpi_description_header sheader
;
2343 uint8_t tableUUID
[16]; //0x24
2344 uint32_t vbiosimageoffset
; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2345 uint32_t lib1Imageoffset
; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2346 uint32_t reserved
[4]; //0x3C
2349 struct vfct_image_header
{
2350 uint32_t pcibus
; //0x4C
2351 uint32_t pcidevice
; //0x50
2352 uint32_t pcifunction
; //0x54
2353 uint16_t vendorid
; //0x58
2354 uint16_t deviceid
; //0x5A
2355 uint16_t ssvid
; //0x5C
2356 uint16_t ssid
; //0x5E
2357 uint32_t revision
; //0x60
2358 uint32_t imagelength
; //0x64
2362 struct gop_vbios_content
{
2363 struct vfct_image_header vbiosheader
;
2364 uint8_t vbioscontent
[1];
2367 struct gop_lib1_content
{
2368 struct vfct_image_header lib1header
;
2369 uint8_t lib1content
[1];
2375 ***************************************************************************
2376 Scratch Register definitions
2377 Each number below indicates which scratch regiser request, Active and
2378 Connect all share the same definitions as display_device_tag defines
2379 ***************************************************************************
2382 enum scratch_register_def
{
2383 ATOM_DEVICE_CONNECT_INFO_DEF
= 0,
2384 ATOM_BL_BRI_LEVEL_INFO_DEF
= 2,
2385 ATOM_ACTIVE_INFO_DEF
= 3,
2386 ATOM_LCD_INFO_DEF
= 4,
2387 ATOM_DEVICE_REQ_INFO_DEF
= 5,
2388 ATOM_ACC_CHANGE_INFO_DEF
= 6,
2389 ATOM_PRE_OS_MODE_INFO_DEF
= 7,
2390 ATOM_PRE_OS_ASSERTION_DEF
= 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2391 ATOM_INTERNAL_TIMER_INFO_DEF
= 10,
2394 enum scratch_device_connect_info_bit_def
{
2395 ATOM_DISPLAY_LCD1_CONNECT
=0x0002,
2396 ATOM_DISPLAY_DFP1_CONNECT
=0x0008,
2397 ATOM_DISPLAY_DFP2_CONNECT
=0x0080,
2398 ATOM_DISPLAY_DFP3_CONNECT
=0x0200,
2399 ATOM_DISPLAY_DFP4_CONNECT
=0x0400,
2400 ATOM_DISPLAY_DFP5_CONNECT
=0x0800,
2401 ATOM_DISPLAY_DFP6_CONNECT
=0x0040,
2402 ATOM_DISPLAY_DFPx_CONNECT
=0x0ec8,
2403 ATOM_CONNECT_INFO_DEVICE_MASK
=0x0fff,
2406 enum scratch_bl_bri_level_info_bit_def
{
2407 ATOM_CURRENT_BL_LEVEL_SHIFT
=0x8,
2409 ATOM_CURRENT_BL_LEVEL_MASK
=0x0000ff00,
2410 ATOM_DEVICE_DPMS_STATE
=0x00010000,
2414 enum scratch_active_info_bits_def
{
2415 ATOM_DISPLAY_LCD1_ACTIVE
=0x0002,
2416 ATOM_DISPLAY_DFP1_ACTIVE
=0x0008,
2417 ATOM_DISPLAY_DFP2_ACTIVE
=0x0080,
2418 ATOM_DISPLAY_DFP3_ACTIVE
=0x0200,
2419 ATOM_DISPLAY_DFP4_ACTIVE
=0x0400,
2420 ATOM_DISPLAY_DFP5_ACTIVE
=0x0800,
2421 ATOM_DISPLAY_DFP6_ACTIVE
=0x0040,
2422 ATOM_ACTIVE_INFO_DEVICE_MASK
=0x0fff,
2425 enum scratch_device_req_info_bits_def
{
2426 ATOM_DISPLAY_LCD1_REQ
=0x0002,
2427 ATOM_DISPLAY_DFP1_REQ
=0x0008,
2428 ATOM_DISPLAY_DFP2_REQ
=0x0080,
2429 ATOM_DISPLAY_DFP3_REQ
=0x0200,
2430 ATOM_DISPLAY_DFP4_REQ
=0x0400,
2431 ATOM_DISPLAY_DFP5_REQ
=0x0800,
2432 ATOM_DISPLAY_DFP6_REQ
=0x0040,
2433 ATOM_REQ_INFO_DEVICE_MASK
=0x0fff,
2436 enum scratch_acc_change_info_bitshift_def
{
2437 ATOM_ACC_CHANGE_ACC_MODE_SHIFT
=4,
2438 ATOM_ACC_CHANGE_LID_STATUS_SHIFT
=6,
2441 enum scratch_acc_change_info_bits_def
{
2442 ATOM_ACC_CHANGE_ACC_MODE
=0x00000010,
2443 ATOM_ACC_CHANGE_LID_STATUS
=0x00000040,
2446 enum scratch_pre_os_mode_info_bits_def
{
2447 ATOM_PRE_OS_MODE_MASK
=0x00000003,
2448 ATOM_PRE_OS_MODE_VGA
=0x00000000,
2449 ATOM_PRE_OS_MODE_VESA
=0x00000001,
2450 ATOM_PRE_OS_MODE_GOP
=0x00000002,
2451 ATOM_PRE_OS_MODE_PIXEL_DEPTH
=0x0000000C,
2452 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK
=0x000000F0,
2453 ATOM_PRE_OS_MODE_8BIT_PAL_EN
=0x00000100,
2454 ATOM_ASIC_INIT_COMPLETE
=0x00000200,
2456 ATOM_PRE_OS_MODE_NUMBER_MASK
=0xFFFF0000,
2463 ***************************************************************************
2464 ATOM firmware ID header file
2465 !! Please keep it at end of the atomfirmware.h !!
2466 ***************************************************************************
2468 #include "atomfirmwareid.h"