2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
30 * enum cgs_gpu_mem_type - GPU memory types
32 enum cgs_gpu_mem_type
{
33 CGS_GPU_MEM_TYPE__VISIBLE_FB
,
34 CGS_GPU_MEM_TYPE__INVISIBLE_FB
,
35 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB
,
36 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB
,
37 CGS_GPU_MEM_TYPE__GART_CACHEABLE
,
38 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
42 * enum cgs_ind_reg - Indirect register spaces
50 CGS_IND_REG__AUDIO_ENDPT
54 * enum cgs_clock - Clocks controlled by the SMU
68 * enum cgs_engine - Engines that can be statically power-gated
82 * enum cgs_voltage_planes - Voltage planes for external camera HW
84 enum cgs_voltage_planes
{
85 CGS_VOLTAGE_PLANE__SENSOR0
,
86 CGS_VOLTAGE_PLANE__SENSOR1
,
91 * enum cgs_ucode_id - Firmware types for different IPs
101 CGS_UCODE_ID_CP_MEC_JT1
,
102 CGS_UCODE_ID_CP_MEC_JT2
,
103 CGS_UCODE_ID_GMCON_RENG
,
105 CGS_UCODE_ID_MAXIMUM
,
108 enum cgs_system_info_id
{
109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID
= 1,
110 CGS_SYSTEM_INFO_PCIE_GEN_INFO
,
111 CGS_SYSTEM_INFO_PCIE_MLW
,
112 CGS_SYSTEM_INFO_CG_FLAGS
,
113 CGS_SYSTEM_INFO_PG_FLAGS
,
114 CGS_SYSTEM_INFO_ID_MAXIMUM
,
117 struct cgs_system_info
{
124 uint64_t padding
[13];
128 * enum cgs_resource_type - GPU resource type
130 enum cgs_resource_type
{
131 CGS_RESOURCE_TYPE_MMIO
= 0,
132 CGS_RESOURCE_TYPE_FB
,
133 CGS_RESOURCE_TYPE_IO
,
134 CGS_RESOURCE_TYPE_DOORBELL
,
135 CGS_RESOURCE_TYPE_ROM
,
139 * struct cgs_clock_limits - Clock limits
141 * Clocks are specified in 10KHz units.
143 struct cgs_clock_limits
{
144 unsigned min
; /**< Minimum supported frequency */
145 unsigned max
; /**< Maxumim supported frequency */
146 unsigned sustainable
; /**< Thermally sustainable frequency */
150 * struct cgs_firmware_info - Firmware information
152 struct cgs_firmware_info
{
154 uint16_t feature_version
;
160 struct cgs_mode_info
{
161 uint32_t refresh_rate
;
163 uint32_t vblank_time_us
;
166 struct cgs_display_info
{
167 uint32_t display_count
;
168 uint32_t active_display_mask
;
169 struct cgs_mode_info
*mode_info
;
172 typedef unsigned long cgs_handle_t
;
174 #define CGS_ACPI_METHOD_ATCS 0x53435441
175 #define CGS_ACPI_METHOD_ATIF 0x46495441
176 #define CGS_ACPI_METHOD_ATPX 0x58505441
177 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
178 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
179 #define CGS_ACPI_MAX_BUFFER_SIZE 256
180 #define CGS_ACPI_TYPE_ANY 0x00
181 #define CGS_ACPI_TYPE_INTEGER 0x01
182 #define CGS_ACPI_TYPE_STRING 0x02
183 #define CGS_ACPI_TYPE_BUFFER 0x03
184 #define CGS_ACPI_TYPE_PACKAGE 0x04
186 struct cgs_acpi_method_argument
{
188 uint32_t method_length
;
189 uint32_t data_length
;
196 struct cgs_acpi_method_info
{
199 uint32_t input_count
;
201 struct cgs_acpi_method_argument
*pinput_argument
;
202 uint32_t output_count
;
203 struct cgs_acpi_method_argument
*poutput_argument
;
208 * cgs_gpu_mem_info() - Return information about memory heaps
209 * @cgs_device: opaque device handle
211 * @mc_start: Start MC address of the heap (output)
212 * @mc_size: MC address space size (output)
213 * @mem_size: maximum amount of memory available for allocation (output)
215 * This function returns information about memory heaps. The type
216 * parameter is used to select the memory heap. The mc_start and
217 * mc_size for GART heaps may be bigger than the memory available for
220 * mc_start and mc_size are undefined for non-contiguous FB memory
221 * types, since buffers allocated with these types may or may not be
224 * Return: 0 on success, -errno otherwise
226 typedef int (*cgs_gpu_mem_info_t
)(void *cgs_device
, enum cgs_gpu_mem_type type
,
227 uint64_t *mc_start
, uint64_t *mc_size
,
231 * cgs_gmap_kmem() - map kernel memory to GART aperture
232 * @cgs_device: opaque device handle
233 * @kmem: pointer to kernel memory
235 * @min_offset: minimum offset from start of GART aperture
236 * @max_offset: maximum offset from start of GART aperture
237 * @kmem_handle: kernel memory handle (output)
238 * @mcaddr: MC address (output)
240 * Return: 0 on success, -errno otherwise
242 typedef int (*cgs_gmap_kmem_t
)(void *cgs_device
, void *kmem
, uint64_t size
,
243 uint64_t min_offset
, uint64_t max_offset
,
244 cgs_handle_t
*kmem_handle
, uint64_t *mcaddr
);
247 * cgs_gunmap_kmem() - unmap kernel memory
248 * @cgs_device: opaque device handle
249 * @kmem_handle: kernel memory handle returned by gmap_kmem
251 * Return: 0 on success, -errno otherwise
253 typedef int (*cgs_gunmap_kmem_t
)(void *cgs_device
, cgs_handle_t kmem_handle
);
256 * cgs_alloc_gpu_mem() - Allocate GPU memory
257 * @cgs_device: opaque device handle
259 * @size: size in bytes
260 * @align: alignment in bytes
261 * @min_offset: minimum offset from start of heap
262 * @max_offset: maximum offset from start of heap
263 * @handle: memory handle (output)
265 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
266 * memory allocation. This guarantees that the MC address returned by
267 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
268 * FB memory types may be GART mapped depending on memory
269 * fragmentation and memory allocator policies.
271 * If min/max_offset are non-0, the allocation will be forced to
272 * reside between these offsets in its respective memory heap. The
273 * base address that the offset relates to, depends on the memory
276 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
277 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
278 * - others: undefined, don't use with max_offset
280 * Return: 0 on success, -errno otherwise
282 typedef int (*cgs_alloc_gpu_mem_t
)(void *cgs_device
, enum cgs_gpu_mem_type type
,
283 uint64_t size
, uint64_t align
,
284 uint64_t min_offset
, uint64_t max_offset
,
285 cgs_handle_t
*handle
);
288 * cgs_free_gpu_mem() - Free GPU memory
289 * @cgs_device: opaque device handle
290 * @handle: memory handle returned by alloc or import
292 * Return: 0 on success, -errno otherwise
294 typedef int (*cgs_free_gpu_mem_t
)(void *cgs_device
, cgs_handle_t handle
);
297 * cgs_gmap_gpu_mem() - GPU-map GPU memory
298 * @cgs_device: opaque device handle
299 * @handle: memory handle returned by alloc or import
300 * @mcaddr: MC address (output)
302 * Ensures that a buffer is GPU accessible and returns its MC address.
304 * Return: 0 on success, -errno otherwise
306 typedef int (*cgs_gmap_gpu_mem_t
)(void *cgs_device
, cgs_handle_t handle
,
310 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
311 * @cgs_device: opaque device handle
312 * @handle: memory handle returned by alloc or import
314 * Allows the buffer to be migrated while it's not used by the GPU.
316 * Return: 0 on success, -errno otherwise
318 typedef int (*cgs_gunmap_gpu_mem_t
)(void *cgs_device
, cgs_handle_t handle
);
321 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
323 * @cgs_device: opaque device handle
324 * @handle: memory handle returned by alloc or import
325 * @map: Kernel virtual address the memory was mapped to (output)
327 * Return: 0 on success, -errno otherwise
329 typedef int (*cgs_kmap_gpu_mem_t
)(void *cgs_device
, cgs_handle_t handle
,
333 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
334 * @cgs_device: opaque device handle
335 * @handle: memory handle returned by alloc or import
337 * Return: 0 on success, -errno otherwise
339 typedef int (*cgs_kunmap_gpu_mem_t
)(void *cgs_device
, cgs_handle_t handle
);
342 * cgs_read_register() - Read an MMIO register
343 * @cgs_device: opaque device handle
344 * @offset: register offset
346 * Return: register value
348 typedef uint32_t (*cgs_read_register_t
)(void *cgs_device
, unsigned offset
);
351 * cgs_write_register() - Write an MMIO register
352 * @cgs_device: opaque device handle
353 * @offset: register offset
354 * @value: register value
356 typedef void (*cgs_write_register_t
)(void *cgs_device
, unsigned offset
,
360 * cgs_read_ind_register() - Read an indirect register
361 * @cgs_device: opaque device handle
362 * @offset: register offset
364 * Return: register value
366 typedef uint32_t (*cgs_read_ind_register_t
)(void *cgs_device
, enum cgs_ind_reg space
,
370 * cgs_write_ind_register() - Write an indirect register
371 * @cgs_device: opaque device handle
372 * @offset: register offset
373 * @value: register value
375 typedef void (*cgs_write_ind_register_t
)(void *cgs_device
, enum cgs_ind_reg space
,
376 unsigned index
, uint32_t value
);
379 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
380 * @cgs_device: opaque device handle
385 typedef uint8_t (*cgs_read_pci_config_byte_t
)(void *cgs_device
, unsigned addr
);
388 * cgs_read_pci_config_word() - Read word from PCI configuration space
389 * @cgs_device: opaque device handle
390 * @addr: address, must be word-aligned
394 typedef uint16_t (*cgs_read_pci_config_word_t
)(void *cgs_device
, unsigned addr
);
397 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
398 * @cgs_device: opaque device handle
399 * @addr: address, must be dword-aligned
403 typedef uint32_t (*cgs_read_pci_config_dword_t
)(void *cgs_device
,
407 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
408 * @cgs_device: opaque device handle
410 * @value: value to write
412 typedef void (*cgs_write_pci_config_byte_t
)(void *cgs_device
, unsigned addr
,
416 * cgs_write_pci_config_word() - Write byte to PCI configuration space
417 * @cgs_device: opaque device handle
418 * @addr: address, must be word-aligned
419 * @value: value to write
421 typedef void (*cgs_write_pci_config_word_t
)(void *cgs_device
, unsigned addr
,
425 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
426 * @cgs_device: opaque device handle
427 * @addr: address, must be dword-aligned
428 * @value: value to write
430 typedef void (*cgs_write_pci_config_dword_t
)(void *cgs_device
, unsigned addr
,
435 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
436 * @cgs_device: opaque device handle
437 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
438 * @size: size of the region
439 * @offset: offset from the start of the region
440 * @resource_base: base address (not including offset) returned
442 * Return: 0 on success, -errno otherwise
444 typedef int (*cgs_get_pci_resource_t
)(void *cgs_device
,
445 enum cgs_resource_type resource_type
,
448 uint64_t *resource_base
);
451 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
452 * @cgs_device: opaque device handle
453 * @table: data table index
454 * @size: size of the table (output, may be NULL)
455 * @frev: table format revision (output, may be NULL)
456 * @crev: table content revision (output, may be NULL)
458 * Return: Pointer to start of the table, or NULL on failure
460 typedef const void *(*cgs_atom_get_data_table_t
)(
461 void *cgs_device
, unsigned table
,
462 uint16_t *size
, uint8_t *frev
, uint8_t *crev
);
465 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
466 * @cgs_device: opaque device handle
467 * @table: data table index
468 * @frev: table format revision (output, may be NULL)
469 * @crev: table content revision (output, may be NULL)
471 * Return: 0 on success, -errno otherwise
473 typedef int (*cgs_atom_get_cmd_table_revs_t
)(void *cgs_device
, unsigned table
,
474 uint8_t *frev
, uint8_t *crev
);
477 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
478 * @cgs_device: opaque device handle
479 * @table: command table index
482 * Return: 0 on success, -errno otherwise
484 typedef int (*cgs_atom_exec_cmd_table_t
)(void *cgs_device
,
485 unsigned table
, void *args
);
488 * cgs_create_pm_request() - Create a power management request
489 * @cgs_device: opaque device handle
490 * @request: handle of created PM request (output)
492 * Return: 0 on success, -errno otherwise
494 typedef int (*cgs_create_pm_request_t
)(void *cgs_device
, cgs_handle_t
*request
);
497 * cgs_destroy_pm_request() - Destroy a power management request
498 * @cgs_device: opaque device handle
499 * @request: handle of created PM request
501 * Return: 0 on success, -errno otherwise
503 typedef int (*cgs_destroy_pm_request_t
)(void *cgs_device
, cgs_handle_t request
);
506 * cgs_set_pm_request() - Activate or deactiveate a PM request
507 * @cgs_device: opaque device handle
508 * @request: PM request handle
509 * @active: 0 = deactivate, non-0 = activate
511 * While a PM request is active, its minimum clock requests are taken
512 * into account as the requested engines are powered up. When the
513 * request is inactive, the engines may be powered down and clocks may
514 * be lower, depending on other PM requests by other driver
517 * Return: 0 on success, -errno otherwise
519 typedef int (*cgs_set_pm_request_t
)(void *cgs_device
, cgs_handle_t request
,
523 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
524 * @cgs_device: opaque device handle
525 * @request: PM request handle
526 * @clock: which clock?
527 * @freq: requested min. frequency in 10KHz units (0 to clear request)
529 * Return: 0 on success, -errno otherwise
531 typedef int (*cgs_pm_request_clock_t
)(void *cgs_device
, cgs_handle_t request
,
532 enum cgs_clock clock
, unsigned freq
);
535 * cgs_pm_request_engine() - Request an engine to be powered up
536 * @cgs_device: opaque device handle
537 * @request: PM request handle
538 * @engine: which engine?
539 * @powered: 0 = powered down, non-0 = powered up
541 * Return: 0 on success, -errno otherwise
543 typedef int (*cgs_pm_request_engine_t
)(void *cgs_device
, cgs_handle_t request
,
544 enum cgs_engine engine
, int powered
);
547 * cgs_pm_query_clock_limits() - Query clock frequency limits
548 * @cgs_device: opaque device handle
549 * @clock: which clock?
550 * @limits: clock limits
552 * Return: 0 on success, -errno otherwise
554 typedef int (*cgs_pm_query_clock_limits_t
)(void *cgs_device
,
555 enum cgs_clock clock
,
556 struct cgs_clock_limits
*limits
);
559 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
560 * @cgs_device: opaque device handle
561 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
562 * @voltages: pointer to array of voltage values in 1mV units
564 * Return: 0 on success, -errno otherwise
566 typedef int (*cgs_set_camera_voltages_t
)(void *cgs_device
, uint32_t mask
,
567 const uint32_t *voltages
);
569 * cgs_get_firmware_info - Get the firmware information from core driver
570 * @cgs_device: opaque device handle
571 * @type: the firmware type
572 * @info: returend firmware information
574 * Return: 0 on success, -errno otherwise
576 typedef int (*cgs_get_firmware_info
)(void *cgs_device
,
577 enum cgs_ucode_id type
,
578 struct cgs_firmware_info
*info
);
580 typedef int(*cgs_set_powergating_state
)(void *cgs_device
,
581 enum amd_ip_block_type block_type
,
582 enum amd_powergating_state state
);
584 typedef int(*cgs_set_clockgating_state
)(void *cgs_device
,
585 enum amd_ip_block_type block_type
,
586 enum amd_clockgating_state state
);
588 typedef int(*cgs_get_active_displays_info
)(
590 struct cgs_display_info
*info
);
592 typedef int (*cgs_notify_dpm_enabled
)(void *cgs_device
, bool enabled
);
594 typedef int (*cgs_call_acpi_method
)(void *cgs_device
,
595 uint32_t acpi_method
,
596 uint32_t acpi_function
,
597 void *pinput
, void *poutput
,
598 uint32_t output_count
,
600 uint32_t output_size
);
602 typedef int (*cgs_query_system_info
)(void *cgs_device
,
603 struct cgs_system_info
*sys_info
);
606 /* memory management calls (similar to KFD interface) */
607 cgs_gpu_mem_info_t gpu_mem_info
;
608 cgs_gmap_kmem_t gmap_kmem
;
609 cgs_gunmap_kmem_t gunmap_kmem
;
610 cgs_alloc_gpu_mem_t alloc_gpu_mem
;
611 cgs_free_gpu_mem_t free_gpu_mem
;
612 cgs_gmap_gpu_mem_t gmap_gpu_mem
;
613 cgs_gunmap_gpu_mem_t gunmap_gpu_mem
;
614 cgs_kmap_gpu_mem_t kmap_gpu_mem
;
615 cgs_kunmap_gpu_mem_t kunmap_gpu_mem
;
617 cgs_read_register_t read_register
;
618 cgs_write_register_t write_register
;
619 cgs_read_ind_register_t read_ind_register
;
620 cgs_write_ind_register_t write_ind_register
;
621 /* PCI configuration space access */
622 cgs_read_pci_config_byte_t read_pci_config_byte
;
623 cgs_read_pci_config_word_t read_pci_config_word
;
624 cgs_read_pci_config_dword_t read_pci_config_dword
;
625 cgs_write_pci_config_byte_t write_pci_config_byte
;
626 cgs_write_pci_config_word_t write_pci_config_word
;
627 cgs_write_pci_config_dword_t write_pci_config_dword
;
629 cgs_get_pci_resource_t get_pci_resource
;
631 cgs_atom_get_data_table_t atom_get_data_table
;
632 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs
;
633 cgs_atom_exec_cmd_table_t atom_exec_cmd_table
;
634 /* Power management */
635 cgs_create_pm_request_t create_pm_request
;
636 cgs_destroy_pm_request_t destroy_pm_request
;
637 cgs_set_pm_request_t set_pm_request
;
638 cgs_pm_request_clock_t pm_request_clock
;
639 cgs_pm_request_engine_t pm_request_engine
;
640 cgs_pm_query_clock_limits_t pm_query_clock_limits
;
641 cgs_set_camera_voltages_t set_camera_voltages
;
643 cgs_get_firmware_info get_firmware_info
;
645 cgs_set_powergating_state set_powergating_state
;
646 cgs_set_clockgating_state set_clockgating_state
;
647 /* display manager */
648 cgs_get_active_displays_info get_active_displays_info
;
649 /* notify dpm enabled */
650 cgs_notify_dpm_enabled notify_dpm_enabled
;
652 cgs_call_acpi_method call_acpi_method
;
653 /* get system info */
654 cgs_query_system_info query_system_info
;
657 struct cgs_os_ops
; /* To be define in OS-specific CGS header */
661 const struct cgs_ops
*ops
;
662 const struct cgs_os_ops
*os_ops
;
663 /* to be embedded at the start of driver private structure */
666 /* Convenience macros that make CGS indirect function calls look like
667 * normal function calls */
668 #define CGS_CALL(func,dev,...) \
669 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
670 #define CGS_OS_CALL(func,dev,...) \
671 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
673 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
674 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
675 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
676 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
677 #define cgs_gunmap_kmem(dev,kmem_handle) \
678 CGS_CALL(gunmap_kmem,dev,keme_handle)
679 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
680 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
681 #define cgs_free_gpu_mem(dev,handle) \
682 CGS_CALL(free_gpu_mem,dev,handle)
683 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
684 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
685 #define cgs_gunmap_gpu_mem(dev,handle) \
686 CGS_CALL(gunmap_gpu_mem,dev,handle)
687 #define cgs_kmap_gpu_mem(dev,handle,map) \
688 CGS_CALL(kmap_gpu_mem,dev,handle,map)
689 #define cgs_kunmap_gpu_mem(dev,handle) \
690 CGS_CALL(kunmap_gpu_mem,dev,handle)
692 #define cgs_read_register(dev,offset) \
693 CGS_CALL(read_register,dev,offset)
694 #define cgs_write_register(dev,offset,value) \
695 CGS_CALL(write_register,dev,offset,value)
696 #define cgs_read_ind_register(dev,space,index) \
697 CGS_CALL(read_ind_register,dev,space,index)
698 #define cgs_write_ind_register(dev,space,index,value) \
699 CGS_CALL(write_ind_register,dev,space,index,value)
701 #define cgs_read_pci_config_byte(dev,addr) \
702 CGS_CALL(read_pci_config_byte,dev,addr)
703 #define cgs_read_pci_config_word(dev,addr) \
704 CGS_CALL(read_pci_config_word,dev,addr)
705 #define cgs_read_pci_config_dword(dev,addr) \
706 CGS_CALL(read_pci_config_dword,dev,addr)
707 #define cgs_write_pci_config_byte(dev,addr,value) \
708 CGS_CALL(write_pci_config_byte,dev,addr,value)
709 #define cgs_write_pci_config_word(dev,addr,value) \
710 CGS_CALL(write_pci_config_word,dev,addr,value)
711 #define cgs_write_pci_config_dword(dev,addr,value) \
712 CGS_CALL(write_pci_config_dword,dev,addr,value)
714 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \
715 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
716 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
717 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
718 #define cgs_atom_exec_cmd_table(dev,table,args) \
719 CGS_CALL(atom_exec_cmd_table,dev,table,args)
721 #define cgs_create_pm_request(dev,request) \
722 CGS_CALL(create_pm_request,dev,request)
723 #define cgs_destroy_pm_request(dev,request) \
724 CGS_CALL(destroy_pm_request,dev,request)
725 #define cgs_set_pm_request(dev,request,active) \
726 CGS_CALL(set_pm_request,dev,request,active)
727 #define cgs_pm_request_clock(dev,request,clock,freq) \
728 CGS_CALL(pm_request_clock,dev,request,clock,freq)
729 #define cgs_pm_request_engine(dev,request,engine,powered) \
730 CGS_CALL(pm_request_engine,dev,request,engine,powered)
731 #define cgs_pm_query_clock_limits(dev,clock,limits) \
732 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
733 #define cgs_set_camera_voltages(dev,mask,voltages) \
734 CGS_CALL(set_camera_voltages,dev,mask,voltages)
735 #define cgs_get_firmware_info(dev, type, info) \
736 CGS_CALL(get_firmware_info, dev, type, info)
737 #define cgs_set_powergating_state(dev, block_type, state) \
738 CGS_CALL(set_powergating_state, dev, block_type, state)
739 #define cgs_set_clockgating_state(dev, block_type, state) \
740 CGS_CALL(set_clockgating_state, dev, block_type, state)
741 #define cgs_notify_dpm_enabled(dev, enabled) \
742 CGS_CALL(notify_dpm_enabled, dev, enabled)
744 #define cgs_get_active_displays_info(dev, info) \
745 CGS_CALL(get_active_displays_info, dev, info)
747 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
748 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
749 #define cgs_query_system_info(dev, sys_info) \
750 CGS_CALL(query_system_info, dev, sys_info)
751 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
753 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
756 #endif /* _CGS_COMMON_H */