]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:


cfcac110ed84db710acf4636405b07a5ee2b82d4
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / pm / swsmu / amdgpu_smu.c
1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_smu.h"
30 #include "smu_internal.h"
31 #include "atom.h"
32 #include "arcturus_ppt.h"
33 #include "navi10_ppt.h"
34 #include "sienna_cichlid_ppt.h"
35 #include "renoir_ppt.h"
36 #include "vangogh_ppt.h"
37 #include "aldebaran_ppt.h"
38 #include "amd_pcie.h"
39
40 /*
41 * DO NOT use these for err/warn/info/debug messages.
42 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
43 * They are more MGPU friendly.
44 */
45 #undef pr_err
46 #undef pr_warn
47 #undef pr_info
48 #undef pr_debug
49
50 static const struct amd_pm_funcs swsmu_pm_funcs;
51 static int smu_force_smuclk_levels(struct smu_context *smu,
52 enum smu_clk_type clk_type,
53 uint32_t mask);
54
55 int smu_sys_get_pp_feature_mask(void *handle, char *buf)
56 {
57 struct smu_context *smu = handle;
58 int size = 0;
59
60 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
61 return -EOPNOTSUPP;
62
63 mutex_lock(&smu->mutex);
64
65 size = smu_get_pp_feature_mask(smu, buf);
66
67 mutex_unlock(&smu->mutex);
68
69 return size;
70 }
71
72 int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask)
73 {
74 struct smu_context *smu = handle;
75 int ret = 0;
76
77 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
78 return -EOPNOTSUPP;
79
80 mutex_lock(&smu->mutex);
81
82 ret = smu_set_pp_feature_mask(smu, new_mask);
83
84 mutex_unlock(&smu->mutex);
85
86 return ret;
87 }
88
89 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
90 {
91 int ret = 0;
92 struct smu_context *smu = &adev->smu;
93
94 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
95 *value = smu_get_gfx_off_status(smu);
96 else
97 ret = -EINVAL;
98
99 return ret;
100 }
101
102 int smu_set_soft_freq_range(struct smu_context *smu,
103 enum smu_clk_type clk_type,
104 uint32_t min,
105 uint32_t max)
106 {
107 int ret = 0;
108
109 mutex_lock(&smu->mutex);
110
111 if (smu->ppt_funcs->set_soft_freq_limited_range)
112 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
113 clk_type,
114 min,
115 max);
116
117 mutex_unlock(&smu->mutex);
118
119 return ret;
120 }
121
122 int smu_get_dpm_freq_range(struct smu_context *smu,
123 enum smu_clk_type clk_type,
124 uint32_t *min,
125 uint32_t *max)
126 {
127 int ret = 0;
128
129 if (!min && !max)
130 return -EINVAL;
131
132 mutex_lock(&smu->mutex);
133
134 if (smu->ppt_funcs->get_dpm_ultimate_freq)
135 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
136 clk_type,
137 min,
138 max);
139
140 mutex_unlock(&smu->mutex);
141
142 return ret;
143 }
144
145 u32 smu_get_mclk(void *handle, bool low)
146 {
147 struct smu_context *smu = handle;
148 uint32_t clk_freq;
149 int ret = 0;
150
151 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
152 low ? &clk_freq : NULL,
153 !low ? &clk_freq : NULL);
154 if (ret)
155 return 0;
156 return clk_freq * 100;
157 }
158
159 u32 smu_get_sclk(void *handle, bool low)
160 {
161 struct smu_context *smu = handle;
162 uint32_t clk_freq;
163 int ret = 0;
164
165 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
166 low ? &clk_freq : NULL,
167 !low ? &clk_freq : NULL);
168 if (ret)
169 return 0;
170 return clk_freq * 100;
171 }
172
173 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
174 bool enable)
175 {
176 struct smu_power_context *smu_power = &smu->smu_power;
177 struct smu_power_gate *power_gate = &smu_power->power_gate;
178 int ret = 0;
179
180 if (!smu->ppt_funcs->dpm_set_vcn_enable)
181 return 0;
182
183 if (atomic_read(&power_gate->vcn_gated) ^ enable)
184 return 0;
185
186 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
187 if (!ret)
188 atomic_set(&power_gate->vcn_gated, !enable);
189
190 return ret;
191 }
192
193 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
194 bool enable)
195 {
196 struct smu_power_context *smu_power = &smu->smu_power;
197 struct smu_power_gate *power_gate = &smu_power->power_gate;
198 int ret = 0;
199
200 mutex_lock(&power_gate->vcn_gate_lock);
201
202 ret = smu_dpm_set_vcn_enable_locked(smu, enable);
203
204 mutex_unlock(&power_gate->vcn_gate_lock);
205
206 return ret;
207 }
208
209 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
210 bool enable)
211 {
212 struct smu_power_context *smu_power = &smu->smu_power;
213 struct smu_power_gate *power_gate = &smu_power->power_gate;
214 int ret = 0;
215
216 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
217 return 0;
218
219 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
220 return 0;
221
222 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
223 if (!ret)
224 atomic_set(&power_gate->jpeg_gated, !enable);
225
226 return ret;
227 }
228
229 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
230 bool enable)
231 {
232 struct smu_power_context *smu_power = &smu->smu_power;
233 struct smu_power_gate *power_gate = &smu_power->power_gate;
234 int ret = 0;
235
236 mutex_lock(&power_gate->jpeg_gate_lock);
237
238 ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
239
240 mutex_unlock(&power_gate->jpeg_gate_lock);
241
242 return ret;
243 }
244
245 /**
246 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
247 *
248 * @handle: smu_context pointer
249 * @block_type: the IP block to power gate/ungate
250 * @gate: to power gate if true, ungate otherwise
251 *
252 * This API uses no smu->mutex lock protection due to:
253 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
254 * This is guarded to be race condition free by the caller.
255 * 2. Or get called on user setting request of power_dpm_force_performance_level.
256 * Under this case, the smu->mutex lock protection is already enforced on
257 * the parent API smu_force_performance_level of the call path.
258 */
259 int smu_dpm_set_power_gate(void *handle, uint32_t block_type,
260 bool gate)
261 {
262 struct smu_context *smu = handle;
263 int ret = 0;
264
265 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
266 return -EOPNOTSUPP;
267
268 switch (block_type) {
269 /*
270 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
271 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
272 */
273 case AMD_IP_BLOCK_TYPE_UVD:
274 case AMD_IP_BLOCK_TYPE_VCN:
275 ret = smu_dpm_set_vcn_enable(smu, !gate);
276 if (ret)
277 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
278 gate ? "gate" : "ungate");
279 break;
280 case AMD_IP_BLOCK_TYPE_GFX:
281 ret = smu_gfx_off_control(smu, gate);
282 if (ret)
283 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
284 gate ? "enable" : "disable");
285 break;
286 case AMD_IP_BLOCK_TYPE_SDMA:
287 ret = smu_powergate_sdma(smu, gate);
288 if (ret)
289 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
290 gate ? "gate" : "ungate");
291 break;
292 case AMD_IP_BLOCK_TYPE_JPEG:
293 ret = smu_dpm_set_jpeg_enable(smu, !gate);
294 if (ret)
295 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
296 gate ? "gate" : "ungate");
297 break;
298 default:
299 dev_err(smu->adev->dev, "Unsupported block type!\n");
300 return -EINVAL;
301 }
302
303 return ret;
304 }
305
306 /**
307 * smu_set_user_clk_dependencies - set user profile clock dependencies
308 *
309 * @smu: smu_context pointer
310 * @clk: enum smu_clk_type type
311 *
312 * Enable/Disable the clock dependency for the @clk type.
313 */
314 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
315 {
316 if (smu->adev->in_suspend)
317 return;
318
319 if (clk == SMU_MCLK) {
320 smu->user_dpm_profile.clk_dependency = 0;
321 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
322 } else if (clk == SMU_FCLK) {
323 /* MCLK takes precedence over FCLK */
324 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
325 return;
326
327 smu->user_dpm_profile.clk_dependency = 0;
328 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
329 } else if (clk == SMU_SOCCLK) {
330 /* MCLK takes precedence over SOCCLK */
331 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
332 return;
333
334 smu->user_dpm_profile.clk_dependency = 0;
335 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
336 } else
337 /* Add clk dependencies here, if any */
338 return;
339 }
340
341 /**
342 * smu_restore_dpm_user_profile - reinstate user dpm profile
343 *
344 * @smu: smu_context pointer
345 *
346 * Restore the saved user power configurations include power limit,
347 * clock frequencies, fan control mode and fan speed.
348 */
349 static void smu_restore_dpm_user_profile(struct smu_context *smu)
350 {
351 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
352 int ret = 0;
353
354 if (!smu->adev->in_suspend)
355 return;
356
357 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
358 return;
359
360 /* Enable restore flag */
361 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
362
363 /* set the user dpm power limit */
364 if (smu->user_dpm_profile.power_limit) {
365 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
366 if (ret)
367 dev_err(smu->adev->dev, "Failed to set power limit value\n");
368 }
369
370 /* set the user dpm clock configurations */
371 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
372 enum smu_clk_type clk_type;
373
374 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
375 /*
376 * Iterate over smu clk type and force the saved user clk
377 * configs, skip if clock dependency is enabled
378 */
379 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
380 smu->user_dpm_profile.clk_mask[clk_type]) {
381 ret = smu_force_smuclk_levels(smu, clk_type,
382 smu->user_dpm_profile.clk_mask[clk_type]);
383 if (ret)
384 dev_err(smu->adev->dev,
385 "Failed to set clock type = %d\n", clk_type);
386 }
387 }
388 }
389
390 /* set the user dpm fan configurations */
391 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) {
392 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
393 if (ret) {
394 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
395 return;
396 }
397
398 if (!ret && smu->user_dpm_profile.fan_speed_percent) {
399 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent);
400 if (ret)
401 dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
402 }
403 }
404
405 /* Disable restore flag */
406 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
407 }
408
409 int smu_get_power_num_states(void *handle,
410 struct pp_states_info *state_info)
411 {
412 if (!state_info)
413 return -EINVAL;
414
415 /* not support power state */
416 memset(state_info, 0, sizeof(struct pp_states_info));
417 state_info->nums = 1;
418 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
419
420 return 0;
421 }
422
423 bool is_support_sw_smu(struct amdgpu_device *adev)
424 {
425 if (adev->asic_type >= CHIP_ARCTURUS)
426 return true;
427
428 return false;
429 }
430
431 bool is_support_cclk_dpm(struct amdgpu_device *adev)
432 {
433 struct smu_context *smu = &adev->smu;
434
435 if (!is_support_sw_smu(adev))
436 return false;
437
438 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
439 return false;
440
441 return true;
442 }
443
444
445 int smu_sys_get_pp_table(void *handle, char **table)
446 {
447 struct smu_context *smu = handle;
448 struct smu_table_context *smu_table = &smu->smu_table;
449 uint32_t powerplay_table_size;
450
451 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
452 return -EOPNOTSUPP;
453
454 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
455 return -EINVAL;
456
457 mutex_lock(&smu->mutex);
458
459 if (smu_table->hardcode_pptable)
460 *table = smu_table->hardcode_pptable;
461 else
462 *table = smu_table->power_play_table;
463
464 powerplay_table_size = smu_table->power_play_table_size;
465
466 mutex_unlock(&smu->mutex);
467
468 return powerplay_table_size;
469 }
470
471 int smu_sys_set_pp_table(void *handle, const char *buf, size_t size)
472 {
473 struct smu_context *smu = handle;
474 struct smu_table_context *smu_table = &smu->smu_table;
475 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
476 int ret = 0;
477
478 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
479 return -EOPNOTSUPP;
480
481 if (header->usStructureSize != size) {
482 dev_err(smu->adev->dev, "pp table size not matched !\n");
483 return -EIO;
484 }
485
486 mutex_lock(&smu->mutex);
487 if (!smu_table->hardcode_pptable)
488 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
489 if (!smu_table->hardcode_pptable) {
490 ret = -ENOMEM;
491 goto failed;
492 }
493
494 memcpy(smu_table->hardcode_pptable, buf, size);
495 smu_table->power_play_table = smu_table->hardcode_pptable;
496 smu_table->power_play_table_size = size;
497
498 /*
499 * Special hw_fini action(for Navi1x, the DPMs disablement will be
500 * skipped) may be needed for custom pptable uploading.
501 */
502 smu->uploading_custom_pp_table = true;
503
504 ret = smu_reset(smu);
505 if (ret)
506 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
507
508 smu->uploading_custom_pp_table = false;
509
510 failed:
511 mutex_unlock(&smu->mutex);
512 return ret;
513 }
514
515 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
516 {
517 struct smu_feature *feature = &smu->smu_feature;
518 int ret = 0;
519 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
520
521 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
522
523 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
524 SMU_FEATURE_MAX/32);
525 if (ret)
526 return ret;
527
528 bitmap_or(feature->allowed, feature->allowed,
529 (unsigned long *)allowed_feature_mask,
530 feature->feature_num);
531
532 return ret;
533 }
534
535 static int smu_set_funcs(struct amdgpu_device *adev)
536 {
537 struct smu_context *smu = &adev->smu;
538
539 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
540 smu->od_enabled = true;
541
542 switch (adev->asic_type) {
543 case CHIP_NAVI10:
544 case CHIP_NAVI14:
545 case CHIP_NAVI12:
546 navi10_set_ppt_funcs(smu);
547 break;
548 case CHIP_ARCTURUS:
549 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
550 arcturus_set_ppt_funcs(smu);
551 /* OD is not supported on Arcturus */
552 smu->od_enabled =false;
553 break;
554 case CHIP_SIENNA_CICHLID:
555 case CHIP_NAVY_FLOUNDER:
556 case CHIP_DIMGREY_CAVEFISH:
557 sienna_cichlid_set_ppt_funcs(smu);
558 break;
559 case CHIP_ALDEBARAN:
560 aldebaran_set_ppt_funcs(smu);
561 /* Enable pp_od_clk_voltage node */
562 smu->od_enabled = true;
563 break;
564 case CHIP_RENOIR:
565 renoir_set_ppt_funcs(smu);
566 break;
567 case CHIP_VANGOGH:
568 vangogh_set_ppt_funcs(smu);
569 break;
570 default:
571 return -EINVAL;
572 }
573
574 return 0;
575 }
576
577 static int smu_early_init(void *handle)
578 {
579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
580 struct smu_context *smu = &adev->smu;
581
582 smu->adev = adev;
583 smu->pm_enabled = !!amdgpu_dpm;
584 smu->is_apu = false;
585 mutex_init(&smu->mutex);
586 mutex_init(&smu->smu_baco.mutex);
587 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
588 smu->smu_baco.platform_support = false;
589
590 adev->powerplay.pp_handle = smu;
591 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
592
593 return smu_set_funcs(adev);
594 }
595
596 static int smu_set_default_dpm_table(struct smu_context *smu)
597 {
598 struct smu_power_context *smu_power = &smu->smu_power;
599 struct smu_power_gate *power_gate = &smu_power->power_gate;
600 int vcn_gate, jpeg_gate;
601 int ret = 0;
602
603 if (!smu->ppt_funcs->set_default_dpm_table)
604 return 0;
605
606 mutex_lock(&power_gate->vcn_gate_lock);
607 mutex_lock(&power_gate->jpeg_gate_lock);
608
609 vcn_gate = atomic_read(&power_gate->vcn_gated);
610 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
611
612 ret = smu_dpm_set_vcn_enable_locked(smu, true);
613 if (ret)
614 goto err0_out;
615
616 ret = smu_dpm_set_jpeg_enable_locked(smu, true);
617 if (ret)
618 goto err1_out;
619
620 ret = smu->ppt_funcs->set_default_dpm_table(smu);
621 if (ret)
622 dev_err(smu->adev->dev,
623 "Failed to setup default dpm clock tables!\n");
624
625 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
626 err1_out:
627 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
628 err0_out:
629 mutex_unlock(&power_gate->jpeg_gate_lock);
630 mutex_unlock(&power_gate->vcn_gate_lock);
631
632 return ret;
633 }
634
635 static int smu_late_init(void *handle)
636 {
637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
638 struct smu_context *smu = &adev->smu;
639 int ret = 0;
640
641 smu_set_fine_grain_gfx_freq_parameters(smu);
642
643 if (!smu->pm_enabled)
644 return 0;
645
646 ret = smu_post_init(smu);
647 if (ret) {
648 dev_err(adev->dev, "Failed to post smu init!\n");
649 return ret;
650 }
651
652 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
653 ret = smu_set_default_od_settings(smu);
654 if (ret) {
655 dev_err(adev->dev, "Failed to setup default OD settings!\n");
656 return ret;
657 }
658 }
659
660 ret = smu_populate_umd_state_clk(smu);
661 if (ret) {
662 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
663 return ret;
664 }
665
666 ret = smu_get_asic_power_limits(smu);
667 if (ret) {
668 dev_err(adev->dev, "Failed to get asic power limits!\n");
669 return ret;
670 }
671
672 smu_get_unique_id(smu);
673
674 smu_get_fan_parameters(smu);
675
676 smu_handle_task(&adev->smu,
677 smu->smu_dpm.dpm_level,
678 AMD_PP_TASK_COMPLETE_INIT,
679 false);
680
681 smu_restore_dpm_user_profile(smu);
682
683 return 0;
684 }
685
686 static int smu_init_fb_allocations(struct smu_context *smu)
687 {
688 struct amdgpu_device *adev = smu->adev;
689 struct smu_table_context *smu_table = &smu->smu_table;
690 struct smu_table *tables = smu_table->tables;
691 struct smu_table *driver_table = &(smu_table->driver_table);
692 uint32_t max_table_size = 0;
693 int ret, i;
694
695 /* VRAM allocation for tool table */
696 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
697 ret = amdgpu_bo_create_kernel(adev,
698 tables[SMU_TABLE_PMSTATUSLOG].size,
699 tables[SMU_TABLE_PMSTATUSLOG].align,
700 tables[SMU_TABLE_PMSTATUSLOG].domain,
701 &tables[SMU_TABLE_PMSTATUSLOG].bo,
702 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
703 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
704 if (ret) {
705 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
706 return ret;
707 }
708 }
709
710 /* VRAM allocation for driver table */
711 for (i = 0; i < SMU_TABLE_COUNT; i++) {
712 if (tables[i].size == 0)
713 continue;
714
715 if (i == SMU_TABLE_PMSTATUSLOG)
716 continue;
717
718 if (max_table_size < tables[i].size)
719 max_table_size = tables[i].size;
720 }
721
722 driver_table->size = max_table_size;
723 driver_table->align = PAGE_SIZE;
724 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
725
726 ret = amdgpu_bo_create_kernel(adev,
727 driver_table->size,
728 driver_table->align,
729 driver_table->domain,
730 &driver_table->bo,
731 &driver_table->mc_address,
732 &driver_table->cpu_addr);
733 if (ret) {
734 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
735 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
736 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
737 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
738 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
739 }
740
741 return ret;
742 }
743
744 static int smu_fini_fb_allocations(struct smu_context *smu)
745 {
746 struct smu_table_context *smu_table = &smu->smu_table;
747 struct smu_table *tables = smu_table->tables;
748 struct smu_table *driver_table = &(smu_table->driver_table);
749
750 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
751 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
752 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
753 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
754
755 amdgpu_bo_free_kernel(&driver_table->bo,
756 &driver_table->mc_address,
757 &driver_table->cpu_addr);
758
759 return 0;
760 }
761
762 /**
763 * smu_alloc_memory_pool - allocate memory pool in the system memory
764 *
765 * @smu: amdgpu_device pointer
766 *
767 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
768 * and DramLogSetDramAddr can notify it changed.
769 *
770 * Returns 0 on success, error on failure.
771 */
772 static int smu_alloc_memory_pool(struct smu_context *smu)
773 {
774 struct amdgpu_device *adev = smu->adev;
775 struct smu_table_context *smu_table = &smu->smu_table;
776 struct smu_table *memory_pool = &smu_table->memory_pool;
777 uint64_t pool_size = smu->pool_size;
778 int ret = 0;
779
780 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
781 return ret;
782
783 memory_pool->size = pool_size;
784 memory_pool->align = PAGE_SIZE;
785 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
786
787 switch (pool_size) {
788 case SMU_MEMORY_POOL_SIZE_256_MB:
789 case SMU_MEMORY_POOL_SIZE_512_MB:
790 case SMU_MEMORY_POOL_SIZE_1_GB:
791 case SMU_MEMORY_POOL_SIZE_2_GB:
792 ret = amdgpu_bo_create_kernel(adev,
793 memory_pool->size,
794 memory_pool->align,
795 memory_pool->domain,
796 &memory_pool->bo,
797 &memory_pool->mc_address,
798 &memory_pool->cpu_addr);
799 if (ret)
800 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
801 break;
802 default:
803 break;
804 }
805
806 return ret;
807 }
808
809 static int smu_free_memory_pool(struct smu_context *smu)
810 {
811 struct smu_table_context *smu_table = &smu->smu_table;
812 struct smu_table *memory_pool = &smu_table->memory_pool;
813
814 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
815 return 0;
816
817 amdgpu_bo_free_kernel(&memory_pool->bo,
818 &memory_pool->mc_address,
819 &memory_pool->cpu_addr);
820
821 memset(memory_pool, 0, sizeof(struct smu_table));
822
823 return 0;
824 }
825
826 static int smu_alloc_dummy_read_table(struct smu_context *smu)
827 {
828 struct smu_table_context *smu_table = &smu->smu_table;
829 struct smu_table *dummy_read_1_table =
830 &smu_table->dummy_read_1_table;
831 struct amdgpu_device *adev = smu->adev;
832 int ret = 0;
833
834 dummy_read_1_table->size = 0x40000;
835 dummy_read_1_table->align = PAGE_SIZE;
836 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
837
838 ret = amdgpu_bo_create_kernel(adev,
839 dummy_read_1_table->size,
840 dummy_read_1_table->align,
841 dummy_read_1_table->domain,
842 &dummy_read_1_table->bo,
843 &dummy_read_1_table->mc_address,
844 &dummy_read_1_table->cpu_addr);
845 if (ret)
846 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
847
848 return ret;
849 }
850
851 static void smu_free_dummy_read_table(struct smu_context *smu)
852 {
853 struct smu_table_context *smu_table = &smu->smu_table;
854 struct smu_table *dummy_read_1_table =
855 &smu_table->dummy_read_1_table;
856
857
858 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
859 &dummy_read_1_table->mc_address,
860 &dummy_read_1_table->cpu_addr);
861
862 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
863 }
864
865 static int smu_smc_table_sw_init(struct smu_context *smu)
866 {
867 int ret;
868
869 /**
870 * Create smu_table structure, and init smc tables such as
871 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
872 */
873 ret = smu_init_smc_tables(smu);
874 if (ret) {
875 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
876 return ret;
877 }
878
879 /**
880 * Create smu_power_context structure, and allocate smu_dpm_context and
881 * context size to fill the smu_power_context data.
882 */
883 ret = smu_init_power(smu);
884 if (ret) {
885 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
886 return ret;
887 }
888
889 /*
890 * allocate vram bos to store smc table contents.
891 */
892 ret = smu_init_fb_allocations(smu);
893 if (ret)
894 return ret;
895
896 ret = smu_alloc_memory_pool(smu);
897 if (ret)
898 return ret;
899
900 ret = smu_alloc_dummy_read_table(smu);
901 if (ret)
902 return ret;
903
904 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
905 if (ret)
906 return ret;
907
908 return 0;
909 }
910
911 static int smu_smc_table_sw_fini(struct smu_context *smu)
912 {
913 int ret;
914
915 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
916
917 smu_free_dummy_read_table(smu);
918
919 ret = smu_free_memory_pool(smu);
920 if (ret)
921 return ret;
922
923 ret = smu_fini_fb_allocations(smu);
924 if (ret)
925 return ret;
926
927 ret = smu_fini_power(smu);
928 if (ret) {
929 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
930 return ret;
931 }
932
933 ret = smu_fini_smc_tables(smu);
934 if (ret) {
935 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
936 return ret;
937 }
938
939 return 0;
940 }
941
942 static void smu_throttling_logging_work_fn(struct work_struct *work)
943 {
944 struct smu_context *smu = container_of(work, struct smu_context,
945 throttling_logging_work);
946
947 smu_log_thermal_throttling(smu);
948 }
949
950 static void smu_interrupt_work_fn(struct work_struct *work)
951 {
952 struct smu_context *smu = container_of(work, struct smu_context,
953 interrupt_work);
954
955 mutex_lock(&smu->mutex);
956
957 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
958 smu->ppt_funcs->interrupt_work(smu);
959
960 mutex_unlock(&smu->mutex);
961 }
962
963 static int smu_sw_init(void *handle)
964 {
965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
966 struct smu_context *smu = &adev->smu;
967 int ret;
968
969 smu->pool_size = adev->pm.smu_prv_buffer_size;
970 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
971 mutex_init(&smu->smu_feature.mutex);
972 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
973 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
974 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
975
976 mutex_init(&smu->sensor_lock);
977 mutex_init(&smu->metrics_lock);
978 mutex_init(&smu->message_lock);
979
980 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
981 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
982 atomic64_set(&smu->throttle_int_counter, 0);
983 smu->watermarks_bitmap = 0;
984 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
985 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
986
987 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
988 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
989 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
990 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
991
992 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
993 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
994 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
995 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
996 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
997 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
998 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
999 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1000
1001 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1002 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1003 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1004 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1005 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1006 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1007 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1008 smu->display_config = &adev->pm.pm_display_cfg;
1009
1010 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1011 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1012
1013 ret = smu_init_microcode(smu);
1014 if (ret) {
1015 dev_err(adev->dev, "Failed to load smu firmware!\n");
1016 return ret;
1017 }
1018
1019 ret = smu_smc_table_sw_init(smu);
1020 if (ret) {
1021 dev_err(adev->dev, "Failed to sw init smc table!\n");
1022 return ret;
1023 }
1024
1025 ret = smu_register_irq_handler(smu);
1026 if (ret) {
1027 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1028 return ret;
1029 }
1030
1031 /* If there is no way to query fan control mode, fan control is not supported */
1032 if (!smu->ppt_funcs->get_fan_control_mode)
1033 smu->adev->pm.no_fan = true;
1034
1035 return 0;
1036 }
1037
1038 static int smu_sw_fini(void *handle)
1039 {
1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041 struct smu_context *smu = &adev->smu;
1042 int ret;
1043
1044 ret = smu_smc_table_sw_fini(smu);
1045 if (ret) {
1046 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1047 return ret;
1048 }
1049
1050 smu_fini_microcode(smu);
1051
1052 return 0;
1053 }
1054
1055 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1056 {
1057 struct amdgpu_device *adev = smu->adev;
1058 struct smu_temperature_range *range =
1059 &smu->thermal_range;
1060 int ret = 0;
1061
1062 if (!smu->ppt_funcs->get_thermal_temperature_range)
1063 return 0;
1064
1065 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1066 if (ret)
1067 return ret;
1068
1069 adev->pm.dpm.thermal.min_temp = range->min;
1070 adev->pm.dpm.thermal.max_temp = range->max;
1071 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1072 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1073 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1074 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1075 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1076 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1077 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1078
1079 return ret;
1080 }
1081
1082 static int smu_smc_hw_setup(struct smu_context *smu)
1083 {
1084 struct amdgpu_device *adev = smu->adev;
1085 uint32_t pcie_gen = 0, pcie_width = 0;
1086 int ret = 0;
1087
1088 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1089 dev_info(adev->dev, "dpm has been enabled\n");
1090 /* this is needed specifically */
1091 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
1092 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1093 ret = smu_system_features_control(smu, true);
1094 return ret;
1095 }
1096
1097 ret = smu_init_display_count(smu, 0);
1098 if (ret) {
1099 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1100 return ret;
1101 }
1102
1103 ret = smu_set_driver_table_location(smu);
1104 if (ret) {
1105 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1106 return ret;
1107 }
1108
1109 /*
1110 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1111 */
1112 ret = smu_set_tool_table_location(smu);
1113 if (ret) {
1114 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1115 return ret;
1116 }
1117
1118 /*
1119 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1120 * pool location.
1121 */
1122 ret = smu_notify_memory_pool_location(smu);
1123 if (ret) {
1124 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1125 return ret;
1126 }
1127
1128 /* smu_dump_pptable(smu); */
1129 /*
1130 * Copy pptable bo in the vram to smc with SMU MSGs such as
1131 * SetDriverDramAddr and TransferTableDram2Smu.
1132 */
1133 ret = smu_write_pptable(smu);
1134 if (ret) {
1135 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1136 return ret;
1137 }
1138
1139 /* issue Run*Btc msg */
1140 ret = smu_run_btc(smu);
1141 if (ret)
1142 return ret;
1143
1144 ret = smu_feature_set_allowed_mask(smu);
1145 if (ret) {
1146 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1147 return ret;
1148 }
1149
1150 ret = smu_system_features_control(smu, true);
1151 if (ret) {
1152 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1153 return ret;
1154 }
1155
1156 if (!smu_is_dpm_running(smu))
1157 dev_info(adev->dev, "dpm has been disabled\n");
1158
1159 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1160 pcie_gen = 3;
1161 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1162 pcie_gen = 2;
1163 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1164 pcie_gen = 1;
1165 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1166 pcie_gen = 0;
1167
1168 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1169 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1170 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1171 */
1172 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1173 pcie_width = 6;
1174 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1175 pcie_width = 5;
1176 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1177 pcie_width = 4;
1178 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1179 pcie_width = 3;
1180 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1181 pcie_width = 2;
1182 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1183 pcie_width = 1;
1184 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1185 if (ret) {
1186 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1187 return ret;
1188 }
1189
1190 ret = smu_get_thermal_temperature_range(smu);
1191 if (ret) {
1192 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1193 return ret;
1194 }
1195
1196 ret = smu_enable_thermal_alert(smu);
1197 if (ret) {
1198 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1199 return ret;
1200 }
1201
1202 /*
1203 * Set initialized values (get from vbios) to dpm tables context such as
1204 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1205 * type of clks.
1206 */
1207 ret = smu_set_default_dpm_table(smu);
1208 if (ret) {
1209 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1210 return ret;
1211 }
1212
1213 ret = smu_notify_display_change(smu);
1214 if (ret)
1215 return ret;
1216
1217 /*
1218 * Set min deep sleep dce fclk with bootup value from vbios via
1219 * SetMinDeepSleepDcefclk MSG.
1220 */
1221 ret = smu_set_min_dcef_deep_sleep(smu,
1222 smu->smu_table.boot_values.dcefclk / 100);
1223 if (ret)
1224 return ret;
1225
1226 return ret;
1227 }
1228
1229 static int smu_start_smc_engine(struct smu_context *smu)
1230 {
1231 struct amdgpu_device *adev = smu->adev;
1232 int ret = 0;
1233
1234 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1235 if (adev->asic_type < CHIP_NAVI10) {
1236 if (smu->ppt_funcs->load_microcode) {
1237 ret = smu->ppt_funcs->load_microcode(smu);
1238 if (ret)
1239 return ret;
1240 }
1241 }
1242 }
1243
1244 if (smu->ppt_funcs->check_fw_status) {
1245 ret = smu->ppt_funcs->check_fw_status(smu);
1246 if (ret) {
1247 dev_err(adev->dev, "SMC is not ready\n");
1248 return ret;
1249 }
1250 }
1251
1252 /*
1253 * Send msg GetDriverIfVersion to check if the return value is equal
1254 * with DRIVER_IF_VERSION of smc header.
1255 */
1256 ret = smu_check_fw_version(smu);
1257 if (ret)
1258 return ret;
1259
1260 return ret;
1261 }
1262
1263 static int smu_hw_init(void *handle)
1264 {
1265 int ret;
1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267 struct smu_context *smu = &adev->smu;
1268
1269 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1270 smu->pm_enabled = false;
1271 return 0;
1272 }
1273
1274 ret = smu_start_smc_engine(smu);
1275 if (ret) {
1276 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1277 return ret;
1278 }
1279
1280 if (smu->is_apu) {
1281 smu_powergate_sdma(&adev->smu, false);
1282 smu_dpm_set_vcn_enable(smu, true);
1283 smu_dpm_set_jpeg_enable(smu, true);
1284 smu_set_gfx_cgpg(&adev->smu, true);
1285 }
1286
1287 if (!smu->pm_enabled)
1288 return 0;
1289
1290 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1291 ret = smu_get_vbios_bootup_values(smu);
1292 if (ret) {
1293 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1294 return ret;
1295 }
1296
1297 ret = smu_setup_pptable(smu);
1298 if (ret) {
1299 dev_err(adev->dev, "Failed to setup pptable!\n");
1300 return ret;
1301 }
1302
1303 ret = smu_get_driver_allowed_feature_mask(smu);
1304 if (ret)
1305 return ret;
1306
1307 ret = smu_smc_hw_setup(smu);
1308 if (ret) {
1309 dev_err(adev->dev, "Failed to setup smc hw!\n");
1310 return ret;
1311 }
1312
1313 /*
1314 * Move maximum sustainable clock retrieving here considering
1315 * 1. It is not needed on resume(from S3).
1316 * 2. DAL settings come between .hw_init and .late_init of SMU.
1317 * And DAL needs to know the maximum sustainable clocks. Thus
1318 * it cannot be put in .late_init().
1319 */
1320 ret = smu_init_max_sustainable_clocks(smu);
1321 if (ret) {
1322 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1323 return ret;
1324 }
1325
1326 adev->pm.dpm_enabled = true;
1327
1328 dev_info(adev->dev, "SMU is initialized successfully!\n");
1329
1330 return 0;
1331 }
1332
1333 static int smu_disable_dpms(struct smu_context *smu)
1334 {
1335 struct amdgpu_device *adev = smu->adev;
1336 int ret = 0;
1337 bool use_baco = !smu->is_apu &&
1338 ((amdgpu_in_reset(adev) &&
1339 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1340 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1341
1342 /*
1343 * For custom pptable uploading, skip the DPM features
1344 * disable process on Navi1x ASICs.
1345 * - As the gfx related features are under control of
1346 * RLC on those ASICs. RLC reinitialization will be
1347 * needed to reenable them. That will cost much more
1348 * efforts.
1349 *
1350 * - SMU firmware can handle the DPM reenablement
1351 * properly.
1352 */
1353 if (smu->uploading_custom_pp_table &&
1354 (adev->asic_type >= CHIP_NAVI10) &&
1355 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1356 return 0;
1357
1358 /*
1359 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1360 * on BACO in. Driver involvement is unnecessary.
1361 */
1362 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1363 use_baco)
1364 return 0;
1365
1366 /*
1367 * For gpu reset, runpm and hibernation through BACO,
1368 * BACO feature has to be kept enabled.
1369 */
1370 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1371 ret = smu_disable_all_features_with_exception(smu,
1372 SMU_FEATURE_BACO_BIT);
1373 if (ret)
1374 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1375 } else {
1376 ret = smu_system_features_control(smu, false);
1377 if (ret)
1378 dev_err(adev->dev, "Failed to disable smu features.\n");
1379 }
1380
1381 if (adev->asic_type >= CHIP_NAVI10 &&
1382 adev->gfx.rlc.funcs->stop)
1383 adev->gfx.rlc.funcs->stop(adev);
1384
1385 return ret;
1386 }
1387
1388 static int smu_smc_hw_cleanup(struct smu_context *smu)
1389 {
1390 struct amdgpu_device *adev = smu->adev;
1391 int ret = 0;
1392
1393 cancel_work_sync(&smu->throttling_logging_work);
1394 cancel_work_sync(&smu->interrupt_work);
1395
1396 ret = smu_disable_thermal_alert(smu);
1397 if (ret) {
1398 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1399 return ret;
1400 }
1401
1402 ret = smu_disable_dpms(smu);
1403 if (ret) {
1404 dev_err(adev->dev, "Fail to disable dpm features!\n");
1405 return ret;
1406 }
1407
1408 return 0;
1409 }
1410
1411 static int smu_hw_fini(void *handle)
1412 {
1413 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1414 struct smu_context *smu = &adev->smu;
1415
1416 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1417 return 0;
1418
1419 if (smu->is_apu) {
1420 smu_powergate_sdma(&adev->smu, true);
1421 smu_dpm_set_vcn_enable(smu, false);
1422 smu_dpm_set_jpeg_enable(smu, false);
1423 }
1424
1425 if (!smu->pm_enabled)
1426 return 0;
1427
1428 adev->pm.dpm_enabled = false;
1429
1430 return smu_smc_hw_cleanup(smu);
1431 }
1432
1433 int smu_reset(struct smu_context *smu)
1434 {
1435 struct amdgpu_device *adev = smu->adev;
1436 int ret;
1437
1438 amdgpu_gfx_off_ctrl(smu->adev, false);
1439
1440 ret = smu_hw_fini(adev);
1441 if (ret)
1442 return ret;
1443
1444 ret = smu_hw_init(adev);
1445 if (ret)
1446 return ret;
1447
1448 ret = smu_late_init(adev);
1449 if (ret)
1450 return ret;
1451
1452 amdgpu_gfx_off_ctrl(smu->adev, true);
1453
1454 return 0;
1455 }
1456
1457 static int smu_suspend(void *handle)
1458 {
1459 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1460 struct smu_context *smu = &adev->smu;
1461 int ret;
1462
1463 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1464 return 0;
1465
1466 if (!smu->pm_enabled)
1467 return 0;
1468
1469 adev->pm.dpm_enabled = false;
1470
1471 ret = smu_smc_hw_cleanup(smu);
1472 if (ret)
1473 return ret;
1474
1475 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1476
1477 if (smu->is_apu)
1478 smu_set_gfx_cgpg(&adev->smu, false);
1479
1480 return 0;
1481 }
1482
1483 static int smu_resume(void *handle)
1484 {
1485 int ret;
1486 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1487 struct smu_context *smu = &adev->smu;
1488
1489 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1490 return 0;
1491
1492 if (!smu->pm_enabled)
1493 return 0;
1494
1495 dev_info(adev->dev, "SMU is resuming...\n");
1496
1497 ret = smu_start_smc_engine(smu);
1498 if (ret) {
1499 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1500 return ret;
1501 }
1502
1503 ret = smu_smc_hw_setup(smu);
1504 if (ret) {
1505 dev_err(adev->dev, "Failed to setup smc hw!\n");
1506 return ret;
1507 }
1508
1509 if (smu->is_apu)
1510 smu_set_gfx_cgpg(&adev->smu, true);
1511
1512 smu->disable_uclk_switch = 0;
1513
1514 adev->pm.dpm_enabled = true;
1515
1516 dev_info(adev->dev, "SMU is resumed successfully!\n");
1517
1518 return 0;
1519 }
1520
1521 int smu_display_configuration_change(struct smu_context *smu,
1522 const struct amd_pp_display_configuration *display_config)
1523 {
1524 int index = 0;
1525 int num_of_active_display = 0;
1526
1527 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1528 return -EOPNOTSUPP;
1529
1530 if (!display_config)
1531 return -EINVAL;
1532
1533 mutex_lock(&smu->mutex);
1534
1535 smu_set_min_dcef_deep_sleep(smu,
1536 display_config->min_dcef_deep_sleep_set_clk / 100);
1537
1538 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1539 if (display_config->displays[index].controller_id != 0)
1540 num_of_active_display++;
1541 }
1542
1543 mutex_unlock(&smu->mutex);
1544
1545 return 0;
1546 }
1547
1548 static int smu_set_clockgating_state(void *handle,
1549 enum amd_clockgating_state state)
1550 {
1551 return 0;
1552 }
1553
1554 static int smu_set_powergating_state(void *handle,
1555 enum amd_powergating_state state)
1556 {
1557 return 0;
1558 }
1559
1560 static int smu_enable_umd_pstate(void *handle,
1561 enum amd_dpm_forced_level *level)
1562 {
1563 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1564 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1565 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1566 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1567
1568 struct smu_context *smu = (struct smu_context*)(handle);
1569 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1570
1571 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1572 return -EINVAL;
1573
1574 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1575 /* enter umd pstate, save current level, disable gfx cg*/
1576 if (*level & profile_mode_mask) {
1577 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1578 smu_dpm_ctx->enable_umd_pstate = true;
1579 smu_gpo_control(smu, false);
1580 amdgpu_device_ip_set_powergating_state(smu->adev,
1581 AMD_IP_BLOCK_TYPE_GFX,
1582 AMD_PG_STATE_UNGATE);
1583 amdgpu_device_ip_set_clockgating_state(smu->adev,
1584 AMD_IP_BLOCK_TYPE_GFX,
1585 AMD_CG_STATE_UNGATE);
1586 smu_gfx_ulv_control(smu, false);
1587 smu_deep_sleep_control(smu, false);
1588 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1589 }
1590 } else {
1591 /* exit umd pstate, restore level, enable gfx cg*/
1592 if (!(*level & profile_mode_mask)) {
1593 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1594 *level = smu_dpm_ctx->saved_dpm_level;
1595 smu_dpm_ctx->enable_umd_pstate = false;
1596 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1597 smu_deep_sleep_control(smu, true);
1598 smu_gfx_ulv_control(smu, true);
1599 amdgpu_device_ip_set_clockgating_state(smu->adev,
1600 AMD_IP_BLOCK_TYPE_GFX,
1601 AMD_CG_STATE_GATE);
1602 amdgpu_device_ip_set_powergating_state(smu->adev,
1603 AMD_IP_BLOCK_TYPE_GFX,
1604 AMD_PG_STATE_GATE);
1605 smu_gpo_control(smu, true);
1606 }
1607 }
1608
1609 return 0;
1610 }
1611
1612 static int smu_bump_power_profile_mode(struct smu_context *smu,
1613 long *param,
1614 uint32_t param_size)
1615 {
1616 int ret = 0;
1617
1618 if (smu->ppt_funcs->set_power_profile_mode)
1619 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1620
1621 return ret;
1622 }
1623
1624 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1625 enum amd_dpm_forced_level level,
1626 bool skip_display_settings)
1627 {
1628 int ret = 0;
1629 int index = 0;
1630 long workload;
1631 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1632
1633 if (!skip_display_settings) {
1634 ret = smu_display_config_changed(smu);
1635 if (ret) {
1636 dev_err(smu->adev->dev, "Failed to change display config!");
1637 return ret;
1638 }
1639 }
1640
1641 ret = smu_apply_clocks_adjust_rules(smu);
1642 if (ret) {
1643 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1644 return ret;
1645 }
1646
1647 if (!skip_display_settings) {
1648 ret = smu_notify_smc_display_config(smu);
1649 if (ret) {
1650 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1651 return ret;
1652 }
1653 }
1654
1655 if (smu_dpm_ctx->dpm_level != level) {
1656 ret = smu_asic_set_performance_level(smu, level);
1657 if (ret) {
1658 dev_err(smu->adev->dev, "Failed to set performance level!");
1659 return ret;
1660 }
1661
1662 /* update the saved copy */
1663 smu_dpm_ctx->dpm_level = level;
1664 }
1665
1666 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1667 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1668 index = fls(smu->workload_mask);
1669 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1670 workload = smu->workload_setting[index];
1671
1672 if (smu->power_profile_mode != workload)
1673 smu_bump_power_profile_mode(smu, &workload, 0);
1674 }
1675
1676 return ret;
1677 }
1678
1679 int smu_handle_task(struct smu_context *smu,
1680 enum amd_dpm_forced_level level,
1681 enum amd_pp_task task_id,
1682 bool lock_needed)
1683 {
1684 int ret = 0;
1685
1686 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1687 return -EOPNOTSUPP;
1688
1689 if (lock_needed)
1690 mutex_lock(&smu->mutex);
1691
1692 switch (task_id) {
1693 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1694 ret = smu_pre_display_config_changed(smu);
1695 if (ret)
1696 goto out;
1697 ret = smu_adjust_power_state_dynamic(smu, level, false);
1698 break;
1699 case AMD_PP_TASK_COMPLETE_INIT:
1700 case AMD_PP_TASK_READJUST_POWER_STATE:
1701 ret = smu_adjust_power_state_dynamic(smu, level, true);
1702 break;
1703 default:
1704 break;
1705 }
1706
1707 out:
1708 if (lock_needed)
1709 mutex_unlock(&smu->mutex);
1710
1711 return ret;
1712 }
1713
1714 int smu_handle_dpm_task(void *handle,
1715 enum amd_pp_task task_id,
1716 enum amd_pm_state_type *user_state)
1717 {
1718 struct smu_context *smu = handle;
1719 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1720
1721 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true);
1722
1723 }
1724
1725
1726 int smu_switch_power_profile(void *handle,
1727 enum PP_SMC_POWER_PROFILE type,
1728 bool en)
1729 {
1730 struct smu_context *smu = handle;
1731 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1732 long workload;
1733 uint32_t index;
1734
1735 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1736 return -EOPNOTSUPP;
1737
1738 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1739 return -EINVAL;
1740
1741 mutex_lock(&smu->mutex);
1742
1743 if (!en) {
1744 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1745 index = fls(smu->workload_mask);
1746 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1747 workload = smu->workload_setting[index];
1748 } else {
1749 smu->workload_mask |= (1 << smu->workload_prority[type]);
1750 index = fls(smu->workload_mask);
1751 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1752 workload = smu->workload_setting[index];
1753 }
1754
1755 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1756 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1757 smu_bump_power_profile_mode(smu, &workload, 0);
1758
1759 mutex_unlock(&smu->mutex);
1760
1761 return 0;
1762 }
1763
1764 enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1765 {
1766 struct smu_context *smu = handle;
1767 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1768 enum amd_dpm_forced_level level;
1769
1770 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1771 return -EOPNOTSUPP;
1772
1773 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1774 return -EINVAL;
1775
1776 mutex_lock(&(smu->mutex));
1777 level = smu_dpm_ctx->dpm_level;
1778 mutex_unlock(&(smu->mutex));
1779
1780 return level;
1781 }
1782
1783 int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level)
1784 {
1785 struct smu_context *smu = handle;
1786 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1787 int ret = 0;
1788
1789 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1790 return -EOPNOTSUPP;
1791
1792 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1793 return -EINVAL;
1794
1795 mutex_lock(&smu->mutex);
1796
1797 ret = smu_enable_umd_pstate(smu, &level);
1798 if (ret) {
1799 mutex_unlock(&smu->mutex);
1800 return ret;
1801 }
1802
1803 ret = smu_handle_task(smu, level,
1804 AMD_PP_TASK_READJUST_POWER_STATE,
1805 false);
1806
1807 mutex_unlock(&smu->mutex);
1808
1809 /* reset user dpm clock state */
1810 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1811 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1812 smu->user_dpm_profile.clk_dependency = 0;
1813 }
1814
1815 return ret;
1816 }
1817
1818 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1819 {
1820 int ret = 0;
1821
1822 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1823 return -EOPNOTSUPP;
1824
1825 mutex_lock(&smu->mutex);
1826 ret = smu_init_display_count(smu, count);
1827 mutex_unlock(&smu->mutex);
1828
1829 return ret;
1830 }
1831
1832 static int smu_force_smuclk_levels(struct smu_context *smu,
1833 enum smu_clk_type clk_type,
1834 uint32_t mask)
1835 {
1836 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1837 int ret = 0;
1838
1839 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1840 return -EOPNOTSUPP;
1841
1842 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1843 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1844 return -EINVAL;
1845 }
1846
1847 mutex_lock(&smu->mutex);
1848
1849 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1850 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1851 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1852 smu->user_dpm_profile.clk_mask[clk_type] = mask;
1853 smu_set_user_clk_dependencies(smu, clk_type);
1854 }
1855 }
1856
1857 mutex_unlock(&smu->mutex);
1858
1859 return ret;
1860 }
1861
1862 int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask)
1863 {
1864 struct smu_context *smu = handle;
1865 enum smu_clk_type clk_type;
1866
1867 switch (type) {
1868 case PP_SCLK:
1869 clk_type = SMU_SCLK; break;
1870 case PP_MCLK:
1871 clk_type = SMU_MCLK; break;
1872 case PP_PCIE:
1873 clk_type = SMU_PCIE; break;
1874 case PP_SOCCLK:
1875 clk_type = SMU_SOCCLK; break;
1876 case PP_FCLK:
1877 clk_type = SMU_FCLK; break;
1878 case PP_DCEFCLK:
1879 clk_type = SMU_DCEFCLK; break;
1880 case PP_VCLK:
1881 clk_type = SMU_VCLK; break;
1882 case PP_DCLK:
1883 clk_type = SMU_DCLK; break;
1884 case OD_SCLK:
1885 clk_type = SMU_OD_SCLK; break;
1886 case OD_MCLK:
1887 clk_type = SMU_OD_MCLK; break;
1888 case OD_VDDC_CURVE:
1889 clk_type = SMU_OD_VDDC_CURVE; break;
1890 case OD_RANGE:
1891 clk_type = SMU_OD_RANGE; break;
1892 default:
1893 return -EINVAL;
1894 }
1895
1896 return smu_force_smuclk_levels(smu, clk_type, mask);
1897 }
1898
1899 /*
1900 * On system suspending or resetting, the dpm_enabled
1901 * flag will be cleared. So that those SMU services which
1902 * are not supported will be gated.
1903 * However, the mp1 state setting should still be granted
1904 * even if the dpm_enabled cleared.
1905 */
1906 int smu_set_mp1_state(void *handle,
1907 enum pp_mp1_state mp1_state)
1908 {
1909 struct smu_context *smu = handle;
1910 uint16_t msg;
1911 int ret;
1912
1913 if (!smu->pm_enabled)
1914 return -EOPNOTSUPP;
1915
1916 mutex_lock(&smu->mutex);
1917
1918 switch (mp1_state) {
1919 case PP_MP1_STATE_SHUTDOWN:
1920 msg = SMU_MSG_PrepareMp1ForShutdown;
1921 break;
1922 case PP_MP1_STATE_UNLOAD:
1923 msg = SMU_MSG_PrepareMp1ForUnload;
1924 break;
1925 case PP_MP1_STATE_RESET:
1926 msg = SMU_MSG_PrepareMp1ForReset;
1927 break;
1928 case PP_MP1_STATE_NONE:
1929 default:
1930 mutex_unlock(&smu->mutex);
1931 return 0;
1932 }
1933
1934 ret = smu_send_smc_msg(smu, msg, NULL);
1935 /* some asics may not support those messages */
1936 if (ret == -EINVAL)
1937 ret = 0;
1938 if (ret)
1939 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1940
1941 mutex_unlock(&smu->mutex);
1942
1943 return ret;
1944 }
1945
1946 int smu_set_df_cstate(void *handle,
1947 enum pp_df_cstate state)
1948 {
1949 struct smu_context *smu = handle;
1950 int ret = 0;
1951
1952 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1953 return -EOPNOTSUPP;
1954
1955 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1956 return 0;
1957
1958 mutex_lock(&smu->mutex);
1959
1960 ret = smu->ppt_funcs->set_df_cstate(smu, state);
1961 if (ret)
1962 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1963
1964 mutex_unlock(&smu->mutex);
1965
1966 return ret;
1967 }
1968
1969 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1970 {
1971 int ret = 0;
1972
1973 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1974 return -EOPNOTSUPP;
1975
1976 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1977 return 0;
1978
1979 mutex_lock(&smu->mutex);
1980
1981 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1982 if (ret)
1983 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1984
1985 mutex_unlock(&smu->mutex);
1986
1987 return ret;
1988 }
1989
1990 int smu_write_watermarks_table(struct smu_context *smu)
1991 {
1992 int ret = 0;
1993
1994 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1995 return -EOPNOTSUPP;
1996
1997 mutex_lock(&smu->mutex);
1998
1999 ret = smu_set_watermarks_table(smu, NULL);
2000
2001 mutex_unlock(&smu->mutex);
2002
2003 return ret;
2004 }
2005
2006 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
2007 struct pp_smu_wm_range_sets *clock_ranges)
2008 {
2009 int ret = 0;
2010
2011 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2012 return -EOPNOTSUPP;
2013
2014 if (smu->disable_watermark)
2015 return 0;
2016
2017 mutex_lock(&smu->mutex);
2018
2019 ret = smu_set_watermarks_table(smu, clock_ranges);
2020
2021 mutex_unlock(&smu->mutex);
2022
2023 return ret;
2024 }
2025
2026 int smu_set_ac_dc(struct smu_context *smu)
2027 {
2028 int ret = 0;
2029
2030 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2031 return -EOPNOTSUPP;
2032
2033 /* controlled by firmware */
2034 if (smu->dc_controlled_by_gpio)
2035 return 0;
2036
2037 mutex_lock(&smu->mutex);
2038 ret = smu_set_power_source(smu,
2039 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2040 SMU_POWER_SOURCE_DC);
2041 if (ret)
2042 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2043 smu->adev->pm.ac_power ? "AC" : "DC");
2044 mutex_unlock(&smu->mutex);
2045
2046 return ret;
2047 }
2048
2049 const struct amd_ip_funcs smu_ip_funcs = {
2050 .name = "smu",
2051 .early_init = smu_early_init,
2052 .late_init = smu_late_init,
2053 .sw_init = smu_sw_init,
2054 .sw_fini = smu_sw_fini,
2055 .hw_init = smu_hw_init,
2056 .hw_fini = smu_hw_fini,
2057 .suspend = smu_suspend,
2058 .resume = smu_resume,
2059 .is_idle = NULL,
2060 .check_soft_reset = NULL,
2061 .wait_for_idle = NULL,
2062 .soft_reset = NULL,
2063 .set_clockgating_state = smu_set_clockgating_state,
2064 .set_powergating_state = smu_set_powergating_state,
2065 .enable_umd_pstate = smu_enable_umd_pstate,
2066 };
2067
2068 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2069 {
2070 .type = AMD_IP_BLOCK_TYPE_SMC,
2071 .major = 11,
2072 .minor = 0,
2073 .rev = 0,
2074 .funcs = &smu_ip_funcs,
2075 };
2076
2077 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2078 {
2079 .type = AMD_IP_BLOCK_TYPE_SMC,
2080 .major = 12,
2081 .minor = 0,
2082 .rev = 0,
2083 .funcs = &smu_ip_funcs,
2084 };
2085
2086 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2087 {
2088 .type = AMD_IP_BLOCK_TYPE_SMC,
2089 .major = 13,
2090 .minor = 0,
2091 .rev = 0,
2092 .funcs = &smu_ip_funcs,
2093 };
2094
2095 int smu_load_microcode(struct smu_context *smu)
2096 {
2097 int ret = 0;
2098
2099 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2100 return -EOPNOTSUPP;
2101
2102 mutex_lock(&smu->mutex);
2103
2104 if (smu->ppt_funcs->load_microcode)
2105 ret = smu->ppt_funcs->load_microcode(smu);
2106
2107 mutex_unlock(&smu->mutex);
2108
2109 return ret;
2110 }
2111
2112 int smu_check_fw_status(struct smu_context *smu)
2113 {
2114 int ret = 0;
2115
2116 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2117 return -EOPNOTSUPP;
2118
2119 mutex_lock(&smu->mutex);
2120
2121 if (smu->ppt_funcs->check_fw_status)
2122 ret = smu->ppt_funcs->check_fw_status(smu);
2123
2124 mutex_unlock(&smu->mutex);
2125
2126 return ret;
2127 }
2128
2129 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2130 {
2131 int ret = 0;
2132
2133 mutex_lock(&smu->mutex);
2134
2135 if (smu->ppt_funcs->set_gfx_cgpg)
2136 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2137
2138 mutex_unlock(&smu->mutex);
2139
2140 return ret;
2141 }
2142
2143 int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2144 {
2145 struct smu_context *smu = handle;
2146 u32 percent;
2147 int ret = 0;
2148
2149 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2150 return -EOPNOTSUPP;
2151
2152 mutex_lock(&smu->mutex);
2153
2154 if (smu->ppt_funcs->set_fan_speed_percent) {
2155 percent = speed * 100 / smu->fan_max_rpm;
2156 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
2157 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2158 smu->user_dpm_profile.fan_speed_percent = percent;
2159 }
2160
2161 mutex_unlock(&smu->mutex);
2162
2163 return ret;
2164 }
2165
2166 int smu_get_power_limit(struct smu_context *smu,
2167 uint32_t *limit,
2168 enum smu_ppt_limit_level limit_level)
2169 {
2170 uint32_t limit_type = *limit >> 24;
2171 int ret = 0;
2172
2173 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2174 return -EOPNOTSUPP;
2175
2176 mutex_lock(&smu->mutex);
2177
2178 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2179 if (smu->ppt_funcs->get_ppt_limit)
2180 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2181 } else {
2182 switch (limit_level) {
2183 case SMU_PPT_LIMIT_CURRENT:
2184 *limit = smu->current_power_limit;
2185 break;
2186 case SMU_PPT_LIMIT_DEFAULT:
2187 *limit = smu->default_power_limit;
2188 break;
2189 case SMU_PPT_LIMIT_MAX:
2190 *limit = smu->max_power_limit;
2191 break;
2192 default:
2193 break;
2194 }
2195 }
2196
2197 mutex_unlock(&smu->mutex);
2198
2199 return ret;
2200 }
2201
2202 int smu_set_power_limit(void *handle, uint32_t limit)
2203 {
2204 struct smu_context *smu = handle;
2205 uint32_t limit_type = limit >> 24;
2206 int ret = 0;
2207
2208 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2209 return -EOPNOTSUPP;
2210
2211 mutex_lock(&smu->mutex);
2212
2213 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2214 if (smu->ppt_funcs->set_power_limit) {
2215 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2216 goto out;
2217 }
2218
2219 if (limit > smu->max_power_limit) {
2220 dev_err(smu->adev->dev,
2221 "New power limit (%d) is over the max allowed %d\n",
2222 limit, smu->max_power_limit);
2223 goto out;
2224 }
2225
2226 if (!limit)
2227 limit = smu->current_power_limit;
2228
2229 if (smu->ppt_funcs->set_power_limit) {
2230 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2231 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2232 smu->user_dpm_profile.power_limit = limit;
2233 }
2234
2235 out:
2236 mutex_unlock(&smu->mutex);
2237
2238 return ret;
2239 }
2240
2241 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2242 {
2243 int ret = 0;
2244
2245 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2246 return -EOPNOTSUPP;
2247
2248 mutex_lock(&smu->mutex);
2249
2250 if (smu->ppt_funcs->print_clk_levels)
2251 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2252
2253 mutex_unlock(&smu->mutex);
2254
2255 return ret;
2256 }
2257
2258 int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf)
2259 {
2260 struct smu_context *smu = handle;
2261 enum smu_clk_type clk_type;
2262
2263 switch (type) {
2264 case PP_SCLK:
2265 clk_type = SMU_SCLK; break;
2266 case PP_MCLK:
2267 clk_type = SMU_MCLK; break;
2268 case PP_PCIE:
2269 clk_type = SMU_PCIE; break;
2270 case PP_SOCCLK:
2271 clk_type = SMU_SOCCLK; break;
2272 case PP_FCLK:
2273 clk_type = SMU_FCLK; break;
2274 case PP_DCEFCLK:
2275 clk_type = SMU_DCEFCLK; break;
2276 case PP_VCLK:
2277 clk_type = SMU_VCLK; break;
2278 case PP_DCLK:
2279 clk_type = SMU_DCLK; break;
2280 case OD_SCLK:
2281 clk_type = SMU_OD_SCLK; break;
2282 case OD_MCLK:
2283 clk_type = SMU_OD_MCLK; break;
2284 case OD_VDDC_CURVE:
2285 clk_type = SMU_OD_VDDC_CURVE; break;
2286 case OD_RANGE:
2287 clk_type = SMU_OD_RANGE; break;
2288 case OD_VDDGFX_OFFSET:
2289 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2290 case OD_CCLK:
2291 clk_type = SMU_OD_CCLK; break;
2292 default:
2293 return -EINVAL;
2294 }
2295
2296 return smu_print_smuclk_levels(smu, clk_type, buf);
2297 }
2298
2299 int smu_od_edit_dpm_table(void *handle,
2300 enum PP_OD_DPM_TABLE_COMMAND type,
2301 long *input, uint32_t size)
2302 {
2303 struct smu_context *smu = handle;
2304 int ret = 0;
2305
2306 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2307 return -EOPNOTSUPP;
2308
2309 mutex_lock(&smu->mutex);
2310
2311 if (smu->ppt_funcs->od_edit_dpm_table) {
2312 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2313 }
2314
2315 mutex_unlock(&smu->mutex);
2316
2317 return ret;
2318 }
2319
2320 int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg)
2321 {
2322 struct smu_context *smu = handle;
2323 struct smu_umd_pstate_table *pstate_table =
2324 &smu->pstate_table;
2325 int ret = 0;
2326 uint32_t *size, size_val;
2327
2328 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2329 return -EOPNOTSUPP;
2330
2331 if (!data || !size_arg)
2332 return -EINVAL;
2333
2334 size_val = *size_arg;
2335 size = &size_val;
2336
2337 mutex_lock(&smu->mutex);
2338
2339 if (smu->ppt_funcs->read_sensor)
2340 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2341 goto unlock;
2342
2343 switch (sensor) {
2344 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2345 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2346 *size = 4;
2347 break;
2348 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2349 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2350 *size = 4;
2351 break;
2352 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2353 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2354 *size = 8;
2355 break;
2356 case AMDGPU_PP_SENSOR_UVD_POWER:
2357 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2358 *size = 4;
2359 break;
2360 case AMDGPU_PP_SENSOR_VCE_POWER:
2361 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2362 *size = 4;
2363 break;
2364 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2365 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2366 *size = 4;
2367 break;
2368 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2369 *(uint32_t *)data = 0;
2370 *size = 4;
2371 break;
2372 default:
2373 *size = 0;
2374 ret = -EOPNOTSUPP;
2375 break;
2376 }
2377
2378 unlock:
2379 mutex_unlock(&smu->mutex);
2380
2381 // assign uint32_t to int
2382 *size_arg = size_val;
2383
2384 return ret;
2385 }
2386
2387 int smu_get_power_profile_mode(void *handle, char *buf)
2388 {
2389 struct smu_context *smu = handle;
2390 int ret = 0;
2391
2392 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2393 return -EOPNOTSUPP;
2394
2395 mutex_lock(&smu->mutex);
2396
2397 if (smu->ppt_funcs->get_power_profile_mode)
2398 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2399
2400 mutex_unlock(&smu->mutex);
2401
2402 return ret;
2403 }
2404
2405 int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size)
2406 {
2407 struct smu_context *smu = handle;
2408 int ret = 0;
2409
2410 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2411 return -EOPNOTSUPP;
2412
2413 mutex_lock(&smu->mutex);
2414
2415 smu_bump_power_profile_mode(smu, param, param_size);
2416
2417 mutex_unlock(&smu->mutex);
2418
2419 return ret;
2420 }
2421
2422
2423 u32 smu_get_fan_control_mode(void *handle)
2424 {
2425 struct smu_context *smu = handle;
2426 u32 ret = 0;
2427
2428 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2429 return AMD_FAN_CTRL_NONE;
2430
2431 mutex_lock(&smu->mutex);
2432
2433 if (smu->ppt_funcs->get_fan_control_mode)
2434 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2435
2436 mutex_unlock(&smu->mutex);
2437
2438 return ret;
2439 }
2440
2441 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2442 {
2443 int ret = 0;
2444
2445 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2446 return -EOPNOTSUPP;
2447
2448 mutex_lock(&smu->mutex);
2449
2450 if (smu->ppt_funcs->set_fan_control_mode) {
2451 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2452 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2453 smu->user_dpm_profile.fan_mode = value;
2454 }
2455
2456 mutex_unlock(&smu->mutex);
2457
2458 /* reset user dpm fan speed */
2459 if (!ret && value != AMD_FAN_CTRL_MANUAL &&
2460 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2461 smu->user_dpm_profile.fan_speed_percent = 0;
2462
2463 return ret;
2464 }
2465
2466 void smu_pp_set_fan_control_mode(void *handle, u32 value) {
2467 struct smu_context *smu = handle;
2468
2469 smu_set_fan_control_mode(smu, value);
2470 }
2471
2472
2473 int smu_get_fan_speed_percent(void *handle, u32 *speed)
2474 {
2475 struct smu_context *smu = handle;
2476 int ret = 0;
2477 uint32_t percent;
2478
2479 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2480 return -EOPNOTSUPP;
2481
2482 mutex_lock(&smu->mutex);
2483
2484 if (smu->ppt_funcs->get_fan_speed_percent) {
2485 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2486 if (!ret) {
2487 *speed = percent > 100 ? 100 : percent;
2488 }
2489 }
2490
2491 mutex_unlock(&smu->mutex);
2492
2493
2494 return ret;
2495 }
2496
2497 int smu_set_fan_speed_percent(void *handle, u32 speed)
2498 {
2499 struct smu_context *smu = handle;
2500 int ret = 0;
2501
2502 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2503 return -EOPNOTSUPP;
2504
2505 mutex_lock(&smu->mutex);
2506
2507 if (smu->ppt_funcs->set_fan_speed_percent) {
2508 if (speed > 100)
2509 speed = 100;
2510 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2511 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2512 smu->user_dpm_profile.fan_speed_percent = speed;
2513 }
2514
2515 mutex_unlock(&smu->mutex);
2516
2517 return ret;
2518 }
2519
2520 int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2521 {
2522 struct smu_context *smu = handle;
2523 int ret = 0;
2524 u32 percent;
2525
2526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2527 return -EOPNOTSUPP;
2528
2529 mutex_lock(&smu->mutex);
2530
2531 if (smu->ppt_funcs->get_fan_speed_percent) {
2532 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2533 *speed = percent * smu->fan_max_rpm / 100;
2534 }
2535
2536 mutex_unlock(&smu->mutex);
2537
2538 return ret;
2539 }
2540
2541 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2542 {
2543 int ret = 0;
2544
2545 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2546 return -EOPNOTSUPP;
2547
2548 mutex_lock(&smu->mutex);
2549
2550 ret = smu_set_min_dcef_deep_sleep(smu, clk);
2551
2552 mutex_unlock(&smu->mutex);
2553
2554 return ret;
2555 }
2556
2557 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2558 enum smu_clk_type clk_type,
2559 struct pp_clock_levels_with_latency *clocks)
2560 {
2561 int ret = 0;
2562
2563 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2564 return -EOPNOTSUPP;
2565
2566 mutex_lock(&smu->mutex);
2567
2568 if (smu->ppt_funcs->get_clock_by_type_with_latency)
2569 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2570
2571 mutex_unlock(&smu->mutex);
2572
2573 return ret;
2574 }
2575
2576 int smu_display_clock_voltage_request(struct smu_context *smu,
2577 struct pp_display_clock_request *clock_req)
2578 {
2579 int ret = 0;
2580
2581 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2582 return -EOPNOTSUPP;
2583
2584 mutex_lock(&smu->mutex);
2585
2586 if (smu->ppt_funcs->display_clock_voltage_request)
2587 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2588
2589 mutex_unlock(&smu->mutex);
2590
2591 return ret;
2592 }
2593
2594
2595 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2596 {
2597 int ret = -EINVAL;
2598
2599 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2600 return -EOPNOTSUPP;
2601
2602 mutex_lock(&smu->mutex);
2603
2604 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2605 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2606
2607 mutex_unlock(&smu->mutex);
2608
2609 return ret;
2610 }
2611
2612 int smu_set_xgmi_pstate(void *handle,
2613 uint32_t pstate)
2614 {
2615 struct smu_context *smu = handle;
2616 int ret = 0;
2617
2618 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2619 return -EOPNOTSUPP;
2620
2621 mutex_lock(&smu->mutex);
2622
2623 if (smu->ppt_funcs->set_xgmi_pstate)
2624 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2625
2626 mutex_unlock(&smu->mutex);
2627
2628 if(ret)
2629 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2630
2631 return ret;
2632 }
2633
2634 int smu_set_azalia_d3_pme(struct smu_context *smu)
2635 {
2636 int ret = 0;
2637
2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2639 return -EOPNOTSUPP;
2640
2641 mutex_lock(&smu->mutex);
2642
2643 if (smu->ppt_funcs->set_azalia_d3_pme)
2644 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2645
2646 mutex_unlock(&smu->mutex);
2647
2648 return ret;
2649 }
2650
2651 /*
2652 * On system suspending or resetting, the dpm_enabled
2653 * flag will be cleared. So that those SMU services which
2654 * are not supported will be gated.
2655 *
2656 * However, the baco/mode1 reset should still be granted
2657 * as they are still supported and necessary.
2658 */
2659 bool smu_baco_is_support(struct smu_context *smu)
2660 {
2661 bool ret = false;
2662
2663 if (!smu->pm_enabled)
2664 return false;
2665
2666 mutex_lock(&smu->mutex);
2667
2668 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2669 ret = smu->ppt_funcs->baco_is_support(smu);
2670
2671 mutex_unlock(&smu->mutex);
2672
2673 return ret;
2674 }
2675
2676 int smu_get_baco_capability(void *handle, bool *cap)
2677 {
2678 struct smu_context *smu = handle;
2679 int ret = 0;
2680
2681 *cap = false;
2682
2683 if (!smu->pm_enabled)
2684 return 0;
2685
2686 mutex_lock(&smu->mutex);
2687
2688 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2689 *cap = smu->ppt_funcs->baco_is_support(smu);
2690
2691 mutex_unlock(&smu->mutex);
2692
2693 return ret;
2694 }
2695
2696
2697 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2698 {
2699 if (smu->ppt_funcs->baco_get_state)
2700 return -EINVAL;
2701
2702 mutex_lock(&smu->mutex);
2703 *state = smu->ppt_funcs->baco_get_state(smu);
2704 mutex_unlock(&smu->mutex);
2705
2706 return 0;
2707 }
2708
2709 int smu_baco_enter(struct smu_context *smu)
2710 {
2711 int ret = 0;
2712
2713 if (!smu->pm_enabled)
2714 return -EOPNOTSUPP;
2715
2716 mutex_lock(&smu->mutex);
2717
2718 if (smu->ppt_funcs->baco_enter)
2719 ret = smu->ppt_funcs->baco_enter(smu);
2720
2721 mutex_unlock(&smu->mutex);
2722
2723 if (ret)
2724 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2725
2726 return ret;
2727 }
2728
2729 int smu_baco_exit(struct smu_context *smu)
2730 {
2731 int ret = 0;
2732
2733 if (!smu->pm_enabled)
2734 return -EOPNOTSUPP;
2735
2736 mutex_lock(&smu->mutex);
2737
2738 if (smu->ppt_funcs->baco_exit)
2739 ret = smu->ppt_funcs->baco_exit(smu);
2740
2741 mutex_unlock(&smu->mutex);
2742
2743 if (ret)
2744 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2745
2746 return ret;
2747 }
2748
2749 int smu_baco_set_state(void *handle, int state)
2750 {
2751 struct smu_context *smu = handle;
2752 int ret = 0;
2753
2754 if (!smu->pm_enabled)
2755 return -EOPNOTSUPP;
2756
2757 if (state == 0) {
2758 mutex_lock(&smu->mutex);
2759
2760 if (smu->ppt_funcs->baco_exit)
2761 ret = smu->ppt_funcs->baco_exit(smu);
2762
2763 mutex_unlock(&smu->mutex);
2764 } else if (state == 1) {
2765 mutex_lock(&smu->mutex);
2766
2767 if (smu->ppt_funcs->baco_enter)
2768 ret = smu->ppt_funcs->baco_enter(smu);
2769
2770 mutex_unlock(&smu->mutex);
2771
2772 } else {
2773 return -EINVAL;
2774 }
2775
2776 if (ret)
2777 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2778 (state)?"enter":"exit");
2779
2780 return ret;
2781 }
2782
2783 bool smu_mode1_reset_is_support(struct smu_context *smu)
2784 {
2785 bool ret = false;
2786
2787 if (!smu->pm_enabled)
2788 return false;
2789
2790 mutex_lock(&smu->mutex);
2791
2792 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2793 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2794
2795 mutex_unlock(&smu->mutex);
2796
2797 return ret;
2798 }
2799
2800 bool smu_mode2_reset_is_support(struct smu_context *smu)
2801 {
2802 bool ret = false;
2803
2804 if (!smu->pm_enabled)
2805 return false;
2806
2807 mutex_lock(&smu->mutex);
2808
2809 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2810 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2811
2812 mutex_unlock(&smu->mutex);
2813
2814 return ret;
2815 }
2816
2817 int smu_mode1_reset(struct smu_context *smu)
2818 {
2819 int ret = 0;
2820
2821 if (!smu->pm_enabled)
2822 return -EOPNOTSUPP;
2823
2824 mutex_lock(&smu->mutex);
2825
2826 if (smu->ppt_funcs->mode1_reset)
2827 ret = smu->ppt_funcs->mode1_reset(smu);
2828
2829 mutex_unlock(&smu->mutex);
2830
2831 return ret;
2832 }
2833
2834 int smu_mode2_reset(void *handle)
2835 {
2836 struct smu_context *smu = handle;
2837 int ret = 0;
2838
2839 if (!smu->pm_enabled)
2840 return -EOPNOTSUPP;
2841
2842 mutex_lock(&smu->mutex);
2843
2844 if (smu->ppt_funcs->mode2_reset)
2845 ret = smu->ppt_funcs->mode2_reset(smu);
2846
2847 mutex_unlock(&smu->mutex);
2848
2849 if (ret)
2850 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2851
2852 return ret;
2853 }
2854
2855 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2856 struct pp_smu_nv_clock_table *max_clocks)
2857 {
2858 int ret = 0;
2859
2860 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2861 return -EOPNOTSUPP;
2862
2863 mutex_lock(&smu->mutex);
2864
2865 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2866 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2867
2868 mutex_unlock(&smu->mutex);
2869
2870 return ret;
2871 }
2872
2873 int smu_get_uclk_dpm_states(struct smu_context *smu,
2874 unsigned int *clock_values_in_khz,
2875 unsigned int *num_states)
2876 {
2877 int ret = 0;
2878
2879 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2880 return -EOPNOTSUPP;
2881
2882 mutex_lock(&smu->mutex);
2883
2884 if (smu->ppt_funcs->get_uclk_dpm_states)
2885 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2886
2887 mutex_unlock(&smu->mutex);
2888
2889 return ret;
2890 }
2891
2892 enum amd_pm_state_type smu_get_current_power_state(void *handle)
2893 {
2894 struct smu_context *smu = handle;
2895 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2896
2897 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2898 return -EOPNOTSUPP;
2899
2900 mutex_lock(&smu->mutex);
2901
2902 if (smu->ppt_funcs->get_current_power_state)
2903 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2904
2905 mutex_unlock(&smu->mutex);
2906
2907 return pm_state;
2908 }
2909
2910 int smu_get_dpm_clock_table(struct smu_context *smu,
2911 struct dpm_clocks *clock_table)
2912 {
2913 int ret = 0;
2914
2915 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2916 return -EOPNOTSUPP;
2917
2918 mutex_lock(&smu->mutex);
2919
2920 if (smu->ppt_funcs->get_dpm_clock_table)
2921 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2922
2923 mutex_unlock(&smu->mutex);
2924
2925 return ret;
2926 }
2927
2928 ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2929 {
2930 struct smu_context *smu = handle;
2931 ssize_t size;
2932
2933 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2934 return -EOPNOTSUPP;
2935
2936 if (!smu->ppt_funcs->get_gpu_metrics)
2937 return -EOPNOTSUPP;
2938
2939 mutex_lock(&smu->mutex);
2940
2941 size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2942
2943 mutex_unlock(&smu->mutex);
2944
2945 return size;
2946 }
2947
2948 int smu_enable_mgpu_fan_boost(void *handle)
2949 {
2950 struct smu_context *smu = handle;
2951 int ret = 0;
2952
2953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2954 return -EOPNOTSUPP;
2955
2956 mutex_lock(&smu->mutex);
2957
2958 if (smu->ppt_funcs->enable_mgpu_fan_boost)
2959 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2960
2961 mutex_unlock(&smu->mutex);
2962
2963 return ret;
2964 }
2965
2966 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
2967 {
2968 int ret = 0;
2969
2970 mutex_lock(&smu->mutex);
2971 if (smu->ppt_funcs->gfx_state_change_set)
2972 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2973 mutex_unlock(&smu->mutex);
2974
2975 return ret;
2976 }
2977
2978 int smu_set_light_sbr(struct smu_context *smu, bool enable)
2979 {
2980 int ret = 0;
2981
2982 mutex_lock(&smu->mutex);
2983 if (smu->ppt_funcs->set_light_sbr)
2984 ret = smu->ppt_funcs->set_light_sbr(smu, enable);
2985 mutex_unlock(&smu->mutex);
2986
2987 return ret;
2988 }
2989
2990
2991 static const struct amd_pm_funcs swsmu_pm_funcs = {
2992 /* export for sysfs */
2993 .set_fan_control_mode = smu_pp_set_fan_control_mode,
2994 .get_fan_control_mode = smu_get_fan_control_mode,
2995 .set_fan_speed_percent = smu_set_fan_speed_percent,
2996 .get_fan_speed_percent = smu_get_fan_speed_percent,
2997 .force_performance_level = smu_force_performance_level,
2998 .read_sensor = smu_read_sensor,
2999 .get_performance_level = smu_get_performance_level,
3000 .get_current_power_state = smu_get_current_power_state,
3001 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3002 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3003 .get_pp_num_states = smu_get_power_num_states,
3004 .get_pp_table = smu_sys_get_pp_table,
3005 .set_pp_table = smu_sys_set_pp_table,
3006 .switch_power_profile = smu_switch_power_profile,
3007 /* export to amdgpu */
3008 .dispatch_tasks = smu_handle_dpm_task,
3009 .set_powergating_by_smu = smu_dpm_set_power_gate,
3010 .set_power_limit = smu_set_power_limit,
3011 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3012 .set_mp1_state = smu_set_mp1_state,
3013 /* export to DC */
3014 .get_sclk = smu_get_sclk,
3015 .get_mclk = smu_get_mclk,
3016 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3017 .get_asic_baco_capability = smu_get_baco_capability,
3018 .set_asic_baco_state = smu_baco_set_state,
3019 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3020 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3021 .asic_reset_mode_2 = smu_mode2_reset,
3022 .set_df_cstate = smu_set_df_cstate,
3023 .set_xgmi_pstate = smu_set_xgmi_pstate,
3024 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3025 .set_power_profile_mode = smu_set_power_profile_mode,
3026 .get_power_profile_mode = smu_get_power_profile_mode,
3027 .force_clock_level = smu_force_ppclk_levels,
3028 .print_clock_levels = smu_print_ppclk_levels,
3029 };
Ubuntu Jammy Linux kernel mirror