2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
35 #include "ppatomctrl.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
75 #define SMC_RAM_END 0x40000
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
84 #define VDDC_VDDCI_DELTA 200
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
102 static const uint16_t polaris10_clock_stretcher_lookup_table
[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table
[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion
[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
116 DPM_EVENT_SRC_ANALOG
= 0,
117 DPM_EVENT_SRC_EXTERNAL
= 1,
118 DPM_EVENT_SRC_DIGITAL
= 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
= 4
123 static const unsigned long PhwPolaris10_Magic
= (unsigned long)(PHM_VIslands_Magic
);
125 struct polaris10_power_state
*cast_phw_polaris10_power_state(
126 struct pp_hw_power_state
*hw_ps
)
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic
== hw_ps
->magic
),
129 "Invalid Powerstate Type!",
132 return (struct polaris10_power_state
*)hw_ps
;
135 const struct polaris10_power_state
*cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state
*hw_ps
)
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic
== hw_ps
->magic
),
139 "Invalid Powerstate Type!",
142 return (const struct polaris10_power_state
*)hw_ps
;
145 static bool polaris10_is_dpm_running(struct pp_hwmgr
*hwmgr
)
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr
->device
,
148 CGS_IND_REG__SMC
, FEATURE_STATUS
, VOLTAGE_CONTROLLER_ON
))
153 * Find the MC microcode version and store it in the HwMgr struct
155 * @param hwmgr the address of the powerplay hardware manager.
158 int phm_get_mc_microcode_version (struct pp_hwmgr
*hwmgr
)
160 cgs_write_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_INDEX
, 0x9F);
162 hwmgr
->microcode_version_info
.MC
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_DATA
);
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
169 uint32_t speedCntl
= 0;
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__PCIE
,
173 ixPCIE_LC_SPEED_CNTL
);
174 return((uint16_t)PHM_GET_FIELD(speedCntl
,
175 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr
*hwmgr
)
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width
= PHM_READ_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
184 PCIE_LC_LINK_WIDTH_CNTL
, LC_LINK_WIDTH_RD
);
186 PP_ASSERT_WITH_CODE((7 >= link_width
),
187 "Invalid PCIe lane width!", return 0);
189 return decode_pcie_lane_width(link_width
);
193 * Enable voltage control
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr
*hwmgr
)
201 (hwmgr
->smumgr
->smumgr_funcs
->send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_Voltage_Cntl_Enable
) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
210 * Checks if we want to support voltage control
212 * @param hwmgr the address of the powerplay hardware manager.
214 static bool polaris10_voltage_control(const struct pp_hwmgr
*hwmgr
)
216 const struct polaris10_hwmgr
*data
=
217 (const struct polaris10_hwmgr
*)(hwmgr
->backend
);
219 return (POLARIS10_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
);
223 * Enable voltage control
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int polaris10_enable_voltage_control(struct pp_hwmgr
*hwmgr
)
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
232 GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, 1);
238 * Create Voltage Tables.
240 * @param hwmgr the address of the powerplay hardware manager.
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
245 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
246 struct phm_ppt_v1_information
*table_info
=
247 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
251 result
= atomctrl_get_voltage_table_v3(hwmgr
,
252 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
,
253 &(data
->mvdd_voltage_table
));
254 PP_ASSERT_WITH_CODE((0 == result
),
255 "Failed to retrieve MVDD table.",
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
258 result
= phm_get_svi2_mvdd_voltage_table(&(data
->mvdd_voltage_table
),
259 table_info
->vdd_dep_on_mclk
);
260 PP_ASSERT_WITH_CODE((0 == result
),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
266 result
= atomctrl_get_voltage_table_v3(hwmgr
,
267 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
,
268 &(data
->vddci_voltage_table
));
269 PP_ASSERT_WITH_CODE((0 == result
),
270 "Failed to retrieve VDDCI table.",
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
273 result
= phm_get_svi2_vddci_voltage_table(&(data
->vddci_voltage_table
),
274 table_info
->vdd_dep_on_mclk
);
275 PP_ASSERT_WITH_CODE((0 == result
),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
281 result
= phm_get_svi2_vdd_voltage_table(&(data
->vddc_voltage_table
),
282 table_info
->vddc_lookup_table
);
283 PP_ASSERT_WITH_CODE((0 == result
),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
289 (data
->vddc_voltage_table
.count
<= (SMU74_MAX_LEVELS_VDDC
)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC
,
292 &(data
->vddc_voltage_table
)));
295 (data
->vddci_voltage_table
.count
<= (SMU74_MAX_LEVELS_VDDCI
)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI
,
298 &(data
->vddci_voltage_table
)));
301 (data
->mvdd_voltage_table
.count
<= (SMU74_MAX_LEVELS_MVDD
)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD
,
304 &(data
->mvdd_voltage_table
)));
310 * Programs static screed detection parameters
312 * @param hwmgr the address of the powerplay hardware manager.
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr
*hwmgr
)
318 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
322 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD_UNIT
,
323 data
->static_screen_threshold_unit
);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
326 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD
,
327 data
->static_screen_threshold
);
333 * Setup display gap for glitch free memory clock switching.
335 * @param hwmgr the address of the powerplay hardware manager.
338 static int polaris10_enable_display_gap(struct pp_hwmgr
*hwmgr
)
340 uint32_t display_gap
=
341 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
342 ixCG_DISPLAY_GAP_CNTL
);
344 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
,
345 DISP_GAP
, DISPLAY_GAP_IGNORE
);
347 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
,
348 DISP_GAP_MCHG
, DISPLAY_GAP_VBLANK
);
350 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
351 ixCG_DISPLAY_GAP_CNTL
, display_gap
);
357 * Programs activity state transition voting clients
359 * @param hwmgr the address of the powerplay hardware manager.
362 static int polaris10_program_voting_clients(struct pp_hwmgr
*hwmgr
)
364 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
368 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
370 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 0);
372 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
373 ixCG_FREQ_TRAN_VOTING_0
, data
->voting_rights_clients0
);
374 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
375 ixCG_FREQ_TRAN_VOTING_1
, data
->voting_rights_clients1
);
376 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
377 ixCG_FREQ_TRAN_VOTING_2
, data
->voting_rights_clients2
);
378 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
379 ixCG_FREQ_TRAN_VOTING_3
, data
->voting_rights_clients3
);
380 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
381 ixCG_FREQ_TRAN_VOTING_4
, data
->voting_rights_clients4
);
382 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
383 ixCG_FREQ_TRAN_VOTING_5
, data
->voting_rights_clients5
);
384 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
385 ixCG_FREQ_TRAN_VOTING_6
, data
->voting_rights_clients6
);
386 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
387 ixCG_FREQ_TRAN_VOTING_7
, data
->voting_rights_clients7
);
393 * Get the location of various tables inside the FW image.
395 * @param hwmgr the address of the powerplay hardware manager.
398 static int polaris10_process_firmware_header(struct pp_hwmgr
*hwmgr
)
400 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
401 struct polaris10_smumgr
*smu_data
= (struct polaris10_smumgr
*)(hwmgr
->smumgr
->backend
);
406 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
407 SMU7_FIRMWARE_HEADER_LOCATION
+
408 offsetof(SMU74_Firmware_Header
, DpmTable
),
409 &tmp
, data
->sram_end
);
412 data
->dpm_table_start
= tmp
;
414 error
|= (0 != result
);
416 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
417 SMU7_FIRMWARE_HEADER_LOCATION
+
418 offsetof(SMU74_Firmware_Header
, SoftRegisters
),
419 &tmp
, data
->sram_end
);
422 data
->soft_regs_start
= tmp
;
423 smu_data
->soft_regs_start
= tmp
;
426 error
|= (0 != result
);
428 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
429 SMU7_FIRMWARE_HEADER_LOCATION
+
430 offsetof(SMU74_Firmware_Header
, mcRegisterTable
),
431 &tmp
, data
->sram_end
);
434 data
->mc_reg_table_start
= tmp
;
436 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
437 SMU7_FIRMWARE_HEADER_LOCATION
+
438 offsetof(SMU74_Firmware_Header
, FanTable
),
439 &tmp
, data
->sram_end
);
442 data
->fan_table_start
= tmp
;
444 error
|= (0 != result
);
446 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
447 SMU7_FIRMWARE_HEADER_LOCATION
+
448 offsetof(SMU74_Firmware_Header
, mcArbDramTimingTable
),
449 &tmp
, data
->sram_end
);
452 data
->arb_table_start
= tmp
;
454 error
|= (0 != result
);
456 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
457 SMU7_FIRMWARE_HEADER_LOCATION
+
458 offsetof(SMU74_Firmware_Header
, Version
),
459 &tmp
, data
->sram_end
);
462 hwmgr
->microcode_version_info
.SMC
= tmp
;
464 error
|= (0 != result
);
466 return error
? -1 : 0;
469 /* Copy one arb setting to another and then switch the active set.
470 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr
*hwmgr
,
473 uint32_t arb_src
, uint32_t arb_dest
)
475 uint32_t mc_arb_dram_timing
;
476 uint32_t mc_arb_dram_timing2
;
478 uint32_t mc_cg_config
;
481 case MC_CG_ARB_FREQ_F0
:
482 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
483 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
484 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
486 case MC_CG_ARB_FREQ_F1
:
487 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
);
488 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
);
489 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
);
496 case MC_CG_ARB_FREQ_F0
:
497 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
498 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
499 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
, burst_time
);
501 case MC_CG_ARB_FREQ_F1
:
502 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
503 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
504 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
, burst_time
);
510 mc_cg_config
= cgs_read_register(hwmgr
->device
, mmMC_CG_CONFIG
);
511 mc_cg_config
|= 0x0000000F;
512 cgs_write_register(hwmgr
->device
, mmMC_CG_CONFIG
, mc_cg_config
);
513 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_CG
, CG_ARB_REQ
, arb_dest
);
519 * Initial switch from ARB F0->F1
521 * @param hwmgr the address of the powerplay hardware manager.
523 * This function is to be called from the SetPowerState table.
525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr
*hwmgr
)
527 return polaris10_copy_and_switch_arb_sets(hwmgr
,
528 MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr
*hwmgr
)
533 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
534 struct phm_ppt_v1_information
*table_info
=
535 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
536 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
537 uint32_t i
, max_entry
;
539 PP_ASSERT_WITH_CODE((data
->use_pcie_performance_levels
||
540 data
->use_pcie_power_saving_levels
), "No pcie performance levels!",
543 if (data
->use_pcie_performance_levels
&&
544 !data
->use_pcie_power_saving_levels
) {
545 data
->pcie_gen_power_saving
= data
->pcie_gen_performance
;
546 data
->pcie_lane_power_saving
= data
->pcie_lane_performance
;
547 } else if (!data
->use_pcie_performance_levels
&&
548 data
->use_pcie_power_saving_levels
) {
549 data
->pcie_gen_performance
= data
->pcie_gen_power_saving
;
550 data
->pcie_lane_performance
= data
->pcie_lane_power_saving
;
553 phm_reset_single_dpm_table(&data
->dpm_table
.pcie_speed_table
,
554 SMU74_MAX_LEVELS_LINK
,
555 MAX_REGULAR_DPM_NUMBER
);
557 if (pcie_table
!= NULL
) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry
= (SMU74_MAX_LEVELS_LINK
< pcie_table
->count
) ?
563 SMU74_MAX_LEVELS_LINK
: pcie_table
->count
;
564 for (i
= 1; i
< max_entry
; i
++) {
565 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, i
- 1,
566 get_pcie_gen_support(data
->pcie_gen_cap
,
567 pcie_table
->entries
[i
].gen_speed
),
568 get_pcie_lane_support(data
->pcie_lane_cap
,
569 pcie_table
->entries
[i
].lane_width
));
571 data
->dpm_table
.pcie_speed_table
.count
= max_entry
- 1;
573 /* Setup BIF_SCLK levels */
574 for (i
= 0; i
< max_entry
; i
++)
575 data
->bif_sclk_table
[i
] = pcie_table
->entries
[i
].pcie_sclk
;
577 /* Hardcode Pcie Table */
578 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 0,
579 get_pcie_gen_support(data
->pcie_gen_cap
,
581 get_pcie_lane_support(data
->pcie_lane_cap
,
583 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 1,
584 get_pcie_gen_support(data
->pcie_gen_cap
,
586 get_pcie_lane_support(data
->pcie_lane_cap
,
588 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 2,
589 get_pcie_gen_support(data
->pcie_gen_cap
,
591 get_pcie_lane_support(data
->pcie_lane_cap
,
593 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 3,
594 get_pcie_gen_support(data
->pcie_gen_cap
,
596 get_pcie_lane_support(data
->pcie_lane_cap
,
598 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 4,
599 get_pcie_gen_support(data
->pcie_gen_cap
,
601 get_pcie_lane_support(data
->pcie_lane_cap
,
603 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 5,
604 get_pcie_gen_support(data
->pcie_gen_cap
,
606 get_pcie_lane_support(data
->pcie_lane_cap
,
609 data
->dpm_table
.pcie_speed_table
.count
= 6;
611 /* Populate last level for boot PCIE level, but do not increment count. */
612 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
,
613 data
->dpm_table
.pcie_speed_table
.count
,
614 get_pcie_gen_support(data
->pcie_gen_cap
,
616 get_pcie_lane_support(data
->pcie_lane_cap
,
623 * This function is to initalize all DPM state tables
624 * for SMU7 based on the dependency table.
625 * Dynamic state patching function will then trim these
626 * state tables to the allowed range based
627 * on the power policy or external client requests,
628 * such as UVD request, etc.
630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
632 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
633 struct phm_ppt_v1_information
*table_info
=
634 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
637 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_sclk_table
=
638 table_info
->vdd_dep_on_sclk
;
639 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
640 table_info
->vdd_dep_on_mclk
;
642 PP_ASSERT_WITH_CODE(dep_sclk_table
!= NULL
,
643 "SCLK dependency table is missing. This table is mandatory",
645 PP_ASSERT_WITH_CODE(dep_sclk_table
->count
>= 1,
646 "SCLK dependency table has to have is missing."
647 "This table is mandatory",
650 PP_ASSERT_WITH_CODE(dep_mclk_table
!= NULL
,
651 "MCLK dependency table is missing. This table is mandatory",
653 PP_ASSERT_WITH_CODE(dep_mclk_table
->count
>= 1,
654 "MCLK dependency table has to have is missing."
655 "This table is mandatory",
658 /* clear the state table to reset everything to default */
659 phm_reset_single_dpm_table(
660 &data
->dpm_table
.sclk_table
, SMU74_MAX_LEVELS_GRAPHICS
, MAX_REGULAR_DPM_NUMBER
);
661 phm_reset_single_dpm_table(
662 &data
->dpm_table
.mclk_table
, SMU74_MAX_LEVELS_MEMORY
, MAX_REGULAR_DPM_NUMBER
);
665 /* Initialize Sclk DPM table based on allow Sclk values */
666 data
->dpm_table
.sclk_table
.count
= 0;
667 for (i
= 0; i
< dep_sclk_table
->count
; i
++) {
668 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
- 1].value
!=
669 dep_sclk_table
->entries
[i
].clk
) {
671 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].value
=
672 dep_sclk_table
->entries
[i
].clk
;
674 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].enabled
=
675 (i
== 0) ? true : false;
676 data
->dpm_table
.sclk_table
.count
++;
680 /* Initialize Mclk DPM table based on allow Mclk values */
681 data
->dpm_table
.mclk_table
.count
= 0;
682 for (i
= 0; i
< dep_mclk_table
->count
; i
++) {
683 if (i
== 0 || data
->dpm_table
.mclk_table
.dpm_levels
684 [data
->dpm_table
.mclk_table
.count
- 1].value
!=
685 dep_mclk_table
->entries
[i
].clk
) {
686 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].value
=
687 dep_mclk_table
->entries
[i
].clk
;
688 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].enabled
=
689 (i
== 0) ? true : false;
690 data
->dpm_table
.mclk_table
.count
++;
694 /* setup PCIE gen speed levels */
695 polaris10_setup_default_pcie_table(hwmgr
);
697 /* save a copy of the default DPM table */
698 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
),
699 sizeof(struct polaris10_dpm_table
));
704 uint8_t convert_to_vid(uint16_t vddc
)
706 return (uint8_t) ((6200 - (vddc
* VOLTAGE_SCALE
)) / 25);
710 * Mvdd table preparation for SMC.
712 * @param *hwmgr The address of the hardware manager.
713 * @param *table The SMC DPM table structure to be populated.
716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr
*hwmgr
,
717 SMU74_Discrete_DpmTable
*table
)
719 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
720 uint32_t count
, level
;
722 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
723 count
= data
->mvdd_voltage_table
.count
;
724 if (count
> SMU_MAX_SMIO_LEVELS
)
725 count
= SMU_MAX_SMIO_LEVELS
;
726 for (level
= 0; level
< count
; level
++) {
727 table
->SmioTable2
.Pattern
[level
].Voltage
=
728 PP_HOST_TO_SMC_US(data
->mvdd_voltage_table
.entries
[count
].value
* VOLTAGE_SCALE
);
729 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
730 table
->SmioTable2
.Pattern
[level
].Smio
=
732 table
->Smio
[level
] |=
733 data
->mvdd_voltage_table
.entries
[level
].smio_low
;
735 table
->SmioMask2
= data
->vddci_voltage_table
.mask_low
;
737 table
->MvddLevelCount
= (uint32_t) PP_HOST_TO_SMC_UL(count
);
743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr
*hwmgr
,
744 struct SMU74_Discrete_DpmTable
*table
)
746 uint32_t count
, level
;
747 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
749 count
= data
->vddci_voltage_table
.count
;
751 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
752 if (count
> SMU_MAX_SMIO_LEVELS
)
753 count
= SMU_MAX_SMIO_LEVELS
;
754 for (level
= 0; level
< count
; ++level
) {
755 table
->SmioTable1
.Pattern
[level
].Voltage
=
756 PP_HOST_TO_SMC_US(data
->vddci_voltage_table
.entries
[level
].value
* VOLTAGE_SCALE
);
757 table
->SmioTable1
.Pattern
[level
].Smio
= (uint8_t) level
;
759 table
->Smio
[level
] |= data
->vddci_voltage_table
.entries
[level
].smio_low
;
763 table
->SmioMask1
= data
->vddci_voltage_table
.mask_low
;
769 * Preparation of vddc and vddgfx CAC tables for SMC.
771 * @param hwmgr the address of the hardware manager
772 * @param table the SMC DPM table structure to be populated
775 static int polaris10_populate_cac_table(struct pp_hwmgr
*hwmgr
,
776 struct SMU74_Discrete_DpmTable
*table
)
780 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
781 struct phm_ppt_v1_information
*table_info
=
782 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
783 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
=
784 table_info
->vddc_lookup_table
;
785 /* tables is already swapped, so in order to use the value from it,
786 * we need to swap it back.
787 * We are populating vddc CAC data to BapmVddc table
788 * in split and merged mode
790 for (count
= 0; count
< lookup_table
->count
; count
++) {
791 index
= phm_get_voltage_index(lookup_table
,
792 data
->vddc_voltage_table
.entries
[count
].value
);
793 table
->BapmVddcVidLoSidd
[count
] = convert_to_vid(lookup_table
->entries
[index
].us_cac_low
);
794 table
->BapmVddcVidHiSidd
[count
] = convert_to_vid(lookup_table
->entries
[index
].us_cac_mid
);
795 table
->BapmVddcVidHiSidd2
[count
] = convert_to_vid(lookup_table
->entries
[index
].us_cac_high
);
802 * Preparation of voltage tables for SMC.
804 * @param hwmgr the address of the hardware manager
805 * @param table the SMC DPM table structure to be populated
809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr
*hwmgr
,
810 struct SMU74_Discrete_DpmTable
*table
)
812 polaris10_populate_smc_vddci_table(hwmgr
, table
);
813 polaris10_populate_smc_mvdd_table(hwmgr
, table
);
814 polaris10_populate_cac_table(hwmgr
, table
);
819 static int polaris10_populate_ulv_level(struct pp_hwmgr
*hwmgr
,
820 struct SMU74_Discrete_Ulv
*state
)
822 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
823 struct phm_ppt_v1_information
*table_info
=
824 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
826 state
->CcPwrDynRm
= 0;
827 state
->CcPwrDynRm1
= 0;
829 state
->VddcOffset
= (uint16_t) table_info
->us_ulv_voltage_offset
;
830 state
->VddcOffsetVid
= (uint8_t)(table_info
->us_ulv_voltage_offset
*
831 VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
833 state
->VddcPhase
= (data
->vddc_phase_shed_control
) ? 0 : 1;
835 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm
);
836 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm1
);
837 CONVERT_FROM_HOST_TO_SMC_US(state
->VddcOffset
);
842 static int polaris10_populate_ulv_state(struct pp_hwmgr
*hwmgr
,
843 struct SMU74_Discrete_DpmTable
*table
)
845 return polaris10_populate_ulv_level(hwmgr
, &table
->Ulv
);
848 static int polaris10_populate_smc_link_level(struct pp_hwmgr
*hwmgr
,
849 struct SMU74_Discrete_DpmTable
*table
)
851 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
852 struct polaris10_dpm_table
*dpm_table
= &data
->dpm_table
;
855 /* Index (dpm_table->pcie_speed_table.count)
856 * is reserved for PCIE boot level. */
857 for (i
= 0; i
<= dpm_table
->pcie_speed_table
.count
; i
++) {
858 table
->LinkLevel
[i
].PcieGenSpeed
=
859 (uint8_t)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
860 table
->LinkLevel
[i
].PcieLaneCount
= (uint8_t)encode_pcie_lane_width(
861 dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
862 table
->LinkLevel
[i
].EnabledForActivity
= 1;
863 table
->LinkLevel
[i
].SPC
= (uint8_t)(data
->pcie_spc_cap
& 0xff);
864 table
->LinkLevel
[i
].DownThreshold
= PP_HOST_TO_SMC_UL(5);
865 table
->LinkLevel
[i
].UpThreshold
= PP_HOST_TO_SMC_UL(30);
868 data
->smc_state_table
.LinkLevelCount
=
869 (uint8_t)dpm_table
->pcie_speed_table
.count
;
870 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
871 phm_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
876 static uint32_t polaris10_get_xclk(struct pp_hwmgr
*hwmgr
)
878 uint32_t reference_clock
, tmp
;
879 struct cgs_display_info info
= {0};
880 struct cgs_mode_info mode_info
;
882 info
.mode_info
= &mode_info
;
884 tmp
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
);
889 cgs_get_active_displays_info(hwmgr
->device
, &info
);
890 reference_clock
= mode_info
.ref_clock
;
892 tmp
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
);
895 return reference_clock
/ 4;
897 return reference_clock
;
901 * Calculates the SCLK dividers using the provided engine clock
903 * @param hwmgr the address of the hardware manager
904 * @param clock the engine clock to use to populate the structure
905 * @param sclk the SMC SCLK structure to be populated
907 static int polaris10_calculate_sclk_params(struct pp_hwmgr
*hwmgr
,
908 uint32_t clock
, SMU_SclkSetting
*sclk_setting
)
910 const struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
911 const SMU74_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
912 struct pp_atomctrl_clock_dividers_ai dividers
;
915 uint32_t pcc_target_percent
, pcc_target_freq
, ss_target_percent
, ss_target_freq
;
920 sclk_setting
->SclkFrequency
= clock
;
921 /* get the engine clock dividers for this clock value */
922 result
= atomctrl_get_engine_pll_dividers_ai(hwmgr
, clock
, ÷rs
);
924 sclk_setting
->Fcw_int
= dividers
.usSclk_fcw_int
;
925 sclk_setting
->Fcw_frac
= dividers
.usSclk_fcw_frac
;
926 sclk_setting
->Pcc_fcw_int
= dividers
.usPcc_fcw_int
;
927 sclk_setting
->PllRange
= dividers
.ucSclkPllRange
;
928 sclk_setting
->Sclk_slew_rate
= 0x400;
929 sclk_setting
->Pcc_up_slew_rate
= dividers
.usPcc_fcw_slew_frac
;
930 sclk_setting
->Pcc_down_slew_rate
= 0xffff;
931 sclk_setting
->SSc_En
= dividers
.ucSscEnable
;
932 sclk_setting
->Fcw1_int
= dividers
.usSsc_fcw1_int
;
933 sclk_setting
->Fcw1_frac
= dividers
.usSsc_fcw1_frac
;
934 sclk_setting
->Sclk_ss_slew_rate
= dividers
.usSsc_fcw_slew_frac
;
938 ref_clock
= polaris10_get_xclk(hwmgr
);
940 for (i
= 0; i
< NUM_SCLK_RANGE
; i
++) {
941 if (clock
> data
->range_table
[i
].trans_lower_frequency
942 && clock
<= data
->range_table
[i
].trans_upper_frequency
) {
943 sclk_setting
->PllRange
= i
;
948 sclk_setting
->Fcw_int
= (uint16_t)((clock
<< table
->SclkFcwRangeTable
[sclk_setting
->PllRange
].postdiv
) / ref_clock
);
949 temp
= clock
<< table
->SclkFcwRangeTable
[sclk_setting
->PllRange
].postdiv
;
951 do_div(temp
, ref_clock
);
952 sclk_setting
->Fcw_frac
= temp
& 0xffff;
954 pcc_target_percent
= 10; /* Hardcode 10% for now. */
955 pcc_target_freq
= clock
- (clock
* pcc_target_percent
/ 100);
956 sclk_setting
->Pcc_fcw_int
= (uint16_t)((pcc_target_freq
<< table
->SclkFcwRangeTable
[sclk_setting
->PllRange
].postdiv
) / ref_clock
);
958 ss_target_percent
= 2; /* Hardcode 2% for now. */
959 sclk_setting
->SSc_En
= 0;
960 if (ss_target_percent
) {
961 sclk_setting
->SSc_En
= 1;
962 ss_target_freq
= clock
- (clock
* ss_target_percent
/ 100);
963 sclk_setting
->Fcw1_int
= (uint16_t)((ss_target_freq
<< table
->SclkFcwRangeTable
[sclk_setting
->PllRange
].postdiv
) / ref_clock
);
964 temp
= ss_target_freq
<< table
->SclkFcwRangeTable
[sclk_setting
->PllRange
].postdiv
;
966 do_div(temp
, ref_clock
);
967 sclk_setting
->Fcw1_frac
= temp
& 0xffff;
973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr
*hwmgr
,
974 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_table
,
975 uint32_t clock
, SMU_VoltageLevel
*voltage
, uint32_t *mvdd
)
979 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
981 *voltage
= *mvdd
= 0;
983 /* clock - voltage dependency table is empty table */
984 if (dep_table
->count
== 0)
987 for (i
= 0; i
< dep_table
->count
; i
++) {
988 /* find first sclk bigger than request */
989 if (dep_table
->entries
[i
].clk
>= clock
) {
990 *voltage
|= (dep_table
->entries
[i
].vddc
*
991 VOLTAGE_SCALE
) << VDDC_SHIFT
;
992 if (POLARIS10_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
993 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
994 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
995 else if (dep_table
->entries
[i
].vddci
)
996 *voltage
|= (dep_table
->entries
[i
].vddci
*
997 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
999 vddci
= phm_find_closest_vddci(&(data
->vddci_voltage_table
),
1000 (dep_table
->entries
[i
].vddc
-
1001 (uint16_t)data
->vddc_vddci_delta
));
1002 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1005 if (POLARIS10_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1006 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
1008 else if (dep_table
->entries
[i
].mvdd
)
1009 *mvdd
= (uint32_t) dep_table
->entries
[i
].mvdd
*
1012 *voltage
|= 1 << PHASES_SHIFT
;
1017 /* sclk is bigger than max sclk in the dependence table */
1018 *voltage
|= (dep_table
->entries
[i
- 1].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
1020 if (POLARIS10_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1021 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
1022 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1023 else if (dep_table
->entries
[i
-1].vddci
) {
1024 vddci
= phm_find_closest_vddci(&(data
->vddci_voltage_table
),
1025 (dep_table
->entries
[i
].vddc
-
1026 (uint16_t)data
->vddc_vddci_delta
));
1027 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1030 if (POLARIS10_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1031 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
* VOLTAGE_SCALE
;
1032 else if (dep_table
->entries
[i
].mvdd
)
1033 *mvdd
= (uint32_t) dep_table
->entries
[i
- 1].mvdd
* VOLTAGE_SCALE
;
1038 static const sclkFcwRange_t Range_Table
[NUM_SCLK_RANGE
] =
1039 { {VCO_2_4
, POSTDIV_DIV_BY_16
, 75, 160, 112},
1040 {VCO_3_6
, POSTDIV_DIV_BY_16
, 112, 224, 160},
1041 {VCO_2_4
, POSTDIV_DIV_BY_8
, 75, 160, 112},
1042 {VCO_3_6
, POSTDIV_DIV_BY_8
, 112, 224, 160},
1043 {VCO_2_4
, POSTDIV_DIV_BY_4
, 75, 160, 112},
1044 {VCO_3_6
, POSTDIV_DIV_BY_4
, 112, 216, 160},
1045 {VCO_2_4
, POSTDIV_DIV_BY_2
, 75, 160, 108},
1046 {VCO_3_6
, POSTDIV_DIV_BY_2
, 112, 216, 160} };
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr
*hwmgr
)
1050 uint32_t i
, ref_clk
;
1051 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1052 SMU74_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
1053 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios
= { { {0} } };
1055 ref_clk
= polaris10_get_xclk(hwmgr
);
1057 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr
, &range_table_from_vbios
)) {
1058 for (i
= 0; i
< NUM_SCLK_RANGE
; i
++) {
1059 table
->SclkFcwRangeTable
[i
].vco_setting
= range_table_from_vbios
.entry
[i
].ucVco_setting
;
1060 table
->SclkFcwRangeTable
[i
].postdiv
= range_table_from_vbios
.entry
[i
].ucPostdiv
;
1061 table
->SclkFcwRangeTable
[i
].fcw_pcc
= range_table_from_vbios
.entry
[i
].usFcw_pcc
;
1063 table
->SclkFcwRangeTable
[i
].fcw_trans_upper
= range_table_from_vbios
.entry
[i
].usFcw_trans_upper
;
1064 table
->SclkFcwRangeTable
[i
].fcw_trans_lower
= range_table_from_vbios
.entry
[i
].usRcw_trans_lower
;
1066 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_pcc
);
1067 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_trans_upper
);
1068 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_trans_lower
);
1073 for (i
= 0; i
< NUM_SCLK_RANGE
; i
++) {
1075 data
->range_table
[i
].trans_lower_frequency
= (ref_clk
* Range_Table
[i
].fcw_trans_lower
) >> Range_Table
[i
].postdiv
;
1076 data
->range_table
[i
].trans_upper_frequency
= (ref_clk
* Range_Table
[i
].fcw_trans_upper
) >> Range_Table
[i
].postdiv
;
1078 table
->SclkFcwRangeTable
[i
].vco_setting
= Range_Table
[i
].vco_setting
;
1079 table
->SclkFcwRangeTable
[i
].postdiv
= Range_Table
[i
].postdiv
;
1080 table
->SclkFcwRangeTable
[i
].fcw_pcc
= Range_Table
[i
].fcw_pcc
;
1082 table
->SclkFcwRangeTable
[i
].fcw_trans_upper
= Range_Table
[i
].fcw_trans_upper
;
1083 table
->SclkFcwRangeTable
[i
].fcw_trans_lower
= Range_Table
[i
].fcw_trans_lower
;
1085 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_pcc
);
1086 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_trans_upper
);
1087 CONVERT_FROM_HOST_TO_SMC_US(table
->SclkFcwRangeTable
[i
].fcw_trans_lower
);
1092 * Populates single SMC SCLK structure using the provided engine clock
1094 * @param hwmgr the address of the hardware manager
1095 * @param clock the engine clock to use to populate the structure
1096 * @param sclk the SMC SCLK structure to be populated
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr
*hwmgr
,
1100 uint32_t clock
, uint16_t sclk_al_threshold
,
1101 struct SMU74_Discrete_GraphicsLevel
*level
)
1103 int result
, i
, temp
;
1104 /* PP_Clocks minClocks; */
1106 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1107 struct phm_ppt_v1_information
*table_info
=
1108 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1109 SMU_SclkSetting curr_sclk_setting
= { 0 };
1111 result
= polaris10_calculate_sclk_params(hwmgr
, clock
, &curr_sclk_setting
);
1113 /* populate graphics levels */
1114 result
= polaris10_get_dependency_volt_by_clk(hwmgr
,
1115 table_info
->vdd_dep_on_sclk
, clock
,
1116 &level
->MinVoltage
, &mvdd
);
1118 PP_ASSERT_WITH_CODE((0 == result
),
1119 "can not find VDDC voltage value for "
1120 "VDDC engine clock dependency table",
1122 level
->ActivityLevel
= sclk_al_threshold
;
1124 level
->CcPwrDynRm
= 0;
1125 level
->CcPwrDynRm1
= 0;
1126 level
->EnabledForActivity
= 0;
1127 level
->EnabledForThrottle
= 1;
1129 level
->DownHyst
= 0;
1130 level
->VoltageDownHyst
= 0;
1131 level
->PowerThrottle
= 0;
1134 * TODO: get minimum clocks from dal configaration
1135 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1137 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1139 /* get level->DeepSleepDivId
1140 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1143 PP_ASSERT_WITH_CODE((clock
>= POLARIS10_MINIMUM_ENGINE_CLOCK
), "Engine clock can't satisfy stutter requirement!", return 0);
1144 for (i
= POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID
; ; i
--) {
1147 if (temp
>= POLARIS10_MINIMUM_ENGINE_CLOCK
|| i
== 0)
1151 level
->DeepSleepDivId
= i
;
1153 /* Default to slow, highest DPM level will be
1154 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1156 if (data
->update_up_hyst
)
1157 level
->UpHyst
= (uint8_t)data
->up_hyst
;
1158 if (data
->update_down_hyst
)
1159 level
->DownHyst
= (uint8_t)data
->down_hyst
;
1161 level
->SclkSetting
= curr_sclk_setting
;
1163 CONVERT_FROM_HOST_TO_SMC_UL(level
->MinVoltage
);
1164 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm
);
1165 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm1
);
1166 CONVERT_FROM_HOST_TO_SMC_US(level
->ActivityLevel
);
1167 CONVERT_FROM_HOST_TO_SMC_UL(level
->SclkSetting
.SclkFrequency
);
1168 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Fcw_int
);
1169 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Fcw_frac
);
1170 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Pcc_fcw_int
);
1171 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Sclk_slew_rate
);
1172 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Pcc_up_slew_rate
);
1173 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Pcc_down_slew_rate
);
1174 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Fcw1_int
);
1175 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Fcw1_frac
);
1176 CONVERT_FROM_HOST_TO_SMC_US(level
->SclkSetting
.Sclk_ss_slew_rate
);
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1183 * @param hwmgr the address of the hardware manager
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
1187 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1188 struct polaris10_dpm_table
*dpm_table
= &data
->dpm_table
;
1189 struct phm_ppt_v1_information
*table_info
=
1190 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1191 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
1192 uint8_t pcie_entry_cnt
= (uint8_t) data
->dpm_table
.pcie_speed_table
.count
;
1194 uint32_t array
= data
->dpm_table_start
+
1195 offsetof(SMU74_Discrete_DpmTable
, GraphicsLevel
);
1196 uint32_t array_size
= sizeof(struct SMU74_Discrete_GraphicsLevel
) *
1197 SMU74_MAX_LEVELS_GRAPHICS
;
1198 struct SMU74_Discrete_GraphicsLevel
*levels
=
1199 data
->smc_state_table
.GraphicsLevel
;
1200 uint32_t i
, max_entry
;
1201 uint8_t hightest_pcie_level_enabled
= 0,
1202 lowest_pcie_level_enabled
= 0,
1203 mid_pcie_level_enabled
= 0,
1206 polaris10_get_sclk_range_table(hwmgr
);
1208 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
1210 result
= polaris10_populate_single_graphic_level(hwmgr
,
1211 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
1212 (uint16_t)data
->activity_target
[i
],
1213 &(data
->smc_state_table
.GraphicsLevel
[i
]));
1217 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1219 levels
[i
].DeepSleepDivId
= 0;
1221 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1222 PHM_PlatformCaps_SPLLShutdownSupport
))
1223 data
->smc_state_table
.GraphicsLevel
[0].SclkSetting
.SSc_En
= 0;
1225 data
->smc_state_table
.GraphicsLevel
[0].EnabledForActivity
= 1;
1226 data
->smc_state_table
.GraphicsDpmLevelCount
=
1227 (uint8_t)dpm_table
->sclk_table
.count
;
1228 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
1229 phm_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
1232 if (pcie_table
!= NULL
) {
1233 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt
),
1234 "There must be 1 or more PCIE levels defined in PPTable.",
1236 max_entry
= pcie_entry_cnt
- 1;
1237 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++)
1238 levels
[i
].pcieDpmLevel
=
1239 (uint8_t) ((i
< max_entry
) ? i
: max_entry
);
1241 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
1242 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1243 (1 << (hightest_pcie_level_enabled
+ 1))) != 0))
1244 hightest_pcie_level_enabled
++;
1246 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
1247 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1248 (1 << lowest_pcie_level_enabled
)) == 0))
1249 lowest_pcie_level_enabled
++;
1251 while ((count
< hightest_pcie_level_enabled
) &&
1252 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1253 (1 << (lowest_pcie_level_enabled
+ 1 + count
))) == 0))
1256 mid_pcie_level_enabled
= (lowest_pcie_level_enabled
+ 1 + count
) <
1257 hightest_pcie_level_enabled
?
1258 (lowest_pcie_level_enabled
+ 1 + count
) :
1259 hightest_pcie_level_enabled
;
1261 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262 for (i
= 2; i
< dpm_table
->sclk_table
.count
; i
++)
1263 levels
[i
].pcieDpmLevel
= hightest_pcie_level_enabled
;
1265 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266 levels
[0].pcieDpmLevel
= lowest_pcie_level_enabled
;
1268 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269 levels
[1].pcieDpmLevel
= mid_pcie_level_enabled
;
1271 /* level count will send to smc once at init smc table and never change */
1272 result
= polaris10_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
1273 (uint32_t)array_size
, data
->sram_end
);
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr
*hwmgr
,
1279 uint32_t clock
, struct SMU74_Discrete_MemoryLevel
*mem_level
)
1281 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1282 struct phm_ppt_v1_information
*table_info
=
1283 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1285 struct cgs_display_info info
= {0, 0, NULL
};
1287 cgs_get_active_displays_info(hwmgr
->device
, &info
);
1289 if (table_info
->vdd_dep_on_mclk
) {
1290 result
= polaris10_get_dependency_volt_by_clk(hwmgr
,
1291 table_info
->vdd_dep_on_mclk
, clock
,
1292 &mem_level
->MinVoltage
, &mem_level
->MinMvdd
);
1293 PP_ASSERT_WITH_CODE((0 == result
),
1294 "can not find MinVddc voltage value from memory "
1295 "VDDC voltage dependency table", return result
);
1298 mem_level
->MclkFrequency
= clock
;
1299 mem_level
->StutterEnable
= 0;
1300 mem_level
->EnabledForThrottle
= 1;
1301 mem_level
->EnabledForActivity
= 0;
1302 mem_level
->UpHyst
= 0;
1303 mem_level
->DownHyst
= 100;
1304 mem_level
->VoltageDownHyst
= 0;
1305 mem_level
->ActivityLevel
= (uint16_t)data
->mclk_activity_target
;
1306 mem_level
->StutterEnable
= false;
1308 mem_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1310 data
->display_timing
.num_existing_displays
= info
.display_count
;
1312 if ((data
->mclk_stutter_mode_threshold
) &&
1313 (clock
<= data
->mclk_stutter_mode_threshold
) &&
1314 (PHM_READ_FIELD(hwmgr
->device
, DPG_PIPE_STUTTER_CONTROL
,
1315 STUTTER_ENABLE
) & 0x1))
1316 mem_level
->StutterEnable
= true;
1319 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinMvdd
);
1320 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MclkFrequency
);
1321 CONVERT_FROM_HOST_TO_SMC_US(mem_level
->ActivityLevel
);
1322 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinVoltage
);
1328 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1330 * @param hwmgr the address of the hardware manager
1332 static int polaris10_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
1334 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1335 struct polaris10_dpm_table
*dpm_table
= &data
->dpm_table
;
1337 /* populate MCLK dpm table to SMU7 */
1338 uint32_t array
= data
->dpm_table_start
+
1339 offsetof(SMU74_Discrete_DpmTable
, MemoryLevel
);
1340 uint32_t array_size
= sizeof(SMU74_Discrete_MemoryLevel
) *
1341 SMU74_MAX_LEVELS_MEMORY
;
1342 struct SMU74_Discrete_MemoryLevel
*levels
=
1343 data
->smc_state_table
.MemoryLevel
;
1346 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
1347 PP_ASSERT_WITH_CODE((0 != dpm_table
->mclk_table
.dpm_levels
[i
].value
),
1348 "can not populate memory level as memory clock is zero",
1350 result
= polaris10_populate_single_memory_level(hwmgr
,
1351 dpm_table
->mclk_table
.dpm_levels
[i
].value
,
1353 if (i
== dpm_table
->mclk_table
.count
- 1) {
1354 levels
[i
].DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_HIGH
;
1355 levels
[i
].EnabledForActivity
= 1;
1361 /* in order to prevent MC activity from stutter mode to push DPM up.
1362 * the UVD change complements this by putting the MCLK in
1363 * a higher state by default such that we are not effected by
1364 * up threshold or and MCLK DPM latency.
1366 levels
[0].ActivityLevel
= (uint16_t)data
->mclk_dpm0_activity_target
;
1367 CONVERT_FROM_HOST_TO_SMC_US(levels
[0].ActivityLevel
);
1369 data
->smc_state_table
.MemoryDpmLevelCount
=
1370 (uint8_t)dpm_table
->mclk_table
.count
;
1371 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
1372 phm_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
1374 /* level count will send to smc once at init smc table and never change */
1375 result
= polaris10_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
1376 (uint32_t)array_size
, data
->sram_end
);
1382 * Populates the SMC MVDD structure using the provided memory clock.
1384 * @param hwmgr the address of the hardware manager
1385 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1386 * @param voltage the SMC VOLTAGE structure to be populated
1388 int polaris10_populate_mvdd_value(struct pp_hwmgr
*hwmgr
,
1389 uint32_t mclk
, SMIO_Pattern
*smio_pat
)
1391 const struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1392 struct phm_ppt_v1_information
*table_info
=
1393 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1396 if (POLARIS10_VOLTAGE_CONTROL_NONE
!= data
->mvdd_control
) {
1397 /* find mvdd value which clock is more than request */
1398 for (i
= 0; i
< table_info
->vdd_dep_on_mclk
->count
; i
++) {
1399 if (mclk
<= table_info
->vdd_dep_on_mclk
->entries
[i
].clk
) {
1400 smio_pat
->Voltage
= data
->mvdd_voltage_table
.entries
[i
].value
;
1404 PP_ASSERT_WITH_CODE(i
< table_info
->vdd_dep_on_mclk
->count
,
1405 "MVDD Voltage is outside the supported range.",
1413 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr
*hwmgr
,
1414 SMU74_Discrete_DpmTable
*table
)
1417 uint32_t sclk_frequency
;
1418 const struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1419 struct phm_ppt_v1_information
*table_info
=
1420 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1421 SMIO_Pattern vol_level
;
1425 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
1427 if (!data
->sclk_dpm_key_disabled
) {
1428 /* Get MinVoltage and Frequency from DPM0,
1429 * already converted to SMC_UL */
1430 sclk_frequency
= data
->dpm_table
.sclk_table
.dpm_levels
[0].value
;
1431 result
= polaris10_get_dependency_volt_by_clk(hwmgr
,
1432 table_info
->vdd_dep_on_sclk
,
1433 table
->ACPILevel
.SclkFrequency
,
1434 &table
->ACPILevel
.MinVoltage
, &mvdd
);
1435 PP_ASSERT_WITH_CODE((0 == result
),
1436 "Cannot find ACPI VDDC voltage value "
1437 "in Clock Dependency Table", );
1439 sclk_frequency
= data
->vbios_boot_state
.sclk_bootup_value
;
1440 table
->ACPILevel
.MinVoltage
=
1441 data
->vbios_boot_state
.vddc_bootup_value
* VOLTAGE_SCALE
;
1444 result
= polaris10_calculate_sclk_params(hwmgr
, sclk_frequency
, &(table
->ACPILevel
.SclkSetting
));
1445 PP_ASSERT_WITH_CODE(result
== 0, "Error retrieving Engine Clock dividers from VBIOS.", return result
);
1447 table
->ACPILevel
.DeepSleepDivId
= 0;
1448 table
->ACPILevel
.CcPwrDynRm
= 0;
1449 table
->ACPILevel
.CcPwrDynRm1
= 0;
1451 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.Flags
);
1452 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.MinVoltage
);
1453 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm
);
1454 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm1
);
1456 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SclkSetting
.SclkFrequency
);
1457 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Fcw_int
);
1458 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Fcw_frac
);
1459 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Pcc_fcw_int
);
1460 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Sclk_slew_rate
);
1461 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Pcc_up_slew_rate
);
1462 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Pcc_down_slew_rate
);
1463 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Fcw1_int
);
1464 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Fcw1_frac
);
1465 CONVERT_FROM_HOST_TO_SMC_US(table
->ACPILevel
.SclkSetting
.Sclk_ss_slew_rate
);
1467 if (!data
->mclk_dpm_key_disabled
) {
1468 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1469 table
->MemoryACPILevel
.MclkFrequency
=
1470 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
;
1471 result
= polaris10_get_dependency_volt_by_clk(hwmgr
,
1472 table_info
->vdd_dep_on_mclk
,
1473 table
->MemoryACPILevel
.MclkFrequency
,
1474 &table
->MemoryACPILevel
.MinVoltage
, &mvdd
);
1475 PP_ASSERT_WITH_CODE((0 == result
),
1476 "Cannot find ACPI VDDCI voltage value "
1477 "in Clock Dependency Table",
1480 table
->MemoryACPILevel
.MclkFrequency
=
1481 data
->vbios_boot_state
.mclk_bootup_value
;
1482 table
->MemoryACPILevel
.MinVoltage
=
1483 data
->vbios_boot_state
.vddci_bootup_value
* VOLTAGE_SCALE
;
1487 if ((POLARIS10_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
) ||
1488 (data
->mclk_dpm_key_disabled
))
1489 us_mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
;
1491 if (!polaris10_populate_mvdd_value(hwmgr
,
1492 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
,
1494 us_mvdd
= vol_level
.Voltage
;
1497 if (0 == polaris10_populate_mvdd_value(hwmgr
, 0, &vol_level
))
1498 table
->MemoryACPILevel
.MinMvdd
= PP_HOST_TO_SMC_UL(vol_level
.Voltage
);
1500 table
->MemoryACPILevel
.MinMvdd
= 0;
1502 table
->MemoryACPILevel
.StutterEnable
= false;
1504 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
1505 table
->MemoryACPILevel
.EnabledForActivity
= 0;
1506 table
->MemoryACPILevel
.UpHyst
= 0;
1507 table
->MemoryACPILevel
.DownHyst
= 100;
1508 table
->MemoryACPILevel
.VoltageDownHyst
= 0;
1509 table
->MemoryACPILevel
.ActivityLevel
=
1510 PP_HOST_TO_SMC_US((uint16_t)data
->mclk_activity_target
);
1512 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MclkFrequency
);
1513 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MinVoltage
);
1518 static int polaris10_populate_smc_vce_level(struct pp_hwmgr
*hwmgr
,
1519 SMU74_Discrete_DpmTable
*table
)
1521 int result
= -EINVAL
;
1523 struct pp_atomctrl_clock_dividers_vi dividers
;
1524 struct phm_ppt_v1_information
*table_info
=
1525 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1526 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
1527 table_info
->mm_dep_table
;
1528 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1530 table
->VceLevelCount
= (uint8_t)(mm_table
->count
);
1531 table
->VceBootLevel
= 0;
1533 for (count
= 0; count
< table
->VceLevelCount
; count
++) {
1534 table
->VceLevel
[count
].Frequency
= mm_table
->entries
[count
].eclk
;
1535 table
->VceLevel
[count
].MinVoltage
= 0;
1536 table
->VceLevel
[count
].MinVoltage
|=
1537 (mm_table
->entries
[count
].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
1538 table
->VceLevel
[count
].MinVoltage
|=
1539 ((mm_table
->entries
[count
].vddc
- data
->vddc_vddci_delta
) *
1540 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1541 table
->VceLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
1543 /*retrieve divider value for VBIOS */
1544 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
1545 table
->VceLevel
[count
].Frequency
, ÷rs
);
1546 PP_ASSERT_WITH_CODE((0 == result
),
1547 "can not find divide id for VCE engine clock",
1550 table
->VceLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
1552 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].Frequency
);
1553 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].MinVoltage
);
1558 static int polaris10_populate_smc_samu_level(struct pp_hwmgr
*hwmgr
,
1559 SMU74_Discrete_DpmTable
*table
)
1561 int result
= -EINVAL
;
1563 struct pp_atomctrl_clock_dividers_vi dividers
;
1564 struct phm_ppt_v1_information
*table_info
=
1565 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1566 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
1567 table_info
->mm_dep_table
;
1568 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1570 table
->SamuBootLevel
= 0;
1571 table
->SamuLevelCount
= (uint8_t)(mm_table
->count
);
1573 for (count
= 0; count
< table
->SamuLevelCount
; count
++) {
1574 /* not sure whether we need evclk or not */
1575 table
->SamuLevel
[count
].MinVoltage
= 0;
1576 table
->SamuLevel
[count
].Frequency
= mm_table
->entries
[count
].samclock
;
1577 table
->SamuLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
1578 VOLTAGE_SCALE
) << VDDC_SHIFT
;
1579 table
->SamuLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
1580 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1581 table
->SamuLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
1583 /* retrieve divider value for VBIOS */
1584 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
1585 table
->SamuLevel
[count
].Frequency
, ÷rs
);
1586 PP_ASSERT_WITH_CODE((0 == result
),
1587 "can not find divide id for samu clock", return result
);
1589 table
->SamuLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
1591 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].Frequency
);
1592 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].MinVoltage
);
1597 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr
*hwmgr
,
1598 int32_t eng_clock
, int32_t mem_clock
,
1599 SMU74_Discrete_MCArbDramTimingTableEntry
*arb_regs
)
1601 uint32_t dram_timing
;
1602 uint32_t dram_timing2
;
1603 uint32_t burst_time
;
1606 result
= atomctrl_set_engine_dram_timings_rv770(hwmgr
,
1607 eng_clock
, mem_clock
);
1608 PP_ASSERT_WITH_CODE(result
== 0,
1609 "Error calling VBIOS to set DRAM_TIMING.", return result
);
1611 dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
1612 dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
1613 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
1616 arb_regs
->McArbDramTiming
= PP_HOST_TO_SMC_UL(dram_timing
);
1617 arb_regs
->McArbDramTiming2
= PP_HOST_TO_SMC_UL(dram_timing2
);
1618 arb_regs
->McArbBurstTime
= (uint8_t)burst_time
;
1623 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr
*hwmgr
)
1625 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1626 struct SMU74_Discrete_MCArbDramTimingTable arb_regs
;
1630 for (i
= 0; i
< data
->dpm_table
.sclk_table
.count
; i
++) {
1631 for (j
= 0; j
< data
->dpm_table
.mclk_table
.count
; j
++) {
1632 result
= polaris10_populate_memory_timing_parameters(hwmgr
,
1633 data
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
1634 data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
1635 &arb_regs
.entries
[i
][j
]);
1637 result
= atomctrl_set_ac_timing_ai(hwmgr
, data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
, j
);
1643 result
= polaris10_copy_bytes_to_smc(
1645 data
->arb_table_start
,
1646 (uint8_t *)&arb_regs
,
1647 sizeof(SMU74_Discrete_MCArbDramTimingTable
),
1652 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr
*hwmgr
,
1653 struct SMU74_Discrete_DpmTable
*table
)
1655 int result
= -EINVAL
;
1657 struct pp_atomctrl_clock_dividers_vi dividers
;
1658 struct phm_ppt_v1_information
*table_info
=
1659 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1660 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
1661 table_info
->mm_dep_table
;
1662 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1664 table
->UvdLevelCount
= (uint8_t)(mm_table
->count
);
1665 table
->UvdBootLevel
= 0;
1667 for (count
= 0; count
< table
->UvdLevelCount
; count
++) {
1668 table
->UvdLevel
[count
].MinVoltage
= 0;
1669 table
->UvdLevel
[count
].VclkFrequency
= mm_table
->entries
[count
].vclk
;
1670 table
->UvdLevel
[count
].DclkFrequency
= mm_table
->entries
[count
].dclk
;
1671 table
->UvdLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
1672 VOLTAGE_SCALE
) << VDDC_SHIFT
;
1673 table
->UvdLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
1674 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1675 table
->UvdLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
1677 /* retrieve divider value for VBIOS */
1678 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
1679 table
->UvdLevel
[count
].VclkFrequency
, ÷rs
);
1680 PP_ASSERT_WITH_CODE((0 == result
),
1681 "can not find divide id for Vclk clock", return result
);
1683 table
->UvdLevel
[count
].VclkDivider
= (uint8_t)dividers
.pll_post_divider
;
1685 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
1686 table
->UvdLevel
[count
].DclkFrequency
, ÷rs
);
1687 PP_ASSERT_WITH_CODE((0 == result
),
1688 "can not find divide id for Dclk clock", return result
);
1690 table
->UvdLevel
[count
].DclkDivider
= (uint8_t)dividers
.pll_post_divider
;
1692 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].VclkFrequency
);
1693 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].DclkFrequency
);
1694 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].MinVoltage
);
1700 static int polaris10_populate_smc_boot_level(struct pp_hwmgr
*hwmgr
,
1701 struct SMU74_Discrete_DpmTable
*table
)
1704 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1706 table
->GraphicsBootLevel
= 0;
1707 table
->MemoryBootLevel
= 0;
1709 /* find boot level from dpm table */
1710 result
= phm_find_boot_level(&(data
->dpm_table
.sclk_table
),
1711 data
->vbios_boot_state
.sclk_bootup_value
,
1712 (uint32_t *)&(table
->GraphicsBootLevel
));
1714 result
= phm_find_boot_level(&(data
->dpm_table
.mclk_table
),
1715 data
->vbios_boot_state
.mclk_bootup_value
,
1716 (uint32_t *)&(table
->MemoryBootLevel
));
1718 table
->BootVddc
= data
->vbios_boot_state
.vddc_bootup_value
*
1720 table
->BootVddci
= data
->vbios_boot_state
.vddci_bootup_value
*
1722 table
->BootMVdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
1725 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddc
);
1726 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddci
);
1727 CONVERT_FROM_HOST_TO_SMC_US(table
->BootMVdd
);
1733 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr
*hwmgr
)
1735 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1736 struct phm_ppt_v1_information
*table_info
=
1737 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1738 uint8_t count
, level
;
1740 count
= (uint8_t)(table_info
->vdd_dep_on_sclk
->count
);
1742 for (level
= 0; level
< count
; level
++) {
1743 if (table_info
->vdd_dep_on_sclk
->entries
[level
].clk
>=
1744 data
->vbios_boot_state
.sclk_bootup_value
) {
1745 data
->smc_state_table
.GraphicsBootLevel
= level
;
1750 count
= (uint8_t)(table_info
->vdd_dep_on_mclk
->count
);
1751 for (level
= 0; level
< count
; level
++) {
1752 if (table_info
->vdd_dep_on_mclk
->entries
[level
].clk
>=
1753 data
->vbios_boot_state
.mclk_bootup_value
) {
1754 data
->smc_state_table
.MemoryBootLevel
= level
;
1762 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr
*hwmgr
)
1764 uint32_t ro
, efuse
, efuse2
, clock_freq
, volt_without_cks
,
1765 volt_with_cks
, value
;
1766 uint16_t clock_freq_u16
;
1767 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1768 uint8_t type
, i
, j
, cks_setting
, stretch_amount
, stretch_amount2
,
1770 struct phm_ppt_v1_information
*table_info
=
1771 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1772 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
1773 table_info
->vdd_dep_on_sclk
;
1775 stretch_amount
= (uint8_t)table_info
->cac_dtp_table
->usClockStretchAmount
;
1777 /* Read SMU_Eefuse to read and calculate RO and determine
1778 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1780 efuse
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1781 ixSMU_EFUSE_0
+ (146 * 4));
1782 efuse2
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1783 ixSMU_EFUSE_0
+ (148 * 4));
1784 efuse
&= 0xFF000000;
1785 efuse
= efuse
>> 24;
1789 ro
= (2300 - 1350) * efuse
/ 255 + 1350;
1791 ro
= (2500 - 1000) * efuse
/ 255 + 1000;
1798 /* Populate Stretch amount */
1799 data
->smc_state_table
.ClockStretcherAmount
= stretch_amount
;
1801 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1802 for (i
= 0; i
< sclk_table
->count
; i
++) {
1803 data
->smc_state_table
.Sclk_CKS_masterEn0_7
|=
1804 sclk_table
->entries
[i
].cks_enable
<< i
;
1805 volt_without_cks
= (uint32_t)((14041 *
1806 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3571 + 75 - ro
) * 1000 /
1807 (4026 - (13924 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
1808 volt_with_cks
= (uint32_t)((13946 *
1809 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3320 + 45 - ro
) * 1000 /
1810 (3664 - (11454 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
1811 if (volt_without_cks
>= volt_with_cks
)
1812 volt_offset
= (uint8_t)(((volt_without_cks
- volt_with_cks
+
1813 sclk_table
->entries
[i
].cks_voffset
) * 100 / 625) + 1);
1814 data
->smc_state_table
.Sclk_voltageOffset
[i
] = volt_offset
;
1817 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
1818 STRETCH_ENABLE
, 0x0);
1819 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
1821 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1822 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
1825 /* Populate CKS Lookup Table */
1826 if (stretch_amount
== 1 || stretch_amount
== 2 || stretch_amount
== 5)
1827 stretch_amount2
= 0;
1828 else if (stretch_amount
== 3 || stretch_amount
== 4)
1829 stretch_amount2
= 1;
1831 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
1832 PHM_PlatformCaps_ClockStretcher
);
1833 PP_ASSERT_WITH_CODE(false,
1834 "Stretch Amount in PPTable not supported\n",
1838 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1840 value
&= 0xFFC2FF87;
1841 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].minFreq
=
1842 polaris10_clock_stretcher_lookup_table
[stretch_amount2
][0];
1843 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].maxFreq
=
1844 polaris10_clock_stretcher_lookup_table
[stretch_amount2
][1];
1845 clock_freq_u16
= (uint16_t)(PP_SMC_TO_HOST_UL(data
->smc_state_table
.
1846 GraphicsLevel
[data
->smc_state_table
.GraphicsDpmLevelCount
- 1].SclkSetting
.SclkFrequency
) / 100);
1847 if (polaris10_clock_stretcher_lookup_table
[stretch_amount2
][0] < clock_freq_u16
1848 && polaris10_clock_stretcher_lookup_table
[stretch_amount2
][1] > clock_freq_u16
) {
1849 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1850 value
|= (polaris10_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 16;
1851 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1852 value
|= (polaris10_clock_stretcher_lookup_table
[stretch_amount2
][2]) << 18;
1853 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1854 value
|= (polaris10_clock_stretch_amount_conversion
1855 [polaris10_clock_stretcher_lookup_table
[stretch_amount2
][3]]
1856 [stretch_amount
]) << 3;
1858 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].minFreq
);
1859 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].maxFreq
);
1860 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
=
1861 polaris10_clock_stretcher_lookup_table
[stretch_amount2
][2] & 0x7F;
1862 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
|=
1863 (polaris10_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 7;
1865 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1866 ixPWR_CKS_CNTL
, value
);
1868 /* Populate DDT Lookup Table */
1869 for (i
= 0; i
< 4; i
++) {
1870 /* Assign the minimum and maximum VID stored
1871 * in the last row of Clock Stretcher Voltage Table.
1873 data
->smc_state_table
.ClockStretcherDataTable
.ClockStretcherDataTableEntry
[i
].minVID
=
1874 (uint8_t) polaris10_clock_stretcher_ddt_table
[type
][i
][2];
1875 data
->smc_state_table
.ClockStretcherDataTable
.ClockStretcherDataTableEntry
[i
].maxVID
=
1876 (uint8_t) polaris10_clock_stretcher_ddt_table
[type
][i
][3];
1877 /* Loop through each SCLK and check the frequency
1878 * to see if it lies within the frequency for clock stretcher.
1880 for (j
= 0; j
< data
->smc_state_table
.GraphicsDpmLevelCount
; j
++) {
1882 clock_freq
= PP_SMC_TO_HOST_UL(
1883 data
->smc_state_table
.GraphicsLevel
[j
].SclkSetting
.SclkFrequency
);
1884 /* Check the allowed frequency against the sclk level[j].
1885 * Sclk's endianness has already been converted,
1886 * and it's in 10Khz unit,
1887 * as opposed to Data table, which is in Mhz unit.
1889 if (clock_freq
>= (polaris10_clock_stretcher_ddt_table
[type
][i
][0]) * 100) {
1891 if (clock_freq
< (polaris10_clock_stretcher_ddt_table
[type
][i
][1]) * 100)
1894 data
->smc_state_table
.ClockStretcherDataTable
.ClockStretcherDataTableEntry
[i
].setting
1895 |= cks_setting
<< (j
* 2);
1897 CONVERT_FROM_HOST_TO_SMC_US(
1898 data
->smc_state_table
.ClockStretcherDataTable
.ClockStretcherDataTableEntry
[i
].setting
);
1901 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
);
1902 value
&= 0xFFFFFFFE;
1903 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
, value
);
1909 * Populates the SMC VRConfig field in DPM table.
1911 * @param hwmgr the address of the hardware manager
1912 * @param table the SMC DPM table structure to be populated
1915 static int polaris10_populate_vr_config(struct pp_hwmgr
*hwmgr
,
1916 struct SMU74_Discrete_DpmTable
*table
)
1918 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1921 config
= VR_MERGED_WITH_VDDC
;
1922 table
->VRConfig
|= (config
<< VRCONF_VDDGFX_SHIFT
);
1924 /* Set Vddc Voltage Controller */
1925 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
1926 config
= VR_SVI2_PLANE_1
;
1927 table
->VRConfig
|= config
;
1929 PP_ASSERT_WITH_CODE(false,
1930 "VDDC should be on SVI2 control in merged mode!",
1933 /* Set Vddci Voltage Controller */
1934 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
1935 config
= VR_SVI2_PLANE_2
; /* only in merged mode */
1936 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
1937 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
1938 config
= VR_SMIO_PATTERN_1
;
1939 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
1941 config
= VR_STATIC_VOLTAGE
;
1942 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
1944 /* Set Mvdd Voltage Controller */
1945 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
1946 config
= VR_SVI2_PLANE_2
;
1947 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
1948 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
1949 config
= VR_SMIO_PATTERN_2
;
1950 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
1952 config
= VR_STATIC_VOLTAGE
;
1953 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
1960 * Initializes the SMC table and uploads it
1962 * @param hwmgr the address of the powerplay hardware manager.
1965 static int polaris10_init_smc_table(struct pp_hwmgr
*hwmgr
)
1968 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
1969 struct phm_ppt_v1_information
*table_info
=
1970 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1971 struct SMU74_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
1972 const struct polaris10_ulv_parm
*ulv
= &(data
->ulv
);
1974 struct pp_atomctrl_gpio_pin_assignment gpio_pin
;
1975 pp_atomctrl_clock_dividers_vi dividers
;
1977 result
= polaris10_setup_default_dpm_tables(hwmgr
);
1978 PP_ASSERT_WITH_CODE(0 == result
,
1979 "Failed to setup default DPM tables!", return result
);
1981 if (POLARIS10_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
)
1982 polaris10_populate_smc_voltage_tables(hwmgr
, table
);
1984 table
->SystemFlags
= 0;
1985 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1986 PHM_PlatformCaps_AutomaticDCTransition
))
1987 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
1989 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1990 PHM_PlatformCaps_StepVddc
))
1991 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
1993 if (data
->is_memory_gddr5
)
1994 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
1996 if (ulv
->ulv_supported
&& table_info
->us_ulv_voltage_offset
) {
1997 result
= polaris10_populate_ulv_state(hwmgr
, table
);
1998 PP_ASSERT_WITH_CODE(0 == result
,
1999 "Failed to initialize ULV state!", return result
);
2000 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2001 ixCG_ULV_PARAMETER
, PPPOLARIS10_CGULVPARAMETER_DFLT
);
2004 result
= polaris10_populate_smc_link_level(hwmgr
, table
);
2005 PP_ASSERT_WITH_CODE(0 == result
,
2006 "Failed to initialize Link Level!", return result
);
2008 result
= polaris10_populate_all_graphic_levels(hwmgr
);
2009 PP_ASSERT_WITH_CODE(0 == result
,
2010 "Failed to initialize Graphics Level!", return result
);
2012 result
= polaris10_populate_all_memory_levels(hwmgr
);
2013 PP_ASSERT_WITH_CODE(0 == result
,
2014 "Failed to initialize Memory Level!", return result
);
2016 result
= polaris10_populate_smc_acpi_level(hwmgr
, table
);
2017 PP_ASSERT_WITH_CODE(0 == result
,
2018 "Failed to initialize ACPI Level!", return result
);
2020 result
= polaris10_populate_smc_vce_level(hwmgr
, table
);
2021 PP_ASSERT_WITH_CODE(0 == result
,
2022 "Failed to initialize VCE Level!", return result
);
2024 result
= polaris10_populate_smc_samu_level(hwmgr
, table
);
2025 PP_ASSERT_WITH_CODE(0 == result
,
2026 "Failed to initialize SAMU Level!", return result
);
2028 /* Since only the initial state is completely set up at this point
2029 * (the other states are just copies of the boot state) we only
2030 * need to populate the ARB settings for the initial state.
2032 result
= polaris10_program_memory_timing_parameters(hwmgr
);
2033 PP_ASSERT_WITH_CODE(0 == result
,
2034 "Failed to Write ARB settings for the initial state.", return result
);
2036 result
= polaris10_populate_smc_uvd_level(hwmgr
, table
);
2037 PP_ASSERT_WITH_CODE(0 == result
,
2038 "Failed to initialize UVD Level!", return result
);
2040 result
= polaris10_populate_smc_boot_level(hwmgr
, table
);
2041 PP_ASSERT_WITH_CODE(0 == result
,
2042 "Failed to initialize Boot Level!", return result
);
2044 result
= polaris10_populate_smc_initailial_state(hwmgr
);
2045 PP_ASSERT_WITH_CODE(0 == result
,
2046 "Failed to initialize Boot State!", return result
);
2048 result
= polaris10_populate_bapm_parameters_in_dpm_table(hwmgr
);
2049 PP_ASSERT_WITH_CODE(0 == result
,
2050 "Failed to populate BAPM Parameters!", return result
);
2052 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2053 PHM_PlatformCaps_ClockStretcher
)) {
2054 result
= polaris10_populate_clock_stretcher_data_table(hwmgr
);
2055 PP_ASSERT_WITH_CODE(0 == result
,
2056 "Failed to populate Clock Stretcher Data Table!",
2059 table
->CurrSclkPllRange
= 0xff;
2060 table
->GraphicsVoltageChangeEnable
= 1;
2061 table
->GraphicsThermThrottleEnable
= 1;
2062 table
->GraphicsInterval
= 1;
2063 table
->VoltageInterval
= 1;
2064 table
->ThermalInterval
= 1;
2065 table
->TemperatureLimitHigh
=
2066 table_info
->cac_dtp_table
->usTargetOperatingTemp
*
2067 POLARIS10_Q88_FORMAT_CONVERSION_UNIT
;
2068 table
->TemperatureLimitLow
=
2069 (table_info
->cac_dtp_table
->usTargetOperatingTemp
- 1) *
2070 POLARIS10_Q88_FORMAT_CONVERSION_UNIT
;
2071 table
->MemoryVoltageChangeEnable
= 1;
2072 table
->MemoryInterval
= 1;
2073 table
->VoltageResponseTime
= 0;
2074 table
->PhaseResponseTime
= 0;
2075 table
->MemoryThermThrottleEnable
= 1;
2076 table
->PCIeBootLinkLevel
= 0;
2077 table
->PCIeGenInterval
= 1;
2078 table
->VRConfig
= 0;
2080 result
= polaris10_populate_vr_config(hwmgr
, table
);
2081 PP_ASSERT_WITH_CODE(0 == result
,
2082 "Failed to populate VRConfig setting!", return result
);
2084 table
->ThermGpio
= 17;
2085 table
->SclkStepSize
= 0x4000;
2087 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_VRHOT_GPIO_PINID
, &gpio_pin
)) {
2088 table
->VRHotGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
2090 table
->VRHotGpio
= POLARIS10_UNUSED_GPIO_PIN
;
2091 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2092 PHM_PlatformCaps_RegulatorHot
);
2095 if (atomctrl_get_pp_assign_pin(hwmgr
, PP_AC_DC_SWITCH_GPIO_PINID
,
2097 table
->AcDcGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
2098 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2099 PHM_PlatformCaps_AutomaticDCTransition
);
2101 table
->AcDcGpio
= POLARIS10_UNUSED_GPIO_PIN
;
2102 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2103 PHM_PlatformCaps_AutomaticDCTransition
);
2106 /* Thermal Output GPIO */
2107 if (atomctrl_get_pp_assign_pin(hwmgr
, THERMAL_INT_OUTPUT_GPIO_PINID
,
2109 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2110 PHM_PlatformCaps_ThermalOutGPIO
);
2112 table
->ThermOutGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
2114 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2115 * since VBIOS will program this register to set 'inactive state',
2116 * driver can then determine 'active state' from this and
2117 * program SMU with correct polarity
2119 table
->ThermOutPolarity
= (0 == (cgs_read_register(hwmgr
->device
, mmGPIOPAD_A
)
2120 & (1 << gpio_pin
.uc_gpio_pin_bit_shift
))) ? 1:0;
2121 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_ONLY
;
2123 /* if required, combine VRHot/PCC with thermal out GPIO */
2124 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_RegulatorHot
)
2125 && phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_CombinePCCWithThermalSignal
))
2126 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_VRHOT
;
2128 table
->ThermOutGpio
= 17;
2129 table
->ThermOutPolarity
= 1;
2130 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_DISABLE
;
2133 /* Populate BIF_SCLK levels into SMC DPM table */
2134 for (i
= 0; i
<= data
->dpm_table
.pcie_speed_table
.count
; i
++) {
2135 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
, data
->bif_sclk_table
[i
], ÷rs
);
2136 PP_ASSERT_WITH_CODE((result
== 0), "Can not find DFS divide id for Sclk", return result
);
2139 table
->Ulv
.BifSclkDfs
= PP_HOST_TO_SMC_US((USHORT
)(dividers
.pll_post_divider
));
2141 table
->LinkLevel
[i
-1].BifSclkDfs
= PP_HOST_TO_SMC_US((USHORT
)(dividers
.pll_post_divider
));
2144 for (i
= 0; i
< SMU74_MAX_ENTRIES_SMIO
; i
++)
2145 table
->Smio
[i
] = PP_HOST_TO_SMC_UL(table
->Smio
[i
]);
2147 CONVERT_FROM_HOST_TO_SMC_UL(table
->SystemFlags
);
2148 CONVERT_FROM_HOST_TO_SMC_UL(table
->VRConfig
);
2149 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask1
);
2150 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask2
);
2151 CONVERT_FROM_HOST_TO_SMC_UL(table
->SclkStepSize
);
2152 CONVERT_FROM_HOST_TO_SMC_UL(table
->CurrSclkPllRange
);
2153 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitHigh
);
2154 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitLow
);
2155 CONVERT_FROM_HOST_TO_SMC_US(table
->VoltageResponseTime
);
2156 CONVERT_FROM_HOST_TO_SMC_US(table
->PhaseResponseTime
);
2158 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2159 result
= polaris10_copy_bytes_to_smc(hwmgr
->smumgr
,
2160 data
->dpm_table_start
+
2161 offsetof(SMU74_Discrete_DpmTable
, SystemFlags
),
2162 (uint8_t *)&(table
->SystemFlags
),
2163 sizeof(SMU74_Discrete_DpmTable
) - 3 * sizeof(SMU74_PIDController
),
2165 PP_ASSERT_WITH_CODE(0 == result
,
2166 "Failed to upload dpm data to SMC memory!", return result
);
2172 * Initialize the ARB DRAM timing table's index field.
2174 * @param hwmgr the address of the powerplay hardware manager.
2177 static int polaris10_init_arb_table_index(struct pp_hwmgr
*hwmgr
)
2179 const struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2183 /* This is a read-modify-write on the first byte of the ARB table.
2184 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2185 * is the field 'current'.
2186 * This solution is ugly, but we never write the whole table only
2187 * individual fields in it.
2188 * In reality this field should not be in that structure
2189 * but in a soft register.
2191 result
= polaris10_read_smc_sram_dword(hwmgr
->smumgr
,
2192 data
->arb_table_start
, &tmp
, data
->sram_end
);
2198 tmp
|= ((uint32_t)MC_CG_ARB_FREQ_F1
) << 24;
2200 return polaris10_write_smc_sram_dword(hwmgr
->smumgr
,
2201 data
->arb_table_start
, tmp
, data
->sram_end
);
2204 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr
*hwmgr
)
2206 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2207 PHM_PlatformCaps_RegulatorHot
))
2208 return smum_send_msg_to_smc(hwmgr
->smumgr
,
2209 PPSMC_MSG_EnableVRHotGPIOInterrupt
);
2214 static int polaris10_enable_sclk_control(struct pp_hwmgr
*hwmgr
)
2216 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
2217 SCLK_PWRMGT_OFF
, 0);
2221 static int polaris10_enable_ulv(struct pp_hwmgr
*hwmgr
)
2223 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2224 struct polaris10_ulv_parm
*ulv
= &(data
->ulv
);
2226 if (ulv
->ulv_supported
)
2227 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_EnableULV
);
2232 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
2234 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2235 PHM_PlatformCaps_SclkDeepSleep
)) {
2236 if (smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_MASTER_DeepSleep_ON
))
2237 PP_ASSERT_WITH_CODE(false,
2238 "Attempt to enable Master Deep Sleep switch failed!",
2241 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
2242 PPSMC_MSG_MASTER_DeepSleep_OFF
)) {
2243 PP_ASSERT_WITH_CODE(false,
2244 "Attempt to disable Master Deep Sleep switch failed!",
2252 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
2254 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2256 /* enable SCLK dpm */
2257 if (!data
->sclk_dpm_key_disabled
)
2258 PP_ASSERT_WITH_CODE(
2259 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DPM_Enable
)),
2260 "Failed to enable SCLK DPM during DPM Start Function!",
2263 /* enable MCLK dpm */
2264 if (0 == data
->mclk_dpm_key_disabled
) {
2266 PP_ASSERT_WITH_CODE(
2267 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2268 PPSMC_MSG_MCLKDPM_Enable
)),
2269 "Failed to enable MCLK DPM during DPM Start Function!",
2273 PHM_WRITE_FIELD(hwmgr
->device
, MC_SEQ_CNTL_3
, CAC_EN
, 0x1);
2275 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC0_CNTL
, 0x5);
2276 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC1_CNTL
, 0x5);
2277 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_CPL_CNTL
, 0x100005);
2279 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC0_CNTL
, 0x400005);
2280 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC1_CNTL
, 0x400005);
2281 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_CPL_CNTL
, 0x500005);
2287 static int polaris10_start_dpm(struct pp_hwmgr
*hwmgr
)
2289 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2291 /*enable general power management */
2293 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
2294 GLOBAL_PWRMGT_EN
, 1);
2296 /* enable sclk deep sleep */
2298 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
2301 /* prepare for PCIE DPM */
2303 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2304 data
->soft_regs_start
+ offsetof(SMU74_SoftRegisters
,
2305 VoltageChangeTimeout
), 0x1000);
2306 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
2307 SWRST_COMMAND_1
, RESETLC
, 0x0);
2309 PP_ASSERT_WITH_CODE(
2310 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2311 PPSMC_MSG_Voltage_Cntl_Enable)),
2312 "Failed to enable voltage DPM during DPM Start Function!",
2316 if (polaris10_enable_sclk_mclk_dpm(hwmgr
)) {
2317 printk(KERN_ERR
"Failed to enable Sclk DPM and Mclk DPM!");
2321 /* enable PCIE dpm */
2322 if (0 == data
->pcie_dpm_key_disabled
) {
2323 PP_ASSERT_WITH_CODE(
2324 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2325 PPSMC_MSG_PCIeDPM_Enable
)),
2326 "Failed to enable pcie DPM during DPM Start Function!",
2330 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2331 PHM_PlatformCaps_Falcon_QuickTransition
)) {
2332 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2333 PPSMC_MSG_EnableACDCGPIOInterrupt
)),
2334 "Failed to enable AC DC GPIO Interrupt!",
2341 static void polaris10_set_dpm_event_sources(struct pp_hwmgr
*hwmgr
, uint32_t sources
)
2344 enum DPM_EVENT_SRC src
;
2348 printk(KERN_ERR
"Unknown throttling event sources.");
2354 case (1 << PHM_AutoThrottleSource_Thermal
):
2356 src
= DPM_EVENT_SRC_DIGITAL
;
2358 case (1 << PHM_AutoThrottleSource_External
):
2360 src
= DPM_EVENT_SRC_EXTERNAL
;
2362 case (1 << PHM_AutoThrottleSource_External
) |
2363 (1 << PHM_AutoThrottleSource_Thermal
):
2365 src
= DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
;
2368 /* Order matters - don't enable thermal protection for the wrong source. */
2370 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_THERMAL_CTRL
,
2371 DPM_EVENT_SRC
, src
);
2372 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
2373 THERMAL_PROTECTION_DIS
,
2374 !phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2375 PHM_PlatformCaps_ThermalController
));
2377 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
2378 THERMAL_PROTECTION_DIS
, 1);
2381 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
2382 PHM_AutoThrottleSource source
)
2384 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2386 if (!(data
->active_auto_throttle_sources
& (1 << source
))) {
2387 data
->active_auto_throttle_sources
|= 1 << source
;
2388 polaris10_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
2393 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
2395 return polaris10_enable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
2398 int polaris10_pcie_performance_request(struct pp_hwmgr
*hwmgr
)
2400 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2401 data
->pcie_performance_request
= true;
2406 int polaris10_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
2408 int tmp_result
, result
= 0;
2409 tmp_result
= (!polaris10_is_dpm_running(hwmgr
)) ? 0 : -1;
2410 PP_ASSERT_WITH_CODE(result
== 0,
2411 "DPM is already running right now, no need to enable DPM!",
2414 if (polaris10_voltage_control(hwmgr
)) {
2415 tmp_result
= polaris10_enable_voltage_control(hwmgr
);
2416 PP_ASSERT_WITH_CODE(tmp_result
== 0,
2417 "Failed to enable voltage control!",
2418 result
= tmp_result
);
2420 tmp_result
= polaris10_construct_voltage_tables(hwmgr
);
2421 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2422 "Failed to contruct voltage tables!",
2423 result
= tmp_result
);
2426 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2427 PHM_PlatformCaps_EngineSpreadSpectrumSupport
))
2428 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
2429 GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, 1);
2431 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2432 PHM_PlatformCaps_ThermalController
))
2433 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
2434 GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, 0);
2436 tmp_result
= polaris10_program_static_screen_threshold_parameters(hwmgr
);
2437 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2438 "Failed to program static screen threshold parameters!",
2439 result
= tmp_result
);
2441 tmp_result
= polaris10_enable_display_gap(hwmgr
);
2442 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2443 "Failed to enable display gap!", result
= tmp_result
);
2445 tmp_result
= polaris10_program_voting_clients(hwmgr
);
2446 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2447 "Failed to program voting clients!", result
= tmp_result
);
2449 tmp_result
= polaris10_process_firmware_header(hwmgr
);
2450 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2451 "Failed to process firmware header!", result
= tmp_result
);
2453 tmp_result
= polaris10_initial_switch_from_arbf0_to_f1(hwmgr
);
2454 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2455 "Failed to initialize switch from ArbF0 to F1!",
2456 result
= tmp_result
);
2458 tmp_result
= polaris10_init_smc_table(hwmgr
);
2459 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2460 "Failed to initialize SMC table!", result
= tmp_result
);
2462 tmp_result
= polaris10_init_arb_table_index(hwmgr
);
2463 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2464 "Failed to initialize ARB table index!", result
= tmp_result
);
2466 tmp_result
= polaris10_populate_pm_fuses(hwmgr
);
2467 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2468 "Failed to populate PM fuses!", result
= tmp_result
);
2470 tmp_result
= polaris10_enable_vrhot_gpio_interrupt(hwmgr
);
2471 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2472 "Failed to enable VR hot GPIO interrupt!", result
= tmp_result
);
2474 tmp_result
= polaris10_enable_sclk_control(hwmgr
);
2475 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2476 "Failed to enable SCLK control!", result
= tmp_result
);
2478 tmp_result
= polaris10_enable_smc_voltage_controller(hwmgr
);
2479 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2480 "Failed to enable voltage control!", result
= tmp_result
);
2482 tmp_result
= polaris10_enable_ulv(hwmgr
);
2483 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2484 "Failed to enable ULV!", result
= tmp_result
);
2486 tmp_result
= polaris10_enable_deep_sleep_master_switch(hwmgr
);
2487 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2488 "Failed to enable deep sleep master switch!", result
= tmp_result
);
2490 tmp_result
= polaris10_start_dpm(hwmgr
);
2491 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2492 "Failed to start DPM!", result
= tmp_result
);
2494 tmp_result
= polaris10_enable_smc_cac(hwmgr
);
2495 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2496 "Failed to enable SMC CAC!", result
= tmp_result
);
2498 tmp_result
= polaris10_enable_power_containment(hwmgr
);
2499 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2500 "Failed to enable power containment!", result
= tmp_result
);
2502 tmp_result
= polaris10_power_control_set_level(hwmgr
);
2503 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2504 "Failed to power control set level!", result
= tmp_result
);
2506 tmp_result
= polaris10_enable_thermal_auto_throttle(hwmgr
);
2507 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2508 "Failed to enable thermal auto throttle!", result
= tmp_result
);
2510 tmp_result
= polaris10_pcie_performance_request(hwmgr
);
2511 PP_ASSERT_WITH_CODE((0 == tmp_result
),
2512 "pcie performance request failed!", result
= tmp_result
);
2517 int polaris10_disable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
2523 int polaris10_reset_asic_tasks(struct pp_hwmgr
*hwmgr
)
2529 int polaris10_hwmgr_backend_fini(struct pp_hwmgr
*hwmgr
)
2531 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2533 if (data
->soft_pp_table
) {
2534 kfree(data
->soft_pp_table
);
2535 data
->soft_pp_table
= NULL
;
2538 return phm_hwmgr_backend_fini(hwmgr
);
2541 int polaris10_set_features_platform_caps(struct pp_hwmgr
*hwmgr
)
2543 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2545 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2546 PHM_PlatformCaps_SclkDeepSleep
);
2548 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2549 PHM_PlatformCaps_DynamicPatchPowerState
);
2551 if (data
->mvdd_control
== POLARIS10_VOLTAGE_CONTROL_NONE
)
2552 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2553 PHM_PlatformCaps_EnableMVDDControl
);
2555 if (data
->vddci_control
== POLARIS10_VOLTAGE_CONTROL_NONE
)
2556 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2557 PHM_PlatformCaps_ControlVDDCI
);
2559 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2560 PHM_PlatformCaps_TablelessHardwareInterface
);
2562 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2563 PHM_PlatformCaps_EnableSMU7ThermalManagement
);
2565 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2566 PHM_PlatformCaps_DynamicPowerManagement
);
2568 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2569 PHM_PlatformCaps_UnTabledHardwareInterface
);
2571 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2572 PHM_PlatformCaps_TablelessHardwareInterface
);
2574 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2575 PHM_PlatformCaps_SMC
);
2577 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2578 PHM_PlatformCaps_NonABMSupportInPPLib
);
2580 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2581 PHM_PlatformCaps_DynamicUVDState
);
2583 /* power tune caps Assume disabled */
2584 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2585 PHM_PlatformCaps_SQRamping
);
2586 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2587 PHM_PlatformCaps_DBRamping
);
2588 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2589 PHM_PlatformCaps_TDRamping
);
2590 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2591 PHM_PlatformCaps_TCPRamping
);
2593 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2594 PHM_PlatformCaps_PowerContainment
);
2595 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2596 PHM_PlatformCaps_CAC
);
2598 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2599 PHM_PlatformCaps_RegulatorHot
);
2601 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2602 PHM_PlatformCaps_AutomaticDCTransition
);
2604 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2605 PHM_PlatformCaps_ODFuzzyFanControlSupport
);
2607 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2608 PHM_PlatformCaps_FanSpeedInTableIsRPM
);
2609 if (hwmgr
->chip_id
== CHIP_POLARIS11
)
2610 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2611 PHM_PlatformCaps_SPLLShutdownSupport
);
2615 static void polaris10_init_dpm_defaults(struct pp_hwmgr
*hwmgr
)
2617 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2619 polaris10_initialize_power_tune_defaults(hwmgr
);
2621 data
->pcie_gen_performance
.max
= PP_PCIEGen1
;
2622 data
->pcie_gen_performance
.min
= PP_PCIEGen3
;
2623 data
->pcie_gen_power_saving
.max
= PP_PCIEGen1
;
2624 data
->pcie_gen_power_saving
.min
= PP_PCIEGen3
;
2625 data
->pcie_lane_performance
.max
= 0;
2626 data
->pcie_lane_performance
.min
= 16;
2627 data
->pcie_lane_power_saving
.max
= 0;
2628 data
->pcie_lane_power_saving
.min
= 16;
2632 * Get Leakage VDDC based on leakage ID.
2634 * @param hwmgr the address of the powerplay hardware manager.
2637 static int polaris10_get_evv_voltages(struct pp_hwmgr
*hwmgr
)
2639 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2644 struct phm_ppt_v1_information
*table_info
=
2645 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
2646 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
2647 table_info
->vdd_dep_on_sclk
;
2650 for (i
= 0; i
< POLARIS10_MAX_LEAKAGE_COUNT
; i
++) {
2651 vv_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
2652 if (!phm_get_sclk_for_voltage_evv(hwmgr
,
2653 table_info
->vddc_lookup_table
, vv_id
, &sclk
)) {
2654 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2655 PHM_PlatformCaps_ClockStretcher
)) {
2656 for (j
= 1; j
< sclk_table
->count
; j
++) {
2657 if (sclk_table
->entries
[j
].clk
== sclk
&&
2658 sclk_table
->entries
[j
].cks_enable
== 0) {
2666 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr
,
2667 VOLTAGE_TYPE_VDDC
, sclk
, vv_id
, &vddc
),
2668 "Error retrieving EVV voltage value!",
2672 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2673 PP_ASSERT_WITH_CODE((vddc
< 2000 && vddc
!= 0),
2674 "Invalid VDDC value", result
= -EINVAL
;);
2676 /* the voltage should not be zero nor equal to leakage ID */
2677 if (vddc
!= 0 && vddc
!= vv_id
) {
2678 data
->vddc_leakage
.actual_voltage
[data
->vddc_leakage
.count
] = (uint16_t)(vddc
/100);
2679 data
->vddc_leakage
.leakage_id
[data
->vddc_leakage
.count
] = vv_id
;
2680 data
->vddc_leakage
.count
++;
2689 * Change virtual leakage voltage to actual value.
2691 * @param hwmgr the address of the powerplay hardware manager.
2692 * @param pointer to changing voltage
2693 * @param pointer to leakage table
2695 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
2696 uint16_t *voltage
, struct polaris10_leakage_voltage
*leakage_table
)
2700 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2701 for (index
= 0; index
< leakage_table
->count
; index
++) {
2702 /* if this voltage matches a leakage voltage ID */
2703 /* patch with actual leakage voltage */
2704 if (leakage_table
->leakage_id
[index
] == *voltage
) {
2705 *voltage
= leakage_table
->actual_voltage
[index
];
2710 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
2711 printk(KERN_ERR
"Voltage value looks like a Leakage ID but it's not patched \n");
2715 * Patch voltage lookup table by EVV leakages.
2717 * @param hwmgr the address of the powerplay hardware manager.
2718 * @param pointer to voltage lookup table
2719 * @param pointer to leakage table
2722 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr
*hwmgr
,
2723 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
2724 struct polaris10_leakage_voltage
*leakage_table
)
2728 for (i
= 0; i
< lookup_table
->count
; i
++)
2729 polaris10_patch_with_vdd_leakage(hwmgr
,
2730 &lookup_table
->entries
[i
].us_vdd
, leakage_table
);
2735 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2736 struct pp_hwmgr
*hwmgr
, struct polaris10_leakage_voltage
*leakage_table
,
2739 struct phm_ppt_v1_information
*table_info
=
2740 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2741 polaris10_patch_with_vdd_leakage(hwmgr
, (uint16_t *)vddc
, leakage_table
);
2742 hwmgr
->dyn_state
.max_clock_voltage_on_dc
.vddc
=
2743 table_info
->max_clock_voltage_on_dc
.vddc
;
2747 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2748 struct pp_hwmgr
*hwmgr
)
2752 struct phm_ppt_v1_information
*table_info
=
2753 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2755 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
2756 table_info
->vdd_dep_on_sclk
;
2757 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
=
2758 table_info
->vdd_dep_on_mclk
;
2759 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2760 table_info
->mm_dep_table
;
2762 for (entryId
= 0; entryId
< sclk_table
->count
; ++entryId
) {
2763 voltageId
= sclk_table
->entries
[entryId
].vddInd
;
2764 sclk_table
->entries
[entryId
].vddc
=
2765 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
2768 for (entryId
= 0; entryId
< mclk_table
->count
; ++entryId
) {
2769 voltageId
= mclk_table
->entries
[entryId
].vddInd
;
2770 mclk_table
->entries
[entryId
].vddc
=
2771 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
2774 for (entryId
= 0; entryId
< mm_table
->count
; ++entryId
) {
2775 voltageId
= mm_table
->entries
[entryId
].vddcInd
;
2776 mm_table
->entries
[entryId
].vddc
=
2777 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
2784 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr
*hwmgr
)
2786 /* Need to determine if we need calculated voltage. */
2790 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr
*hwmgr
)
2792 /* Need to determine if we need calculated voltage from mm table. */
2796 static int polaris10_sort_lookup_table(struct pp_hwmgr
*hwmgr
,
2797 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
)
2799 uint32_t table_size
, i
, j
;
2800 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record
;
2801 table_size
= lookup_table
->count
;
2803 PP_ASSERT_WITH_CODE(0 != lookup_table
->count
,
2804 "Lookup table is empty", return -EINVAL
);
2806 /* Sorting voltages */
2807 for (i
= 0; i
< table_size
- 1; i
++) {
2808 for (j
= i
+ 1; j
> 0; j
--) {
2809 if (lookup_table
->entries
[j
].us_vdd
<
2810 lookup_table
->entries
[j
- 1].us_vdd
) {
2811 tmp_voltage_lookup_record
= lookup_table
->entries
[j
- 1];
2812 lookup_table
->entries
[j
- 1] = lookup_table
->entries
[j
];
2813 lookup_table
->entries
[j
] = tmp_voltage_lookup_record
;
2821 static int polaris10_complete_dependency_tables(struct pp_hwmgr
*hwmgr
)
2825 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2826 struct phm_ppt_v1_information
*table_info
=
2827 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2829 tmp_result
= polaris10_patch_lookup_table_with_leakage(hwmgr
,
2830 table_info
->vddc_lookup_table
, &(data
->vddc_leakage
));
2832 result
= tmp_result
;
2834 tmp_result
= polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr
,
2835 &(data
->vddc_leakage
), &table_info
->max_clock_voltage_on_dc
.vddc
);
2837 result
= tmp_result
;
2839 tmp_result
= polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr
);
2841 result
= tmp_result
;
2843 tmp_result
= polaris10_calc_voltage_dependency_tables(hwmgr
);
2845 result
= tmp_result
;
2847 tmp_result
= polaris10_calc_mm_voltage_dependency_table(hwmgr
);
2849 result
= tmp_result
;
2851 tmp_result
= polaris10_sort_lookup_table(hwmgr
, table_info
->vddc_lookup_table
);
2853 result
= tmp_result
;
2858 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr
*hwmgr
)
2860 struct phm_ppt_v1_information
*table_info
=
2861 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2863 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_sclk_vdd_table
=
2864 table_info
->vdd_dep_on_sclk
;
2865 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_mclk_vdd_table
=
2866 table_info
->vdd_dep_on_mclk
;
2868 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
!= NULL
,
2869 "VDD dependency on SCLK table is missing. \
2870 This table is mandatory", return -EINVAL
);
2871 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
->count
>= 1,
2872 "VDD dependency on SCLK table has to have is missing. \
2873 This table is mandatory", return -EINVAL
);
2875 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
!= NULL
,
2876 "VDD dependency on MCLK table is missing. \
2877 This table is mandatory", return -EINVAL
);
2878 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
->count
>= 1,
2879 "VDD dependency on MCLK table has to have is missing. \
2880 This table is mandatory", return -EINVAL
);
2882 table_info
->max_clock_voltage_on_ac
.sclk
=
2883 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].clk
;
2884 table_info
->max_clock_voltage_on_ac
.mclk
=
2885 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].clk
;
2886 table_info
->max_clock_voltage_on_ac
.vddc
=
2887 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
2888 table_info
->max_clock_voltage_on_ac
.vddci
=
2889 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].vddci
;
2891 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
= table_info
->max_clock_voltage_on_ac
.sclk
;
2892 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
= table_info
->max_clock_voltage_on_ac
.mclk
;
2893 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
= table_info
->max_clock_voltage_on_ac
.vddc
;
2894 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
=table_info
->max_clock_voltage_on_ac
.vddci
;
2899 int polaris10_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
2901 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
2902 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment
;
2905 struct phm_ppt_v1_information
*table_info
=
2906 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2908 data
->dll_default_on
= false;
2909 data
->sram_end
= SMC_RAM_END
;
2910 data
->mclk_dpm0_activity_target
= 0xa;
2911 data
->disable_dpm_mask
= 0xFF;
2912 data
->static_screen_threshold
= PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT
;
2913 data
->static_screen_threshold_unit
= PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT
;
2914 data
->activity_target
[0] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2915 data
->activity_target
[1] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2916 data
->activity_target
[2] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2917 data
->activity_target
[3] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2918 data
->activity_target
[4] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2919 data
->activity_target
[5] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2920 data
->activity_target
[6] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2921 data
->activity_target
[7] = PPPOLARIS10_TARGETACTIVITY_DFLT
;
2923 data
->voting_rights_clients0
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0
;
2924 data
->voting_rights_clients1
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1
;
2925 data
->voting_rights_clients2
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2
;
2926 data
->voting_rights_clients3
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3
;
2927 data
->voting_rights_clients4
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4
;
2928 data
->voting_rights_clients5
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5
;
2929 data
->voting_rights_clients6
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6
;
2930 data
->voting_rights_clients7
= PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7
;
2932 data
->vddc_vddci_delta
= VDDC_VDDCI_DELTA
;
2934 data
->mclk_activity_target
= PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT
;
2936 /* need to set voltage control types before EVV patching */
2937 data
->voltage_control
= POLARIS10_VOLTAGE_CONTROL_NONE
;
2938 data
->vddci_control
= POLARIS10_VOLTAGE_CONTROL_NONE
;
2939 data
->mvdd_control
= POLARIS10_VOLTAGE_CONTROL_NONE
;
2941 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
2942 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
))
2943 data
->voltage_control
= POLARIS10_VOLTAGE_CONTROL_BY_SVID2
;
2945 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2946 PHM_PlatformCaps_EnableMVDDControl
)) {
2947 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
2948 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
))
2949 data
->mvdd_control
= POLARIS10_VOLTAGE_CONTROL_BY_GPIO
;
2950 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
2951 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_SVID2
))
2952 data
->mvdd_control
= POLARIS10_VOLTAGE_CONTROL_BY_SVID2
;
2955 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2956 PHM_PlatformCaps_ControlVDDCI
)) {
2957 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
2958 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
2959 data
->vddci_control
= POLARIS10_VOLTAGE_CONTROL_BY_GPIO
;
2960 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
2961 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_SVID2
))
2962 data
->vddci_control
= POLARIS10_VOLTAGE_CONTROL_BY_SVID2
;
2965 polaris10_set_features_platform_caps(hwmgr
);
2967 polaris10_init_dpm_defaults(hwmgr
);
2969 /* Get leakage voltage based on leakage ID. */
2970 result
= polaris10_get_evv_voltages(hwmgr
);
2973 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
2977 polaris10_complete_dependency_tables(hwmgr
);
2978 polaris10_set_private_data_based_on_pptable(hwmgr
);
2980 /* Initalize Dynamic State Adjustment Rule Settings */
2981 result
= phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr
);
2984 struct cgs_system_info sys_info
= {0};
2986 data
->is_tlu_enabled
= 0;
2988 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
2989 POLARIS10_MAX_HARDWARE_POWERLEVELS
;
2990 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
2991 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
2994 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_PCC_GPIO_PINID
, &gpio_pin_assignment
)) {
2995 temp_reg
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCNB_PWRMGT_CNTL
);
2996 switch (gpio_pin_assignment
.uc_gpio_pin_bit_shift
) {
2998 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x1);
3001 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x2);
3004 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW
, 0x1);
3007 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, FORCE_NB_PS1
, 0x1);
3010 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, DPM_ENABLED
, 0x1);
3013 PP_ASSERT_WITH_CODE(0,
3014 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3018 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCNB_PWRMGT_CNTL
, temp_reg
);
3021 if (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
!= 0 &&
3022 hwmgr
->thermal_controller
.advanceFanControlParameters
.ucFanControlMode
) {
3023 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMMinLimit
=
3024 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.ucMinimumPWMLimit
;
3026 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMMaxLimit
=
3027 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanPWM
;
3029 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMStep
= 1;
3031 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMMaxLimit
= 100;
3033 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMMinLimit
=
3034 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.ucMinimumPWMLimit
;
3036 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMStep
= 1;
3038 table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
= (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
>= 50) ?
3039 (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
-50) : 0;
3041 table_info
->cac_dtp_table
->usOperatingTempMaxLimit
= table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
;
3042 table_info
->cac_dtp_table
->usOperatingTempStep
= 1;
3043 table_info
->cac_dtp_table
->usOperatingTempHyst
= 1;
3045 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanPWM
=
3046 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanPWM
;
3048 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanRPM
=
3049 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanRPM
;
3051 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMinLimit
=
3052 table_info
->cac_dtp_table
->usOperatingTempMinLimit
;
3054 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMaxLimit
=
3055 table_info
->cac_dtp_table
->usOperatingTempMaxLimit
;
3057 hwmgr
->dyn_state
.cac_dtp_table
->usDefaultTargetOperatingTemp
=
3058 table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
;
3060 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempStep
=
3061 table_info
->cac_dtp_table
->usOperatingTempStep
;
3063 hwmgr
->dyn_state
.cac_dtp_table
->usTargetOperatingTemp
=
3064 table_info
->cac_dtp_table
->usTargetOperatingTemp
;
3067 sys_info
.size
= sizeof(struct cgs_system_info
);
3068 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_GEN_INFO
;
3069 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
3071 data
->pcie_gen_cap
= 0x30007;
3073 data
->pcie_gen_cap
= (uint32_t)sys_info
.value
;
3074 if (data
->pcie_gen_cap
& CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)
3075 data
->pcie_spc_cap
= 20;
3076 sys_info
.size
= sizeof(struct cgs_system_info
);
3077 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_MLW
;
3078 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
3080 data
->pcie_lane_cap
= 0x2f0000;
3082 data
->pcie_lane_cap
= (uint32_t)sys_info
.value
;
3084 hwmgr
->platform_descriptor
.vbiosInterruptId
= 0x20000400; /* IRQ_SOURCE1_SW_INT */
3085 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3086 hwmgr
->platform_descriptor
.clockStep
.engineClock
= 500;
3087 hwmgr
->platform_descriptor
.clockStep
.memoryClock
= 500;
3089 /* Ignore return value in here, we are cleaning up a mess. */
3090 polaris10_hwmgr_backend_fini(hwmgr
);
3096 static int polaris10_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
3098 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3099 uint32_t level
, tmp
;
3101 if (!data
->pcie_dpm_key_disabled
) {
3102 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3104 tmp
= data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
3109 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3110 PPSMC_MSG_PCIeDPM_ForceLevel
, level
);
3114 if (!data
->sclk_dpm_key_disabled
) {
3115 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3117 tmp
= data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
3122 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3123 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3128 if (!data
->mclk_dpm_key_disabled
) {
3129 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3131 tmp
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
3136 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3137 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3145 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
)
3147 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3149 phm_apply_dal_min_voltage_request(hwmgr
);
3151 if (!data
->sclk_dpm_key_disabled
) {
3152 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
)
3153 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3154 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3155 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3158 if (!data
->mclk_dpm_key_disabled
) {
3159 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
)
3160 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3161 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3162 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
3168 static int polaris10_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
3170 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3172 if (!polaris10_is_dpm_running(hwmgr
))
3175 if (!data
->pcie_dpm_key_disabled
) {
3176 smum_send_msg_to_smc(hwmgr
->smumgr
,
3177 PPSMC_MSG_PCIeDPM_UnForceLevel
);
3180 return polaris10_upload_dpm_level_enable_mask(hwmgr
);
3183 static int polaris10_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
3185 struct polaris10_hwmgr
*data
=
3186 (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3189 if (!data
->sclk_dpm_key_disabled
)
3190 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3191 level
= phm_get_lowest_enabled_level(hwmgr
,
3192 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3193 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3194 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3199 if (!data
->mclk_dpm_key_disabled
) {
3200 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3201 level
= phm_get_lowest_enabled_level(hwmgr
,
3202 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
3203 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3204 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3209 if (!data
->pcie_dpm_key_disabled
) {
3210 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3211 level
= phm_get_lowest_enabled_level(hwmgr
,
3212 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
3213 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3214 PPSMC_MSG_PCIeDPM_ForceLevel
,
3222 static int polaris10_force_dpm_level(struct pp_hwmgr
*hwmgr
,
3223 enum amd_dpm_forced_level level
)
3228 case AMD_DPM_FORCED_LEVEL_HIGH
:
3229 ret
= polaris10_force_dpm_highest(hwmgr
);
3233 case AMD_DPM_FORCED_LEVEL_LOW
:
3234 ret
= polaris10_force_dpm_lowest(hwmgr
);
3238 case AMD_DPM_FORCED_LEVEL_AUTO
:
3239 ret
= polaris10_unforce_dpm_levels(hwmgr
);
3247 hwmgr
->dpm_level
= level
;
3252 static int polaris10_get_power_state_size(struct pp_hwmgr
*hwmgr
)
3254 return sizeof(struct polaris10_power_state
);
3258 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
3259 struct pp_power_state
*request_ps
,
3260 const struct pp_power_state
*current_ps
)
3263 struct polaris10_power_state
*polaris10_ps
=
3264 cast_phw_polaris10_power_state(&request_ps
->hardware
);
3267 struct PP_Clocks minimum_clocks
= {0};
3268 bool disable_mclk_switching
;
3269 bool disable_mclk_switching_for_frame_lock
;
3270 struct cgs_display_info info
= {0};
3271 const struct phm_clock_and_voltage_limits
*max_limits
;
3273 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3274 struct phm_ppt_v1_information
*table_info
=
3275 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3277 int32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
3279 data
->battery_state
= (PP_StateUILabel_Battery
==
3280 request_ps
->classification
.ui_label
);
3282 PP_ASSERT_WITH_CODE(polaris10_ps
->performance_level_count
== 2,
3283 "VI should always have 2 performance levels",
3286 max_limits
= (PP_PowerSource_AC
== hwmgr
->power_source
) ?
3287 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
3288 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3290 /* Cap clock DPM tables at DC MAX if it is in DC. */
3291 if (PP_PowerSource_DC
== hwmgr
->power_source
) {
3292 for (i
= 0; i
< polaris10_ps
->performance_level_count
; i
++) {
3293 if (polaris10_ps
->performance_levels
[i
].memory_clock
> max_limits
->mclk
)
3294 polaris10_ps
->performance_levels
[i
].memory_clock
= max_limits
->mclk
;
3295 if (polaris10_ps
->performance_levels
[i
].engine_clock
> max_limits
->sclk
)
3296 polaris10_ps
->performance_levels
[i
].engine_clock
= max_limits
->sclk
;
3300 polaris10_ps
->vce_clks
.evclk
= hwmgr
->vce_arbiter
.evclk
;
3301 polaris10_ps
->vce_clks
.ecclk
= hwmgr
->vce_arbiter
.ecclk
;
3303 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3305 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3307 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3309 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3310 PHM_PlatformCaps_StablePState
)) {
3311 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3312 stable_pstate_sclk
= (max_limits
->sclk
* 75) / 100;
3314 for (count
= table_info
->vdd_dep_on_sclk
->count
- 1;
3315 count
>= 0; count
--) {
3316 if (stable_pstate_sclk
>=
3317 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
3318 stable_pstate_sclk
=
3319 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
3325 stable_pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[0].clk
;
3327 stable_pstate_mclk
= max_limits
->mclk
;
3329 minimum_clocks
.engineClock
= stable_pstate_sclk
;
3330 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
3333 if (minimum_clocks
.engineClock
< hwmgr
->gfx_arbiter
.sclk
)
3334 minimum_clocks
.engineClock
= hwmgr
->gfx_arbiter
.sclk
;
3336 if (minimum_clocks
.memoryClock
< hwmgr
->gfx_arbiter
.mclk
)
3337 minimum_clocks
.memoryClock
= hwmgr
->gfx_arbiter
.mclk
;
3339 polaris10_ps
->sclk_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
3341 if (0 != hwmgr
->gfx_arbiter
.sclk_over_drive
) {
3342 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.sclk_over_drive
<=
3343 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
),
3344 "Overdrive sclk exceeds limit",
3345 hwmgr
->gfx_arbiter
.sclk_over_drive
=
3346 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
3348 if (hwmgr
->gfx_arbiter
.sclk_over_drive
>= hwmgr
->gfx_arbiter
.sclk
)
3349 polaris10_ps
->performance_levels
[1].engine_clock
=
3350 hwmgr
->gfx_arbiter
.sclk_over_drive
;
3353 if (0 != hwmgr
->gfx_arbiter
.mclk_over_drive
) {
3354 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.mclk_over_drive
<=
3355 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
),
3356 "Overdrive mclk exceeds limit",
3357 hwmgr
->gfx_arbiter
.mclk_over_drive
=
3358 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
3360 if (hwmgr
->gfx_arbiter
.mclk_over_drive
>= hwmgr
->gfx_arbiter
.mclk
)
3361 polaris10_ps
->performance_levels
[1].memory_clock
=
3362 hwmgr
->gfx_arbiter
.mclk_over_drive
;
3365 disable_mclk_switching_for_frame_lock
= phm_cap_enabled(
3366 hwmgr
->platform_descriptor
.platformCaps
,
3367 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
3369 disable_mclk_switching
= (1 < info
.display_count
) ||
3370 disable_mclk_switching_for_frame_lock
;
3372 sclk
= polaris10_ps
->performance_levels
[0].engine_clock
;
3373 mclk
= polaris10_ps
->performance_levels
[0].memory_clock
;
3375 if (disable_mclk_switching
)
3376 mclk
= polaris10_ps
->performance_levels
3377 [polaris10_ps
->performance_level_count
- 1].memory_clock
;
3379 if (sclk
< minimum_clocks
.engineClock
)
3380 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ?
3381 max_limits
->sclk
: minimum_clocks
.engineClock
;
3383 if (mclk
< minimum_clocks
.memoryClock
)
3384 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ?
3385 max_limits
->mclk
: minimum_clocks
.memoryClock
;
3387 polaris10_ps
->performance_levels
[0].engine_clock
= sclk
;
3388 polaris10_ps
->performance_levels
[0].memory_clock
= mclk
;
3390 polaris10_ps
->performance_levels
[1].engine_clock
=
3391 (polaris10_ps
->performance_levels
[1].engine_clock
>=
3392 polaris10_ps
->performance_levels
[0].engine_clock
) ?
3393 polaris10_ps
->performance_levels
[1].engine_clock
:
3394 polaris10_ps
->performance_levels
[0].engine_clock
;
3396 if (disable_mclk_switching
) {
3397 if (mclk
< polaris10_ps
->performance_levels
[1].memory_clock
)
3398 mclk
= polaris10_ps
->performance_levels
[1].memory_clock
;
3400 polaris10_ps
->performance_levels
[0].memory_clock
= mclk
;
3401 polaris10_ps
->performance_levels
[1].memory_clock
= mclk
;
3403 if (polaris10_ps
->performance_levels
[1].memory_clock
<
3404 polaris10_ps
->performance_levels
[0].memory_clock
)
3405 polaris10_ps
->performance_levels
[1].memory_clock
=
3406 polaris10_ps
->performance_levels
[0].memory_clock
;
3409 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3410 PHM_PlatformCaps_StablePState
)) {
3411 for (i
= 0; i
< polaris10_ps
->performance_level_count
; i
++) {
3412 polaris10_ps
->performance_levels
[i
].engine_clock
= stable_pstate_sclk
;
3413 polaris10_ps
->performance_levels
[i
].memory_clock
= stable_pstate_mclk
;
3414 polaris10_ps
->performance_levels
[i
].pcie_gen
= data
->pcie_gen_performance
.max
;
3415 polaris10_ps
->performance_levels
[i
].pcie_lane
= data
->pcie_gen_performance
.max
;
3422 static int polaris10_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
3424 struct pp_power_state
*ps
;
3425 struct polaris10_power_state
*polaris10_ps
;
3430 ps
= hwmgr
->request_ps
;
3435 polaris10_ps
= cast_phw_polaris10_power_state(&ps
->hardware
);
3438 return polaris10_ps
->performance_levels
[0].memory_clock
;
3440 return polaris10_ps
->performance_levels
3441 [polaris10_ps
->performance_level_count
-1].memory_clock
;
3444 static int polaris10_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
3446 struct pp_power_state
*ps
;
3447 struct polaris10_power_state
*polaris10_ps
;
3452 ps
= hwmgr
->request_ps
;
3457 polaris10_ps
= cast_phw_polaris10_power_state(&ps
->hardware
);
3460 return polaris10_ps
->performance_levels
[0].engine_clock
;
3462 return polaris10_ps
->performance_levels
3463 [polaris10_ps
->performance_level_count
-1].engine_clock
;
3466 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr
*hwmgr
,
3467 struct pp_hw_power_state
*hw_ps
)
3469 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3470 struct polaris10_power_state
*ps
= (struct polaris10_power_state
*)hw_ps
;
3471 ATOM_FIRMWARE_INFO_V2_2
*fw_info
;
3474 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
3476 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3477 * We assume here that fw_info is unchanged if this call fails.
3479 fw_info
= (ATOM_FIRMWARE_INFO_V2_2
*)cgs_atom_get_data_table(
3480 hwmgr
->device
, index
,
3481 &size
, &frev
, &crev
);
3483 /* During a test, there is no firmware info table. */
3486 /* Patch the state. */
3487 data
->vbios_boot_state
.sclk_bootup_value
=
3488 le32_to_cpu(fw_info
->ulDefaultEngineClock
);
3489 data
->vbios_boot_state
.mclk_bootup_value
=
3490 le32_to_cpu(fw_info
->ulDefaultMemoryClock
);
3491 data
->vbios_boot_state
.mvdd_bootup_value
=
3492 le16_to_cpu(fw_info
->usBootUpMVDDCVoltage
);
3493 data
->vbios_boot_state
.vddc_bootup_value
=
3494 le16_to_cpu(fw_info
->usBootUpVDDCVoltage
);
3495 data
->vbios_boot_state
.vddci_bootup_value
=
3496 le16_to_cpu(fw_info
->usBootUpVDDCIVoltage
);
3497 data
->vbios_boot_state
.pcie_gen_bootup_value
=
3498 phm_get_current_pcie_speed(hwmgr
);
3500 data
->vbios_boot_state
.pcie_lane_bootup_value
=
3501 (uint16_t)phm_get_current_pcie_lane_number(hwmgr
);
3503 /* set boot power state */
3504 ps
->performance_levels
[0].memory_clock
= data
->vbios_boot_state
.mclk_bootup_value
;
3505 ps
->performance_levels
[0].engine_clock
= data
->vbios_boot_state
.sclk_bootup_value
;
3506 ps
->performance_levels
[0].pcie_gen
= data
->vbios_boot_state
.pcie_gen_bootup_value
;
3507 ps
->performance_levels
[0].pcie_lane
= data
->vbios_boot_state
.pcie_lane_bootup_value
;
3512 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr
*hwmgr
,
3513 void *state
, struct pp_power_state
*power_state
,
3514 void *pp_table
, uint32_t classification_flag
)
3516 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3517 struct polaris10_power_state
*polaris10_power_state
=
3518 (struct polaris10_power_state
*)(&(power_state
->hardware
));
3519 struct polaris10_performance_level
*performance_level
;
3520 ATOM_Tonga_State
*state_entry
= (ATOM_Tonga_State
*)state
;
3521 ATOM_Tonga_POWERPLAYTABLE
*powerplay_table
=
3522 (ATOM_Tonga_POWERPLAYTABLE
*)pp_table
;
3523 ATOM_Tonga_SCLK_Dependency_Table
*sclk_dep_table
=
3524 (ATOM_Tonga_SCLK_Dependency_Table
*)
3525 (((unsigned long)powerplay_table
) +
3526 le16_to_cpu(powerplay_table
->usSclkDependencyTableOffset
));
3527 ATOM_Tonga_MCLK_Dependency_Table
*mclk_dep_table
=
3528 (ATOM_Tonga_MCLK_Dependency_Table
*)
3529 (((unsigned long)powerplay_table
) +
3530 le16_to_cpu(powerplay_table
->usMclkDependencyTableOffset
));
3532 /* The following fields are not initialized here: id orderedList allStatesList */
3533 power_state
->classification
.ui_label
=
3534 (le16_to_cpu(state_entry
->usClassification
) &
3535 ATOM_PPLIB_CLASSIFICATION_UI_MASK
) >>
3536 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
;
3537 power_state
->classification
.flags
= classification_flag
;
3538 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3540 power_state
->classification
.temporary_state
= false;
3541 power_state
->classification
.to_be_deleted
= false;
3543 power_state
->validation
.disallowOnDC
=
3544 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3545 ATOM_Tonga_DISALLOW_ON_DC
));
3547 power_state
->pcie
.lanes
= 0;
3549 power_state
->display
.disableFrameModulation
= false;
3550 power_state
->display
.limitRefreshrate
= false;
3551 power_state
->display
.enableVariBright
=
3552 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3553 ATOM_Tonga_ENABLE_VARIBRIGHT
));
3555 power_state
->validation
.supportedPowerLevels
= 0;
3556 power_state
->uvd_clocks
.VCLK
= 0;
3557 power_state
->uvd_clocks
.DCLK
= 0;
3558 power_state
->temperatures
.min
= 0;
3559 power_state
->temperatures
.max
= 0;
3561 performance_level
= &(polaris10_power_state
->performance_levels
3562 [polaris10_power_state
->performance_level_count
++]);
3564 PP_ASSERT_WITH_CODE(
3565 (polaris10_power_state
->performance_level_count
< SMU74_MAX_LEVELS_GRAPHICS
),
3566 "Performance levels exceeds SMC limit!",
3569 PP_ASSERT_WITH_CODE(
3570 (polaris10_power_state
->performance_level_count
<=
3571 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
3572 "Performance levels exceeds Driver limit!",
3575 /* Performance levels are arranged from low to high. */
3576 performance_level
->memory_clock
= mclk_dep_table
->entries
3577 [state_entry
->ucMemoryClockIndexLow
].ulMclk
;
3578 performance_level
->engine_clock
= sclk_dep_table
->entries
3579 [state_entry
->ucEngineClockIndexLow
].ulSclk
;
3580 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3581 state_entry
->ucPCIEGenLow
);
3582 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3583 state_entry
->ucPCIELaneHigh
);
3585 performance_level
= &(polaris10_power_state
->performance_levels
3586 [polaris10_power_state
->performance_level_count
++]);
3587 performance_level
->memory_clock
= mclk_dep_table
->entries
3588 [state_entry
->ucMemoryClockIndexHigh
].ulMclk
;
3589 performance_level
->engine_clock
= sclk_dep_table
->entries
3590 [state_entry
->ucEngineClockIndexHigh
].ulSclk
;
3591 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3592 state_entry
->ucPCIEGenHigh
);
3593 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3594 state_entry
->ucPCIELaneHigh
);
3599 static int polaris10_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
3600 unsigned long entry_index
, struct pp_power_state
*state
)
3603 struct polaris10_power_state
*ps
;
3604 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3605 struct phm_ppt_v1_information
*table_info
=
3606 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3607 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
3608 table_info
->vdd_dep_on_mclk
;
3610 state
->hardware
.magic
= PHM_VIslands_Magic
;
3612 ps
= (struct polaris10_power_state
*)(&state
->hardware
);
3614 result
= tonga_get_powerplay_table_entry(hwmgr
, entry_index
, state
,
3615 polaris10_get_pp_table_entry_callback_func
);
3617 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3618 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3619 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3621 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
3622 if (dep_mclk_table
->entries
[0].clk
!=
3623 data
->vbios_boot_state
.mclk_bootup_value
)
3624 printk(KERN_ERR
"Single MCLK entry VDDCI/MCLK dependency table "
3625 "does not match VBIOS boot MCLK level");
3626 if (dep_mclk_table
->entries
[0].vddci
!=
3627 data
->vbios_boot_state
.vddci_bootup_value
)
3628 printk(KERN_ERR
"Single VDDCI entry VDDCI/MCLK dependency table "
3629 "does not match VBIOS boot VDDCI level");
3632 /* set DC compatible flag if this state supports DC */
3633 if (!state
->validation
.disallowOnDC
)
3634 ps
->dc_compatible
= true;
3636 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
3637 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
3639 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3640 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3645 switch (state
->classification
.ui_label
) {
3646 case PP_StateUILabel_Performance
:
3647 data
->use_pcie_performance_levels
= true;
3649 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3650 if (data
->pcie_gen_performance
.max
<
3651 ps
->performance_levels
[i
].pcie_gen
)
3652 data
->pcie_gen_performance
.max
=
3653 ps
->performance_levels
[i
].pcie_gen
;
3655 if (data
->pcie_gen_performance
.min
>
3656 ps
->performance_levels
[i
].pcie_gen
)
3657 data
->pcie_gen_performance
.min
=
3658 ps
->performance_levels
[i
].pcie_gen
;
3660 if (data
->pcie_lane_performance
.max
<
3661 ps
->performance_levels
[i
].pcie_lane
)
3662 data
->pcie_lane_performance
.max
=
3663 ps
->performance_levels
[i
].pcie_lane
;
3665 if (data
->pcie_lane_performance
.min
>
3666 ps
->performance_levels
[i
].pcie_lane
)
3667 data
->pcie_lane_performance
.min
=
3668 ps
->performance_levels
[i
].pcie_lane
;
3671 case PP_StateUILabel_Battery
:
3672 data
->use_pcie_power_saving_levels
= true;
3674 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3675 if (data
->pcie_gen_power_saving
.max
<
3676 ps
->performance_levels
[i
].pcie_gen
)
3677 data
->pcie_gen_power_saving
.max
=
3678 ps
->performance_levels
[i
].pcie_gen
;
3680 if (data
->pcie_gen_power_saving
.min
>
3681 ps
->performance_levels
[i
].pcie_gen
)
3682 data
->pcie_gen_power_saving
.min
=
3683 ps
->performance_levels
[i
].pcie_gen
;
3685 if (data
->pcie_lane_power_saving
.max
<
3686 ps
->performance_levels
[i
].pcie_lane
)
3687 data
->pcie_lane_power_saving
.max
=
3688 ps
->performance_levels
[i
].pcie_lane
;
3690 if (data
->pcie_lane_power_saving
.min
>
3691 ps
->performance_levels
[i
].pcie_lane
)
3692 data
->pcie_lane_power_saving
.min
=
3693 ps
->performance_levels
[i
].pcie_lane
;
3704 polaris10_print_current_perforce_level(struct pp_hwmgr
*hwmgr
, struct seq_file
*m
)
3706 uint32_t sclk
, mclk
, activity_percent
;
3708 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3710 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
3712 sclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
3714 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
3716 mclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
3717 seq_printf(m
, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3718 mclk
/ 100, sclk
/ 100);
3720 offset
= data
->soft_regs_start
+ offsetof(SMU74_SoftRegisters
, AverageGraphicsActivity
);
3721 activity_percent
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, offset
);
3722 activity_percent
+= 0x80;
3723 activity_percent
>>= 8;
3725 seq_printf(m
, "\n [GPU load]: %u%%\n\n", activity_percent
> 100 ? 100 : activity_percent
);
3727 seq_printf(m
, "uvd %sabled\n", data
->uvd_power_gated
? "dis" : "en");
3729 seq_printf(m
, "vce %sabled\n", data
->vce_power_gated
? "dis" : "en");
3732 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
3734 const struct phm_set_power_state_input
*states
=
3735 (const struct phm_set_power_state_input
*)input
;
3736 const struct polaris10_power_state
*polaris10_ps
=
3737 cast_const_phw_polaris10_power_state(states
->pnew_state
);
3738 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3739 struct polaris10_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
3740 uint32_t sclk
= polaris10_ps
->performance_levels
3741 [polaris10_ps
->performance_level_count
- 1].engine_clock
;
3742 struct polaris10_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
3743 uint32_t mclk
= polaris10_ps
->performance_levels
3744 [polaris10_ps
->performance_level_count
- 1].memory_clock
;
3745 struct PP_Clocks min_clocks
= {0};
3747 struct cgs_display_info info
= {0};
3749 data
->need_update_smu7_dpm_table
= 0;
3751 for (i
= 0; i
< sclk_table
->count
; i
++) {
3752 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
3756 if (i
>= sclk_table
->count
)
3757 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
3759 /* TODO: Check SCLK in DAL's minimum clocks
3760 * in case DeepSleep divider update is required.
3762 if (data
->display_timing
.min_clock_in_sr
!= min_clocks
.engineClockInSR
&&
3763 (min_clocks
.engineClockInSR
>= POLARIS10_MINIMUM_ENGINE_CLOCK
||
3764 data
->display_timing
.min_clock_in_sr
>= POLARIS10_MINIMUM_ENGINE_CLOCK
))
3765 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
3768 for (i
= 0; i
< mclk_table
->count
; i
++) {
3769 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
3773 if (i
>= mclk_table
->count
)
3774 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
3776 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3778 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
3779 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
3784 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr
*hwmgr
,
3785 const struct polaris10_power_state
*polaris10_ps
)
3788 uint32_t sclk
, max_sclk
= 0;
3789 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3790 struct polaris10_dpm_table
*dpm_table
= &data
->dpm_table
;
3792 for (i
= 0; i
< polaris10_ps
->performance_level_count
; i
++) {
3793 sclk
= polaris10_ps
->performance_levels
[i
].engine_clock
;
3794 if (max_sclk
< sclk
)
3798 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
3799 if (dpm_table
->sclk_table
.dpm_levels
[i
].value
== max_sclk
)
3800 return (uint16_t) ((i
>= dpm_table
->pcie_speed_table
.count
) ?
3801 dpm_table
->pcie_speed_table
.dpm_levels
3802 [dpm_table
->pcie_speed_table
.count
- 1].value
:
3803 dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
);
3809 static int polaris10_request_link_speed_change_before_state_change(
3810 struct pp_hwmgr
*hwmgr
, const void *input
)
3812 const struct phm_set_power_state_input
*states
=
3813 (const struct phm_set_power_state_input
*)input
;
3814 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3815 const struct polaris10_power_state
*polaris10_nps
=
3816 cast_const_phw_polaris10_power_state(states
->pnew_state
);
3817 const struct polaris10_power_state
*polaris10_cps
=
3818 cast_const_phw_polaris10_power_state(states
->pcurrent_state
);
3820 uint16_t target_link_speed
= polaris10_get_maximum_link_speed(hwmgr
, polaris10_nps
);
3821 uint16_t current_link_speed
;
3823 if (data
->force_pcie_gen
== PP_PCIEGenInvalid
)
3824 current_link_speed
= polaris10_get_maximum_link_speed(hwmgr
, polaris10_cps
);
3826 current_link_speed
= data
->force_pcie_gen
;
3828 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
3829 data
->pspp_notify_required
= false;
3831 if (target_link_speed
> current_link_speed
) {
3832 switch (target_link_speed
) {
3834 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN3
, false))
3836 data
->force_pcie_gen
= PP_PCIEGen2
;
3837 if (current_link_speed
== PP_PCIEGen2
)
3840 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN2
, false))
3843 data
->force_pcie_gen
= phm_get_current_pcie_speed(hwmgr
);
3847 if (target_link_speed
< current_link_speed
)
3848 data
->pspp_notify_required
= true;
3854 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
3856 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3858 if (0 == data
->need_update_smu7_dpm_table
)
3861 if ((0 == data
->sclk_dpm_key_disabled
) &&
3862 (data
->need_update_smu7_dpm_table
&
3863 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
3864 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr
),
3865 "Trying to freeze SCLK DPM when DPM is disabled",
3867 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3868 PPSMC_MSG_SCLKDPM_FreezeLevel
),
3869 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3873 if ((0 == data
->mclk_dpm_key_disabled
) &&
3874 (data
->need_update_smu7_dpm_table
&
3875 DPMTABLE_OD_UPDATE_MCLK
)) {
3876 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr
),
3877 "Trying to freeze MCLK DPM when DPM is disabled",
3879 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3880 PPSMC_MSG_MCLKDPM_FreezeLevel
),
3881 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3888 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3889 struct pp_hwmgr
*hwmgr
, const void *input
)
3892 const struct phm_set_power_state_input
*states
=
3893 (const struct phm_set_power_state_input
*)input
;
3894 const struct polaris10_power_state
*polaris10_ps
=
3895 cast_const_phw_polaris10_power_state(states
->pnew_state
);
3896 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
3897 uint32_t sclk
= polaris10_ps
->performance_levels
3898 [polaris10_ps
->performance_level_count
- 1].engine_clock
;
3899 uint32_t mclk
= polaris10_ps
->performance_levels
3900 [polaris10_ps
->performance_level_count
- 1].memory_clock
;
3901 struct polaris10_dpm_table
*dpm_table
= &data
->dpm_table
;
3903 struct polaris10_dpm_table
*golden_dpm_table
= &data
->golden_dpm_table
;
3904 uint32_t dpm_count
, clock_percent
;
3907 if (0 == data
->need_update_smu7_dpm_table
)
3910 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
3911 dpm_table
->sclk_table
.dpm_levels
3912 [dpm_table
->sclk_table
.count
- 1].value
= sclk
;
3914 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
3915 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
3916 /* Need to do calculation based on the golden DPM table
3917 * as the Heatmap GPU Clock axis is also based on the default values
3919 PP_ASSERT_WITH_CODE(
3920 (golden_dpm_table
->sclk_table
.dpm_levels
3921 [golden_dpm_table
->sclk_table
.count
- 1].value
!= 0),
3924 dpm_count
= dpm_table
->sclk_table
.count
< 2 ? 0 : dpm_table
->sclk_table
.count
- 2;
3926 for (i
= dpm_count
; i
> 1; i
--) {
3927 if (sclk
> golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
) {
3930 - golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
3932 / golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
;
3934 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3935 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
+
3936 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
3939 } else if (golden_dpm_table
->sclk_table
.dpm_levels
[dpm_table
->sclk_table
.count
-1].value
> sclk
) {
3941 ((golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
- 1].value
3943 / golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
;
3945 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3946 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
-
3947 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
3948 clock_percent
) / 100;
3950 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3951 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
;
3956 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
3957 dpm_table
->mclk_table
.dpm_levels
3958 [dpm_table
->mclk_table
.count
- 1].value
= mclk
;
3960 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
3961 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
3963 PP_ASSERT_WITH_CODE(
3964 (golden_dpm_table
->mclk_table
.dpm_levels
3965 [golden_dpm_table
->mclk_table
.count
-1].value
!= 0),
3968 dpm_count
= dpm_table
->mclk_table
.count
< 2 ? 0 : dpm_table
->mclk_table
.count
- 2;
3969 for (i
= dpm_count
; i
> 1; i
--) {
3970 if (golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
< mclk
) {
3971 clock_percent
= ((mclk
-
3972 golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
) * 100)
3973 / golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
;
3975 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3976 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
+
3977 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
3978 clock_percent
) / 100;
3980 } else if (golden_dpm_table
->mclk_table
.dpm_levels
[dpm_table
->mclk_table
.count
-1].value
> mclk
) {
3982 (golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
- mclk
)
3984 / golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
;
3986 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3987 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
-
3988 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
3989 clock_percent
) / 100;
3991 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3992 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
;
3997 if (data
->need_update_smu7_dpm_table
&
3998 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
)) {
3999 result
= polaris10_populate_all_graphic_levels(hwmgr
);
4000 PP_ASSERT_WITH_CODE((0 == result
),
4001 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4005 if (data
->need_update_smu7_dpm_table
&
4006 (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
4007 /*populate MCLK dpm table to SMU7 */
4008 result
= polaris10_populate_all_memory_levels(hwmgr
);
4009 PP_ASSERT_WITH_CODE((0 == result
),
4010 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4017 static int polaris10_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
4018 struct polaris10_single_dpm_table
*dpm_table
,
4019 uint32_t low_limit
, uint32_t high_limit
)
4023 for (i
= 0; i
< dpm_table
->count
; i
++) {
4024 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
)
4025 || (dpm_table
->dpm_levels
[i
].value
> high_limit
))
4026 dpm_table
->dpm_levels
[i
].enabled
= false;
4028 dpm_table
->dpm_levels
[i
].enabled
= true;
4034 static int polaris10_trim_dpm_states(struct pp_hwmgr
*hwmgr
,
4035 const struct polaris10_power_state
*polaris10_ps
)
4038 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4039 uint32_t high_limit_count
;
4041 PP_ASSERT_WITH_CODE((polaris10_ps
->performance_level_count
>= 1),
4042 "power state did not have any performance level",
4045 high_limit_count
= (1 == polaris10_ps
->performance_level_count
) ? 0 : 1;
4047 polaris10_trim_single_dpm_states(hwmgr
,
4048 &(data
->dpm_table
.sclk_table
),
4049 polaris10_ps
->performance_levels
[0].engine_clock
,
4050 polaris10_ps
->performance_levels
[high_limit_count
].engine_clock
);
4052 polaris10_trim_single_dpm_states(hwmgr
,
4053 &(data
->dpm_table
.mclk_table
),
4054 polaris10_ps
->performance_levels
[0].memory_clock
,
4055 polaris10_ps
->performance_levels
[high_limit_count
].memory_clock
);
4060 static int polaris10_generate_dpm_level_enable_mask(
4061 struct pp_hwmgr
*hwmgr
, const void *input
)
4064 const struct phm_set_power_state_input
*states
=
4065 (const struct phm_set_power_state_input
*)input
;
4066 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4067 const struct polaris10_power_state
*polaris10_ps
=
4068 cast_const_phw_polaris10_power_state(states
->pnew_state
);
4070 result
= polaris10_trim_dpm_states(hwmgr
, polaris10_ps
);
4074 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
4075 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.sclk_table
);
4076 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
4077 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.mclk_table
);
4078 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
4079 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.pcie_speed_table
);
4084 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4086 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4087 PPSMC_MSG_UVDDPM_Enable
:
4088 PPSMC_MSG_UVDDPM_Disable
);
4091 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4093 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4094 PPSMC_MSG_VCEDPM_Enable
:
4095 PPSMC_MSG_VCEDPM_Disable
);
4098 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4100 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4101 PPSMC_MSG_SAMUDPM_Enable
:
4102 PPSMC_MSG_SAMUDPM_Disable
);
4105 int polaris10_update_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4107 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4108 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4109 struct phm_ppt_v1_information
*table_info
=
4110 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4113 data
->smc_state_table
.UvdBootLevel
= 0;
4114 if (table_info
->mm_dep_table
->count
> 0)
4115 data
->smc_state_table
.UvdBootLevel
=
4116 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4117 mm_boot_level_offset
= data
->dpm_table_start
+
4118 offsetof(SMU74_Discrete_DpmTable
, UvdBootLevel
);
4119 mm_boot_level_offset
/= 4;
4120 mm_boot_level_offset
*= 4;
4121 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4122 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4123 mm_boot_level_value
&= 0x00FFFFFF;
4124 mm_boot_level_value
|= data
->smc_state_table
.UvdBootLevel
<< 24;
4125 cgs_write_ind_register(hwmgr
->device
,
4126 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4128 if (!phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4129 PHM_PlatformCaps_UVDDPM
) ||
4130 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4131 PHM_PlatformCaps_StablePState
))
4132 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4133 PPSMC_MSG_UVDDPM_SetEnabledMask
,
4134 (uint32_t)(1 << data
->smc_state_table
.UvdBootLevel
));
4137 return polaris10_enable_disable_uvd_dpm(hwmgr
, !bgate
);
4140 static int polaris10_update_vce_dpm(struct pp_hwmgr
*hwmgr
, const void *input
)
4142 const struct phm_set_power_state_input
*states
=
4143 (const struct phm_set_power_state_input
*)input
;
4144 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4145 const struct polaris10_power_state
*polaris10_nps
=
4146 cast_const_phw_polaris10_power_state(states
->pnew_state
);
4147 const struct polaris10_power_state
*polaris10_cps
=
4148 cast_const_phw_polaris10_power_state(states
->pcurrent_state
);
4150 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4151 struct phm_ppt_v1_information
*table_info
=
4152 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4154 if (polaris10_nps
->vce_clks
.evclk
> 0 &&
4155 (polaris10_cps
== NULL
|| polaris10_cps
->vce_clks
.evclk
== 0)) {
4157 data
->smc_state_table
.VceBootLevel
=
4158 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4160 mm_boot_level_offset
= data
->dpm_table_start
+
4161 offsetof(SMU74_Discrete_DpmTable
, VceBootLevel
);
4162 mm_boot_level_offset
/= 4;
4163 mm_boot_level_offset
*= 4;
4164 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4165 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4166 mm_boot_level_value
&= 0xFF00FFFF;
4167 mm_boot_level_value
|= data
->smc_state_table
.VceBootLevel
<< 16;
4168 cgs_write_ind_register(hwmgr
->device
,
4169 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4171 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_StablePState
)) {
4172 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4173 PPSMC_MSG_VCEDPM_SetEnabledMask
,
4174 (uint32_t)1 << data
->smc_state_table
.VceBootLevel
);
4176 polaris10_enable_disable_vce_dpm(hwmgr
, true);
4177 } else if (polaris10_nps
->vce_clks
.evclk
== 0 &&
4178 polaris10_cps
!= NULL
&&
4179 polaris10_cps
->vce_clks
.evclk
> 0)
4180 polaris10_enable_disable_vce_dpm(hwmgr
, false);
4186 int polaris10_update_samu_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4188 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4189 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4190 struct phm_ppt_v1_information
*table_info
=
4191 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4194 data
->smc_state_table
.SamuBootLevel
=
4195 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4196 mm_boot_level_offset
= data
->dpm_table_start
+
4197 offsetof(SMU74_Discrete_DpmTable
, SamuBootLevel
);
4198 mm_boot_level_offset
/= 4;
4199 mm_boot_level_offset
*= 4;
4200 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4201 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4202 mm_boot_level_value
&= 0xFFFFFF00;
4203 mm_boot_level_value
|= data
->smc_state_table
.SamuBootLevel
<< 0;
4204 cgs_write_ind_register(hwmgr
->device
,
4205 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4207 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4208 PHM_PlatformCaps_StablePState
))
4209 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4210 PPSMC_MSG_SAMUDPM_SetEnabledMask
,
4211 (uint32_t)(1 << data
->smc_state_table
.SamuBootLevel
));
4214 return polaris10_enable_disable_samu_dpm(hwmgr
, !bgate
);
4217 static int polaris10_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4219 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4222 uint32_t low_sclk_interrupt_threshold
= 0;
4224 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4225 PHM_PlatformCaps_SclkThrottleLowNotification
)
4226 && (hwmgr
->gfx_arbiter
.sclk_threshold
!=
4227 data
->low_sclk_interrupt_threshold
)) {
4228 data
->low_sclk_interrupt_threshold
=
4229 hwmgr
->gfx_arbiter
.sclk_threshold
;
4230 low_sclk_interrupt_threshold
=
4231 data
->low_sclk_interrupt_threshold
;
4233 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold
);
4235 result
= polaris10_copy_bytes_to_smc(
4237 data
->dpm_table_start
+
4238 offsetof(SMU74_Discrete_DpmTable
,
4239 LowSclkInterruptThreshold
),
4240 (uint8_t *)&low_sclk_interrupt_threshold
,
4248 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr
*hwmgr
)
4250 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4252 if (data
->need_update_smu7_dpm_table
&
4253 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_OD_UPDATE_MCLK
))
4254 return polaris10_program_memory_timing_parameters(hwmgr
);
4259 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4261 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4263 if (0 == data
->need_update_smu7_dpm_table
)
4266 if ((0 == data
->sclk_dpm_key_disabled
) &&
4267 (data
->need_update_smu7_dpm_table
&
4268 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4270 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr
),
4271 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4273 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4274 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4275 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4279 if ((0 == data
->mclk_dpm_key_disabled
) &&
4280 (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
4282 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr
),
4283 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4285 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4286 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4287 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4291 data
->need_update_smu7_dpm_table
= 0;
4296 static int polaris10_notify_link_speed_change_after_state_change(
4297 struct pp_hwmgr
*hwmgr
, const void *input
)
4299 const struct phm_set_power_state_input
*states
=
4300 (const struct phm_set_power_state_input
*)input
;
4301 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4302 const struct polaris10_power_state
*polaris10_ps
=
4303 cast_const_phw_polaris10_power_state(states
->pnew_state
);
4304 uint16_t target_link_speed
= polaris10_get_maximum_link_speed(hwmgr
, polaris10_ps
);
4307 if (data
->pspp_notify_required
) {
4308 if (target_link_speed
== PP_PCIEGen3
)
4309 request
= PCIE_PERF_REQ_GEN3
;
4310 else if (target_link_speed
== PP_PCIEGen2
)
4311 request
= PCIE_PERF_REQ_GEN2
;
4313 request
= PCIE_PERF_REQ_GEN1
;
4315 if (request
== PCIE_PERF_REQ_GEN1
&&
4316 phm_get_current_pcie_speed(hwmgr
) > 0)
4319 if (acpi_pcie_perf_request(hwmgr
->device
, request
, false)) {
4320 if (PP_PCIEGen2
== target_link_speed
)
4321 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4323 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4330 static int polaris10_set_power_state_tasks(struct pp_hwmgr
*hwmgr
, const void *input
)
4332 int tmp_result
, result
= 0;
4333 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4335 tmp_result
= polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
4336 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4337 "Failed to find DPM states clocks in DPM table!",
4338 result
= tmp_result
);
4340 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4341 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4343 polaris10_request_link_speed_change_before_state_change(hwmgr
, input
);
4344 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4345 "Failed to request link speed change before state change!",
4346 result
= tmp_result
);
4349 tmp_result
= polaris10_freeze_sclk_mclk_dpm(hwmgr
);
4350 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4351 "Failed to freeze SCLK MCLK DPM!", result
= tmp_result
);
4353 tmp_result
= polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
4354 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4355 "Failed to populate and upload SCLK MCLK DPM levels!",
4356 result
= tmp_result
);
4358 tmp_result
= polaris10_generate_dpm_level_enable_mask(hwmgr
, input
);
4359 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4360 "Failed to generate DPM level enabled mask!",
4361 result
= tmp_result
);
4363 tmp_result
= polaris10_update_vce_dpm(hwmgr
, input
);
4364 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4365 "Failed to update VCE DPM!",
4366 result
= tmp_result
);
4368 tmp_result
= polaris10_update_sclk_threshold(hwmgr
);
4369 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4370 "Failed to update SCLK threshold!",
4371 result
= tmp_result
);
4373 tmp_result
= polaris10_program_mem_timing_parameters(hwmgr
);
4374 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4375 "Failed to program memory timing parameters!",
4376 result
= tmp_result
);
4378 tmp_result
= polaris10_unfreeze_sclk_mclk_dpm(hwmgr
);
4379 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4380 "Failed to unfreeze SCLK MCLK DPM!",
4381 result
= tmp_result
);
4383 tmp_result
= polaris10_upload_dpm_level_enable_mask(hwmgr
);
4384 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4385 "Failed to upload DPM level enabled mask!",
4386 result
= tmp_result
);
4388 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4389 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4391 polaris10_notify_link_speed_change_after_state_change(hwmgr
, input
);
4392 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4393 "Failed to notify link speed change after state change!",
4394 result
= tmp_result
);
4396 data
->apply_optimized_settings
= false;
4400 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
)
4402 hwmgr
->thermal_controller
.
4403 advanceFanControlParameters
.usMaxFanPWM
= us_max_fan_pwm
;
4405 if (phm_is_hw_access_blocked(hwmgr
))
4408 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4409 PPSMC_MSG_SetFanPwmMax
, us_max_fan_pwm
);
4412 int polaris10_notify_smc_display_change(struct pp_hwmgr
*hwmgr
, bool has_display
)
4414 PPSMC_Msg msg
= has_display
? (PPSMC_Msg
)PPSMC_HasDisplay
: (PPSMC_Msg
)PPSMC_NoDisplay
;
4416 return (smum_send_msg_to_smc(hwmgr
->smumgr
, msg
) == 0) ? 0 : -1;
4419 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
*hwmgr
)
4421 uint32_t num_active_displays
= 0;
4422 struct cgs_display_info info
= {0};
4423 info
.mode_info
= NULL
;
4425 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4427 num_active_displays
= info
.display_count
;
4429 if (num_active_displays
> 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4430 polaris10_notify_smc_display_change(hwmgr
, false);
4432 polaris10_notify_smc_display_change(hwmgr
, true);
4438 * Programs the display gap
4440 * @param hwmgr the address of the powerplay hardware manager.
4443 int polaris10_program_display_gap(struct pp_hwmgr
*hwmgr
)
4445 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4446 uint32_t num_active_displays
= 0;
4447 uint32_t display_gap
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
);
4448 uint32_t display_gap2
;
4449 uint32_t pre_vbi_time_in_us
;
4450 uint32_t frame_time_in_us
;
4452 uint32_t refresh_rate
= 0;
4453 struct cgs_display_info info
= {0};
4454 struct cgs_mode_info mode_info
;
4456 info
.mode_info
= &mode_info
;
4458 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4459 num_active_displays
= info
.display_count
;
4461 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
, DISP_GAP
, (num_active_displays
> 0) ? DISPLAY_GAP_VBLANK_OR_WM
: DISPLAY_GAP_IGNORE
);
4462 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
, display_gap
);
4464 ref_clock
= mode_info
.ref_clock
;
4465 refresh_rate
= mode_info
.refresh_rate
;
4467 if (0 == refresh_rate
)
4470 frame_time_in_us
= 1000000 / refresh_rate
;
4472 pre_vbi_time_in_us
= frame_time_in_us
- 200 - mode_info
.vblank_time_us
;
4473 display_gap2
= pre_vbi_time_in_us
* (ref_clock
/ 100);
4475 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL2
, display_gap2
);
4477 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, data
->soft_regs_start
+ offsetof(SMU74_SoftRegisters
, PreVBlankGap
), 0x64);
4479 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, data
->soft_regs_start
+ offsetof(SMU74_SoftRegisters
, VBlankTimeout
), (frame_time_in_us
- pre_vbi_time_in_us
));
4481 polaris10_notify_smc_display_change(hwmgr
, num_active_displays
!= 0);
4487 int polaris10_display_configuration_changed_task(struct pp_hwmgr
*hwmgr
)
4489 return polaris10_program_display_gap(hwmgr
);
4493 * Set maximum target operating fan output RPM
4495 * @param hwmgr: the address of the powerplay hardware manager.
4496 * @param usMaxFanRpm: max operating fan RPM value.
4497 * @return The response that came from the SMC.
4499 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_rpm
)
4501 hwmgr
->thermal_controller
.
4502 advanceFanControlParameters
.usMaxFanRPM
= us_max_fan_rpm
;
4504 if (phm_is_hw_access_blocked(hwmgr
))
4507 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4508 PPSMC_MSG_SetFanRpmMax
, us_max_fan_rpm
);
4511 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr
*hwmgr
,
4512 const void *thermal_interrupt_info
)
4517 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr
*hwmgr
)
4519 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4520 bool is_update_required
= false;
4521 struct cgs_display_info info
= {0, 0, NULL
};
4523 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4525 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
4526 is_update_required
= true;
4527 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4528 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4529 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4530 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4531 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4532 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4533 is_update_required = true;
4535 return is_update_required
;
4538 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level
*pl1
,
4539 const struct polaris10_performance_level
*pl2
)
4541 return ((pl1
->memory_clock
== pl2
->memory_clock
) &&
4542 (pl1
->engine_clock
== pl2
->engine_clock
) &&
4543 (pl1
->pcie_gen
== pl2
->pcie_gen
) &&
4544 (pl1
->pcie_lane
== pl2
->pcie_lane
));
4547 int polaris10_check_states_equal(struct pp_hwmgr
*hwmgr
, const struct pp_hw_power_state
*pstate1
, const struct pp_hw_power_state
*pstate2
, bool *equal
)
4549 const struct polaris10_power_state
*psa
= cast_const_phw_polaris10_power_state(pstate1
);
4550 const struct polaris10_power_state
*psb
= cast_const_phw_polaris10_power_state(pstate2
);
4553 if (pstate1
== NULL
|| pstate2
== NULL
|| equal
== NULL
)
4556 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4557 if (psa
->performance_level_count
!= psb
->performance_level_count
) {
4562 for (i
= 0; i
< psa
->performance_level_count
; i
++) {
4563 if (!polaris10_are_power_levels_equal(&(psa
->performance_levels
[i
]), &(psb
->performance_levels
[i
]))) {
4564 /* If we have found even one performance level pair that is different the states are different. */
4570 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4571 *equal
= ((psa
->uvd_clks
.vclk
== psb
->uvd_clks
.vclk
) && (psa
->uvd_clks
.dclk
== psb
->uvd_clks
.dclk
));
4572 *equal
&= ((psa
->vce_clks
.evclk
== psb
->vce_clks
.evclk
) && (psa
->vce_clks
.ecclk
== psb
->vce_clks
.ecclk
));
4573 *equal
&= (psa
->sclk_threshold
== psb
->sclk_threshold
);
4578 int polaris10_upload_mc_firmware(struct pp_hwmgr
*hwmgr
)
4580 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4582 uint32_t vbios_version
;
4584 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4586 phm_get_mc_microcode_version(hwmgr
);
4587 vbios_version
= hwmgr
->microcode_version_info
.MC
& 0xf;
4588 /* Full version of MC ucode has already been loaded. */
4589 if (vbios_version
== 0) {
4590 data
->need_long_memory_training
= false;
4594 data
->need_long_memory_training
= true;
4597 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4598 pfd = &tonga_mcmeFirmware;
4599 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4600 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4601 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4602 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4608 * Read clock related registers.
4610 * @param hwmgr the address of the powerplay hardware manager.
4613 static int polaris10_read_clock_registers(struct pp_hwmgr
*hwmgr
)
4615 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4617 data
->clock_registers
.vCG_SPLL_FUNC_CNTL
= cgs_read_ind_register(hwmgr
->device
,
4618 CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL
)
4619 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK
;
4621 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
= cgs_read_ind_register(hwmgr
->device
,
4622 CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_2
)
4623 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK
;
4625 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
= cgs_read_ind_register(hwmgr
->device
,
4626 CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_4
)
4627 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK
;
4633 * Find out if memory is GDDR5.
4635 * @param hwmgr the address of the powerplay hardware manager.
4638 static int polaris10_get_memory_type(struct pp_hwmgr
*hwmgr
)
4640 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4643 temp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC0
);
4645 data
->is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
==
4646 ((temp
& MC_SEQ_MISC0_GDDR5_MASK
) >>
4647 MC_SEQ_MISC0_GDDR5_SHIFT
));
4653 * Enables Dynamic Power Management by SMC
4655 * @param hwmgr the address of the powerplay hardware manager.
4658 static int polaris10_enable_acpi_power_management(struct pp_hwmgr
*hwmgr
)
4660 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
4661 GENERAL_PWRMGT
, STATIC_PM_EN
, 1);
4667 * Initialize PowerGating States for different engines
4669 * @param hwmgr the address of the powerplay hardware manager.
4672 static int polaris10_init_power_gate_state(struct pp_hwmgr
*hwmgr
)
4674 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4676 data
->uvd_power_gated
= false;
4677 data
->vce_power_gated
= false;
4678 data
->samu_power_gated
= false;
4683 static int polaris10_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4685 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4686 data
->low_sclk_interrupt_threshold
= 0;
4691 int polaris10_setup_asic_task(struct pp_hwmgr
*hwmgr
)
4693 int tmp_result
, result
= 0;
4695 polaris10_upload_mc_firmware(hwmgr
);
4697 tmp_result
= polaris10_read_clock_registers(hwmgr
);
4698 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4699 "Failed to read clock registers!", result
= tmp_result
);
4701 tmp_result
= polaris10_get_memory_type(hwmgr
);
4702 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4703 "Failed to get memory type!", result
= tmp_result
);
4705 tmp_result
= polaris10_enable_acpi_power_management(hwmgr
);
4706 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4707 "Failed to enable ACPI power management!", result
= tmp_result
);
4709 tmp_result
= polaris10_init_power_gate_state(hwmgr
);
4710 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4711 "Failed to init power gate state!", result
= tmp_result
);
4713 tmp_result
= phm_get_mc_microcode_version(hwmgr
);
4714 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4715 "Failed to get MC microcode version!", result
= tmp_result
);
4717 tmp_result
= polaris10_init_sclk_threshold(hwmgr
);
4718 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4719 "Failed to init sclk threshold!", result
= tmp_result
);
4724 static int polaris10_get_pp_table(struct pp_hwmgr
*hwmgr
, char **table
)
4726 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4728 if (!data
->soft_pp_table
) {
4729 data
->soft_pp_table
= kmemdup(hwmgr
->soft_pp_table
,
4730 hwmgr
->soft_pp_table_size
,
4732 if (!data
->soft_pp_table
)
4736 *table
= (char *)&data
->soft_pp_table
;
4738 return hwmgr
->soft_pp_table_size
;
4741 static int polaris10_set_pp_table(struct pp_hwmgr
*hwmgr
, const char *buf
, size_t size
)
4743 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4745 if (!data
->soft_pp_table
) {
4746 data
->soft_pp_table
= kzalloc(hwmgr
->soft_pp_table_size
, GFP_KERNEL
);
4747 if (!data
->soft_pp_table
)
4751 memcpy(data
->soft_pp_table
, buf
, size
);
4753 hwmgr
->soft_pp_table
= data
->soft_pp_table
;
4755 /* TODO: re-init powerplay to implement modified pptable */
4760 static int polaris10_force_clock_level(struct pp_hwmgr
*hwmgr
,
4761 enum pp_clock_type type
, uint32_t mask
)
4763 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4765 if (hwmgr
->dpm_level
!= AMD_DPM_FORCED_LEVEL_MANUAL
)
4770 if (!data
->sclk_dpm_key_disabled
)
4771 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4772 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4773 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
& mask
);
4776 if (!data
->mclk_dpm_key_disabled
)
4777 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4778 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4779 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& mask
);
4783 uint32_t tmp
= mask
& data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
4789 if (!data
->pcie_dpm_key_disabled
)
4790 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4791 PPSMC_MSG_PCIeDPM_ForceLevel
,
4802 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
4804 uint32_t speedCntl
= 0;
4806 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4807 speedCntl
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__PCIE
,
4808 ixPCIE_LC_SPEED_CNTL
);
4809 return((uint16_t)PHM_GET_FIELD(speedCntl
,
4810 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
4813 static int polaris10_print_clock_levels(struct pp_hwmgr
*hwmgr
,
4814 enum pp_clock_type type
, char *buf
)
4816 struct polaris10_hwmgr
*data
= (struct polaris10_hwmgr
*)(hwmgr
->backend
);
4817 struct polaris10_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
4818 struct polaris10_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
4819 struct polaris10_single_dpm_table
*pcie_table
= &(data
->dpm_table
.pcie_speed_table
);
4820 int i
, now
, size
= 0;
4821 uint32_t clock
, pcie_speed
;
4825 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
4826 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4828 for (i
= 0; i
< sclk_table
->count
; i
++) {
4829 if (clock
> sclk_table
->dpm_levels
[i
].value
)
4835 for (i
= 0; i
< sclk_table
->count
; i
++)
4836 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4837 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
4838 (i
== now
) ? "*" : "");
4841 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
4842 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4844 for (i
= 0; i
< mclk_table
->count
; i
++) {
4845 if (clock
> mclk_table
->dpm_levels
[i
].value
)
4851 for (i
= 0; i
< mclk_table
->count
; i
++)
4852 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4853 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
4854 (i
== now
) ? "*" : "");
4857 pcie_speed
= polaris10_get_current_pcie_speed(hwmgr
);
4858 for (i
= 0; i
< pcie_table
->count
; i
++) {
4859 if (pcie_speed
!= pcie_table
->dpm_levels
[i
].value
)
4865 for (i
= 0; i
< pcie_table
->count
; i
++)
4866 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
4867 (pcie_table
->dpm_levels
[i
].value
== 0) ? "2.5GB, x8" :
4868 (pcie_table
->dpm_levels
[i
].value
== 1) ? "5.0GB, x16" :
4869 (pcie_table
->dpm_levels
[i
].value
== 2) ? "8.0GB, x16" : "",
4870 (i
== now
) ? "*" : "");
4878 static int polaris10_set_fan_control_mode(struct pp_hwmgr
*hwmgr
, uint32_t mode
)
4881 /* stop auto-manage */
4882 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4883 PHM_PlatformCaps_MicrocodeFanControl
))
4884 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr
);
4885 polaris10_fan_ctrl_set_static_mode(hwmgr
, mode
);
4887 /* restart auto-manage */
4888 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr
);
4893 static int polaris10_get_fan_control_mode(struct pp_hwmgr
*hwmgr
)
4895 if (hwmgr
->fan_ctrl_is_in_default_mode
)
4896 return hwmgr
->fan_ctrl_default_mode
;
4898 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
4899 CG_FDO_CTRL2
, FDO_PWM_MODE
);
4902 static const struct pp_hwmgr_func polaris10_hwmgr_funcs
= {
4903 .backend_init
= &polaris10_hwmgr_backend_init
,
4904 .backend_fini
= &polaris10_hwmgr_backend_fini
,
4905 .asic_setup
= &polaris10_setup_asic_task
,
4906 .dynamic_state_management_enable
= &polaris10_enable_dpm_tasks
,
4907 .apply_state_adjust_rules
= polaris10_apply_state_adjust_rules
,
4908 .force_dpm_level
= &polaris10_force_dpm_level
,
4909 .power_state_set
= polaris10_set_power_state_tasks
,
4910 .get_power_state_size
= polaris10_get_power_state_size
,
4911 .get_mclk
= polaris10_dpm_get_mclk
,
4912 .get_sclk
= polaris10_dpm_get_sclk
,
4913 .patch_boot_state
= polaris10_dpm_patch_boot_state
,
4914 .get_pp_table_entry
= polaris10_get_pp_table_entry
,
4915 .get_num_of_pp_table_entries
= tonga_get_number_of_powerplay_table_entries
,
4916 .print_current_perforce_level
= polaris10_print_current_perforce_level
,
4917 .powerdown_uvd
= polaris10_phm_powerdown_uvd
,
4918 .powergate_uvd
= polaris10_phm_powergate_uvd
,
4919 .powergate_vce
= polaris10_phm_powergate_vce
,
4920 .disable_clock_power_gating
= polaris10_phm_disable_clock_power_gating
,
4921 .update_clock_gatings
= polaris10_phm_update_clock_gatings
,
4922 .notify_smc_display_config_after_ps_adjustment
= polaris10_notify_smc_display_config_after_ps_adjustment
,
4923 .display_config_changed
= polaris10_display_configuration_changed_task
,
4924 .set_max_fan_pwm_output
= polaris10_set_max_fan_pwm_output
,
4925 .set_max_fan_rpm_output
= polaris10_set_max_fan_rpm_output
,
4926 .get_temperature
= polaris10_thermal_get_temperature
,
4927 .stop_thermal_controller
= polaris10_thermal_stop_thermal_controller
,
4928 .get_fan_speed_info
= polaris10_fan_ctrl_get_fan_speed_info
,
4929 .get_fan_speed_percent
= polaris10_fan_ctrl_get_fan_speed_percent
,
4930 .set_fan_speed_percent
= polaris10_fan_ctrl_set_fan_speed_percent
,
4931 .reset_fan_speed_to_default
= polaris10_fan_ctrl_reset_fan_speed_to_default
,
4932 .get_fan_speed_rpm
= polaris10_fan_ctrl_get_fan_speed_rpm
,
4933 .set_fan_speed_rpm
= polaris10_fan_ctrl_set_fan_speed_rpm
,
4934 .uninitialize_thermal_controller
= polaris10_thermal_ctrl_uninitialize_thermal_controller
,
4935 .register_internal_thermal_interrupt
= polaris10_register_internal_thermal_interrupt
,
4936 .check_smc_update_required_for_display_configuration
= polaris10_check_smc_update_required_for_display_configuration
,
4937 .check_states_equal
= polaris10_check_states_equal
,
4938 .set_fan_control_mode
= polaris10_set_fan_control_mode
,
4939 .get_fan_control_mode
= polaris10_get_fan_control_mode
,
4940 .get_pp_table
= polaris10_get_pp_table
,
4941 .set_pp_table
= polaris10_set_pp_table
,
4942 .force_clock_level
= polaris10_force_clock_level
,
4943 .print_clock_levels
= polaris10_print_clock_levels
,
4944 .enable_per_cu_power_gating
= polaris10_phm_enable_per_cu_power_gating
,
4947 int polaris10_hwmgr_init(struct pp_hwmgr
*hwmgr
)
4949 struct polaris10_hwmgr
*data
;
4951 data
= kzalloc (sizeof(struct polaris10_hwmgr
), GFP_KERNEL
);
4955 hwmgr
->backend
= data
;
4956 hwmgr
->hwmgr_func
= &polaris10_hwmgr_funcs
;
4957 hwmgr
->pptable_func
= &tonga_pptable_funcs
;
4958 pp_polaris10_thermal_initialize(hwmgr
);