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drm/amd/powerplay: fix mclk in high clock for baffin
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include "linux/delay.h"
27 #include "pp_acpi.h"
28 #include "hwmgr.h"
29 #include "polaris10_hwmgr.h"
30 #include "polaris10_powertune.h"
31 #include "polaris10_dyn_defaults.h"
32 #include "polaris10_smumgr.h"
33 #include "pp_debug.h"
34 #include "ppatomctrl.h"
35 #include "atombios.h"
36 #include "tonga_pptable.h"
37 #include "pppcielanes.h"
38 #include "amd_pcie_helpers.h"
39 #include "hardwaremanager.h"
40 #include "tonga_processpptables.h"
41 #include "cgs_common.h"
42 #include "smu74.h"
43 #include "smu_ucode_xfer_vi.h"
44 #include "smu74_discrete.h"
45 #include "smu/smu_7_1_3_d.h"
46 #include "smu/smu_7_1_3_sh_mask.h"
47 #include "gmc/gmc_8_1_d.h"
48 #include "gmc/gmc_8_1_sh_mask.h"
49 #include "oss/oss_3_0_d.h"
50 #include "gca/gfx_8_0_d.h"
51 #include "bif/bif_5_0_d.h"
52 #include "bif/bif_5_0_sh_mask.h"
53 #include "gmc/gmc_8_1_d.h"
54 #include "gmc/gmc_8_1_sh_mask.h"
55 #include "bif/bif_5_0_d.h"
56 #include "bif/bif_5_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
59
60 #include "polaris10_thermal.h"
61 #include "polaris10_clockpowergating.h"
62
63 #define MC_CG_ARB_FREQ_F0 0x0a
64 #define MC_CG_ARB_FREQ_F1 0x0b
65 #define MC_CG_ARB_FREQ_F2 0x0c
66 #define MC_CG_ARB_FREQ_F3 0x0d
67
68 #define MC_CG_SEQ_DRAMCONF_S0 0x05
69 #define MC_CG_SEQ_DRAMCONF_S1 0x06
70 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
71 #define MC_CG_SEQ_YCLK_RESUME 0x0a
72
73
74 #define SMC_RAM_END 0x40000
75
76 #define SMC_CG_IND_START 0xc0030000
77 #define SMC_CG_IND_END 0xc0040000
78
79 #define VOLTAGE_SCALE 4
80 #define VOLTAGE_VID_OFFSET_SCALE1 625
81 #define VOLTAGE_VID_OFFSET_SCALE2 100
82
83 #define VDDC_VDDCI_DELTA 200
84
85 #define MEM_FREQ_LOW_LATENCY 25000
86 #define MEM_FREQ_HIGH_LATENCY 80000
87
88 #define MEM_LATENCY_HIGH 45
89 #define MEM_LATENCY_LOW 35
90 #define MEM_LATENCY_ERR 0xFFFF
91
92 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
93 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
94 #define MC_SEQ_MISC0_GDDR5_VALUE 5
95
96
97 #define PCIE_BUS_CLK 10000
98 #define TCLK (PCIE_BUS_CLK / 10)
99
100
101 uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
102 {600, 1050, 6, 1} };
103
104 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
105 uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
106 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
107
108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
109 uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
110 {0, 2, 4, 5, 6, 5} };
111
112 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
113 enum DPM_EVENT_SRC {
114 DPM_EVENT_SRC_ANALOG = 0,
115 DPM_EVENT_SRC_EXTERNAL = 1,
116 DPM_EVENT_SRC_DIGITAL = 2,
117 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
118 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
119 };
120
121 const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
122
123 struct polaris10_power_state *cast_phw_polaris10_power_state(
124 struct pp_hw_power_state *hw_ps)
125 {
126 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
127 "Invalid Powerstate Type!",
128 return NULL);
129
130 return (struct polaris10_power_state *)hw_ps;
131 }
132
133 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
134 const struct pp_hw_power_state *hw_ps)
135 {
136 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
137 "Invalid Powerstate Type!",
138 return NULL);
139
140 return (const struct polaris10_power_state *)hw_ps;
141 }
142
143 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
144 {
145 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
146 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
147 ? true : false;
148 }
149
150 /**
151 * Find the MC microcode version and store it in the HwMgr struct
152 *
153 * @param hwmgr the address of the powerplay hardware manager.
154 * @return always 0
155 */
156 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
157 {
158 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
159
160 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
161
162 return 0;
163 }
164
165 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
166 {
167 uint32_t speedCntl = 0;
168
169 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
170 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
171 ixPCIE_LC_SPEED_CNTL);
172 return((uint16_t)PHM_GET_FIELD(speedCntl,
173 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
174 }
175
176 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
177 {
178 uint32_t link_width;
179
180 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
181 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
182 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
183
184 PP_ASSERT_WITH_CODE((7 >= link_width),
185 "Invalid PCIe lane width!", return 0);
186
187 return decode_pcie_lane_width(link_width);
188 }
189
190 void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
191 {
192 struct phm_ppt_v1_information *table_info =
193 (struct phm_ppt_v1_information *)hwmgr->pptable;
194 struct phm_clock_voltage_dependency_table *table =
195 table_info->vddc_dep_on_dal_pwrl;
196 struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
197 enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
198 uint32_t req_vddc = 0, req_volt, i;
199
200 if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
201 dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
202 return;
203
204 for (i = 0; i < table->count; i++) {
205 if (dal_power_level == table->entries[i].clk) {
206 req_vddc = table->entries[i].v;
207 break;
208 }
209 }
210
211 vddc_table = table_info->vdd_dep_on_sclk;
212 for (i = 0; i < vddc_table->count; i++) {
213 if (req_vddc <= vddc_table->entries[i].vddc) {
214 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
215 << VDDC_SHIFT;
216 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
217 PPSMC_MSG_VddC_Request, req_volt);
218 return;
219 }
220 }
221 printk(KERN_ERR "DAL requested level can not"
222 " found a available voltage in VDDC DPM Table \n");
223 }
224
225 /**
226 * Enable voltage control
227 *
228 * @param pHwMgr the address of the powerplay hardware manager.
229 * @return always PP_Result_OK
230 */
231 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
232 {
233 PP_ASSERT_WITH_CODE(
234 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
235 "Failed to enable voltage DPM during DPM Start Function!",
236 return 1;
237 );
238
239 return 0;
240 }
241
242 /**
243 * Checks if we want to support voltage control
244 *
245 * @param hwmgr the address of the powerplay hardware manager.
246 */
247 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
248 {
249 const struct polaris10_hwmgr *data =
250 (const struct polaris10_hwmgr *)(hwmgr->backend);
251
252 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
253 }
254
255 /**
256 * Enable voltage control
257 *
258 * @param hwmgr the address of the powerplay hardware manager.
259 * @return always 0
260 */
261 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
262 {
263 /* enable voltage control */
264 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
265 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
266
267 return 0;
268 }
269
270 /**
271 * Create Voltage Tables.
272 *
273 * @param hwmgr the address of the powerplay hardware manager.
274 * @return always 0
275 */
276 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
277 {
278 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
279 struct phm_ppt_v1_information *table_info =
280 (struct phm_ppt_v1_information *)hwmgr->pptable;
281 int result;
282
283 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
284 result = atomctrl_get_voltage_table_v3(hwmgr,
285 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
286 &(data->mvdd_voltage_table));
287 PP_ASSERT_WITH_CODE((0 == result),
288 "Failed to retrieve MVDD table.",
289 return result);
290 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
291 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
292 table_info->vdd_dep_on_mclk);
293 PP_ASSERT_WITH_CODE((0 == result),
294 "Failed to retrieve SVI2 MVDD table from dependancy table.",
295 return result;);
296 }
297
298 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
299 result = atomctrl_get_voltage_table_v3(hwmgr,
300 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
301 &(data->vddci_voltage_table));
302 PP_ASSERT_WITH_CODE((0 == result),
303 "Failed to retrieve VDDCI table.",
304 return result);
305 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
306 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
307 table_info->vdd_dep_on_mclk);
308 PP_ASSERT_WITH_CODE((0 == result),
309 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
310 return result);
311 }
312
313 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
314 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
315 table_info->vddc_lookup_table);
316 PP_ASSERT_WITH_CODE((0 == result),
317 "Failed to retrieve SVI2 VDDC table from lookup table.",
318 return result);
319 }
320
321 PP_ASSERT_WITH_CODE(
322 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
323 "Too many voltage values for VDDC. Trimming to fit state table.",
324 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
325 &(data->vddc_voltage_table)));
326
327 PP_ASSERT_WITH_CODE(
328 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
329 "Too many voltage values for VDDCI. Trimming to fit state table.",
330 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
331 &(data->vddci_voltage_table)));
332
333 PP_ASSERT_WITH_CODE(
334 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
335 "Too many voltage values for MVDD. Trimming to fit state table.",
336 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
337 &(data->mvdd_voltage_table)));
338
339 return 0;
340 }
341
342 /**
343 * Programs static screed detection parameters
344 *
345 * @param hwmgr the address of the powerplay hardware manager.
346 * @return always 0
347 */
348 static int polaris10_program_static_screen_threshold_parameters(
349 struct pp_hwmgr *hwmgr)
350 {
351 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
352
353 /* Set static screen threshold unit */
354 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
355 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
356 data->static_screen_threshold_unit);
357 /* Set static screen threshold */
358 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
359 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
360 data->static_screen_threshold);
361
362 return 0;
363 }
364
365 /**
366 * Setup display gap for glitch free memory clock switching.
367 *
368 * @param hwmgr the address of the powerplay hardware manager.
369 * @return always 0
370 */
371 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
372 {
373 uint32_t display_gap =
374 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_DISPLAY_GAP_CNTL);
376
377 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
378 DISP_GAP, DISPLAY_GAP_IGNORE);
379
380 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
381 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
382
383 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
384 ixCG_DISPLAY_GAP_CNTL, display_gap);
385
386 return 0;
387 }
388
389 /**
390 * Programs activity state transition voting clients
391 *
392 * @param hwmgr the address of the powerplay hardware manager.
393 * @return always 0
394 */
395 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
396 {
397 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
398
399 /* Clear reset for voting clients before enabling DPM */
400 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
401 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
402 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
403 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
404
405 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
406 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
407 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
408 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
409 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
410 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
411 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
412 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
413 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
414 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
415 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
416 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
417 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
418 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
419 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
420 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
421
422 return 0;
423 }
424
425 /**
426 * Get the location of various tables inside the FW image.
427 *
428 * @param hwmgr the address of the powerplay hardware manager.
429 * @return always 0
430 */
431 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
432 {
433 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
434 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
435 uint32_t tmp;
436 int result;
437 bool error = false;
438
439 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
440 SMU7_FIRMWARE_HEADER_LOCATION +
441 offsetof(SMU74_Firmware_Header, DpmTable),
442 &tmp, data->sram_end);
443
444 if (0 == result)
445 data->dpm_table_start = tmp;
446
447 error |= (0 != result);
448
449 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
450 SMU7_FIRMWARE_HEADER_LOCATION +
451 offsetof(SMU74_Firmware_Header, SoftRegisters),
452 &tmp, data->sram_end);
453
454 if (!result) {
455 data->soft_regs_start = tmp;
456 smu_data->soft_regs_start = tmp;
457 }
458
459 error |= (0 != result);
460
461 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
462 SMU7_FIRMWARE_HEADER_LOCATION +
463 offsetof(SMU74_Firmware_Header, mcRegisterTable),
464 &tmp, data->sram_end);
465
466 if (!result)
467 data->mc_reg_table_start = tmp;
468
469 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
470 SMU7_FIRMWARE_HEADER_LOCATION +
471 offsetof(SMU74_Firmware_Header, FanTable),
472 &tmp, data->sram_end);
473
474 if (!result)
475 data->fan_table_start = tmp;
476
477 error |= (0 != result);
478
479 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
480 SMU7_FIRMWARE_HEADER_LOCATION +
481 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
482 &tmp, data->sram_end);
483
484 if (!result)
485 data->arb_table_start = tmp;
486
487 error |= (0 != result);
488
489 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
490 SMU7_FIRMWARE_HEADER_LOCATION +
491 offsetof(SMU74_Firmware_Header, Version),
492 &tmp, data->sram_end);
493
494 if (!result)
495 hwmgr->microcode_version_info.SMC = tmp;
496
497 error |= (0 != result);
498
499 return error ? -1 : 0;
500 }
501
502 /* Copy one arb setting to another and then switch the active set.
503 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
504 */
505 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
506 uint32_t arb_src, uint32_t arb_dest)
507 {
508 uint32_t mc_arb_dram_timing;
509 uint32_t mc_arb_dram_timing2;
510 uint32_t burst_time;
511 uint32_t mc_cg_config;
512
513 switch (arb_src) {
514 case MC_CG_ARB_FREQ_F0:
515 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
516 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
517 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
518 break;
519 case MC_CG_ARB_FREQ_F1:
520 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
521 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
522 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 switch (arb_dest) {
529 case MC_CG_ARB_FREQ_F0:
530 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
531 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
532 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
533 break;
534 case MC_CG_ARB_FREQ_F1:
535 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
536 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
537 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
544 mc_cg_config |= 0x0000000F;
545 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
546 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
547
548 return 0;
549 }
550
551 /**
552 * Initial switch from ARB F0->F1
553 *
554 * @param hwmgr the address of the powerplay hardware manager.
555 * @return always 0
556 * This function is to be called from the SetPowerState table.
557 */
558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
559 {
560 return polaris10_copy_and_switch_arb_sets(hwmgr,
561 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
562 }
563
564 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
565 {
566 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
567 struct phm_ppt_v1_information *table_info =
568 (struct phm_ppt_v1_information *)(hwmgr->pptable);
569 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
570 uint32_t i, max_entry;
571
572 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
573 data->use_pcie_power_saving_levels), "No pcie performance levels!",
574 return -EINVAL);
575
576 if (data->use_pcie_performance_levels &&
577 !data->use_pcie_power_saving_levels) {
578 data->pcie_gen_power_saving = data->pcie_gen_performance;
579 data->pcie_lane_power_saving = data->pcie_lane_performance;
580 } else if (!data->use_pcie_performance_levels &&
581 data->use_pcie_power_saving_levels) {
582 data->pcie_gen_performance = data->pcie_gen_power_saving;
583 data->pcie_lane_performance = data->pcie_lane_power_saving;
584 }
585
586 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
587 SMU74_MAX_LEVELS_LINK,
588 MAX_REGULAR_DPM_NUMBER);
589
590 if (pcie_table != NULL) {
591 /* max_entry is used to make sure we reserve one PCIE level
592 * for boot level (fix for A+A PSPP issue).
593 * If PCIE table from PPTable have ULV entry + 8 entries,
594 * then ignore the last entry.*/
595 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
596 SMU74_MAX_LEVELS_LINK : pcie_table->count;
597 for (i = 1; i < max_entry; i++) {
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
599 get_pcie_gen_support(data->pcie_gen_cap,
600 pcie_table->entries[i].gen_speed),
601 get_pcie_lane_support(data->pcie_lane_cap,
602 pcie_table->entries[i].lane_width));
603 }
604 data->dpm_table.pcie_speed_table.count = max_entry - 1;
605
606 /* Setup BIF_SCLK levels */
607 for (i = 0; i < max_entry; i++)
608 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
609 } else {
610 /* Hardcode Pcie Table */
611 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
612 get_pcie_gen_support(data->pcie_gen_cap,
613 PP_Min_PCIEGen),
614 get_pcie_lane_support(data->pcie_lane_cap,
615 PP_Max_PCIELane));
616 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
617 get_pcie_gen_support(data->pcie_gen_cap,
618 PP_Min_PCIEGen),
619 get_pcie_lane_support(data->pcie_lane_cap,
620 PP_Max_PCIELane));
621 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
622 get_pcie_gen_support(data->pcie_gen_cap,
623 PP_Max_PCIEGen),
624 get_pcie_lane_support(data->pcie_lane_cap,
625 PP_Max_PCIELane));
626 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
627 get_pcie_gen_support(data->pcie_gen_cap,
628 PP_Max_PCIEGen),
629 get_pcie_lane_support(data->pcie_lane_cap,
630 PP_Max_PCIELane));
631 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
632 get_pcie_gen_support(data->pcie_gen_cap,
633 PP_Max_PCIEGen),
634 get_pcie_lane_support(data->pcie_lane_cap,
635 PP_Max_PCIELane));
636 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
637 get_pcie_gen_support(data->pcie_gen_cap,
638 PP_Max_PCIEGen),
639 get_pcie_lane_support(data->pcie_lane_cap,
640 PP_Max_PCIELane));
641
642 data->dpm_table.pcie_speed_table.count = 6;
643 }
644 /* Populate last level for boot PCIE level, but do not increment count. */
645 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
646 data->dpm_table.pcie_speed_table.count,
647 get_pcie_gen_support(data->pcie_gen_cap,
648 PP_Min_PCIEGen),
649 get_pcie_lane_support(data->pcie_lane_cap,
650 PP_Max_PCIELane));
651
652 return 0;
653 }
654
655 /*
656 * This function is to initalize all DPM state tables
657 * for SMU7 based on the dependency table.
658 * Dynamic state patching function will then trim these
659 * state tables to the allowed range based
660 * on the power policy or external client requests,
661 * such as UVD request, etc.
662 */
663 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
664 {
665 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
666 struct phm_ppt_v1_information *table_info =
667 (struct phm_ppt_v1_information *)(hwmgr->pptable);
668 uint32_t i;
669
670 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
671 table_info->vdd_dep_on_sclk;
672 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
673 table_info->vdd_dep_on_mclk;
674
675 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
676 "SCLK dependency table is missing. This table is mandatory",
677 return -EINVAL);
678 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
679 "SCLK dependency table has to have is missing."
680 "This table is mandatory",
681 return -EINVAL);
682
683 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
684 "MCLK dependency table is missing. This table is mandatory",
685 return -EINVAL);
686 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
687 "MCLK dependency table has to have is missing."
688 "This table is mandatory",
689 return -EINVAL);
690
691 /* clear the state table to reset everything to default */
692 phm_reset_single_dpm_table(
693 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
694 phm_reset_single_dpm_table(
695 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
696
697
698 /* Initialize Sclk DPM table based on allow Sclk values */
699 data->dpm_table.sclk_table.count = 0;
700 for (i = 0; i < dep_sclk_table->count; i++) {
701 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
702 dep_sclk_table->entries[i].clk) {
703
704 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
705 dep_sclk_table->entries[i].clk;
706
707 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
708 (i == 0) ? true : false;
709 data->dpm_table.sclk_table.count++;
710 }
711 }
712
713 /* Initialize Mclk DPM table based on allow Mclk values */
714 data->dpm_table.mclk_table.count = 0;
715 for (i = 0; i < dep_mclk_table->count; i++) {
716 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
717 [data->dpm_table.mclk_table.count - 1].value !=
718 dep_mclk_table->entries[i].clk) {
719 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
720 dep_mclk_table->entries[i].clk;
721 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
722 (i == 0) ? true : false;
723 data->dpm_table.mclk_table.count++;
724 }
725 }
726
727 /* setup PCIE gen speed levels */
728 polaris10_setup_default_pcie_table(hwmgr);
729
730 /* save a copy of the default DPM table */
731 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
732 sizeof(struct polaris10_dpm_table));
733
734 return 0;
735 }
736
737 uint8_t convert_to_vid(uint16_t vddc)
738 {
739 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
740 }
741
742 /**
743 * Mvdd table preparation for SMC.
744 *
745 * @param *hwmgr The address of the hardware manager.
746 * @param *table The SMC DPM table structure to be populated.
747 * @return 0
748 */
749 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
750 SMU74_Discrete_DpmTable *table)
751 {
752 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
753 uint32_t count, level;
754
755 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
756 count = data->mvdd_voltage_table.count;
757 if (count > SMU_MAX_SMIO_LEVELS)
758 count = SMU_MAX_SMIO_LEVELS;
759 for (level = 0; level < count; level++) {
760 table->SmioTable2.Pattern[level].Voltage =
761 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
762 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
763 table->SmioTable2.Pattern[level].Smio =
764 (uint8_t) level;
765 table->Smio[level] |=
766 data->mvdd_voltage_table.entries[level].smio_low;
767 }
768 table->SmioMask2 = data->vddci_voltage_table.mask_low;
769
770 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
771 }
772
773 return 0;
774 }
775
776 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
777 struct SMU74_Discrete_DpmTable *table)
778 {
779 uint32_t count, level;
780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
781
782 count = data->vddci_voltage_table.count;
783
784 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
785 if (count > SMU_MAX_SMIO_LEVELS)
786 count = SMU_MAX_SMIO_LEVELS;
787 for (level = 0; level < count; ++level) {
788 table->SmioTable1.Pattern[level].Voltage =
789 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
790 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
791
792 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
793 }
794 }
795
796 table->SmioMask1 = data->vddci_voltage_table.mask_low;
797
798 return 0;
799 }
800
801 /**
802 * Preparation of vddc and vddgfx CAC tables for SMC.
803 *
804 * @param hwmgr the address of the hardware manager
805 * @param table the SMC DPM table structure to be populated
806 * @return always 0
807 */
808 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
809 struct SMU74_Discrete_DpmTable *table)
810 {
811 uint32_t count;
812 uint8_t index;
813 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
814 struct phm_ppt_v1_information *table_info =
815 (struct phm_ppt_v1_information *)(hwmgr->pptable);
816 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
817 table_info->vddc_lookup_table;
818 /* tables is already swapped, so in order to use the value from it,
819 * we need to swap it back.
820 * We are populating vddc CAC data to BapmVddc table
821 * in split and merged mode
822 */
823 for (count = 0; count < lookup_table->count; count++) {
824 index = phm_get_voltage_index(lookup_table,
825 data->vddc_voltage_table.entries[count].value);
826 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
827 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
828 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
829 }
830
831 return 0;
832 }
833
834 /**
835 * Preparation of voltage tables for SMC.
836 *
837 * @param hwmgr the address of the hardware manager
838 * @param table the SMC DPM table structure to be populated
839 * @return always 0
840 */
841
842 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
843 struct SMU74_Discrete_DpmTable *table)
844 {
845 polaris10_populate_smc_vddci_table(hwmgr, table);
846 polaris10_populate_smc_mvdd_table(hwmgr, table);
847 polaris10_populate_cac_table(hwmgr, table);
848
849 return 0;
850 }
851
852 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
853 struct SMU74_Discrete_Ulv *state)
854 {
855 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
856 struct phm_ppt_v1_information *table_info =
857 (struct phm_ppt_v1_information *)(hwmgr->pptable);
858
859 state->CcPwrDynRm = 0;
860 state->CcPwrDynRm1 = 0;
861
862 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
863 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
864 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
865
866 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
867
868 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
869 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
870 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
871
872 return 0;
873 }
874
875 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
876 struct SMU74_Discrete_DpmTable *table)
877 {
878 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
879 }
880
881 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
882 struct SMU74_Discrete_DpmTable *table)
883 {
884 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
885 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
886 int i;
887
888 /* Index (dpm_table->pcie_speed_table.count)
889 * is reserved for PCIE boot level. */
890 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
891 table->LinkLevel[i].PcieGenSpeed =
892 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
893 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
894 dpm_table->pcie_speed_table.dpm_levels[i].param1);
895 table->LinkLevel[i].EnabledForActivity = 1;
896 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
897 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
898 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
899 }
900
901 data->smc_state_table.LinkLevelCount =
902 (uint8_t)dpm_table->pcie_speed_table.count;
903 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
904 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
905
906 return 0;
907 }
908
909 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
910 {
911 uint32_t reference_clock, tmp;
912 struct cgs_display_info info = {0};
913 struct cgs_mode_info mode_info;
914
915 info.mode_info = &mode_info;
916
917 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
918
919 if (tmp)
920 return TCLK;
921
922 cgs_get_active_displays_info(hwmgr->device, &info);
923 reference_clock = mode_info.ref_clock;
924
925 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
926
927 if (0 != tmp)
928 return reference_clock / 4;
929
930 return reference_clock;
931 }
932
933 /**
934 * Calculates the SCLK dividers using the provided engine clock
935 *
936 * @param hwmgr the address of the hardware manager
937 * @param clock the engine clock to use to populate the structure
938 * @param sclk the SMC SCLK structure to be populated
939 */
940 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
941 uint32_t clock, SMU_SclkSetting *sclk_setting)
942 {
943 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
944 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
945 struct pp_atomctrl_clock_dividers_ai dividers;
946
947 uint32_t ref_clock;
948 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
949 uint8_t i;
950 int result;
951 uint64_t temp;
952
953 sclk_setting->SclkFrequency = clock;
954 /* get the engine clock dividers for this clock value */
955 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
956 if (result == 0) {
957 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
958 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
959 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
960 sclk_setting->PllRange = dividers.ucSclkPllRange;
961 sclk_setting->Sclk_slew_rate = 0x400;
962 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
963 sclk_setting->Pcc_down_slew_rate = 0xffff;
964 sclk_setting->SSc_En = dividers.ucSscEnable;
965 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
966 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
967 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
968 return result;
969 }
970
971 ref_clock = polaris10_get_xclk(hwmgr);
972
973 for (i = 0; i < NUM_SCLK_RANGE; i++) {
974 if (clock > data->range_table[i].trans_lower_frequency
975 && clock <= data->range_table[i].trans_upper_frequency) {
976 sclk_setting->PllRange = i;
977 break;
978 }
979 }
980
981 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
982 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
983 temp <<= 0x10;
984 sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
985
986 pcc_target_percent = 10; /* Hardcode 10% for now. */
987 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
988 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
989
990 ss_target_percent = 2; /* Hardcode 2% for now. */
991 sclk_setting->SSc_En = 0;
992 if (ss_target_percent) {
993 sclk_setting->SSc_En = 1;
994 ss_target_freq = clock - (clock * ss_target_percent / 100);
995 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
996 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
997 temp <<= 0x10;
998 sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
999 }
1000
1001 return 0;
1002 }
1003
1004 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1005 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1006 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1007 {
1008 uint32_t i;
1009 uint16_t vddci;
1010 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1011
1012 *voltage = *mvdd = 0;
1013
1014 /* clock - voltage dependency table is empty table */
1015 if (dep_table->count == 0)
1016 return -EINVAL;
1017
1018 for (i = 0; i < dep_table->count; i++) {
1019 /* find first sclk bigger than request */
1020 if (dep_table->entries[i].clk >= clock) {
1021 *voltage |= (dep_table->entries[i].vddc *
1022 VOLTAGE_SCALE) << VDDC_SHIFT;
1023 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1024 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1025 VOLTAGE_SCALE) << VDDCI_SHIFT;
1026 else if (dep_table->entries[i].vddci)
1027 *voltage |= (dep_table->entries[i].vddci *
1028 VOLTAGE_SCALE) << VDDCI_SHIFT;
1029 else {
1030 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1031 (dep_table->entries[i].vddc -
1032 (uint16_t)data->vddc_vddci_delta));
1033 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1034 }
1035
1036 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1037 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1038 VOLTAGE_SCALE;
1039 else if (dep_table->entries[i].mvdd)
1040 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1041 VOLTAGE_SCALE;
1042
1043 *voltage |= 1 << PHASES_SHIFT;
1044 return 0;
1045 }
1046 }
1047
1048 /* sclk is bigger than max sclk in the dependence table */
1049 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1050
1051 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1052 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1053 VOLTAGE_SCALE) << VDDCI_SHIFT;
1054 else if (dep_table->entries[i-1].vddci) {
1055 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1056 (dep_table->entries[i].vddc -
1057 (uint16_t)data->vddc_vddci_delta));
1058 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1059 }
1060
1061 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1062 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1063 else if (dep_table->entries[i].mvdd)
1064 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1065
1066 return 0;
1067 }
1068
1069 sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1070 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1071 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1072 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1073 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1074 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1075 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1076 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1077
1078 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1079 {
1080 uint32_t i, ref_clk;
1081 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1082 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1083 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1084
1085 ref_clk = polaris10_get_xclk(hwmgr);
1086
1087 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1088 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1089 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1090 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1091 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1092
1093 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1094 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1095
1096 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1097 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1098 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1099 }
1100 return;
1101 }
1102
1103 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1104
1105 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1106 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1107
1108 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1109 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1110 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1111
1112 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1113 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1114
1115 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1116 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1117 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1118 }
1119 }
1120
1121 /**
1122 * Populates single SMC SCLK structure using the provided engine clock
1123 *
1124 * @param hwmgr the address of the hardware manager
1125 * @param clock the engine clock to use to populate the structure
1126 * @param sclk the SMC SCLK structure to be populated
1127 */
1128
1129 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1130 uint32_t clock, uint16_t sclk_al_threshold,
1131 struct SMU74_Discrete_GraphicsLevel *level)
1132 {
1133 int result, i, temp;
1134 /* PP_Clocks minClocks; */
1135 uint32_t mvdd;
1136 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1137 struct phm_ppt_v1_information *table_info =
1138 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1139 SMU_SclkSetting curr_sclk_setting = { 0 };
1140
1141 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1142
1143 /* populate graphics levels */
1144 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1145 table_info->vdd_dep_on_sclk, clock,
1146 &level->MinVoltage, &mvdd);
1147
1148 PP_ASSERT_WITH_CODE((0 == result),
1149 "can not find VDDC voltage value for "
1150 "VDDC engine clock dependency table",
1151 return result);
1152 level->ActivityLevel = sclk_al_threshold;
1153
1154 level->CcPwrDynRm = 0;
1155 level->CcPwrDynRm1 = 0;
1156 level->EnabledForActivity = 0;
1157 level->EnabledForThrottle = 1;
1158 level->UpHyst = 10;
1159 level->DownHyst = 0;
1160 level->VoltageDownHyst = 0;
1161 level->PowerThrottle = 0;
1162
1163 /*
1164 * TODO: get minimum clocks from dal configaration
1165 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1166 */
1167 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1168
1169 /* get level->DeepSleepDivId
1170 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1171 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1172 */
1173 PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
1174 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1175 temp = clock / (1UL << i);
1176
1177 if (temp >= 2500 || i == 0)
1178 break;
1179 }
1180
1181 level->DeepSleepDivId = i;
1182
1183 /* Default to slow, highest DPM level will be
1184 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1185 */
1186 if (data->update_up_hyst)
1187 level->UpHyst = (uint8_t)data->up_hyst;
1188 if (data->update_down_hyst)
1189 level->DownHyst = (uint8_t)data->down_hyst;
1190
1191 level->SclkSetting = curr_sclk_setting;
1192
1193 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1194 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1195 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1196 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1197 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1198 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1199 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1200 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1201 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1202 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1203 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1204 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1205 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1206 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1207 return 0;
1208 }
1209
1210 /**
1211 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1212 *
1213 * @param hwmgr the address of the hardware manager
1214 */
1215 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1216 {
1217 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1218 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1219 struct phm_ppt_v1_information *table_info =
1220 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1221 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1222 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1223 int result = 0;
1224 uint32_t array = data->dpm_table_start +
1225 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1226 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1227 SMU74_MAX_LEVELS_GRAPHICS;
1228 struct SMU74_Discrete_GraphicsLevel *levels =
1229 data->smc_state_table.GraphicsLevel;
1230 uint32_t i, max_entry;
1231 uint8_t hightest_pcie_level_enabled = 0,
1232 lowest_pcie_level_enabled = 0,
1233 mid_pcie_level_enabled = 0,
1234 count = 0;
1235
1236 polaris10_get_sclk_range_table(hwmgr);
1237
1238 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1239
1240 result = polaris10_populate_single_graphic_level(hwmgr,
1241 dpm_table->sclk_table.dpm_levels[i].value,
1242 (uint16_t)data->activity_target[i],
1243 &(data->smc_state_table.GraphicsLevel[i]));
1244 if (result)
1245 return result;
1246
1247 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1248 if (i > 1)
1249 levels[i].DeepSleepDivId = 0;
1250 }
1251
1252 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1253 data->smc_state_table.GraphicsDpmLevelCount =
1254 (uint8_t)dpm_table->sclk_table.count;
1255 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1256 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1257
1258
1259 if (pcie_table != NULL) {
1260 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1261 "There must be 1 or more PCIE levels defined in PPTable.",
1262 return -EINVAL);
1263 max_entry = pcie_entry_cnt - 1;
1264 for (i = 0; i < dpm_table->sclk_table.count; i++)
1265 levels[i].pcieDpmLevel =
1266 (uint8_t) ((i < max_entry) ? i : max_entry);
1267 } else {
1268 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1269 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1270 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1271 hightest_pcie_level_enabled++;
1272
1273 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1274 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1275 (1 << lowest_pcie_level_enabled)) == 0))
1276 lowest_pcie_level_enabled++;
1277
1278 while ((count < hightest_pcie_level_enabled) &&
1279 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1280 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1281 count++;
1282
1283 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1284 hightest_pcie_level_enabled ?
1285 (lowest_pcie_level_enabled + 1 + count) :
1286 hightest_pcie_level_enabled;
1287
1288 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1289 for (i = 2; i < dpm_table->sclk_table.count; i++)
1290 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1291
1292 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1293 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1294
1295 /* set pcieDpmLevel to mid_pcie_level_enabled */
1296 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1297 }
1298 /* level count will send to smc once at init smc table and never change */
1299 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1300 (uint32_t)array_size, data->sram_end);
1301
1302 return result;
1303 }
1304
1305 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1306 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1307 {
1308 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1309 struct phm_ppt_v1_information *table_info =
1310 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1311 int result = 0;
1312 struct cgs_display_info info = {0, 0, NULL};
1313
1314 cgs_get_active_displays_info(hwmgr->device, &info);
1315
1316 if (table_info->vdd_dep_on_mclk) {
1317 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1318 table_info->vdd_dep_on_mclk, clock,
1319 &mem_level->MinVoltage, &mem_level->MinMvdd);
1320 PP_ASSERT_WITH_CODE((0 == result),
1321 "can not find MinVddc voltage value from memory "
1322 "VDDC voltage dependency table", return result);
1323 }
1324
1325 mem_level->MclkFrequency = clock;
1326 mem_level->StutterEnable = 0;
1327 mem_level->EnabledForThrottle = 1;
1328 mem_level->EnabledForActivity = 0;
1329 mem_level->UpHyst = 0;
1330 mem_level->DownHyst = 100;
1331 mem_level->VoltageDownHyst = 0;
1332 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1333 mem_level->StutterEnable = false;
1334
1335 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1336
1337 data->display_timing.num_existing_displays = info.display_count;
1338
1339 if ((data->mclk_stutter_mode_threshold) &&
1340 (clock <= data->mclk_stutter_mode_threshold) &&
1341 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1342 STUTTER_ENABLE) & 0x1))
1343 mem_level->StutterEnable = true;
1344
1345 if (!result) {
1346 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1347 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1348 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1349 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1350 }
1351 return result;
1352 }
1353
1354 /**
1355 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1356 *
1357 * @param hwmgr the address of the hardware manager
1358 */
1359 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1360 {
1361 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1362 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1363 int result;
1364 /* populate MCLK dpm table to SMU7 */
1365 uint32_t array = data->dpm_table_start +
1366 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1367 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1368 SMU74_MAX_LEVELS_MEMORY;
1369 struct SMU74_Discrete_MemoryLevel *levels =
1370 data->smc_state_table.MemoryLevel;
1371 uint32_t i;
1372
1373 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1374 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1375 "can not populate memory level as memory clock is zero",
1376 return -EINVAL);
1377 result = polaris10_populate_single_memory_level(hwmgr,
1378 dpm_table->mclk_table.dpm_levels[i].value,
1379 &levels[i]);
1380 if (i == dpm_table->mclk_table.count - 1) {
1381 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1382 levels[i].EnabledForActivity = 1;
1383 }
1384 if (result)
1385 return result;
1386 }
1387
1388 /* in order to prevent MC activity from stutter mode to push DPM up.
1389 * the UVD change complements this by putting the MCLK in
1390 * a higher state by default such that we are not effected by
1391 * up threshold or and MCLK DPM latency.
1392 */
1393 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1394 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1395
1396 data->smc_state_table.MemoryDpmLevelCount =
1397 (uint8_t)dpm_table->mclk_table.count;
1398 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1399 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1400
1401 /* level count will send to smc once at init smc table and never change */
1402 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1403 (uint32_t)array_size, data->sram_end);
1404
1405 return result;
1406 }
1407
1408 /**
1409 * Populates the SMC MVDD structure using the provided memory clock.
1410 *
1411 * @param hwmgr the address of the hardware manager
1412 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1413 * @param voltage the SMC VOLTAGE structure to be populated
1414 */
1415 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1416 uint32_t mclk, SMIO_Pattern *smio_pat)
1417 {
1418 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1419 struct phm_ppt_v1_information *table_info =
1420 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1421 uint32_t i = 0;
1422
1423 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1424 /* find mvdd value which clock is more than request */
1425 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1426 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1427 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1428 break;
1429 }
1430 }
1431 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1432 "MVDD Voltage is outside the supported range.",
1433 return -EINVAL);
1434 } else
1435 return -EINVAL;
1436
1437 return 0;
1438 }
1439
1440 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1441 SMU74_Discrete_DpmTable *table)
1442 {
1443 int result = 0;
1444 uint32_t sclk_frequency;
1445 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1446 struct phm_ppt_v1_information *table_info =
1447 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1448 SMIO_Pattern vol_level;
1449 uint32_t mvdd;
1450 uint16_t us_mvdd;
1451
1452 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1453
1454 if (!data->sclk_dpm_key_disabled) {
1455 /* Get MinVoltage and Frequency from DPM0,
1456 * already converted to SMC_UL */
1457 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1458 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1459 table_info->vdd_dep_on_sclk,
1460 table->ACPILevel.SclkFrequency,
1461 &table->ACPILevel.MinVoltage, &mvdd);
1462 PP_ASSERT_WITH_CODE((0 == result),
1463 "Cannot find ACPI VDDC voltage value "
1464 "in Clock Dependency Table", );
1465 } else {
1466 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1467 table->ACPILevel.MinVoltage =
1468 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1469 }
1470
1471 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1472 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1473
1474 table->ACPILevel.DeepSleepDivId = 0;
1475 table->ACPILevel.CcPwrDynRm = 0;
1476 table->ACPILevel.CcPwrDynRm1 = 0;
1477
1478 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1479 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1480 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1481 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1482
1483 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1484 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1485 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1486 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1487 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1488 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1489 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1490 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1491 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1492 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1493
1494 if (!data->mclk_dpm_key_disabled) {
1495 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1496 table->MemoryACPILevel.MclkFrequency =
1497 data->dpm_table.mclk_table.dpm_levels[0].value;
1498 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1499 table_info->vdd_dep_on_mclk,
1500 table->MemoryACPILevel.MclkFrequency,
1501 &table->MemoryACPILevel.MinVoltage, &mvdd);
1502 PP_ASSERT_WITH_CODE((0 == result),
1503 "Cannot find ACPI VDDCI voltage value "
1504 "in Clock Dependency Table",
1505 );
1506 } else {
1507 table->MemoryACPILevel.MclkFrequency =
1508 data->vbios_boot_state.mclk_bootup_value;
1509 table->MemoryACPILevel.MinVoltage =
1510 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1511 }
1512
1513 us_mvdd = 0;
1514 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1515 (data->mclk_dpm_key_disabled))
1516 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1517 else {
1518 if (!polaris10_populate_mvdd_value(hwmgr,
1519 data->dpm_table.mclk_table.dpm_levels[0].value,
1520 &vol_level))
1521 us_mvdd = vol_level.Voltage;
1522 }
1523
1524 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1525 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1526 else
1527 table->MemoryACPILevel.MinMvdd = 0;
1528
1529 table->MemoryACPILevel.StutterEnable = false;
1530
1531 table->MemoryACPILevel.EnabledForThrottle = 0;
1532 table->MemoryACPILevel.EnabledForActivity = 0;
1533 table->MemoryACPILevel.UpHyst = 0;
1534 table->MemoryACPILevel.DownHyst = 100;
1535 table->MemoryACPILevel.VoltageDownHyst = 0;
1536 table->MemoryACPILevel.ActivityLevel =
1537 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1538
1539 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1540 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1541
1542 return result;
1543 }
1544
1545 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1546 SMU74_Discrete_DpmTable *table)
1547 {
1548 int result = -EINVAL;
1549 uint8_t count;
1550 struct pp_atomctrl_clock_dividers_vi dividers;
1551 struct phm_ppt_v1_information *table_info =
1552 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1553 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1554 table_info->mm_dep_table;
1555 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1556
1557 table->VceLevelCount = (uint8_t)(mm_table->count);
1558 table->VceBootLevel = 0;
1559
1560 for (count = 0; count < table->VceLevelCount; count++) {
1561 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1562 table->VceLevel[count].MinVoltage |=
1563 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1564 table->VceLevel[count].MinVoltage |=
1565 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1566 VOLTAGE_SCALE) << VDDCI_SHIFT;
1567 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1568
1569 /*retrieve divider value for VBIOS */
1570 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1571 table->VceLevel[count].Frequency, &dividers);
1572 PP_ASSERT_WITH_CODE((0 == result),
1573 "can not find divide id for VCE engine clock",
1574 return result);
1575
1576 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1577
1578 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1579 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1580 }
1581 return result;
1582 }
1583
1584 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1585 SMU74_Discrete_DpmTable *table)
1586 {
1587 int result = -EINVAL;
1588 uint8_t count;
1589 struct pp_atomctrl_clock_dividers_vi dividers;
1590 struct phm_ppt_v1_information *table_info =
1591 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1592 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1593 table_info->mm_dep_table;
1594 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1595
1596 table->SamuBootLevel = 0;
1597 table->SamuLevelCount = (uint8_t)(mm_table->count);
1598
1599 for (count = 0; count < table->SamuLevelCount; count++) {
1600 /* not sure whether we need evclk or not */
1601 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1602 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1603 VOLTAGE_SCALE) << VDDC_SHIFT;
1604 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1605 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1606 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1607
1608 /* retrieve divider value for VBIOS */
1609 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1610 table->SamuLevel[count].Frequency, &dividers);
1611 PP_ASSERT_WITH_CODE((0 == result),
1612 "can not find divide id for samu clock", return result);
1613
1614 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1615
1616 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1617 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1618 }
1619 return result;
1620 }
1621
1622 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1623 int32_t eng_clock, int32_t mem_clock,
1624 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1625 {
1626 uint32_t dram_timing;
1627 uint32_t dram_timing2;
1628 uint32_t burst_time;
1629 int result;
1630
1631 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1632 eng_clock, mem_clock);
1633 PP_ASSERT_WITH_CODE(result == 0,
1634 "Error calling VBIOS to set DRAM_TIMING.", return result);
1635
1636 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1637 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1638 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1639
1640
1641 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1642 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1643 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1644
1645 return 0;
1646 }
1647
1648 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1649 {
1650 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1651 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1652 uint32_t i, j;
1653 int result = 0;
1654
1655 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1656 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1657 result = polaris10_populate_memory_timing_parameters(hwmgr,
1658 data->dpm_table.sclk_table.dpm_levels[i].value,
1659 data->dpm_table.mclk_table.dpm_levels[j].value,
1660 &arb_regs.entries[i][j]);
1661 if (result == 0)
1662 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1663 if (result != 0)
1664 return result;
1665 }
1666 }
1667
1668 result = polaris10_copy_bytes_to_smc(
1669 hwmgr->smumgr,
1670 data->arb_table_start,
1671 (uint8_t *)&arb_regs,
1672 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1673 data->sram_end);
1674 return result;
1675 }
1676
1677 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1678 struct SMU74_Discrete_DpmTable *table)
1679 {
1680 int result = -EINVAL;
1681 uint8_t count;
1682 struct pp_atomctrl_clock_dividers_vi dividers;
1683 struct phm_ppt_v1_information *table_info =
1684 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1685 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1686 table_info->mm_dep_table;
1687 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1688
1689 table->UvdLevelCount = (uint8_t)(mm_table->count);
1690 table->UvdBootLevel = 0;
1691
1692 for (count = 0; count < table->UvdLevelCount; count++) {
1693 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1694 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1695 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1696 VOLTAGE_SCALE) << VDDC_SHIFT;
1697 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1698 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1699 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1700
1701 /* retrieve divider value for VBIOS */
1702 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1703 table->UvdLevel[count].VclkFrequency, &dividers);
1704 PP_ASSERT_WITH_CODE((0 == result),
1705 "can not find divide id for Vclk clock", return result);
1706
1707 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1708
1709 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1710 table->UvdLevel[count].DclkFrequency, &dividers);
1711 PP_ASSERT_WITH_CODE((0 == result),
1712 "can not find divide id for Dclk clock", return result);
1713
1714 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1715
1716 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1717 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1718 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1719
1720 }
1721 return result;
1722 }
1723
1724 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1725 struct SMU74_Discrete_DpmTable *table)
1726 {
1727 int result = 0;
1728 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1729
1730 table->GraphicsBootLevel = 0;
1731 table->MemoryBootLevel = 0;
1732
1733 /* find boot level from dpm table */
1734 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1735 data->vbios_boot_state.sclk_bootup_value,
1736 (uint32_t *)&(table->GraphicsBootLevel));
1737
1738 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1739 data->vbios_boot_state.mclk_bootup_value,
1740 (uint32_t *)&(table->MemoryBootLevel));
1741
1742 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1743 VOLTAGE_SCALE;
1744 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1745 VOLTAGE_SCALE;
1746 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1747 VOLTAGE_SCALE;
1748
1749 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1750 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1751 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1752
1753 return 0;
1754 }
1755
1756
1757 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1758 {
1759 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1760 struct phm_ppt_v1_information *table_info =
1761 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1762 uint8_t count, level;
1763
1764 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1765
1766 for (level = 0; level < count; level++) {
1767 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1768 data->vbios_boot_state.sclk_bootup_value) {
1769 data->smc_state_table.GraphicsBootLevel = level;
1770 break;
1771 }
1772 }
1773
1774 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1775 for (level = 0; level < count; level++) {
1776 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1777 data->vbios_boot_state.mclk_bootup_value) {
1778 data->smc_state_table.MemoryBootLevel = level;
1779 break;
1780 }
1781 }
1782
1783 return 0;
1784 }
1785
1786 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1787 {
1788 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1789 volt_with_cks, value;
1790 uint16_t clock_freq_u16;
1791 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1792 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1793 volt_offset = 0;
1794 struct phm_ppt_v1_information *table_info =
1795 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1796 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1797 table_info->vdd_dep_on_sclk;
1798
1799 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1800
1801 /* Read SMU_Eefuse to read and calculate RO and determine
1802 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1803 */
1804 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1805 ixSMU_EFUSE_0 + (146 * 4));
1806 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1807 ixSMU_EFUSE_0 + (148 * 4));
1808 efuse &= 0xFF000000;
1809 efuse = efuse >> 24;
1810 efuse2 &= 0xF;
1811
1812 if (efuse2 == 1)
1813 ro = (2300 - 1350) * efuse / 255 + 1350;
1814 else
1815 ro = (2500 - 1000) * efuse / 255 + 1000;
1816
1817 if (ro >= 1660)
1818 type = 0;
1819 else
1820 type = 1;
1821
1822 /* Populate Stretch amount */
1823 data->smc_state_table.ClockStretcherAmount = stretch_amount;
1824
1825 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1826 for (i = 0; i < sclk_table->count; i++) {
1827 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1828 sclk_table->entries[i].cks_enable << i;
1829 volt_without_cks = (uint32_t)((14041 *
1830 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1831 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1832 volt_with_cks = (uint32_t)((13946 *
1833 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1834 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1835 if (volt_without_cks >= volt_with_cks)
1836 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1837 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1838 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1839 }
1840
1841 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1842 STRETCH_ENABLE, 0x0);
1843 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1844 masterReset, 0x1);
1845 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1846 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1847 masterReset, 0x0);
1848
1849 /* Populate CKS Lookup Table */
1850 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1851 stretch_amount2 = 0;
1852 else if (stretch_amount == 3 || stretch_amount == 4)
1853 stretch_amount2 = 1;
1854 else {
1855 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1856 PHM_PlatformCaps_ClockStretcher);
1857 PP_ASSERT_WITH_CODE(false,
1858 "Stretch Amount in PPTable not supported\n",
1859 return -EINVAL);
1860 }
1861
1862 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1863 ixPWR_CKS_CNTL);
1864 value &= 0xFFC2FF87;
1865 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1866 polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
1867 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1868 polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
1869 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1870 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
1871 if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1872 && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
1873 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1874 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1875 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1876 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1877 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1878 value |= (polaris10_clock_stretch_amount_conversion
1879 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
1880 [stretch_amount]) << 3;
1881 }
1882 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1883 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1884 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1885 polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1886 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1887 (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1888
1889 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1890 ixPWR_CKS_CNTL, value);
1891
1892 /* Populate DDT Lookup Table */
1893 for (i = 0; i < 4; i++) {
1894 /* Assign the minimum and maximum VID stored
1895 * in the last row of Clock Stretcher Voltage Table.
1896 */
1897 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
1898 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
1899 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
1900 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
1901 /* Loop through each SCLK and check the frequency
1902 * to see if it lies within the frequency for clock stretcher.
1903 */
1904 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1905 cks_setting = 0;
1906 clock_freq = PP_SMC_TO_HOST_UL(
1907 data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1908 /* Check the allowed frequency against the sclk level[j].
1909 * Sclk's endianness has already been converted,
1910 * and it's in 10Khz unit,
1911 * as opposed to Data table, which is in Mhz unit.
1912 */
1913 if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
1914 cks_setting |= 0x2;
1915 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
1916 cks_setting |= 0x1;
1917 }
1918 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1919 |= cks_setting << (j * 2);
1920 }
1921 CONVERT_FROM_HOST_TO_SMC_US(
1922 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1923 }
1924
1925 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1926 value &= 0xFFFFFFFE;
1927 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1928
1929 return 0;
1930 }
1931
1932 /**
1933 * Populates the SMC VRConfig field in DPM table.
1934 *
1935 * @param hwmgr the address of the hardware manager
1936 * @param table the SMC DPM table structure to be populated
1937 * @return always 0
1938 */
1939 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1940 struct SMU74_Discrete_DpmTable *table)
1941 {
1942 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1943 uint16_t config;
1944
1945 config = VR_MERGED_WITH_VDDC;
1946 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1947
1948 /* Set Vddc Voltage Controller */
1949 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1950 config = VR_SVI2_PLANE_1;
1951 table->VRConfig |= config;
1952 } else {
1953 PP_ASSERT_WITH_CODE(false,
1954 "VDDC should be on SVI2 control in merged mode!",
1955 );
1956 }
1957 /* Set Vddci Voltage Controller */
1958 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1959 config = VR_SVI2_PLANE_2; /* only in merged mode */
1960 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1961 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1962 config = VR_SMIO_PATTERN_1;
1963 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1964 } else {
1965 config = VR_STATIC_VOLTAGE;
1966 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1967 }
1968 /* Set Mvdd Voltage Controller */
1969 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1970 config = VR_SVI2_PLANE_2;
1971 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1972 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1973 config = VR_SMIO_PATTERN_2;
1974 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1975 } else {
1976 config = VR_STATIC_VOLTAGE;
1977 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1978 }
1979
1980 return 0;
1981 }
1982
1983 /**
1984 * Initializes the SMC table and uploads it
1985 *
1986 * @param hwmgr the address of the powerplay hardware manager.
1987 * @return always 0
1988 */
1989 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1990 {
1991 int result;
1992 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1993 struct phm_ppt_v1_information *table_info =
1994 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1995 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1996 const struct polaris10_ulv_parm *ulv = &(data->ulv);
1997 uint8_t i;
1998 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1999 pp_atomctrl_clock_dividers_vi dividers;
2000
2001 result = polaris10_setup_default_dpm_tables(hwmgr);
2002 PP_ASSERT_WITH_CODE(0 == result,
2003 "Failed to setup default DPM tables!", return result);
2004
2005 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2006 polaris10_populate_smc_voltage_tables(hwmgr, table);
2007
2008 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2009 PHM_PlatformCaps_AutomaticDCTransition))
2010 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2011
2012 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2013 PHM_PlatformCaps_StepVddc))
2014 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2015
2016 if (data->is_memory_gddr5)
2017 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2018
2019 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2020 result = polaris10_populate_ulv_state(hwmgr, table);
2021 PP_ASSERT_WITH_CODE(0 == result,
2022 "Failed to initialize ULV state!", return result);
2023 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2024 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2025 }
2026
2027 result = polaris10_populate_smc_link_level(hwmgr, table);
2028 PP_ASSERT_WITH_CODE(0 == result,
2029 "Failed to initialize Link Level!", return result);
2030
2031 result = polaris10_populate_all_graphic_levels(hwmgr);
2032 PP_ASSERT_WITH_CODE(0 == result,
2033 "Failed to initialize Graphics Level!", return result);
2034
2035 result = polaris10_populate_all_memory_levels(hwmgr);
2036 PP_ASSERT_WITH_CODE(0 == result,
2037 "Failed to initialize Memory Level!", return result);
2038
2039 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2040 PP_ASSERT_WITH_CODE(0 == result,
2041 "Failed to initialize ACPI Level!", return result);
2042
2043 result = polaris10_populate_smc_vce_level(hwmgr, table);
2044 PP_ASSERT_WITH_CODE(0 == result,
2045 "Failed to initialize VCE Level!", return result);
2046
2047 result = polaris10_populate_smc_samu_level(hwmgr, table);
2048 PP_ASSERT_WITH_CODE(0 == result,
2049 "Failed to initialize SAMU Level!", return result);
2050
2051 /* Since only the initial state is completely set up at this point
2052 * (the other states are just copies of the boot state) we only
2053 * need to populate the ARB settings for the initial state.
2054 */
2055 result = polaris10_program_memory_timing_parameters(hwmgr);
2056 PP_ASSERT_WITH_CODE(0 == result,
2057 "Failed to Write ARB settings for the initial state.", return result);
2058
2059 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2060 PP_ASSERT_WITH_CODE(0 == result,
2061 "Failed to initialize UVD Level!", return result);
2062
2063 result = polaris10_populate_smc_boot_level(hwmgr, table);
2064 PP_ASSERT_WITH_CODE(0 == result,
2065 "Failed to initialize Boot Level!", return result);
2066
2067 result = polaris10_populate_smc_initailial_state(hwmgr);
2068 PP_ASSERT_WITH_CODE(0 == result,
2069 "Failed to initialize Boot State!", return result);
2070
2071 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2072 PP_ASSERT_WITH_CODE(0 == result,
2073 "Failed to populate BAPM Parameters!", return result);
2074
2075 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2076 PHM_PlatformCaps_ClockStretcher)) {
2077 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2078 PP_ASSERT_WITH_CODE(0 == result,
2079 "Failed to populate Clock Stretcher Data Table!",
2080 return result);
2081 }
2082
2083 table->GraphicsVoltageChangeEnable = 1;
2084 table->GraphicsThermThrottleEnable = 1;
2085 table->GraphicsInterval = 1;
2086 table->VoltageInterval = 1;
2087 table->ThermalInterval = 1;
2088 table->TemperatureLimitHigh =
2089 table_info->cac_dtp_table->usTargetOperatingTemp *
2090 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2091 table->TemperatureLimitLow =
2092 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2093 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2094 table->MemoryVoltageChangeEnable = 1;
2095 table->MemoryInterval = 1;
2096 table->VoltageResponseTime = 0;
2097 table->PhaseResponseTime = 0;
2098 table->MemoryThermThrottleEnable = 1;
2099 table->PCIeBootLinkLevel = 0;
2100 table->PCIeGenInterval = 1;
2101
2102 result = polaris10_populate_vr_config(hwmgr, table);
2103 PP_ASSERT_WITH_CODE(0 == result,
2104 "Failed to populate VRConfig setting!", return result);
2105
2106 table->ThermGpio = 17;
2107 table->SclkStepSize = 0x4000;
2108
2109 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2110 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2111 } else {
2112 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2114 PHM_PlatformCaps_RegulatorHot);
2115 }
2116
2117 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2118 &gpio_pin)) {
2119 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2120 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2121 PHM_PlatformCaps_AutomaticDCTransition);
2122 } else {
2123 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2124 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2125 PHM_PlatformCaps_AutomaticDCTransition);
2126 }
2127
2128 /* Thermal Output GPIO */
2129 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2130 &gpio_pin)) {
2131 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2132 PHM_PlatformCaps_ThermalOutGPIO);
2133
2134 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2135
2136 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2137 * since VBIOS will program this register to set 'inactive state',
2138 * driver can then determine 'active state' from this and
2139 * program SMU with correct polarity
2140 */
2141 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2142 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2143 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2144
2145 /* if required, combine VRHot/PCC with thermal out GPIO */
2146 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2147 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2148 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2149 } else {
2150 table->ThermOutGpio = 17;
2151 table->ThermOutPolarity = 1;
2152 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2153 }
2154
2155 /* Populate BIF_SCLK levels into SMC DPM table */
2156 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2157 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2158 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2159
2160 if (i == 0)
2161 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2162 else
2163 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2164 }
2165
2166 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2167 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2168
2169 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2170 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2171 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2172 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2173 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2174 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2175 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2176 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2177 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2178
2179 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2180 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2181 data->dpm_table_start +
2182 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2183 (uint8_t *)&(table->SystemFlags),
2184 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2185 data->sram_end);
2186 PP_ASSERT_WITH_CODE(0 == result,
2187 "Failed to upload dpm data to SMC memory!", return result);
2188
2189 return 0;
2190 }
2191
2192 /**
2193 * Initialize the ARB DRAM timing table's index field.
2194 *
2195 * @param hwmgr the address of the powerplay hardware manager.
2196 * @return always 0
2197 */
2198 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2199 {
2200 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2201 uint32_t tmp;
2202 int result;
2203
2204 /* This is a read-modify-write on the first byte of the ARB table.
2205 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2206 * is the field 'current'.
2207 * This solution is ugly, but we never write the whole table only
2208 * individual fields in it.
2209 * In reality this field should not be in that structure
2210 * but in a soft register.
2211 */
2212 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2213 data->arb_table_start, &tmp, data->sram_end);
2214
2215 if (result)
2216 return result;
2217
2218 tmp &= 0x00FFFFFF;
2219 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2220
2221 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2222 data->arb_table_start, tmp, data->sram_end);
2223 }
2224
2225 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2226 {
2227 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2228 PHM_PlatformCaps_RegulatorHot))
2229 return smum_send_msg_to_smc(hwmgr->smumgr,
2230 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2231
2232 return 0;
2233 }
2234
2235 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2236 {
2237 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2238 SCLK_PWRMGT_OFF, 0);
2239 return 0;
2240 }
2241
2242 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2243 {
2244 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2245 struct polaris10_ulv_parm *ulv = &(data->ulv);
2246
2247 if (ulv->ulv_supported)
2248 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2249
2250 return 0;
2251 }
2252
2253 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2254 {
2255 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2256 PHM_PlatformCaps_SclkDeepSleep)) {
2257 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2258 PP_ASSERT_WITH_CODE(false,
2259 "Attempt to enable Master Deep Sleep switch failed!",
2260 return -1);
2261 } else {
2262 if (smum_send_msg_to_smc(hwmgr->smumgr,
2263 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2264 PP_ASSERT_WITH_CODE(false,
2265 "Attempt to disable Master Deep Sleep switch failed!",
2266 return -1);
2267 }
2268 }
2269
2270 return 0;
2271 }
2272
2273 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2274 {
2275 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2276
2277 /* enable SCLK dpm */
2278 if (!data->sclk_dpm_key_disabled)
2279 PP_ASSERT_WITH_CODE(
2280 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2281 "Failed to enable SCLK DPM during DPM Start Function!",
2282 return -1);
2283
2284 /* enable MCLK dpm */
2285 if (0 == data->mclk_dpm_key_disabled) {
2286
2287 PP_ASSERT_WITH_CODE(
2288 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2289 PPSMC_MSG_MCLKDPM_Enable)),
2290 "Failed to enable MCLK DPM during DPM Start Function!",
2291 return -1);
2292
2293
2294 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2295
2296 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2297 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2298 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2299 udelay(10);
2300 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2301 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2302 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2303 }
2304
2305 return 0;
2306 }
2307
2308 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2309 {
2310 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2311
2312 /*enable general power management */
2313
2314 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2315 GLOBAL_PWRMGT_EN, 1);
2316
2317 /* enable sclk deep sleep */
2318
2319 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2320 DYNAMIC_PM_EN, 1);
2321
2322 /* prepare for PCIE DPM */
2323
2324 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2325 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2326 VoltageChangeTimeout), 0x1000);
2327 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2328 SWRST_COMMAND_1, RESETLC, 0x0);
2329 /*
2330 PP_ASSERT_WITH_CODE(
2331 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2332 PPSMC_MSG_Voltage_Cntl_Enable)),
2333 "Failed to enable voltage DPM during DPM Start Function!",
2334 return -1);
2335 */
2336
2337 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2338 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2339 return -1;
2340 }
2341
2342 /* enable PCIE dpm */
2343 if (0 == data->pcie_dpm_key_disabled) {
2344 PP_ASSERT_WITH_CODE(
2345 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2346 PPSMC_MSG_PCIeDPM_Enable)),
2347 "Failed to enable pcie DPM during DPM Start Function!",
2348 return -1);
2349 }
2350
2351 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2352 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2353 "Failed to enable AC DC GPIO Interrupt!",
2354 );
2355
2356 return 0;
2357 }
2358
2359 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2360 {
2361 bool protection;
2362 enum DPM_EVENT_SRC src;
2363
2364 switch (sources) {
2365 default:
2366 printk(KERN_ERR "Unknown throttling event sources.");
2367 /* fall through */
2368 case 0:
2369 protection = false;
2370 /* src is unused */
2371 break;
2372 case (1 << PHM_AutoThrottleSource_Thermal):
2373 protection = true;
2374 src = DPM_EVENT_SRC_DIGITAL;
2375 break;
2376 case (1 << PHM_AutoThrottleSource_External):
2377 protection = true;
2378 src = DPM_EVENT_SRC_EXTERNAL;
2379 break;
2380 case (1 << PHM_AutoThrottleSource_External) |
2381 (1 << PHM_AutoThrottleSource_Thermal):
2382 protection = true;
2383 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2384 break;
2385 }
2386 /* Order matters - don't enable thermal protection for the wrong source. */
2387 if (protection) {
2388 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2389 DPM_EVENT_SRC, src);
2390 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2391 THERMAL_PROTECTION_DIS,
2392 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2393 PHM_PlatformCaps_ThermalController));
2394 } else
2395 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2396 THERMAL_PROTECTION_DIS, 1);
2397 }
2398
2399 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2400 PHM_AutoThrottleSource source)
2401 {
2402 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2403
2404 if (!(data->active_auto_throttle_sources & (1 << source))) {
2405 data->active_auto_throttle_sources |= 1 << source;
2406 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2407 }
2408 return 0;
2409 }
2410
2411 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2412 {
2413 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2414 }
2415
2416 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2417 {
2418 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2419 data->pcie_performance_request = true;
2420
2421 return 0;
2422 }
2423
2424 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2425 {
2426 int tmp_result, result = 0;
2427 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2428 PP_ASSERT_WITH_CODE(result == 0,
2429 "DPM is already running right now, no need to enable DPM!",
2430 return 0);
2431
2432 if (polaris10_voltage_control(hwmgr)) {
2433 tmp_result = polaris10_enable_voltage_control(hwmgr);
2434 PP_ASSERT_WITH_CODE(tmp_result == 0,
2435 "Failed to enable voltage control!",
2436 result = tmp_result);
2437
2438 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2439 PP_ASSERT_WITH_CODE((0 == tmp_result),
2440 "Failed to contruct voltage tables!",
2441 result = tmp_result);
2442 }
2443
2444 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2445 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2446 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2447 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2448
2449 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2450 PHM_PlatformCaps_ThermalController))
2451 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2452 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2453
2454 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2455 PP_ASSERT_WITH_CODE((0 == tmp_result),
2456 "Failed to program static screen threshold parameters!",
2457 result = tmp_result);
2458
2459 tmp_result = polaris10_enable_display_gap(hwmgr);
2460 PP_ASSERT_WITH_CODE((0 == tmp_result),
2461 "Failed to enable display gap!", result = tmp_result);
2462
2463 tmp_result = polaris10_program_voting_clients(hwmgr);
2464 PP_ASSERT_WITH_CODE((0 == tmp_result),
2465 "Failed to program voting clients!", result = tmp_result);
2466
2467 tmp_result = polaris10_process_firmware_header(hwmgr);
2468 PP_ASSERT_WITH_CODE((0 == tmp_result),
2469 "Failed to process firmware header!", result = tmp_result);
2470
2471 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2472 PP_ASSERT_WITH_CODE((0 == tmp_result),
2473 "Failed to initialize switch from ArbF0 to F1!",
2474 result = tmp_result);
2475
2476 tmp_result = polaris10_init_smc_table(hwmgr);
2477 PP_ASSERT_WITH_CODE((0 == tmp_result),
2478 "Failed to initialize SMC table!", result = tmp_result);
2479
2480 tmp_result = polaris10_init_arb_table_index(hwmgr);
2481 PP_ASSERT_WITH_CODE((0 == tmp_result),
2482 "Failed to initialize ARB table index!", result = tmp_result);
2483
2484 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2485 PP_ASSERT_WITH_CODE((0 == tmp_result),
2486 "Failed to populate PM fuses!", result = tmp_result);
2487
2488 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2489 PP_ASSERT_WITH_CODE((0 == tmp_result),
2490 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2491
2492 tmp_result = polaris10_enable_sclk_control(hwmgr);
2493 PP_ASSERT_WITH_CODE((0 == tmp_result),
2494 "Failed to enable SCLK control!", result = tmp_result);
2495
2496 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2497 PP_ASSERT_WITH_CODE((0 == tmp_result),
2498 "Failed to enable voltage control!", result = tmp_result);
2499
2500 tmp_result = polaris10_enable_ulv(hwmgr);
2501 PP_ASSERT_WITH_CODE((0 == tmp_result),
2502 "Failed to enable ULV!", result = tmp_result);
2503
2504 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2505 PP_ASSERT_WITH_CODE((0 == tmp_result),
2506 "Failed to enable deep sleep master switch!", result = tmp_result);
2507
2508 tmp_result = polaris10_start_dpm(hwmgr);
2509 PP_ASSERT_WITH_CODE((0 == tmp_result),
2510 "Failed to start DPM!", result = tmp_result);
2511
2512 tmp_result = polaris10_enable_smc_cac(hwmgr);
2513 PP_ASSERT_WITH_CODE((0 == tmp_result),
2514 "Failed to enable SMC CAC!", result = tmp_result);
2515
2516 tmp_result = polaris10_enable_power_containment(hwmgr);
2517 PP_ASSERT_WITH_CODE((0 == tmp_result),
2518 "Failed to enable power containment!", result = tmp_result);
2519
2520 tmp_result = polaris10_power_control_set_level(hwmgr);
2521 PP_ASSERT_WITH_CODE((0 == tmp_result),
2522 "Failed to power control set level!", result = tmp_result);
2523
2524 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2525 PP_ASSERT_WITH_CODE((0 == tmp_result),
2526 "Failed to enable thermal auto throttle!", result = tmp_result);
2527
2528 tmp_result = polaris10_pcie_performance_request(hwmgr);
2529 PP_ASSERT_WITH_CODE((0 == tmp_result),
2530 "Failed to enable thermal auto throttle!", result = tmp_result);
2531
2532 return result;
2533 }
2534
2535 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2536 {
2537
2538 return 0;
2539 }
2540
2541 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2542 {
2543
2544 return 0;
2545 }
2546
2547 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2548 {
2549 return phm_hwmgr_backend_fini(hwmgr);
2550 }
2551
2552 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2553 {
2554 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2555
2556 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2557 PHM_PlatformCaps_SclkDeepSleep);
2558
2559 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2560 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2561 PHM_PlatformCaps_EnableMVDDControl);
2562
2563 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2564 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2565 PHM_PlatformCaps_ControlVDDCI);
2566
2567 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2568 PHM_PlatformCaps_TablelessHardwareInterface);
2569
2570 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2571 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2572
2573 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2574 PHM_PlatformCaps_DynamicPowerManagement);
2575
2576 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2577 PHM_PlatformCaps_TablelessHardwareInterface);
2578
2579 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2580 PHM_PlatformCaps_SMC);
2581
2582 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2583 PHM_PlatformCaps_NonABMSupportInPPLib);
2584
2585 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2586 PHM_PlatformCaps_DynamicUVDState);
2587
2588 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2589 PHM_PlatformCaps_SclkThrottleLowNotification);
2590
2591 /* power tune caps Assume disabled */
2592 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2593 PHM_PlatformCaps_PowerContainment);
2594 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2595 PHM_PlatformCaps_CAC);
2596 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2597 PHM_PlatformCaps_SQRamping);
2598 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2599 PHM_PlatformCaps_DBRamping);
2600 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2601 PHM_PlatformCaps_TDRamping);
2602 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2603 PHM_PlatformCaps_TCPRamping);
2604
2605 return 0;
2606 }
2607
2608 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2609 {
2610 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2611
2612 polaris10_initialize_power_tune_defaults(hwmgr);
2613
2614 data->pcie_gen_performance.max = PP_PCIEGen1;
2615 data->pcie_gen_performance.min = PP_PCIEGen3;
2616 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2617 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2618 data->pcie_lane_performance.max = 0;
2619 data->pcie_lane_performance.min = 16;
2620 data->pcie_lane_power_saving.max = 0;
2621 data->pcie_lane_power_saving.min = 16;
2622 }
2623
2624 /**
2625 * Get Leakage VDDC based on leakage ID.
2626 *
2627 * @param hwmgr the address of the powerplay hardware manager.
2628 * @return always 0
2629 */
2630 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2631 {
2632 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2633 uint16_t vv_id;
2634 uint16_t vddc = 0;
2635 uint16_t i, j;
2636 uint32_t sclk = 0;
2637 struct phm_ppt_v1_information *table_info =
2638 (struct phm_ppt_v1_information *)hwmgr->pptable;
2639 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2640 table_info->vdd_dep_on_sclk;
2641 int result;
2642
2643 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2644 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2645 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2646 table_info->vddc_lookup_table, vv_id, &sclk)) {
2647 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2648 PHM_PlatformCaps_ClockStretcher)) {
2649 for (j = 1; j < sclk_table->count; j++) {
2650 if (sclk_table->entries[j].clk == sclk &&
2651 sclk_table->entries[j].cks_enable == 0) {
2652 sclk += 5000;
2653 break;
2654 }
2655 }
2656 }
2657
2658
2659 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2660 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2661 "Error retrieving EVV voltage value!",
2662 continue);
2663
2664
2665 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2666 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2667 "Invalid VDDC value", result = -EINVAL;);
2668
2669 /* the voltage should not be zero nor equal to leakage ID */
2670 if (vddc != 0 && vddc != vv_id) {
2671 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2672 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2673 data->vddc_leakage.count++;
2674 }
2675 }
2676 }
2677
2678 return 0;
2679 }
2680
2681 /**
2682 * Change virtual leakage voltage to actual value.
2683 *
2684 * @param hwmgr the address of the powerplay hardware manager.
2685 * @param pointer to changing voltage
2686 * @param pointer to leakage table
2687 */
2688 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2689 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2690 {
2691 uint32_t index;
2692
2693 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2694 for (index = 0; index < leakage_table->count; index++) {
2695 /* if this voltage matches a leakage voltage ID */
2696 /* patch with actual leakage voltage */
2697 if (leakage_table->leakage_id[index] == *voltage) {
2698 *voltage = leakage_table->actual_voltage[index];
2699 break;
2700 }
2701 }
2702
2703 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2704 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2705 }
2706
2707 /**
2708 * Patch voltage lookup table by EVV leakages.
2709 *
2710 * @param hwmgr the address of the powerplay hardware manager.
2711 * @param pointer to voltage lookup table
2712 * @param pointer to leakage table
2713 * @return always 0
2714 */
2715 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2716 phm_ppt_v1_voltage_lookup_table *lookup_table,
2717 struct polaris10_leakage_voltage *leakage_table)
2718 {
2719 uint32_t i;
2720
2721 for (i = 0; i < lookup_table->count; i++)
2722 polaris10_patch_with_vdd_leakage(hwmgr,
2723 &lookup_table->entries[i].us_vdd, leakage_table);
2724
2725 return 0;
2726 }
2727
2728 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2729 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2730 uint16_t *vddc)
2731 {
2732 struct phm_ppt_v1_information *table_info =
2733 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2734 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2735 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2736 table_info->max_clock_voltage_on_dc.vddc;
2737 return 0;
2738 }
2739
2740 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2741 struct pp_hwmgr *hwmgr)
2742 {
2743 uint8_t entryId;
2744 uint8_t voltageId;
2745 struct phm_ppt_v1_information *table_info =
2746 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2747
2748 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2749 table_info->vdd_dep_on_sclk;
2750 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2751 table_info->vdd_dep_on_mclk;
2752 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2753 table_info->mm_dep_table;
2754
2755 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2756 voltageId = sclk_table->entries[entryId].vddInd;
2757 sclk_table->entries[entryId].vddc =
2758 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2759 }
2760
2761 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2762 voltageId = mclk_table->entries[entryId].vddInd;
2763 mclk_table->entries[entryId].vddc =
2764 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2765 }
2766
2767 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2768 voltageId = mm_table->entries[entryId].vddcInd;
2769 mm_table->entries[entryId].vddc =
2770 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2771 }
2772
2773 return 0;
2774
2775 }
2776
2777 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2778 {
2779 /* Need to determine if we need calculated voltage. */
2780 return 0;
2781 }
2782
2783 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2784 {
2785 /* Need to determine if we need calculated voltage from mm table. */
2786 return 0;
2787 }
2788
2789 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2790 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2791 {
2792 uint32_t table_size, i, j;
2793 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2794 table_size = lookup_table->count;
2795
2796 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2797 "Lookup table is empty", return -EINVAL);
2798
2799 /* Sorting voltages */
2800 for (i = 0; i < table_size - 1; i++) {
2801 for (j = i + 1; j > 0; j--) {
2802 if (lookup_table->entries[j].us_vdd <
2803 lookup_table->entries[j - 1].us_vdd) {
2804 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2805 lookup_table->entries[j - 1] = lookup_table->entries[j];
2806 lookup_table->entries[j] = tmp_voltage_lookup_record;
2807 }
2808 }
2809 }
2810
2811 return 0;
2812 }
2813
2814 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2815 {
2816 int result = 0;
2817 int tmp_result;
2818 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2819 struct phm_ppt_v1_information *table_info =
2820 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2821
2822 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2823 table_info->vddc_lookup_table, &(data->vddc_leakage));
2824 if (tmp_result)
2825 result = tmp_result;
2826
2827 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2828 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2829 if (tmp_result)
2830 result = tmp_result;
2831
2832 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2833 if (tmp_result)
2834 result = tmp_result;
2835
2836 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2837 if (tmp_result)
2838 result = tmp_result;
2839
2840 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2841 if (tmp_result)
2842 result = tmp_result;
2843
2844 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2845 if (tmp_result)
2846 result = tmp_result;
2847
2848 return result;
2849 }
2850
2851 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2852 {
2853 struct phm_ppt_v1_information *table_info =
2854 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2855
2856 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2857 table_info->vdd_dep_on_sclk;
2858 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2859 table_info->vdd_dep_on_mclk;
2860
2861 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2862 "VDD dependency on SCLK table is missing. \
2863 This table is mandatory", return -EINVAL);
2864 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2865 "VDD dependency on SCLK table has to have is missing. \
2866 This table is mandatory", return -EINVAL);
2867
2868 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2869 "VDD dependency on MCLK table is missing. \
2870 This table is mandatory", return -EINVAL);
2871 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2872 "VDD dependency on MCLK table has to have is missing. \
2873 This table is mandatory", return -EINVAL);
2874
2875 table_info->max_clock_voltage_on_ac.sclk =
2876 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2877 table_info->max_clock_voltage_on_ac.mclk =
2878 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2879 table_info->max_clock_voltage_on_ac.vddc =
2880 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2881 table_info->max_clock_voltage_on_ac.vddci =
2882 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2883
2884 return 0;
2885 }
2886
2887 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2888 {
2889 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2890 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2891 uint32_t temp_reg;
2892 int result;
2893
2894 data->dll_default_on = false;
2895 data->sram_end = SMC_RAM_END;
2896
2897 data->disable_dpm_mask = 0xFF;
2898 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2899 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2900 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2901 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2902 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2903 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2904 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2905 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2906 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2907 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2908
2909 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2910 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2911 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2912 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2913 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2914 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2915 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2916 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2917
2918 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2919
2920 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2921
2922 /* need to set voltage control types before EVV patching */
2923 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2924 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2925 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2926
2927 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2928 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2929 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2930
2931 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2932 PHM_PlatformCaps_DynamicPatchPowerState);
2933
2934 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2935 PHM_PlatformCaps_EnableMVDDControl)) {
2936 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2937 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2938 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2939 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2940 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2941 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2942 }
2943
2944 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2945 PHM_PlatformCaps_ControlVDDCI)) {
2946 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2947 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2948 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2949 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2950 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2951 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2952 }
2953
2954 polaris10_set_features_platform_caps(hwmgr);
2955
2956 polaris10_init_dpm_defaults(hwmgr);
2957
2958 /* Get leakage voltage based on leakage ID. */
2959 result = polaris10_get_evv_voltages(hwmgr);
2960
2961 if (result) {
2962 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
2963 return -1;
2964 }
2965
2966 polaris10_complete_dependency_tables(hwmgr);
2967 polaris10_set_private_data_based_on_pptable(hwmgr);
2968
2969 /* Initalize Dynamic State Adjustment Rule Settings */
2970 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2971
2972 if (0 == result) {
2973 struct cgs_system_info sys_info = {0};
2974
2975 data->is_tlu_enabled = 0;
2976
2977 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2978 POLARIS10_MAX_HARDWARE_POWERLEVELS;
2979 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2980 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2981 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2982 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2983 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2984 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2985
2986 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2987 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2988 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2989 case 0:
2990 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2991 break;
2992 case 1:
2993 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2994 break;
2995 case 2:
2996 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2997 break;
2998 case 3:
2999 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3000 break;
3001 case 4:
3002 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3003 break;
3004 default:
3005 PP_ASSERT_WITH_CODE(0,
3006 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3007 );
3008 break;
3009 }
3010 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3011 }
3012
3013 sys_info.size = sizeof(struct cgs_system_info);
3014 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3015 result = cgs_query_system_info(hwmgr->device, &sys_info);
3016 if (result)
3017 data->pcie_gen_cap = 0x30007;
3018 else
3019 data->pcie_gen_cap = (uint32_t)sys_info.value;
3020 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3021 data->pcie_spc_cap = 20;
3022 sys_info.size = sizeof(struct cgs_system_info);
3023 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3024 result = cgs_query_system_info(hwmgr->device, &sys_info);
3025 if (result)
3026 data->pcie_lane_cap = 0x2f0000;
3027 else
3028 data->pcie_lane_cap = (uint32_t)sys_info.value;
3029 } else {
3030 /* Ignore return value in here, we are cleaning up a mess. */
3031 polaris10_hwmgr_backend_fini(hwmgr);
3032 }
3033
3034 return 0;
3035 }
3036
3037 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3038 {
3039 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3040 uint32_t level, tmp;
3041
3042 if (!data->pcie_dpm_key_disabled) {
3043 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3044 level = 0;
3045 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3046 while (tmp >>= 1)
3047 level++;
3048
3049 if (level)
3050 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3051 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3052 }
3053 }
3054
3055 if (!data->sclk_dpm_key_disabled) {
3056 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3057 level = 0;
3058 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3059 while (tmp >>= 1)
3060 level++;
3061
3062 if (level)
3063 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3064 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3065 (1 << level));
3066 }
3067 }
3068
3069 if (!data->mclk_dpm_key_disabled) {
3070 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3071 level = 0;
3072 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3073 while (tmp >>= 1)
3074 level++;
3075
3076 if (level)
3077 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3078 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3079 (1 << level));
3080 }
3081 }
3082
3083 return 0;
3084 }
3085
3086 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3087 {
3088 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3089
3090 phm_apply_dal_min_voltage_request(hwmgr);
3091
3092 if (!data->sclk_dpm_key_disabled) {
3093 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3094 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3095 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3096 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3097 }
3098
3099 if (!data->mclk_dpm_key_disabled) {
3100 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3101 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3102 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3103 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3104 }
3105
3106 return 0;
3107 }
3108
3109 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3110 {
3111 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3112
3113 if (!polaris10_is_dpm_running(hwmgr))
3114 return -EINVAL;
3115
3116 if (!data->pcie_dpm_key_disabled) {
3117 smum_send_msg_to_smc(hwmgr->smumgr,
3118 PPSMC_MSG_PCIeDPM_UnForceLevel);
3119 }
3120
3121 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3122 }
3123
3124 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3125 {
3126 struct polaris10_hwmgr *data =
3127 (struct polaris10_hwmgr *)(hwmgr->backend);
3128 uint32_t level;
3129
3130 if (!data->sclk_dpm_key_disabled)
3131 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3132 level = phm_get_lowest_enabled_level(hwmgr,
3133 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3134 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3135 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3136 (1 << level));
3137
3138 }
3139 /* uvd is enabled, can't set mclk low right now
3140 if (!data->mclk_dpm_key_disabled) {
3141 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3142 level = phm_get_lowest_enabled_level(hwmgr,
3143 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3144 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3145 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3146 (1 << level));
3147 }
3148 }
3149 */
3150 if (!data->pcie_dpm_key_disabled) {
3151 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3152 level = phm_get_lowest_enabled_level(hwmgr,
3153 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3154 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3155 PPSMC_MSG_PCIeDPM_ForceLevel,
3156 (level));
3157 }
3158 }
3159
3160 return 0;
3161
3162 }
3163 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3164 enum amd_dpm_forced_level level)
3165 {
3166 int ret = 0;
3167
3168 switch (level) {
3169 case AMD_DPM_FORCED_LEVEL_HIGH:
3170 ret = polaris10_force_dpm_highest(hwmgr);
3171 if (ret)
3172 return ret;
3173 break;
3174 case AMD_DPM_FORCED_LEVEL_LOW:
3175 ret = polaris10_force_dpm_lowest(hwmgr);
3176 if (ret)
3177 return ret;
3178 break;
3179 case AMD_DPM_FORCED_LEVEL_AUTO:
3180 ret = polaris10_unforce_dpm_levels(hwmgr);
3181 if (ret)
3182 return ret;
3183 break;
3184 default:
3185 break;
3186 }
3187
3188 hwmgr->dpm_level = level;
3189
3190 return ret;
3191 }
3192
3193 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3194 {
3195 return sizeof(struct polaris10_power_state);
3196 }
3197
3198
3199 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3200 struct pp_power_state *request_ps,
3201 const struct pp_power_state *current_ps)
3202 {
3203
3204 struct polaris10_power_state *polaris10_ps =
3205 cast_phw_polaris10_power_state(&request_ps->hardware);
3206 uint32_t sclk;
3207 uint32_t mclk;
3208 struct PP_Clocks minimum_clocks = {0};
3209 bool disable_mclk_switching;
3210 bool disable_mclk_switching_for_frame_lock;
3211 struct cgs_display_info info = {0};
3212 const struct phm_clock_and_voltage_limits *max_limits;
3213 uint32_t i;
3214 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3215 struct phm_ppt_v1_information *table_info =
3216 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3217 int32_t count;
3218 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3219
3220 data->battery_state = (PP_StateUILabel_Battery ==
3221 request_ps->classification.ui_label);
3222
3223 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3224 "VI should always have 2 performance levels",
3225 );
3226
3227 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3228 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3229 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3230
3231 /* Cap clock DPM tables at DC MAX if it is in DC. */
3232 if (PP_PowerSource_DC == hwmgr->power_source) {
3233 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3234 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3235 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3236 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3237 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3238 }
3239 }
3240
3241 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3242 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3243
3244 cgs_get_active_displays_info(hwmgr->device, &info);
3245
3246 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3247
3248 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3249
3250 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3251 PHM_PlatformCaps_StablePState)) {
3252 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3253 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3254
3255 for (count = table_info->vdd_dep_on_sclk->count - 1;
3256 count >= 0; count--) {
3257 if (stable_pstate_sclk >=
3258 table_info->vdd_dep_on_sclk->entries[count].clk) {
3259 stable_pstate_sclk =
3260 table_info->vdd_dep_on_sclk->entries[count].clk;
3261 break;
3262 }
3263 }
3264
3265 if (count < 0)
3266 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3267
3268 stable_pstate_mclk = max_limits->mclk;
3269
3270 minimum_clocks.engineClock = stable_pstate_sclk;
3271 minimum_clocks.memoryClock = stable_pstate_mclk;
3272 }
3273
3274 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3275 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3276
3277 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3278 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3279
3280 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3281
3282 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3283 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3284 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3285 "Overdrive sclk exceeds limit",
3286 hwmgr->gfx_arbiter.sclk_over_drive =
3287 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3288
3289 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3290 polaris10_ps->performance_levels[1].engine_clock =
3291 hwmgr->gfx_arbiter.sclk_over_drive;
3292 }
3293
3294 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3295 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3296 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3297 "Overdrive mclk exceeds limit",
3298 hwmgr->gfx_arbiter.mclk_over_drive =
3299 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3300
3301 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3302 polaris10_ps->performance_levels[1].memory_clock =
3303 hwmgr->gfx_arbiter.mclk_over_drive;
3304 }
3305
3306 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3307 hwmgr->platform_descriptor.platformCaps,
3308 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3309
3310 disable_mclk_switching = (1 < info.display_count) ||
3311 disable_mclk_switching_for_frame_lock;
3312
3313 sclk = polaris10_ps->performance_levels[0].engine_clock;
3314 mclk = polaris10_ps->performance_levels[0].memory_clock;
3315
3316 if (disable_mclk_switching)
3317 mclk = polaris10_ps->performance_levels
3318 [polaris10_ps->performance_level_count - 1].memory_clock;
3319
3320 if (sclk < minimum_clocks.engineClock)
3321 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3322 max_limits->sclk : minimum_clocks.engineClock;
3323
3324 if (mclk < minimum_clocks.memoryClock)
3325 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3326 max_limits->mclk : minimum_clocks.memoryClock;
3327
3328 polaris10_ps->performance_levels[0].engine_clock = sclk;
3329 polaris10_ps->performance_levels[0].memory_clock = mclk;
3330
3331 polaris10_ps->performance_levels[1].engine_clock =
3332 (polaris10_ps->performance_levels[1].engine_clock >=
3333 polaris10_ps->performance_levels[0].engine_clock) ?
3334 polaris10_ps->performance_levels[1].engine_clock :
3335 polaris10_ps->performance_levels[0].engine_clock;
3336
3337 if (disable_mclk_switching) {
3338 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3339 mclk = polaris10_ps->performance_levels[1].memory_clock;
3340
3341 polaris10_ps->performance_levels[0].memory_clock = mclk;
3342 polaris10_ps->performance_levels[1].memory_clock = mclk;
3343 } else {
3344 if (polaris10_ps->performance_levels[1].memory_clock <
3345 polaris10_ps->performance_levels[0].memory_clock)
3346 polaris10_ps->performance_levels[1].memory_clock =
3347 polaris10_ps->performance_levels[0].memory_clock;
3348 }
3349
3350 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3351 PHM_PlatformCaps_StablePState)) {
3352 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3353 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3354 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3355 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3356 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3357 }
3358 }
3359 return 0;
3360 }
3361
3362
3363 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3364 {
3365 struct pp_power_state *ps;
3366 struct polaris10_power_state *polaris10_ps;
3367
3368 if (hwmgr == NULL)
3369 return -EINVAL;
3370
3371 ps = hwmgr->request_ps;
3372
3373 if (ps == NULL)
3374 return -EINVAL;
3375
3376 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3377
3378 if (low)
3379 return polaris10_ps->performance_levels[0].memory_clock;
3380 else
3381 return polaris10_ps->performance_levels
3382 [polaris10_ps->performance_level_count-1].memory_clock;
3383 }
3384
3385 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3386 {
3387 struct pp_power_state *ps;
3388 struct polaris10_power_state *polaris10_ps;
3389
3390 if (hwmgr == NULL)
3391 return -EINVAL;
3392
3393 ps = hwmgr->request_ps;
3394
3395 if (ps == NULL)
3396 return -EINVAL;
3397
3398 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3399
3400 if (low)
3401 return polaris10_ps->performance_levels[0].engine_clock;
3402 else
3403 return polaris10_ps->performance_levels
3404 [polaris10_ps->performance_level_count-1].engine_clock;
3405 }
3406
3407 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3408 struct pp_hw_power_state *hw_ps)
3409 {
3410 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3411 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3412 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3413 uint16_t size;
3414 uint8_t frev, crev;
3415 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3416
3417 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3418 * We assume here that fw_info is unchanged if this call fails.
3419 */
3420 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3421 hwmgr->device, index,
3422 &size, &frev, &crev);
3423 if (!fw_info)
3424 /* During a test, there is no firmware info table. */
3425 return 0;
3426
3427 /* Patch the state. */
3428 data->vbios_boot_state.sclk_bootup_value =
3429 le32_to_cpu(fw_info->ulDefaultEngineClock);
3430 data->vbios_boot_state.mclk_bootup_value =
3431 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3432 data->vbios_boot_state.mvdd_bootup_value =
3433 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3434 data->vbios_boot_state.vddc_bootup_value =
3435 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3436 data->vbios_boot_state.vddci_bootup_value =
3437 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3438 data->vbios_boot_state.pcie_gen_bootup_value =
3439 phm_get_current_pcie_speed(hwmgr);
3440
3441 data->vbios_boot_state.pcie_lane_bootup_value =
3442 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3443
3444 /* set boot power state */
3445 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3446 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3447 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3448 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3449
3450 return 0;
3451 }
3452
3453 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3454 void *state, struct pp_power_state *power_state,
3455 void *pp_table, uint32_t classification_flag)
3456 {
3457 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3458 struct polaris10_power_state *polaris10_power_state =
3459 (struct polaris10_power_state *)(&(power_state->hardware));
3460 struct polaris10_performance_level *performance_level;
3461 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3462 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3463 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3464 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3465 (ATOM_Tonga_SCLK_Dependency_Table *)
3466 (((unsigned long)powerplay_table) +
3467 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3468 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3469 (ATOM_Tonga_MCLK_Dependency_Table *)
3470 (((unsigned long)powerplay_table) +
3471 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3472
3473 /* The following fields are not initialized here: id orderedList allStatesList */
3474 power_state->classification.ui_label =
3475 (le16_to_cpu(state_entry->usClassification) &
3476 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3477 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3478 power_state->classification.flags = classification_flag;
3479 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3480
3481 power_state->classification.temporary_state = false;
3482 power_state->classification.to_be_deleted = false;
3483
3484 power_state->validation.disallowOnDC =
3485 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3486 ATOM_Tonga_DISALLOW_ON_DC));
3487
3488 power_state->pcie.lanes = 0;
3489
3490 power_state->display.disableFrameModulation = false;
3491 power_state->display.limitRefreshrate = false;
3492 power_state->display.enableVariBright =
3493 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3494 ATOM_Tonga_ENABLE_VARIBRIGHT));
3495
3496 power_state->validation.supportedPowerLevels = 0;
3497 power_state->uvd_clocks.VCLK = 0;
3498 power_state->uvd_clocks.DCLK = 0;
3499 power_state->temperatures.min = 0;
3500 power_state->temperatures.max = 0;
3501
3502 performance_level = &(polaris10_power_state->performance_levels
3503 [polaris10_power_state->performance_level_count++]);
3504
3505 PP_ASSERT_WITH_CODE(
3506 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3507 "Performance levels exceeds SMC limit!",
3508 return -1);
3509
3510 PP_ASSERT_WITH_CODE(
3511 (polaris10_power_state->performance_level_count <=
3512 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3513 "Performance levels exceeds Driver limit!",
3514 return -1);
3515
3516 /* Performance levels are arranged from low to high. */
3517 performance_level->memory_clock = mclk_dep_table->entries
3518 [state_entry->ucMemoryClockIndexLow].ulMclk;
3519 performance_level->engine_clock = sclk_dep_table->entries
3520 [state_entry->ucEngineClockIndexLow].ulSclk;
3521 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3522 state_entry->ucPCIEGenLow);
3523 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3524 state_entry->ucPCIELaneHigh);
3525
3526 performance_level = &(polaris10_power_state->performance_levels
3527 [polaris10_power_state->performance_level_count++]);
3528 performance_level->memory_clock = mclk_dep_table->entries
3529 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3530 performance_level->engine_clock = sclk_dep_table->entries
3531 [state_entry->ucEngineClockIndexHigh].ulSclk;
3532 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3533 state_entry->ucPCIEGenHigh);
3534 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3535 state_entry->ucPCIELaneHigh);
3536
3537 return 0;
3538 }
3539
3540 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3541 unsigned long entry_index, struct pp_power_state *state)
3542 {
3543 int result;
3544 struct polaris10_power_state *ps;
3545 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3546 struct phm_ppt_v1_information *table_info =
3547 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3548 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3549 table_info->vdd_dep_on_mclk;
3550
3551 state->hardware.magic = PHM_VIslands_Magic;
3552
3553 ps = (struct polaris10_power_state *)(&state->hardware);
3554
3555 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3556 polaris10_get_pp_table_entry_callback_func);
3557
3558 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3559 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3560 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3561 */
3562 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3563 if (dep_mclk_table->entries[0].clk !=
3564 data->vbios_boot_state.mclk_bootup_value)
3565 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3566 "does not match VBIOS boot MCLK level");
3567 if (dep_mclk_table->entries[0].vddci !=
3568 data->vbios_boot_state.vddci_bootup_value)
3569 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3570 "does not match VBIOS boot VDDCI level");
3571 }
3572
3573 /* set DC compatible flag if this state supports DC */
3574 if (!state->validation.disallowOnDC)
3575 ps->dc_compatible = true;
3576
3577 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3578 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3579
3580 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3581 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3582
3583 if (!result) {
3584 uint32_t i;
3585
3586 switch (state->classification.ui_label) {
3587 case PP_StateUILabel_Performance:
3588 data->use_pcie_performance_levels = true;
3589
3590 for (i = 0; i < ps->performance_level_count; i++) {
3591 if (data->pcie_gen_performance.max <
3592 ps->performance_levels[i].pcie_gen)
3593 data->pcie_gen_performance.max =
3594 ps->performance_levels[i].pcie_gen;
3595
3596 if (data->pcie_gen_performance.min >
3597 ps->performance_levels[i].pcie_gen)
3598 data->pcie_gen_performance.min =
3599 ps->performance_levels[i].pcie_gen;
3600
3601 if (data->pcie_lane_performance.max <
3602 ps->performance_levels[i].pcie_lane)
3603 data->pcie_lane_performance.max =
3604 ps->performance_levels[i].pcie_lane;
3605
3606 if (data->pcie_lane_performance.min >
3607 ps->performance_levels[i].pcie_lane)
3608 data->pcie_lane_performance.min =
3609 ps->performance_levels[i].pcie_lane;
3610 }
3611 break;
3612 case PP_StateUILabel_Battery:
3613 data->use_pcie_power_saving_levels = true;
3614
3615 for (i = 0; i < ps->performance_level_count; i++) {
3616 if (data->pcie_gen_power_saving.max <
3617 ps->performance_levels[i].pcie_gen)
3618 data->pcie_gen_power_saving.max =
3619 ps->performance_levels[i].pcie_gen;
3620
3621 if (data->pcie_gen_power_saving.min >
3622 ps->performance_levels[i].pcie_gen)
3623 data->pcie_gen_power_saving.min =
3624 ps->performance_levels[i].pcie_gen;
3625
3626 if (data->pcie_lane_power_saving.max <
3627 ps->performance_levels[i].pcie_lane)
3628 data->pcie_lane_power_saving.max =
3629 ps->performance_levels[i].pcie_lane;
3630
3631 if (data->pcie_lane_power_saving.min >
3632 ps->performance_levels[i].pcie_lane)
3633 data->pcie_lane_power_saving.min =
3634 ps->performance_levels[i].pcie_lane;
3635 }
3636 break;
3637 default:
3638 break;
3639 }
3640 }
3641 return 0;
3642 }
3643
3644 static void
3645 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3646 {
3647 uint32_t sclk, mclk, activity_percent;
3648 uint32_t offset;
3649 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3650
3651 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3652
3653 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3654
3655 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3656
3657 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3658 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3659 mclk / 100, sclk / 100);
3660
3661 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3662 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3663 activity_percent += 0x80;
3664 activity_percent >>= 8;
3665
3666 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3667
3668 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3669
3670 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
3671 }
3672
3673 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3674 {
3675 const struct phm_set_power_state_input *states =
3676 (const struct phm_set_power_state_input *)input;
3677 const struct polaris10_power_state *polaris10_ps =
3678 cast_const_phw_polaris10_power_state(states->pnew_state);
3679 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3680 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3681 uint32_t sclk = polaris10_ps->performance_levels
3682 [polaris10_ps->performance_level_count - 1].engine_clock;
3683 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3684 uint32_t mclk = polaris10_ps->performance_levels
3685 [polaris10_ps->performance_level_count - 1].memory_clock;
3686 struct PP_Clocks min_clocks = {0};
3687 uint32_t i;
3688 struct cgs_display_info info = {0};
3689
3690 data->need_update_smu7_dpm_table = 0;
3691
3692 for (i = 0; i < sclk_table->count; i++) {
3693 if (sclk == sclk_table->dpm_levels[i].value)
3694 break;
3695 }
3696
3697 if (i >= sclk_table->count)
3698 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3699 else {
3700 /* TODO: Check SCLK in DAL's minimum clocks
3701 * in case DeepSleep divider update is required.
3702 */
3703 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3704 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3705 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3706 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3707 }
3708
3709 for (i = 0; i < mclk_table->count; i++) {
3710 if (mclk == mclk_table->dpm_levels[i].value)
3711 break;
3712 }
3713
3714 if (i >= mclk_table->count)
3715 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3716
3717 cgs_get_active_displays_info(hwmgr->device, &info);
3718
3719 if (data->display_timing.num_existing_displays != info.display_count)
3720 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3721
3722 return 0;
3723 }
3724
3725 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3726 const struct polaris10_power_state *polaris10_ps)
3727 {
3728 uint32_t i;
3729 uint32_t sclk, max_sclk = 0;
3730 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3731 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3732
3733 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3734 sclk = polaris10_ps->performance_levels[i].engine_clock;
3735 if (max_sclk < sclk)
3736 max_sclk = sclk;
3737 }
3738
3739 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3740 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3741 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3742 dpm_table->pcie_speed_table.dpm_levels
3743 [dpm_table->pcie_speed_table.count - 1].value :
3744 dpm_table->pcie_speed_table.dpm_levels[i].value);
3745 }
3746
3747 return 0;
3748 }
3749
3750 static int polaris10_request_link_speed_change_before_state_change(
3751 struct pp_hwmgr *hwmgr, const void *input)
3752 {
3753 const struct phm_set_power_state_input *states =
3754 (const struct phm_set_power_state_input *)input;
3755 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3756 const struct polaris10_power_state *polaris10_nps =
3757 cast_const_phw_polaris10_power_state(states->pnew_state);
3758 const struct polaris10_power_state *polaris10_cps =
3759 cast_const_phw_polaris10_power_state(states->pcurrent_state);
3760
3761 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3762 uint16_t current_link_speed;
3763
3764 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3765 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3766 else
3767 current_link_speed = data->force_pcie_gen;
3768
3769 data->force_pcie_gen = PP_PCIEGenInvalid;
3770 data->pspp_notify_required = false;
3771
3772 if (target_link_speed > current_link_speed) {
3773 switch (target_link_speed) {
3774 case PP_PCIEGen3:
3775 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3776 break;
3777 data->force_pcie_gen = PP_PCIEGen2;
3778 if (current_link_speed == PP_PCIEGen2)
3779 break;
3780 case PP_PCIEGen2:
3781 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3782 break;
3783 default:
3784 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3785 break;
3786 }
3787 } else {
3788 if (target_link_speed < current_link_speed)
3789 data->pspp_notify_required = true;
3790 }
3791
3792 return 0;
3793 }
3794
3795 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3796 {
3797 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3798
3799 if (0 == data->need_update_smu7_dpm_table)
3800 return 0;
3801
3802 if ((0 == data->sclk_dpm_key_disabled) &&
3803 (data->need_update_smu7_dpm_table &
3804 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3805 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3806 "Trying to freeze SCLK DPM when DPM is disabled",
3807 );
3808 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3809 PPSMC_MSG_SCLKDPM_FreezeLevel),
3810 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3811 return -1);
3812 }
3813
3814 if ((0 == data->mclk_dpm_key_disabled) &&
3815 (data->need_update_smu7_dpm_table &
3816 DPMTABLE_OD_UPDATE_MCLK)) {
3817 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3818 "Trying to freeze MCLK DPM when DPM is disabled",
3819 );
3820 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3821 PPSMC_MSG_MCLKDPM_FreezeLevel),
3822 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3823 return -1);
3824 }
3825
3826 return 0;
3827 }
3828
3829 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3830 struct pp_hwmgr *hwmgr, const void *input)
3831 {
3832 int result = 0;
3833 const struct phm_set_power_state_input *states =
3834 (const struct phm_set_power_state_input *)input;
3835 const struct polaris10_power_state *polaris10_ps =
3836 cast_const_phw_polaris10_power_state(states->pnew_state);
3837 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3838 uint32_t sclk = polaris10_ps->performance_levels
3839 [polaris10_ps->performance_level_count - 1].engine_clock;
3840 uint32_t mclk = polaris10_ps->performance_levels
3841 [polaris10_ps->performance_level_count - 1].memory_clock;
3842 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3843
3844 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3845 uint32_t dpm_count, clock_percent;
3846 uint32_t i;
3847
3848 if (0 == data->need_update_smu7_dpm_table)
3849 return 0;
3850
3851 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3852 dpm_table->sclk_table.dpm_levels
3853 [dpm_table->sclk_table.count - 1].value = sclk;
3854
3855 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3856 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3857 /* Need to do calculation based on the golden DPM table
3858 * as the Heatmap GPU Clock axis is also based on the default values
3859 */
3860 PP_ASSERT_WITH_CODE(
3861 (golden_dpm_table->sclk_table.dpm_levels
3862 [golden_dpm_table->sclk_table.count - 1].value != 0),
3863 "Divide by 0!",
3864 return -1);
3865 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3866
3867 for (i = dpm_count; i > 1; i--) {
3868 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3869 clock_percent =
3870 ((sclk
3871 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3872 ) * 100)
3873 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3874
3875 dpm_table->sclk_table.dpm_levels[i].value =
3876 golden_dpm_table->sclk_table.dpm_levels[i].value +
3877 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3878 clock_percent)/100;
3879
3880 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3881 clock_percent =
3882 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3883 - sclk) * 100)
3884 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3885
3886 dpm_table->sclk_table.dpm_levels[i].value =
3887 golden_dpm_table->sclk_table.dpm_levels[i].value -
3888 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3889 clock_percent) / 100;
3890 } else
3891 dpm_table->sclk_table.dpm_levels[i].value =
3892 golden_dpm_table->sclk_table.dpm_levels[i].value;
3893 }
3894 }
3895 }
3896
3897 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3898 dpm_table->mclk_table.dpm_levels
3899 [dpm_table->mclk_table.count - 1].value = mclk;
3900
3901 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3902 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3903
3904 PP_ASSERT_WITH_CODE(
3905 (golden_dpm_table->mclk_table.dpm_levels
3906 [golden_dpm_table->mclk_table.count-1].value != 0),
3907 "Divide by 0!",
3908 return -1);
3909 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3910 for (i = dpm_count; i > 1; i--) {
3911 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3912 clock_percent = ((mclk -
3913 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3914 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3915
3916 dpm_table->mclk_table.dpm_levels[i].value =
3917 golden_dpm_table->mclk_table.dpm_levels[i].value +
3918 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3919 clock_percent) / 100;
3920
3921 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
3922 clock_percent = (
3923 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
3924 * 100)
3925 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3926
3927 dpm_table->mclk_table.dpm_levels[i].value =
3928 golden_dpm_table->mclk_table.dpm_levels[i].value -
3929 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3930 clock_percent) / 100;
3931 } else
3932 dpm_table->mclk_table.dpm_levels[i].value =
3933 golden_dpm_table->mclk_table.dpm_levels[i].value;
3934 }
3935 }
3936 }
3937
3938 if (data->need_update_smu7_dpm_table &
3939 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3940 result = polaris10_populate_all_graphic_levels(hwmgr);
3941 PP_ASSERT_WITH_CODE((0 == result),
3942 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3943 return result);
3944 }
3945
3946 if (data->need_update_smu7_dpm_table &
3947 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3948 /*populate MCLK dpm table to SMU7 */
3949 result = polaris10_populate_all_memory_levels(hwmgr);
3950 PP_ASSERT_WITH_CODE((0 == result),
3951 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3952 return result);
3953 }
3954
3955 return result;
3956 }
3957
3958 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3959 struct polaris10_single_dpm_table *dpm_table,
3960 uint32_t low_limit, uint32_t high_limit)
3961 {
3962 uint32_t i;
3963 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3964
3965 for (i = 0; i < dpm_table->count; i++) {
3966 if ((dpm_table->dpm_levels[i].value < low_limit)
3967 || (dpm_table->dpm_levels[i].value > high_limit))
3968 dpm_table->dpm_levels[i].enabled = false;
3969 else if (((1 << i) & data->disable_dpm_mask) == 0)
3970 dpm_table->dpm_levels[i].enabled = false;
3971 else
3972 dpm_table->dpm_levels[i].enabled = true;
3973 }
3974
3975 return 0;
3976 }
3977
3978 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3979 const struct polaris10_power_state *polaris10_ps)
3980 {
3981 int result = 0;
3982 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3983 uint32_t high_limit_count;
3984
3985 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
3986 "power state did not have any performance level",
3987 return -1);
3988
3989 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
3990
3991 polaris10_trim_single_dpm_states(hwmgr,
3992 &(data->dpm_table.sclk_table),
3993 polaris10_ps->performance_levels[0].engine_clock,
3994 polaris10_ps->performance_levels[high_limit_count].engine_clock);
3995
3996 polaris10_trim_single_dpm_states(hwmgr,
3997 &(data->dpm_table.mclk_table),
3998 polaris10_ps->performance_levels[0].memory_clock,
3999 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4000
4001 return result;
4002 }
4003
4004 static int polaris10_generate_dpm_level_enable_mask(
4005 struct pp_hwmgr *hwmgr, const void *input)
4006 {
4007 int result;
4008 const struct phm_set_power_state_input *states =
4009 (const struct phm_set_power_state_input *)input;
4010 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4011 const struct polaris10_power_state *polaris10_ps =
4012 cast_const_phw_polaris10_power_state(states->pnew_state);
4013
4014 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4015 if (result)
4016 return result;
4017
4018 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4019 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4020 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4021 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4022 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4023 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4024
4025 return 0;
4026 }
4027
4028 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4029 {
4030 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4031 PPSMC_MSG_UVDDPM_Enable :
4032 PPSMC_MSG_UVDDPM_Disable);
4033 }
4034
4035 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4036 {
4037 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4038 PPSMC_MSG_VCEDPM_Enable :
4039 PPSMC_MSG_VCEDPM_Disable);
4040 }
4041
4042 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4043 {
4044 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4045 PPSMC_MSG_SAMUDPM_Enable :
4046 PPSMC_MSG_SAMUDPM_Disable);
4047 }
4048
4049 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4050 {
4051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4052 uint32_t mm_boot_level_offset, mm_boot_level_value;
4053 struct phm_ppt_v1_information *table_info =
4054 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4055
4056 if (!bgate) {
4057 data->smc_state_table.UvdBootLevel = 0;
4058 if (table_info->mm_dep_table->count > 0)
4059 data->smc_state_table.UvdBootLevel =
4060 (uint8_t) (table_info->mm_dep_table->count - 1);
4061 mm_boot_level_offset = data->dpm_table_start +
4062 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4063 mm_boot_level_offset /= 4;
4064 mm_boot_level_offset *= 4;
4065 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4066 CGS_IND_REG__SMC, mm_boot_level_offset);
4067 mm_boot_level_value &= 0x00FFFFFF;
4068 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4069 cgs_write_ind_register(hwmgr->device,
4070 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4071
4072 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4073 PHM_PlatformCaps_UVDDPM) ||
4074 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4075 PHM_PlatformCaps_StablePState))
4076 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4077 PPSMC_MSG_UVDDPM_SetEnabledMask,
4078 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4079 }
4080
4081 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4082 }
4083
4084 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4085 {
4086 const struct phm_set_power_state_input *states =
4087 (const struct phm_set_power_state_input *)input;
4088 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4089 const struct polaris10_power_state *polaris10_nps =
4090 cast_const_phw_polaris10_power_state(states->pnew_state);
4091 const struct polaris10_power_state *polaris10_cps =
4092 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4093
4094 uint32_t mm_boot_level_offset, mm_boot_level_value;
4095 struct phm_ppt_v1_information *table_info =
4096 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4097
4098 if (polaris10_nps->vce_clks.evclk > 0 &&
4099 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4100
4101 data->smc_state_table.VceBootLevel =
4102 (uint8_t) (table_info->mm_dep_table->count - 1);
4103
4104 mm_boot_level_offset = data->dpm_table_start +
4105 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4106 mm_boot_level_offset /= 4;
4107 mm_boot_level_offset *= 4;
4108 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4109 CGS_IND_REG__SMC, mm_boot_level_offset);
4110 mm_boot_level_value &= 0xFF00FFFF;
4111 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4112 cgs_write_ind_register(hwmgr->device,
4113 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4114
4115 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4116 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4117 PPSMC_MSG_VCEDPM_SetEnabledMask,
4118 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4119
4120 polaris10_enable_disable_vce_dpm(hwmgr, true);
4121 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4122 polaris10_cps != NULL &&
4123 polaris10_cps->vce_clks.evclk > 0)
4124 polaris10_enable_disable_vce_dpm(hwmgr, false);
4125 }
4126
4127 return 0;
4128 }
4129
4130 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4131 {
4132 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4133 uint32_t mm_boot_level_offset, mm_boot_level_value;
4134 struct phm_ppt_v1_information *table_info =
4135 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4136
4137 if (!bgate) {
4138 data->smc_state_table.SamuBootLevel =
4139 (uint8_t) (table_info->mm_dep_table->count - 1);
4140 mm_boot_level_offset = data->dpm_table_start +
4141 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4142 mm_boot_level_offset /= 4;
4143 mm_boot_level_offset *= 4;
4144 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4145 CGS_IND_REG__SMC, mm_boot_level_offset);
4146 mm_boot_level_value &= 0xFFFFFF00;
4147 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4148 cgs_write_ind_register(hwmgr->device,
4149 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4150
4151 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4152 PHM_PlatformCaps_StablePState))
4153 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4154 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4155 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4156 }
4157
4158 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4159 }
4160
4161 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4162 {
4163 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4164
4165 int result = 0;
4166 uint32_t low_sclk_interrupt_threshold = 0;
4167
4168 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4169 PHM_PlatformCaps_SclkThrottleLowNotification)
4170 && (hwmgr->gfx_arbiter.sclk_threshold !=
4171 data->low_sclk_interrupt_threshold)) {
4172 data->low_sclk_interrupt_threshold =
4173 hwmgr->gfx_arbiter.sclk_threshold;
4174 low_sclk_interrupt_threshold =
4175 data->low_sclk_interrupt_threshold;
4176
4177 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4178
4179 result = polaris10_copy_bytes_to_smc(
4180 hwmgr->smumgr,
4181 data->dpm_table_start +
4182 offsetof(SMU74_Discrete_DpmTable,
4183 LowSclkInterruptThreshold),
4184 (uint8_t *)&low_sclk_interrupt_threshold,
4185 sizeof(uint32_t),
4186 data->sram_end);
4187 }
4188
4189 return result;
4190 }
4191
4192 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4193 {
4194 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4195
4196 if (data->need_update_smu7_dpm_table &
4197 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4198 return polaris10_program_memory_timing_parameters(hwmgr);
4199
4200 return 0;
4201 }
4202
4203 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4204 {
4205 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4206
4207 if (0 == data->need_update_smu7_dpm_table)
4208 return 0;
4209
4210 if ((0 == data->sclk_dpm_key_disabled) &&
4211 (data->need_update_smu7_dpm_table &
4212 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4213
4214 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4215 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4216 );
4217 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4218 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4219 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4220 return -1);
4221 }
4222
4223 if ((0 == data->mclk_dpm_key_disabled) &&
4224 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4225
4226 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4227 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4228 );
4229 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4230 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4231 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4232 return -1);
4233 }
4234
4235 data->need_update_smu7_dpm_table = 0;
4236
4237 return 0;
4238 }
4239
4240 static int polaris10_notify_link_speed_change_after_state_change(
4241 struct pp_hwmgr *hwmgr, const void *input)
4242 {
4243 const struct phm_set_power_state_input *states =
4244 (const struct phm_set_power_state_input *)input;
4245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4246 const struct polaris10_power_state *polaris10_ps =
4247 cast_const_phw_polaris10_power_state(states->pnew_state);
4248 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4249 uint8_t request;
4250
4251 if (data->pspp_notify_required) {
4252 if (target_link_speed == PP_PCIEGen3)
4253 request = PCIE_PERF_REQ_GEN3;
4254 else if (target_link_speed == PP_PCIEGen2)
4255 request = PCIE_PERF_REQ_GEN2;
4256 else
4257 request = PCIE_PERF_REQ_GEN1;
4258
4259 if (request == PCIE_PERF_REQ_GEN1 &&
4260 phm_get_current_pcie_speed(hwmgr) > 0)
4261 return 0;
4262
4263 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4264 if (PP_PCIEGen2 == target_link_speed)
4265 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4266 else
4267 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4268 }
4269 }
4270
4271 return 0;
4272 }
4273
4274 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4275 {
4276 int tmp_result, result = 0;
4277 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4278
4279 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4280 PP_ASSERT_WITH_CODE((0 == tmp_result),
4281 "Failed to find DPM states clocks in DPM table!",
4282 result = tmp_result);
4283
4284 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4285 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4286 tmp_result =
4287 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4288 PP_ASSERT_WITH_CODE((0 == tmp_result),
4289 "Failed to request link speed change before state change!",
4290 result = tmp_result);
4291 }
4292
4293 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4294 PP_ASSERT_WITH_CODE((0 == tmp_result),
4295 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4296
4297 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4298 PP_ASSERT_WITH_CODE((0 == tmp_result),
4299 "Failed to populate and upload SCLK MCLK DPM levels!",
4300 result = tmp_result);
4301
4302 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4303 PP_ASSERT_WITH_CODE((0 == tmp_result),
4304 "Failed to generate DPM level enabled mask!",
4305 result = tmp_result);
4306
4307 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4308 PP_ASSERT_WITH_CODE((0 == tmp_result),
4309 "Failed to update VCE DPM!",
4310 result = tmp_result);
4311
4312 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4313 PP_ASSERT_WITH_CODE((0 == tmp_result),
4314 "Failed to update SCLK threshold!",
4315 result = tmp_result);
4316
4317 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4318 PP_ASSERT_WITH_CODE((0 == tmp_result),
4319 "Failed to program memory timing parameters!",
4320 result = tmp_result);
4321
4322 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4323 PP_ASSERT_WITH_CODE((0 == tmp_result),
4324 "Failed to unfreeze SCLK MCLK DPM!",
4325 result = tmp_result);
4326
4327 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4328 PP_ASSERT_WITH_CODE((0 == tmp_result),
4329 "Failed to upload DPM level enabled mask!",
4330 result = tmp_result);
4331
4332 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4333 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4334 tmp_result =
4335 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4336 PP_ASSERT_WITH_CODE((0 == tmp_result),
4337 "Failed to notify link speed change after state change!",
4338 result = tmp_result);
4339 }
4340 data->apply_optimized_settings = false;
4341 return result;
4342 }
4343
4344 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4345 {
4346 hwmgr->thermal_controller.
4347 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4348
4349 if (phm_is_hw_access_blocked(hwmgr))
4350 return 0;
4351
4352 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4353 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4354 }
4355
4356 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4357 {
4358 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4359
4360 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4361 }
4362
4363 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4364 {
4365 uint32_t num_active_displays = 0;
4366 struct cgs_display_info info = {0};
4367 info.mode_info = NULL;
4368
4369 cgs_get_active_displays_info(hwmgr->device, &info);
4370
4371 num_active_displays = info.display_count;
4372
4373 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4374 polaris10_notify_smc_display_change(hwmgr, false);
4375 else
4376 polaris10_notify_smc_display_change(hwmgr, true);
4377
4378 return 0;
4379 }
4380
4381 /**
4382 * Programs the display gap
4383 *
4384 * @param hwmgr the address of the powerplay hardware manager.
4385 * @return always OK
4386 */
4387 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4388 {
4389 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4390 uint32_t num_active_displays = 0;
4391 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4392 uint32_t display_gap2;
4393 uint32_t pre_vbi_time_in_us;
4394 uint32_t frame_time_in_us;
4395 uint32_t ref_clock;
4396 uint32_t refresh_rate = 0;
4397 struct cgs_display_info info = {0};
4398 struct cgs_mode_info mode_info;
4399
4400 info.mode_info = &mode_info;
4401
4402 cgs_get_active_displays_info(hwmgr->device, &info);
4403 num_active_displays = info.display_count;
4404
4405 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4407
4408 ref_clock = mode_info.ref_clock;
4409 refresh_rate = mode_info.refresh_rate;
4410
4411 if (0 == refresh_rate)
4412 refresh_rate = 60;
4413
4414 frame_time_in_us = 1000000 / refresh_rate;
4415
4416 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4417 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4418
4419 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4420
4421 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4422
4423 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4424
4425 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4426
4427 return 0;
4428 }
4429
4430
4431 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4432 {
4433 return polaris10_program_display_gap(hwmgr);
4434 }
4435
4436 /**
4437 * Set maximum target operating fan output RPM
4438 *
4439 * @param hwmgr: the address of the powerplay hardware manager.
4440 * @param usMaxFanRpm: max operating fan RPM value.
4441 * @return The response that came from the SMC.
4442 */
4443 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4444 {
4445 hwmgr->thermal_controller.
4446 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4447
4448 if (phm_is_hw_access_blocked(hwmgr))
4449 return 0;
4450
4451 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4452 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4453 }
4454
4455 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4456 const void *thermal_interrupt_info)
4457 {
4458 return 0;
4459 }
4460
4461 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4462 {
4463 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4464 bool is_update_required = false;
4465 struct cgs_display_info info = {0, 0, NULL};
4466
4467 cgs_get_active_displays_info(hwmgr->device, &info);
4468
4469 if (data->display_timing.num_existing_displays != info.display_count)
4470 is_update_required = true;
4471 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4472 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4473 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4474 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4475 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4476 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4477 is_update_required = true;
4478 */
4479 return is_update_required;
4480 }
4481
4482 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4483 const struct polaris10_performance_level *pl2)
4484 {
4485 return ((pl1->memory_clock == pl2->memory_clock) &&
4486 (pl1->engine_clock == pl2->engine_clock) &&
4487 (pl1->pcie_gen == pl2->pcie_gen) &&
4488 (pl1->pcie_lane == pl2->pcie_lane));
4489 }
4490
4491 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4492 {
4493 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4494 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4495 int i;
4496
4497 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4498 return -EINVAL;
4499
4500 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4501 if (psa->performance_level_count != psb->performance_level_count) {
4502 *equal = false;
4503 return 0;
4504 }
4505
4506 for (i = 0; i < psa->performance_level_count; i++) {
4507 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4508 /* If we have found even one performance level pair that is different the states are different. */
4509 *equal = false;
4510 return 0;
4511 }
4512 }
4513
4514 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4515 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4516 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4517 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4518
4519 return 0;
4520 }
4521
4522 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4523 {
4524 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4525
4526 uint32_t vbios_version;
4527
4528 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4529
4530 phm_get_mc_microcode_version(hwmgr);
4531 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4532 /* Full version of MC ucode has already been loaded. */
4533 if (vbios_version == 0) {
4534 data->need_long_memory_training = false;
4535 return 0;
4536 }
4537
4538 data->need_long_memory_training = true;
4539
4540 /*
4541 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4542 pfd = &tonga_mcmeFirmware;
4543 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4544 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4545 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4546 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4547 */
4548 return 0;
4549 }
4550
4551 /**
4552 * Read clock related registers.
4553 *
4554 * @param hwmgr the address of the powerplay hardware manager.
4555 * @return always 0
4556 */
4557 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4558 {
4559 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4560
4561 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4562 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4563 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4564
4565 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4566 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4567 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4568
4569 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4570 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4571 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4572
4573 return 0;
4574 }
4575
4576 /**
4577 * Find out if memory is GDDR5.
4578 *
4579 * @param hwmgr the address of the powerplay hardware manager.
4580 * @return always 0
4581 */
4582 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4583 {
4584 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4585 uint32_t temp;
4586
4587 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4588
4589 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4590 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4591 MC_SEQ_MISC0_GDDR5_SHIFT));
4592
4593 return 0;
4594 }
4595
4596 /**
4597 * Enables Dynamic Power Management by SMC
4598 *
4599 * @param hwmgr the address of the powerplay hardware manager.
4600 * @return always 0
4601 */
4602 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4603 {
4604 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4605 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4606
4607 return 0;
4608 }
4609
4610 /**
4611 * Initialize PowerGating States for different engines
4612 *
4613 * @param hwmgr the address of the powerplay hardware manager.
4614 * @return always 0
4615 */
4616 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4617 {
4618 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4619
4620 data->uvd_power_gated = false;
4621 data->vce_power_gated = false;
4622 data->samu_power_gated = false;
4623
4624 return 0;
4625 }
4626
4627 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4628 {
4629 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4630 data->low_sclk_interrupt_threshold = 0;
4631
4632 return 0;
4633 }
4634
4635 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4636 {
4637 int tmp_result, result = 0;
4638
4639 polaris10_upload_mc_firmware(hwmgr);
4640
4641 tmp_result = polaris10_read_clock_registers(hwmgr);
4642 PP_ASSERT_WITH_CODE((0 == tmp_result),
4643 "Failed to read clock registers!", result = tmp_result);
4644
4645 tmp_result = polaris10_get_memory_type(hwmgr);
4646 PP_ASSERT_WITH_CODE((0 == tmp_result),
4647 "Failed to get memory type!", result = tmp_result);
4648
4649 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4650 PP_ASSERT_WITH_CODE((0 == tmp_result),
4651 "Failed to enable ACPI power management!", result = tmp_result);
4652
4653 tmp_result = polaris10_init_power_gate_state(hwmgr);
4654 PP_ASSERT_WITH_CODE((0 == tmp_result),
4655 "Failed to init power gate state!", result = tmp_result);
4656
4657 tmp_result = phm_get_mc_microcode_version(hwmgr);
4658 PP_ASSERT_WITH_CODE((0 == tmp_result),
4659 "Failed to get MC microcode version!", result = tmp_result);
4660
4661 tmp_result = polaris10_init_sclk_threshold(hwmgr);
4662 PP_ASSERT_WITH_CODE((0 == tmp_result),
4663 "Failed to init sclk threshold!", result = tmp_result);
4664
4665 return result;
4666 }
4667
4668 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4669 {
4670 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4671
4672 *table = (char *)&data->smc_state_table;
4673
4674 return sizeof(struct SMU74_Discrete_DpmTable);
4675 }
4676
4677 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4678 {
4679 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4680
4681 void *table = (void *)&data->smc_state_table;
4682
4683 memcpy(table, buf, size);
4684
4685 return 0;
4686 }
4687
4688 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4689 enum pp_clock_type type, int level)
4690 {
4691 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4692
4693 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4694 return -EINVAL;
4695
4696 switch (type) {
4697 case PP_SCLK:
4698 if (!data->sclk_dpm_key_disabled)
4699 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4700 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4701 (1 << level));
4702 break;
4703 case PP_MCLK:
4704 if (!data->mclk_dpm_key_disabled)
4705 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4706 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4707 (1 << level));
4708 break;
4709 case PP_PCIE:
4710 if (!data->pcie_dpm_key_disabled)
4711 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4712 PPSMC_MSG_PCIeDPM_ForceLevel,
4713 (1 << level));
4714 break;
4715 default:
4716 break;
4717 }
4718
4719 return 0;
4720 }
4721
4722 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4723 {
4724 uint32_t speedCntl = 0;
4725
4726 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4727 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4728 ixPCIE_LC_SPEED_CNTL);
4729 return((uint16_t)PHM_GET_FIELD(speedCntl,
4730 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4731 }
4732
4733 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4734 enum pp_clock_type type, char *buf)
4735 {
4736 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4737 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4738 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4739 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4740 int i, now, size = 0;
4741 uint32_t clock, pcie_speed;
4742
4743 switch (type) {
4744 case PP_SCLK:
4745 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4746 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4747
4748 for (i = 0; i < sclk_table->count; i++) {
4749 if (clock > sclk_table->dpm_levels[i].value)
4750 continue;
4751 break;
4752 }
4753 now = i;
4754
4755 for (i = 0; i < sclk_table->count; i++)
4756 size += sprintf(buf + size, "%d: %uMhz %s\n",
4757 i, sclk_table->dpm_levels[i].value / 100,
4758 (i == now) ? "*" : "");
4759 break;
4760 case PP_MCLK:
4761 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4762 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4763
4764 for (i = 0; i < mclk_table->count; i++) {
4765 if (clock > mclk_table->dpm_levels[i].value)
4766 continue;
4767 break;
4768 }
4769 now = i;
4770
4771 for (i = 0; i < mclk_table->count; i++)
4772 size += sprintf(buf + size, "%d: %uMhz %s\n",
4773 i, mclk_table->dpm_levels[i].value / 100,
4774 (i == now) ? "*" : "");
4775 break;
4776 case PP_PCIE:
4777 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4778 for (i = 0; i < pcie_table->count; i++) {
4779 if (pcie_speed != pcie_table->dpm_levels[i].value)
4780 continue;
4781 break;
4782 }
4783 now = i;
4784
4785 for (i = 0; i < pcie_table->count; i++)
4786 size += sprintf(buf + size, "%d: %s %s\n", i,
4787 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4788 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4789 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4790 (i == now) ? "*" : "");
4791 break;
4792 default:
4793 break;
4794 }
4795 return size;
4796 }
4797
4798 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4799 .backend_init = &polaris10_hwmgr_backend_init,
4800 .backend_fini = &polaris10_hwmgr_backend_fini,
4801 .asic_setup = &polaris10_setup_asic_task,
4802 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4803 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4804 .force_dpm_level = &polaris10_force_dpm_level,
4805 .power_state_set = polaris10_set_power_state_tasks,
4806 .get_power_state_size = polaris10_get_power_state_size,
4807 .get_mclk = polaris10_dpm_get_mclk,
4808 .get_sclk = polaris10_dpm_get_sclk,
4809 .patch_boot_state = polaris10_dpm_patch_boot_state,
4810 .get_pp_table_entry = polaris10_get_pp_table_entry,
4811 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4812 .print_current_perforce_level = polaris10_print_current_perforce_level,
4813 .powerdown_uvd = polaris10_phm_powerdown_uvd,
4814 .powergate_uvd = polaris10_phm_powergate_uvd,
4815 .powergate_vce = polaris10_phm_powergate_vce,
4816 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4817 .update_clock_gatings = polaris10_phm_update_clock_gatings,
4818 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4819 .display_config_changed = polaris10_display_configuration_changed_task,
4820 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4821 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4822 .get_temperature = polaris10_thermal_get_temperature,
4823 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4824 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4825 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4826 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4827 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4828 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4829 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4830 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4831 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4832 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4833 .check_states_equal = polaris10_check_states_equal,
4834 .get_pp_table = polaris10_get_pp_table,
4835 .set_pp_table = polaris10_set_pp_table,
4836 .force_clock_level = polaris10_force_clock_level,
4837 .print_clock_levels = polaris10_print_clock_levels,
4838 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4839 };
4840
4841 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4842 {
4843 struct polaris10_hwmgr *data;
4844
4845 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
4846 if (data == NULL)
4847 return -ENOMEM;
4848
4849 hwmgr->backend = data;
4850 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
4851 hwmgr->pptable_func = &tonga_pptable_funcs;
4852 pp_polaris10_thermal_initialize(hwmgr);
4853
4854 return 0;
4855 }
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