drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef POLARIS10_POWERTUNE_H
  24 #define POLARIS10_POWERTUNE_H
  25
  26 enum polaris10_pt_config_reg_type {
  27         POLARIS10_CONFIGREG_MMR = 0,
  28         POLARIS10_CONFIGREG_SMC_IND,
  29         POLARIS10_CONFIGREG_DIDT_IND,
  30         POLARIS10_CONFIGREG_CACHE,
  31         POLARIS10_CONFIGREG_MAX
  32 };
  33
  34 /* PowerContainment Features */
  35 #define POWERCONTAINMENT_FEATURE_DTE             0x00000001
  36 #define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
  37 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
  38
  39 struct polaris10_pt_config_reg {
  40         uint32_t                           offset;
  41         uint32_t                           mask;
  42         uint32_t                           shift;
  43         uint32_t                           value;
  44         enum polaris10_pt_config_reg_type       type;
  45 };
  46
  47 struct polaris10_pt_defaults {
  48         uint8_t   SviLoadLineEn;
  49         uint8_t   SviLoadLineVddC;
  50         uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
  51         uint8_t   TDC_MAWt;
  52         uint8_t   TdcWaterfallCtl;
  53         uint8_t   DTEAmbientTempBase;
  54
  55         uint32_t  DisplayCac;
  56         uint32_t  BAPM_TEMP_GRADIENT;
  57         uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
  58         uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
  59 };
  60
  61 void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
  62 int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
  63 int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
  64 int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr);
  65 int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr);
  66 int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
  67 int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);
  68
  69 #endif  /* POLARIS10_POWERTUNE_H */
  70