drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef PP_ATOMFWCTRL_H
  25 #define PP_ATOMFWCTRL_H
  26
  27 #include "hwmgr.h"
  28
  29 typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
  30
  31 #define GetIndexIntoMasterCmdTable(FieldName) \
  32         (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
  33 #define GetIndexIntoMasterDataTable(FieldName) \
  34         (((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
  35
  36 #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
  37
  38 struct pp_atomfwctrl_voltage_table_entry {
  39         uint16_t value;
  40         uint32_t  smio_low;
  41 };
  42
  43 struct pp_atomfwctrl_voltage_table {
  44         uint32_t count;
  45         uint32_t mask_low;
  46         uint32_t phase_delay;
  47         uint8_t psi0_enable;
  48         uint8_t psi1_enable;
  49         uint8_t max_vid_step;
  50         uint8_t telemetry_offset;
  51         uint8_t telemetry_slope;
  52         struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
  53 };
  54
  55 struct pp_atomfwctrl_gpio_pin_assignment {
  56         uint16_t us_gpio_pin_aindex;
  57         uint8_t uc_gpio_pin_bit_shift;
  58 };
  59
  60 struct pp_atomfwctrl_clock_dividers_soc15 {
  61         uint32_t   ulClock;           /* the actual clock */
  62         uint32_t   ulDid;             /* DFS divider */
  63         uint32_t   ulPll_fb_mult;     /* Feedback Multiplier:  bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
  64         uint32_t   ulPll_ss_fbsmult;  /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
  65         uint16_t   usPll_ss_slew_frac;
  66         uint8_t    ucPll_ss_enable;
  67         uint8_t    ucReserve;
  68         uint32_t   ulReserve[2];
  69 };
  70
  71 struct pp_atomfwctrl_avfs_parameters {
  72         uint32_t   ulMaxVddc;
  73         uint32_t   ulMinVddc;
  74
  75         uint32_t   ulMeanNsigmaAcontant0;
  76         uint32_t   ulMeanNsigmaAcontant1;
  77         uint32_t   ulMeanNsigmaAcontant2;
  78         uint16_t   usMeanNsigmaDcTolSigma;
  79         uint16_t   usMeanNsigmaPlatformMean;
  80         uint16_t   usMeanNsigmaPlatformSigma;
  81         uint32_t   ulGbVdroopTableCksoffA0;
  82         uint32_t   ulGbVdroopTableCksoffA1;
  83         uint32_t   ulGbVdroopTableCksoffA2;
  84         uint32_t   ulGbVdroopTableCksonA0;
  85         uint32_t   ulGbVdroopTableCksonA1;
  86         uint32_t   ulGbVdroopTableCksonA2;
  87
  88         uint32_t   ulGbFuseTableCksoffM1;
  89         uint32_t   ulGbFuseTableCksoffM2;
  90         uint32_t   ulGbFuseTableCksoffB;
  91
  92         uint32_t   ulGbFuseTableCksonM1;
  93         uint32_t   ulGbFuseTableCksonM2;
  94         uint32_t   ulGbFuseTableCksonB;
  95
  96         uint8_t    ucEnableGbVdroopTableCkson;
  97         uint8_t    ucEnableGbFuseTableCkson;
  98         uint16_t   usPsmAgeComfactor;
  99
 100         uint32_t   ulDispclk2GfxclkM1;
 101         uint32_t   ulDispclk2GfxclkM2;
 102         uint32_t   ulDispclk2GfxclkB;
 103         uint32_t   ulDcefclk2GfxclkM1;
 104         uint32_t   ulDcefclk2GfxclkM2;
 105         uint32_t   ulDcefclk2GfxclkB;
 106         uint32_t   ulPixelclk2GfxclkM1;
 107         uint32_t   ulPixelclk2GfxclkM2;
 108         uint32_t   ulPixelclk2GfxclkB;
 109         uint32_t   ulPhyclk2GfxclkM1;
 110         uint32_t   ulPhyclk2GfxclkM2;
 111         uint32_t   ulPhyclk2GfxclkB;
 112         uint32_t   ulAcgGbVdroopTableA0;
 113         uint32_t   ulAcgGbVdroopTableA1;
 114         uint32_t   ulAcgGbVdroopTableA2;
 115         uint32_t   ulAcgGbFuseTableM1;
 116         uint32_t   ulAcgGbFuseTableM2;
 117         uint32_t   ulAcgGbFuseTableB;
 118         uint32_t   ucAcgEnableGbVdroopTable;
 119         uint32_t   ucAcgEnableGbFuseTable;
 120 };
 121
 122 struct pp_atomfwctrl_gpio_parameters {
 123         uint8_t   ucAcDcGpio;
 124         uint8_t   ucAcDcPolarity;
 125         uint8_t   ucVR0HotGpio;
 126         uint8_t   ucVR0HotPolarity;
 127         uint8_t   ucVR1HotGpio;
 128         uint8_t   ucVR1HotPolarity;
 129         uint8_t   ucFwCtfGpio;
 130         uint8_t   ucFwCtfPolarity;
 131 };
 132
 133 struct pp_atomfwctrl_bios_boot_up_values {
 134         uint32_t   ulRevision;
 135         uint32_t   ulGfxClk;
 136         uint32_t   ulUClk;
 137         uint32_t   ulSocClk;
 138         uint32_t   ulDCEFClk;
 139         uint32_t   ulEClk;
 140         uint32_t   ulVClk;
 141         uint32_t   ulDClk;
 142         uint16_t   usVddc;
 143         uint16_t   usVddci;
 144         uint16_t   usMvddc;
 145         uint16_t   usVddGfx;
 146         uint8_t    ucCoolingID;
 147 };
 148
 149 struct pp_atomfwctrl_smc_dpm_parameters
 150 {
 151   uint8_t  liquid1_i2c_address;
 152   uint8_t  liquid2_i2c_address;
 153   uint8_t  vr_i2c_address;
 154   uint8_t  plx_i2c_address;
 155   uint8_t  liquid_i2c_linescl;
 156   uint8_t  liquid_i2c_linesda;
 157   uint8_t  vr_i2c_linescl;
 158   uint8_t  vr_i2c_linesda;
 159   uint8_t  plx_i2c_linescl;
 160   uint8_t  plx_i2c_linesda;
 161   uint8_t  vrsensorpresent;
 162   uint8_t  liquidsensorpresent;
 163   uint16_t maxvoltagestepgfx;
 164   uint16_t maxvoltagestepsoc;
 165   uint8_t  vddgfxvrmapping;
 166   uint8_t  vddsocvrmapping;
 167   uint8_t  vddmem0vrmapping;
 168   uint8_t  vddmem1vrmapping;
 169   uint8_t  gfxulvphasesheddingmask;
 170   uint8_t  soculvphasesheddingmask;
 171
 172   uint16_t gfxmaxcurrent;
 173   uint8_t  gfxoffset;
 174   uint8_t  padding_telemetrygfx;
 175   uint16_t socmaxcurrent;
 176   uint8_t  socoffset;
 177   uint8_t  padding_telemetrysoc;
 178   uint16_t mem0maxcurrent;
 179   uint8_t  mem0offset;
 180   uint8_t  padding_telemetrymem0;
 181   uint16_t mem1maxcurrent;
 182   uint8_t  mem1offset;
 183   uint8_t  padding_telemetrymem1;
 184
 185   uint8_t  acdcgpio;
 186   uint8_t  acdcpolarity;
 187   uint8_t  vr0hotgpio;
 188   uint8_t  vr0hotpolarity;
 189   uint8_t  vr1hotgpio;
 190   uint8_t  vr1hotpolarity;
 191   uint8_t  padding1;
 192   uint8_t  padding2;
 193
 194   uint8_t  ledpin0;
 195   uint8_t  ledpin1;
 196   uint8_t  ledpin2;
 197
 198         uint8_t  pllgfxclkspreadenabled;
 199         uint8_t  pllgfxclkspreadpercent;
 200         uint16_t pllgfxclkspreadfreq;
 201
 202   uint8_t  uclkspreadenabled;
 203   uint8_t  uclkspreadpercent;
 204   uint16_t uclkspreadfreq;
 205
 206   uint8_t socclkspreadenabled;
 207   uint8_t socclkspreadpercent;
 208   uint16_t socclkspreadfreq;
 209
 210         uint8_t  acggfxclkspreadenabled;
 211         uint8_t  acggfxclkspreadpercent;
 212         uint16_t acggfxclkspreadfreq;
 213
 214         uint8_t Vr2_I2C_address;
 215 };
 216
 217 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
 218                 uint32_t clock_type, uint32_t clock_value,
 219                 struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
 220 int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
 221 bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
 222                 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
 223
 224 int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 225                 uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
 226 bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
 227                 uint8_t voltage_type, uint8_t voltage_mode);
 228
 229 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 230                 struct pp_atomfwctrl_avfs_parameters *param);
 231 int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
 232                 struct pp_atomfwctrl_gpio_parameters *param);
 233
 234 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 235                         struct pp_atomfwctrl_bios_boot_up_values *boot_values);
 236 int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
 237                         struct pp_atomfwctrl_smc_dpm_parameters *param);
 238 int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
 239                                         uint8_t id, uint32_t *frequency);
 240
 241 #endif
 242