2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <asm/div64.h>
30 #include "ppatomctrl.h"
32 #include "pptable_v1_0.h"
33 #include "pppcielanes.h"
34 #include "amd_pcie_helpers.h"
35 #include "hardwaremanager.h"
36 #include "process_pptables_v1_0.h"
37 #include "cgs_common.h"
39 #include "smu7_common.h"
42 #include "smu7_hwmgr.h"
43 #include "smu7_smumgr.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu7_powertune.h"
46 #include "smu7_dyn_defaults.h"
47 #include "smu7_thermal.h"
48 #include "smu7_clockpowergating.h"
49 #include "processpptables.h"
51 #define MC_CG_ARB_FREQ_F0 0x0a
52 #define MC_CG_ARB_FREQ_F1 0x0b
53 #define MC_CG_ARB_FREQ_F2 0x0c
54 #define MC_CG_ARB_FREQ_F3 0x0d
56 #define MC_CG_SEQ_DRAMCONF_S0 0x05
57 #define MC_CG_SEQ_DRAMCONF_S1 0x06
58 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
59 #define MC_CG_SEQ_YCLK_RESUME 0x0a
61 #define SMC_CG_IND_START 0xc0030000
62 #define SMC_CG_IND_END 0xc0040000
64 #define VOLTAGE_SCALE 4
65 #define VOLTAGE_VID_OFFSET_SCALE1 625
66 #define VOLTAGE_VID_OFFSET_SCALE2 100
68 #define MEM_FREQ_LOW_LATENCY 25000
69 #define MEM_FREQ_HIGH_LATENCY 80000
71 #define MEM_LATENCY_HIGH 45
72 #define MEM_LATENCY_LOW 35
73 #define MEM_LATENCY_ERR 0xFFFF
75 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
76 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
77 #define MC_SEQ_MISC0_GDDR5_VALUE 5
79 #define PCIE_BUS_CLK 10000
80 #define TCLK (PCIE_BUS_CLK / 10)
83 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
85 DPM_EVENT_SRC_ANALOG
= 0,
86 DPM_EVENT_SRC_EXTERNAL
= 1,
87 DPM_EVENT_SRC_DIGITAL
= 2,
88 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
89 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
= 4
92 static int smu7_avfs_control(struct pp_hwmgr
*hwmgr
, bool enable
);
93 static const unsigned long PhwVIslands_Magic
= (unsigned long)(PHM_VIslands_Magic
);
94 static int smu7_force_clock_level(struct pp_hwmgr
*hwmgr
,
95 enum pp_clock_type type
, uint32_t mask
);
97 static struct smu7_power_state
*cast_phw_smu7_power_state(
98 struct pp_hw_power_state
*hw_ps
)
100 PP_ASSERT_WITH_CODE((PhwVIslands_Magic
== hw_ps
->magic
),
101 "Invalid Powerstate Type!",
104 return (struct smu7_power_state
*)hw_ps
;
107 static const struct smu7_power_state
*cast_const_phw_smu7_power_state(
108 const struct pp_hw_power_state
*hw_ps
)
110 PP_ASSERT_WITH_CODE((PhwVIslands_Magic
== hw_ps
->magic
),
111 "Invalid Powerstate Type!",
114 return (const struct smu7_power_state
*)hw_ps
;
118 * Find the MC microcode version and store it in the HwMgr struct
120 * @param hwmgr the address of the powerplay hardware manager.
123 static int smu7_get_mc_microcode_version(struct pp_hwmgr
*hwmgr
)
125 cgs_write_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_INDEX
, 0x9F);
127 hwmgr
->microcode_version_info
.MC
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_DATA
);
132 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
134 uint32_t speedCntl
= 0;
136 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
137 speedCntl
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__PCIE
,
138 ixPCIE_LC_SPEED_CNTL
);
139 return((uint16_t)PHM_GET_FIELD(speedCntl
,
140 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
143 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr
*hwmgr
)
147 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
148 link_width
= PHM_READ_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
149 PCIE_LC_LINK_WIDTH_CNTL
, LC_LINK_WIDTH_RD
);
151 PP_ASSERT_WITH_CODE((7 >= link_width
),
152 "Invalid PCIe lane width!", return 0);
154 return decode_pcie_lane_width(link_width
);
158 * Enable voltage control
160 * @param pHwMgr the address of the powerplay hardware manager.
161 * @return always PP_Result_OK
163 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr
*hwmgr
)
165 if (hwmgr
->feature_mask
& PP_SMC_VOLTAGE_CONTROL_MASK
)
166 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_Voltage_Cntl_Enable
);
172 * Checks if we want to support voltage control
174 * @param hwmgr the address of the powerplay hardware manager.
176 static bool smu7_voltage_control(const struct pp_hwmgr
*hwmgr
)
178 const struct smu7_hwmgr
*data
=
179 (const struct smu7_hwmgr
*)(hwmgr
->backend
);
181 return (SMU7_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
);
185 * Enable voltage control
187 * @param hwmgr the address of the powerplay hardware manager.
190 static int smu7_enable_voltage_control(struct pp_hwmgr
*hwmgr
)
192 /* enable voltage control */
193 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
194 GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, 1);
199 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table
*voltage_table
,
200 struct phm_clock_voltage_dependency_table
*voltage_dependency_table
205 PP_ASSERT_WITH_CODE((NULL
!= voltage_table
),
206 "Voltage Dependency Table empty.", return -EINVAL
;);
208 voltage_table
->mask_low
= 0;
209 voltage_table
->phase_delay
= 0;
210 voltage_table
->count
= voltage_dependency_table
->count
;
212 for (i
= 0; i
< voltage_dependency_table
->count
; i
++) {
213 voltage_table
->entries
[i
].value
=
214 voltage_dependency_table
->entries
[i
].v
;
215 voltage_table
->entries
[i
].smio_low
= 0;
223 * Create Voltage Tables.
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int smu7_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
230 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
231 struct phm_ppt_v1_information
*table_info
=
232 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
236 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
237 result
= atomctrl_get_voltage_table_v3(hwmgr
,
238 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
,
239 &(data
->mvdd_voltage_table
));
240 PP_ASSERT_WITH_CODE((0 == result
),
241 "Failed to retrieve MVDD table.",
243 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
244 if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
245 result
= phm_get_svi2_mvdd_voltage_table(&(data
->mvdd_voltage_table
),
246 table_info
->vdd_dep_on_mclk
);
247 else if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
248 result
= phm_get_svi2_voltage_table_v0(&(data
->mvdd_voltage_table
),
249 hwmgr
->dyn_state
.mvdd_dependency_on_mclk
);
251 PP_ASSERT_WITH_CODE((0 == result
),
252 "Failed to retrieve SVI2 MVDD table from dependancy table.",
256 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
257 result
= atomctrl_get_voltage_table_v3(hwmgr
,
258 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
,
259 &(data
->vddci_voltage_table
));
260 PP_ASSERT_WITH_CODE((0 == result
),
261 "Failed to retrieve VDDCI table.",
263 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
264 if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
265 result
= phm_get_svi2_vddci_voltage_table(&(data
->vddci_voltage_table
),
266 table_info
->vdd_dep_on_mclk
);
267 else if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
268 result
= phm_get_svi2_voltage_table_v0(&(data
->vddci_voltage_table
),
269 hwmgr
->dyn_state
.vddci_dependency_on_mclk
);
270 PP_ASSERT_WITH_CODE((0 == result
),
271 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
275 if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->vdd_gfx_control
) {
276 /* VDDGFX has only SVI2 voltage control */
277 result
= phm_get_svi2_vdd_voltage_table(&(data
->vddgfx_voltage_table
),
278 table_info
->vddgfx_lookup_table
);
279 PP_ASSERT_WITH_CODE((0 == result
),
280 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result
;);
284 if (SMU7_VOLTAGE_CONTROL_BY_GPIO
== data
->voltage_control
) {
285 result
= atomctrl_get_voltage_table_v3(hwmgr
,
286 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_GPIO_LUT
,
287 &data
->vddc_voltage_table
);
288 PP_ASSERT_WITH_CODE((0 == result
),
289 "Failed to retrieve VDDC table.", return result
;);
290 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
292 if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
293 result
= phm_get_svi2_voltage_table_v0(&data
->vddc_voltage_table
,
294 hwmgr
->dyn_state
.vddc_dependency_on_mclk
);
295 else if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
296 result
= phm_get_svi2_vdd_voltage_table(&(data
->vddc_voltage_table
),
297 table_info
->vddc_lookup_table
);
299 PP_ASSERT_WITH_CODE((0 == result
),
300 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result
;);
303 tmp
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_VDDC
);
305 (data
->vddc_voltage_table
.count
<= tmp
),
306 "Too many voltage values for VDDC. Trimming to fit state table.",
307 phm_trim_voltage_table_to_fit_state_table(tmp
,
308 &(data
->vddc_voltage_table
)));
310 tmp
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_VDDGFX
);
312 (data
->vddgfx_voltage_table
.count
<= tmp
),
313 "Too many voltage values for VDDC. Trimming to fit state table.",
314 phm_trim_voltage_table_to_fit_state_table(tmp
,
315 &(data
->vddgfx_voltage_table
)));
317 tmp
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_VDDCI
);
319 (data
->vddci_voltage_table
.count
<= tmp
),
320 "Too many voltage values for VDDCI. Trimming to fit state table.",
321 phm_trim_voltage_table_to_fit_state_table(tmp
,
322 &(data
->vddci_voltage_table
)));
324 tmp
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_MVDD
);
326 (data
->mvdd_voltage_table
.count
<= tmp
),
327 "Too many voltage values for MVDD. Trimming to fit state table.",
328 phm_trim_voltage_table_to_fit_state_table(tmp
,
329 &(data
->mvdd_voltage_table
)));
335 * Programs static screed detection parameters
337 * @param hwmgr the address of the powerplay hardware manager.
340 static int smu7_program_static_screen_threshold_parameters(
341 struct pp_hwmgr
*hwmgr
)
343 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
345 /* Set static screen threshold unit */
346 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
347 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD_UNIT
,
348 data
->static_screen_threshold_unit
);
349 /* Set static screen threshold */
350 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
351 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD
,
352 data
->static_screen_threshold
);
358 * Setup display gap for glitch free memory clock switching.
360 * @param hwmgr the address of the powerplay hardware manager.
363 static int smu7_enable_display_gap(struct pp_hwmgr
*hwmgr
)
365 uint32_t display_gap
=
366 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
367 ixCG_DISPLAY_GAP_CNTL
);
369 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
,
370 DISP_GAP
, DISPLAY_GAP_IGNORE
);
372 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
,
373 DISP_GAP_MCHG
, DISPLAY_GAP_VBLANK
);
375 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
376 ixCG_DISPLAY_GAP_CNTL
, display_gap
);
382 * Programs activity state transition voting clients
384 * @param hwmgr the address of the powerplay hardware manager.
387 static int smu7_program_voting_clients(struct pp_hwmgr
*hwmgr
)
389 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
391 /* Clear reset for voting clients before enabling DPM */
392 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
393 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 0);
394 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
395 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 0);
397 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
398 ixCG_FREQ_TRAN_VOTING_0
, data
->voting_rights_clients0
);
399 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
400 ixCG_FREQ_TRAN_VOTING_1
, data
->voting_rights_clients1
);
401 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
402 ixCG_FREQ_TRAN_VOTING_2
, data
->voting_rights_clients2
);
403 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
404 ixCG_FREQ_TRAN_VOTING_3
, data
->voting_rights_clients3
);
405 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
406 ixCG_FREQ_TRAN_VOTING_4
, data
->voting_rights_clients4
);
407 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
408 ixCG_FREQ_TRAN_VOTING_5
, data
->voting_rights_clients5
);
409 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
410 ixCG_FREQ_TRAN_VOTING_6
, data
->voting_rights_clients6
);
411 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
412 ixCG_FREQ_TRAN_VOTING_7
, data
->voting_rights_clients7
);
417 static int smu7_clear_voting_clients(struct pp_hwmgr
*hwmgr
)
419 /* Reset voting clients before disabling DPM */
420 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
421 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 1);
422 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
423 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 1);
425 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
426 ixCG_FREQ_TRAN_VOTING_0
, 0);
427 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
428 ixCG_FREQ_TRAN_VOTING_1
, 0);
429 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
430 ixCG_FREQ_TRAN_VOTING_2
, 0);
431 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
432 ixCG_FREQ_TRAN_VOTING_3
, 0);
433 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
434 ixCG_FREQ_TRAN_VOTING_4
, 0);
435 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
436 ixCG_FREQ_TRAN_VOTING_5
, 0);
437 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
438 ixCG_FREQ_TRAN_VOTING_6
, 0);
439 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
440 ixCG_FREQ_TRAN_VOTING_7
, 0);
445 /* Copy one arb setting to another and then switch the active set.
446 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
448 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr
*hwmgr
,
449 uint32_t arb_src
, uint32_t arb_dest
)
451 uint32_t mc_arb_dram_timing
;
452 uint32_t mc_arb_dram_timing2
;
454 uint32_t mc_cg_config
;
457 case MC_CG_ARB_FREQ_F0
:
458 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
459 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
460 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
462 case MC_CG_ARB_FREQ_F1
:
463 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
);
464 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
);
465 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
);
472 case MC_CG_ARB_FREQ_F0
:
473 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
474 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
475 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
, burst_time
);
477 case MC_CG_ARB_FREQ_F1
:
478 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
479 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
480 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
, burst_time
);
486 mc_cg_config
= cgs_read_register(hwmgr
->device
, mmMC_CG_CONFIG
);
487 mc_cg_config
|= 0x0000000F;
488 cgs_write_register(hwmgr
->device
, mmMC_CG_CONFIG
, mc_cg_config
);
489 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_CG
, CG_ARB_REQ
, arb_dest
);
494 static int smu7_reset_to_default(struct pp_hwmgr
*hwmgr
)
496 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_ResetToDefaults
);
500 * Initial switch from ARB F0->F1
502 * @param hwmgr the address of the powerplay hardware manager.
504 * This function is to be called from the SetPowerState table.
506 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr
*hwmgr
)
508 return smu7_copy_and_switch_arb_sets(hwmgr
,
509 MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
512 static int smu7_force_switch_to_arbf0(struct pp_hwmgr
*hwmgr
)
516 tmp
= (cgs_read_ind_register(hwmgr
->device
,
517 CGS_IND_REG__SMC
, ixSMC_SCRATCH9
) &
520 if (tmp
== MC_CG_ARB_FREQ_F0
)
523 return smu7_copy_and_switch_arb_sets(hwmgr
,
524 tmp
, MC_CG_ARB_FREQ_F0
);
527 static int smu7_setup_default_pcie_table(struct pp_hwmgr
*hwmgr
)
529 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
531 struct phm_ppt_v1_information
*table_info
=
532 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
533 struct phm_ppt_v1_pcie_table
*pcie_table
= NULL
;
535 uint32_t i
, max_entry
;
538 PP_ASSERT_WITH_CODE((data
->use_pcie_performance_levels
||
539 data
->use_pcie_power_saving_levels
), "No pcie performance levels!",
542 if (table_info
!= NULL
)
543 pcie_table
= table_info
->pcie_table
;
545 if (data
->use_pcie_performance_levels
&&
546 !data
->use_pcie_power_saving_levels
) {
547 data
->pcie_gen_power_saving
= data
->pcie_gen_performance
;
548 data
->pcie_lane_power_saving
= data
->pcie_lane_performance
;
549 } else if (!data
->use_pcie_performance_levels
&&
550 data
->use_pcie_power_saving_levels
) {
551 data
->pcie_gen_performance
= data
->pcie_gen_power_saving
;
552 data
->pcie_lane_performance
= data
->pcie_lane_power_saving
;
554 tmp
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_LINK
);
555 phm_reset_single_dpm_table(&data
->dpm_table
.pcie_speed_table
,
557 MAX_REGULAR_DPM_NUMBER
);
559 if (pcie_table
!= NULL
) {
560 /* max_entry is used to make sure we reserve one PCIE level
561 * for boot level (fix for A+A PSPP issue).
562 * If PCIE table from PPTable have ULV entry + 8 entries,
563 * then ignore the last entry.*/
564 max_entry
= (tmp
< pcie_table
->count
) ? tmp
: pcie_table
->count
;
565 for (i
= 1; i
< max_entry
; i
++) {
566 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, i
- 1,
567 get_pcie_gen_support(data
->pcie_gen_cap
,
568 pcie_table
->entries
[i
].gen_speed
),
569 get_pcie_lane_support(data
->pcie_lane_cap
,
570 pcie_table
->entries
[i
].lane_width
));
572 data
->dpm_table
.pcie_speed_table
.count
= max_entry
- 1;
573 smum_update_smc_table(hwmgr
, SMU_BIF_TABLE
);
575 /* Hardcode Pcie Table */
576 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 0,
577 get_pcie_gen_support(data
->pcie_gen_cap
,
579 get_pcie_lane_support(data
->pcie_lane_cap
,
581 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 1,
582 get_pcie_gen_support(data
->pcie_gen_cap
,
584 get_pcie_lane_support(data
->pcie_lane_cap
,
586 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 2,
587 get_pcie_gen_support(data
->pcie_gen_cap
,
589 get_pcie_lane_support(data
->pcie_lane_cap
,
591 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 3,
592 get_pcie_gen_support(data
->pcie_gen_cap
,
594 get_pcie_lane_support(data
->pcie_lane_cap
,
596 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 4,
597 get_pcie_gen_support(data
->pcie_gen_cap
,
599 get_pcie_lane_support(data
->pcie_lane_cap
,
601 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 5,
602 get_pcie_gen_support(data
->pcie_gen_cap
,
604 get_pcie_lane_support(data
->pcie_lane_cap
,
607 data
->dpm_table
.pcie_speed_table
.count
= 6;
609 /* Populate last level for boot PCIE level, but do not increment count. */
610 phm_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
,
611 data
->dpm_table
.pcie_speed_table
.count
,
612 get_pcie_gen_support(data
->pcie_gen_cap
,
614 get_pcie_lane_support(data
->pcie_lane_cap
,
620 static int smu7_reset_dpm_tables(struct pp_hwmgr
*hwmgr
)
622 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
624 memset(&(data
->dpm_table
), 0x00, sizeof(data
->dpm_table
));
626 phm_reset_single_dpm_table(
627 &data
->dpm_table
.sclk_table
,
628 smum_get_mac_definition(hwmgr
->smumgr
,
629 SMU_MAX_LEVELS_GRAPHICS
),
630 MAX_REGULAR_DPM_NUMBER
);
631 phm_reset_single_dpm_table(
632 &data
->dpm_table
.mclk_table
,
633 smum_get_mac_definition(hwmgr
->smumgr
,
634 SMU_MAX_LEVELS_MEMORY
), MAX_REGULAR_DPM_NUMBER
);
636 phm_reset_single_dpm_table(
637 &data
->dpm_table
.vddc_table
,
638 smum_get_mac_definition(hwmgr
->smumgr
,
639 SMU_MAX_LEVELS_VDDC
),
640 MAX_REGULAR_DPM_NUMBER
);
641 phm_reset_single_dpm_table(
642 &data
->dpm_table
.vddci_table
,
643 smum_get_mac_definition(hwmgr
->smumgr
,
644 SMU_MAX_LEVELS_VDDCI
), MAX_REGULAR_DPM_NUMBER
);
646 phm_reset_single_dpm_table(
647 &data
->dpm_table
.mvdd_table
,
648 smum_get_mac_definition(hwmgr
->smumgr
,
649 SMU_MAX_LEVELS_MVDD
),
650 MAX_REGULAR_DPM_NUMBER
);
654 * This function is to initialize all DPM state tables
655 * for SMU7 based on the dependency table.
656 * Dynamic state patching function will then trim these
657 * state tables to the allowed range based
658 * on the power policy or external client requests,
659 * such as UVD request, etc.
662 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr
*hwmgr
)
664 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
665 struct phm_clock_voltage_dependency_table
*allowed_vdd_sclk_table
=
666 hwmgr
->dyn_state
.vddc_dependency_on_sclk
;
667 struct phm_clock_voltage_dependency_table
*allowed_vdd_mclk_table
=
668 hwmgr
->dyn_state
.vddc_dependency_on_mclk
;
669 struct phm_cac_leakage_table
*std_voltage_table
=
670 hwmgr
->dyn_state
.cac_leakage_table
;
673 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table
!= NULL
,
674 "SCLK dependency table is missing. This table is mandatory", return -EINVAL
);
675 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table
->count
>= 1,
676 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL
);
678 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
!= NULL
,
679 "MCLK dependency table is missing. This table is mandatory", return -EINVAL
);
680 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
->count
>= 1,
681 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL
);
684 /* Initialize Sclk DPM table based on allow Sclk values*/
685 data
->dpm_table
.sclk_table
.count
= 0;
687 for (i
= 0; i
< allowed_vdd_sclk_table
->count
; i
++) {
688 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
-1].value
!=
689 allowed_vdd_sclk_table
->entries
[i
].clk
) {
690 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].value
=
691 allowed_vdd_sclk_table
->entries
[i
].clk
;
692 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].enabled
= 1; /*(i==0) ? 1 : 0; to do */
693 data
->dpm_table
.sclk_table
.count
++;
697 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
!= NULL
,
698 "MCLK dependency table is missing. This table is mandatory", return -EINVAL
);
699 /* Initialize Mclk DPM table based on allow Mclk values */
700 data
->dpm_table
.mclk_table
.count
= 0;
701 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
702 if (i
== 0 || data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
-1].value
!=
703 allowed_vdd_mclk_table
->entries
[i
].clk
) {
704 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].value
=
705 allowed_vdd_mclk_table
->entries
[i
].clk
;
706 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].enabled
= 1; /*(i==0) ? 1 : 0; */
707 data
->dpm_table
.mclk_table
.count
++;
711 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
712 for (i
= 0; i
< allowed_vdd_sclk_table
->count
; i
++) {
713 data
->dpm_table
.vddc_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
714 data
->dpm_table
.vddc_table
.dpm_levels
[i
].param1
= std_voltage_table
->entries
[i
].Leakage
;
715 /* param1 is for corresponding std voltage */
716 data
->dpm_table
.vddc_table
.dpm_levels
[i
].enabled
= 1;
719 data
->dpm_table
.vddc_table
.count
= allowed_vdd_sclk_table
->count
;
720 allowed_vdd_mclk_table
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
722 if (NULL
!= allowed_vdd_mclk_table
) {
723 /* Initialize Vddci DPM table based on allow Mclk values */
724 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
725 data
->dpm_table
.vddci_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
726 data
->dpm_table
.vddci_table
.dpm_levels
[i
].enabled
= 1;
728 data
->dpm_table
.vddci_table
.count
= allowed_vdd_mclk_table
->count
;
731 allowed_vdd_mclk_table
= hwmgr
->dyn_state
.mvdd_dependency_on_mclk
;
733 if (NULL
!= allowed_vdd_mclk_table
) {
735 * Initialize MVDD DPM table based on allow Mclk
738 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
739 data
->dpm_table
.mvdd_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
740 data
->dpm_table
.mvdd_table
.dpm_levels
[i
].enabled
= 1;
742 data
->dpm_table
.mvdd_table
.count
= allowed_vdd_mclk_table
->count
;
748 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr
*hwmgr
)
750 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
751 struct phm_ppt_v1_information
*table_info
=
752 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
755 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_sclk_table
;
756 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
;
758 if (table_info
== NULL
)
761 dep_sclk_table
= table_info
->vdd_dep_on_sclk
;
762 dep_mclk_table
= table_info
->vdd_dep_on_mclk
;
764 PP_ASSERT_WITH_CODE(dep_sclk_table
!= NULL
,
765 "SCLK dependency table is missing.",
767 PP_ASSERT_WITH_CODE(dep_sclk_table
->count
>= 1,
768 "SCLK dependency table count is 0.",
771 PP_ASSERT_WITH_CODE(dep_mclk_table
!= NULL
,
772 "MCLK dependency table is missing.",
774 PP_ASSERT_WITH_CODE(dep_mclk_table
->count
>= 1,
775 "MCLK dependency table count is 0",
778 /* Initialize Sclk DPM table based on allow Sclk values */
779 data
->dpm_table
.sclk_table
.count
= 0;
780 for (i
= 0; i
< dep_sclk_table
->count
; i
++) {
781 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
- 1].value
!=
782 dep_sclk_table
->entries
[i
].clk
) {
784 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].value
=
785 dep_sclk_table
->entries
[i
].clk
;
787 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].enabled
=
788 (i
== 0) ? true : false;
789 data
->dpm_table
.sclk_table
.count
++;
793 /* Initialize Mclk DPM table based on allow Mclk values */
794 data
->dpm_table
.mclk_table
.count
= 0;
795 for (i
= 0; i
< dep_mclk_table
->count
; i
++) {
796 if (i
== 0 || data
->dpm_table
.mclk_table
.dpm_levels
797 [data
->dpm_table
.mclk_table
.count
- 1].value
!=
798 dep_mclk_table
->entries
[i
].clk
) {
799 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].value
=
800 dep_mclk_table
->entries
[i
].clk
;
801 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].enabled
=
802 (i
== 0) ? true : false;
803 data
->dpm_table
.mclk_table
.count
++;
810 static int smu7_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
812 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
814 smu7_reset_dpm_tables(hwmgr
);
816 if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
817 smu7_setup_dpm_tables_v1(hwmgr
);
818 else if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
819 smu7_setup_dpm_tables_v0(hwmgr
);
821 smu7_setup_default_pcie_table(hwmgr
);
823 /* save a copy of the default DPM table */
824 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
),
825 sizeof(struct smu7_dpm_table
));
829 uint32_t smu7_get_xclk(struct pp_hwmgr
*hwmgr
)
831 uint32_t reference_clock
, tmp
;
832 struct cgs_display_info info
= {0};
833 struct cgs_mode_info mode_info
;
835 info
.mode_info
= &mode_info
;
837 tmp
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
);
842 cgs_get_active_displays_info(hwmgr
->device
, &info
);
843 reference_clock
= mode_info
.ref_clock
;
845 tmp
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
);
848 return reference_clock
/ 4;
850 return reference_clock
;
853 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr
*hwmgr
)
856 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
857 PHM_PlatformCaps_RegulatorHot
))
858 return smum_send_msg_to_smc(hwmgr
->smumgr
,
859 PPSMC_MSG_EnableVRHotGPIOInterrupt
);
864 static int smu7_enable_sclk_control(struct pp_hwmgr
*hwmgr
)
866 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
871 static int smu7_enable_ulv(struct pp_hwmgr
*hwmgr
)
873 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
875 if (data
->ulv_supported
)
876 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_EnableULV
);
881 static int smu7_disable_ulv(struct pp_hwmgr
*hwmgr
)
883 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
885 if (data
->ulv_supported
)
886 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DisableULV
);
891 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
893 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
894 PHM_PlatformCaps_SclkDeepSleep
)) {
895 if (smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_MASTER_DeepSleep_ON
))
896 PP_ASSERT_WITH_CODE(false,
897 "Attempt to enable Master Deep Sleep switch failed!",
900 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
901 PPSMC_MSG_MASTER_DeepSleep_OFF
)) {
902 PP_ASSERT_WITH_CODE(false,
903 "Attempt to disable Master Deep Sleep switch failed!",
911 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
913 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
914 PHM_PlatformCaps_SclkDeepSleep
)) {
915 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
916 PPSMC_MSG_MASTER_DeepSleep_OFF
)) {
917 PP_ASSERT_WITH_CODE(false,
918 "Attempt to disable Master Deep Sleep switch failed!",
926 static int smu7_disable_handshake_uvd(struct pp_hwmgr
*hwmgr
)
928 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
929 uint32_t soft_register_value
= 0;
930 uint32_t handshake_disables_offset
= data
->soft_regs_start
931 + smum_get_offsetof(hwmgr
->smumgr
,
932 SMU_SoftRegisters
, HandshakeDisables
);
934 soft_register_value
= cgs_read_ind_register(hwmgr
->device
,
935 CGS_IND_REG__SMC
, handshake_disables_offset
);
936 soft_register_value
|= smum_get_mac_definition(hwmgr
->smumgr
,
937 SMU_UVD_MCLK_HANDSHAKE_DISABLE
);
938 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
939 handshake_disables_offset
, soft_register_value
);
943 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
945 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
947 /* enable SCLK dpm */
948 if (!data
->sclk_dpm_key_disabled
)
950 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DPM_Enable
)),
951 "Failed to enable SCLK DPM during DPM Start Function!",
954 /* enable MCLK dpm */
955 if (0 == data
->mclk_dpm_key_disabled
) {
956 if (!(hwmgr
->feature_mask
& PP_UVD_HANDSHAKE_MASK
))
957 smu7_disable_handshake_uvd(hwmgr
);
959 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
960 PPSMC_MSG_MCLKDPM_Enable
)),
961 "Failed to enable MCLK DPM during DPM Start Function!",
964 PHM_WRITE_FIELD(hwmgr
->device
, MC_SEQ_CNTL_3
, CAC_EN
, 0x1);
966 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC0_CNTL
, 0x5);
967 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC1_CNTL
, 0x5);
968 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_CPL_CNTL
, 0x100005);
970 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC0_CNTL
, 0x400005);
971 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_MC1_CNTL
, 0x400005);
972 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixLCAC_CPL_CNTL
, 0x500005);
978 static int smu7_start_dpm(struct pp_hwmgr
*hwmgr
)
980 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
982 /*enable general power management */
984 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
985 GLOBAL_PWRMGT_EN
, 1);
987 /* enable sclk deep sleep */
989 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
992 /* prepare for PCIE DPM */
994 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
995 data
->soft_regs_start
+
996 smum_get_offsetof(hwmgr
->smumgr
, SMU_SoftRegisters
,
997 VoltageChangeTimeout
), 0x1000);
998 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
999 SWRST_COMMAND_1
, RESETLC
, 0x0);
1001 if (smu7_enable_sclk_mclk_dpm(hwmgr
)) {
1002 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1006 /* enable PCIE dpm */
1007 if (0 == data
->pcie_dpm_key_disabled
) {
1008 PP_ASSERT_WITH_CODE(
1009 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
1010 PPSMC_MSG_PCIeDPM_Enable
)),
1011 "Failed to enable pcie DPM during DPM Start Function!",
1015 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1016 PHM_PlatformCaps_Falcon_QuickTransition
)) {
1017 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
1018 PPSMC_MSG_EnableACDCGPIOInterrupt
)),
1019 "Failed to enable AC DC GPIO Interrupt!",
1026 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
1028 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1030 /* disable SCLK dpm */
1031 if (!data
->sclk_dpm_key_disabled
) {
1032 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
1033 "Trying to disable SCLK DPM when DPM is disabled",
1035 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DPM_Disable
);
1038 /* disable MCLK dpm */
1039 if (!data
->mclk_dpm_key_disabled
) {
1040 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
1041 "Trying to disable MCLK DPM when DPM is disabled",
1043 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_MCLKDPM_Disable
);
1049 static int smu7_stop_dpm(struct pp_hwmgr
*hwmgr
)
1051 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1053 /* disable general power management */
1054 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
1055 GLOBAL_PWRMGT_EN
, 0);
1056 /* disable sclk deep sleep */
1057 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
1060 /* disable PCIE dpm */
1061 if (!data
->pcie_dpm_key_disabled
) {
1062 PP_ASSERT_WITH_CODE(
1063 (smum_send_msg_to_smc(hwmgr
->smumgr
,
1064 PPSMC_MSG_PCIeDPM_Disable
) == 0),
1065 "Failed to disable pcie DPM during DPM Stop Function!",
1069 smu7_disable_sclk_mclk_dpm(hwmgr
);
1071 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
1072 "Trying to disable voltage DPM when DPM is disabled",
1075 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_Voltage_Cntl_Disable
);
1080 static void smu7_set_dpm_event_sources(struct pp_hwmgr
*hwmgr
, uint32_t sources
)
1083 enum DPM_EVENT_SRC src
;
1087 pr_err("Unknown throttling event sources.");
1093 case (1 << PHM_AutoThrottleSource_Thermal
):
1095 src
= DPM_EVENT_SRC_DIGITAL
;
1097 case (1 << PHM_AutoThrottleSource_External
):
1099 src
= DPM_EVENT_SRC_EXTERNAL
;
1101 case (1 << PHM_AutoThrottleSource_External
) |
1102 (1 << PHM_AutoThrottleSource_Thermal
):
1104 src
= DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
;
1107 /* Order matters - don't enable thermal protection for the wrong source. */
1109 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_THERMAL_CTRL
,
1110 DPM_EVENT_SRC
, src
);
1111 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
1112 THERMAL_PROTECTION_DIS
,
1113 !phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1114 PHM_PlatformCaps_ThermalController
));
1116 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
1117 THERMAL_PROTECTION_DIS
, 1);
1120 static int smu7_enable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
1121 PHM_AutoThrottleSource source
)
1123 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1125 if (!(data
->active_auto_throttle_sources
& (1 << source
))) {
1126 data
->active_auto_throttle_sources
|= 1 << source
;
1127 smu7_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
1132 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
1134 return smu7_enable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
1137 static int smu7_disable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
1138 PHM_AutoThrottleSource source
)
1140 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1142 if (data
->active_auto_throttle_sources
& (1 << source
)) {
1143 data
->active_auto_throttle_sources
&= ~(1 << source
);
1144 smu7_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
1149 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
1151 return smu7_disable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
1154 static int smu7_pcie_performance_request(struct pp_hwmgr
*hwmgr
)
1156 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1157 data
->pcie_performance_request
= true;
1162 static int smu7_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
1167 tmp_result
= (!smum_is_dpm_running(hwmgr
)) ? 0 : -1;
1168 PP_ASSERT_WITH_CODE(tmp_result
== 0,
1169 "DPM is already running",
1172 if (smu7_voltage_control(hwmgr
)) {
1173 tmp_result
= smu7_enable_voltage_control(hwmgr
);
1174 PP_ASSERT_WITH_CODE(tmp_result
== 0,
1175 "Failed to enable voltage control!",
1176 result
= tmp_result
);
1178 tmp_result
= smu7_construct_voltage_tables(hwmgr
);
1179 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1180 "Failed to contruct voltage tables!",
1181 result
= tmp_result
);
1183 smum_initialize_mc_reg_table(hwmgr
);
1185 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1186 PHM_PlatformCaps_EngineSpreadSpectrumSupport
))
1187 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1188 GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, 1);
1190 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1191 PHM_PlatformCaps_ThermalController
))
1192 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1193 GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, 0);
1195 tmp_result
= smu7_program_static_screen_threshold_parameters(hwmgr
);
1196 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1197 "Failed to program static screen threshold parameters!",
1198 result
= tmp_result
);
1200 tmp_result
= smu7_enable_display_gap(hwmgr
);
1201 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1202 "Failed to enable display gap!", result
= tmp_result
);
1204 tmp_result
= smu7_program_voting_clients(hwmgr
);
1205 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1206 "Failed to program voting clients!", result
= tmp_result
);
1208 tmp_result
= smum_process_firmware_header(hwmgr
);
1209 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1210 "Failed to process firmware header!", result
= tmp_result
);
1212 tmp_result
= smu7_initial_switch_from_arbf0_to_f1(hwmgr
);
1213 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1214 "Failed to initialize switch from ArbF0 to F1!",
1215 result
= tmp_result
);
1217 result
= smu7_setup_default_dpm_tables(hwmgr
);
1218 PP_ASSERT_WITH_CODE(0 == result
,
1219 "Failed to setup default DPM tables!", return result
);
1221 tmp_result
= smum_init_smc_table(hwmgr
);
1222 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1223 "Failed to initialize SMC table!", result
= tmp_result
);
1225 tmp_result
= smu7_enable_vrhot_gpio_interrupt(hwmgr
);
1226 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1227 "Failed to enable VR hot GPIO interrupt!", result
= tmp_result
);
1229 smum_send_msg_to_smc(hwmgr
->smumgr
, (PPSMC_Msg
)PPSMC_NoDisplay
);
1231 tmp_result
= smu7_enable_sclk_control(hwmgr
);
1232 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1233 "Failed to enable SCLK control!", result
= tmp_result
);
1235 tmp_result
= smu7_enable_smc_voltage_controller(hwmgr
);
1236 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1237 "Failed to enable voltage control!", result
= tmp_result
);
1239 tmp_result
= smu7_enable_ulv(hwmgr
);
1240 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1241 "Failed to enable ULV!", result
= tmp_result
);
1243 tmp_result
= smu7_enable_deep_sleep_master_switch(hwmgr
);
1244 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1245 "Failed to enable deep sleep master switch!", result
= tmp_result
);
1247 tmp_result
= smu7_enable_didt_config(hwmgr
);
1248 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1249 "Failed to enable deep sleep master switch!", result
= tmp_result
);
1251 tmp_result
= smu7_start_dpm(hwmgr
);
1252 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1253 "Failed to start DPM!", result
= tmp_result
);
1255 tmp_result
= smu7_enable_smc_cac(hwmgr
);
1256 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1257 "Failed to enable SMC CAC!", result
= tmp_result
);
1259 tmp_result
= smu7_enable_power_containment(hwmgr
);
1260 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1261 "Failed to enable power containment!", result
= tmp_result
);
1263 tmp_result
= smu7_power_control_set_level(hwmgr
);
1264 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1265 "Failed to power control set level!", result
= tmp_result
);
1267 tmp_result
= smu7_enable_thermal_auto_throttle(hwmgr
);
1268 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1269 "Failed to enable thermal auto throttle!", result
= tmp_result
);
1271 tmp_result
= smu7_pcie_performance_request(hwmgr
);
1272 PP_ASSERT_WITH_CODE((0 == tmp_result
),
1273 "pcie performance request failed!", result
= tmp_result
);
1278 int smu7_disable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
1280 int tmp_result
, result
= 0;
1282 tmp_result
= (smum_is_dpm_running(hwmgr
)) ? 0 : -1;
1283 PP_ASSERT_WITH_CODE(tmp_result
== 0,
1284 "DPM is not running right now, no need to disable DPM!",
1287 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1288 PHM_PlatformCaps_ThermalController
))
1289 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1290 GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, 1);
1292 tmp_result
= smu7_disable_power_containment(hwmgr
);
1293 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1294 "Failed to disable power containment!", result
= tmp_result
);
1296 tmp_result
= smu7_disable_smc_cac(hwmgr
);
1297 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1298 "Failed to disable SMC CAC!", result
= tmp_result
);
1300 tmp_result
= smu7_disable_didt_config(hwmgr
);
1301 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1302 "Failed to disable DIDT!", result
= tmp_result
);
1304 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1305 CG_SPLL_SPREAD_SPECTRUM
, SSEN
, 0);
1306 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1307 GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, 0);
1309 tmp_result
= smu7_disable_thermal_auto_throttle(hwmgr
);
1310 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1311 "Failed to disable thermal auto throttle!", result
= tmp_result
);
1313 tmp_result
= smu7_avfs_control(hwmgr
, false);
1314 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1315 "Failed to disable AVFS!", result
= tmp_result
);
1317 tmp_result
= smu7_stop_dpm(hwmgr
);
1318 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1319 "Failed to stop DPM!", result
= tmp_result
);
1321 tmp_result
= smu7_disable_deep_sleep_master_switch(hwmgr
);
1322 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1323 "Failed to disable deep sleep master switch!", result
= tmp_result
);
1325 tmp_result
= smu7_disable_ulv(hwmgr
);
1326 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1327 "Failed to disable ULV!", result
= tmp_result
);
1329 tmp_result
= smu7_clear_voting_clients(hwmgr
);
1330 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1331 "Failed to clear voting clients!", result
= tmp_result
);
1333 tmp_result
= smu7_reset_to_default(hwmgr
);
1334 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1335 "Failed to reset to default!", result
= tmp_result
);
1337 tmp_result
= smu7_force_switch_to_arbf0(hwmgr
);
1338 PP_ASSERT_WITH_CODE((tmp_result
== 0),
1339 "Failed to force to switch arbf0!", result
= tmp_result
);
1344 int smu7_reset_asic_tasks(struct pp_hwmgr
*hwmgr
)
1350 static void smu7_init_dpm_defaults(struct pp_hwmgr
*hwmgr
)
1352 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1353 struct phm_ppt_v1_information
*table_info
=
1354 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1355 struct cgs_system_info sys_info
= {0};
1358 data
->dll_default_on
= false;
1359 data
->mclk_dpm0_activity_target
= 0xa;
1360 data
->mclk_activity_target
= SMU7_MCLK_TARGETACTIVITY_DFLT
;
1361 data
->vddc_vddgfx_delta
= 300;
1362 data
->static_screen_threshold
= SMU7_STATICSCREENTHRESHOLD_DFLT
;
1363 data
->static_screen_threshold_unit
= SMU7_STATICSCREENTHRESHOLDUNIT_DFLT
;
1364 data
->voting_rights_clients0
= SMU7_VOTINGRIGHTSCLIENTS_DFLT0
;
1365 data
->voting_rights_clients1
= SMU7_VOTINGRIGHTSCLIENTS_DFLT1
;
1366 data
->voting_rights_clients2
= SMU7_VOTINGRIGHTSCLIENTS_DFLT2
;
1367 data
->voting_rights_clients3
= SMU7_VOTINGRIGHTSCLIENTS_DFLT3
;
1368 data
->voting_rights_clients4
= SMU7_VOTINGRIGHTSCLIENTS_DFLT4
;
1369 data
->voting_rights_clients5
= SMU7_VOTINGRIGHTSCLIENTS_DFLT5
;
1370 data
->voting_rights_clients6
= SMU7_VOTINGRIGHTSCLIENTS_DFLT6
;
1371 data
->voting_rights_clients7
= SMU7_VOTINGRIGHTSCLIENTS_DFLT7
;
1373 data
->mclk_dpm_key_disabled
= hwmgr
->feature_mask
& PP_MCLK_DPM_MASK
? false : true;
1374 data
->sclk_dpm_key_disabled
= hwmgr
->feature_mask
& PP_SCLK_DPM_MASK
? false : true;
1375 data
->pcie_dpm_key_disabled
= hwmgr
->feature_mask
& PP_PCIE_DPM_MASK
? false : true;
1376 /* need to set voltage control types before EVV patching */
1377 data
->voltage_control
= SMU7_VOLTAGE_CONTROL_NONE
;
1378 data
->vddci_control
= SMU7_VOLTAGE_CONTROL_NONE
;
1379 data
->mvdd_control
= SMU7_VOLTAGE_CONTROL_NONE
;
1380 data
->enable_tdc_limit_feature
= true;
1381 data
->enable_pkg_pwr_tracking_feature
= true;
1382 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
1383 data
->ulv_supported
= hwmgr
->feature_mask
& PP_ULV_MASK
? true : false;
1385 if (hwmgr
->chip_id
== CHIP_POLARIS12
|| hwmgr
->smumgr
->is_kicker
) {
1388 atomctrl_get_svi2_info(hwmgr
, VOLTAGE_TYPE_VDDC
, &tmp1
, &tmp2
,
1390 tmp3
= (tmp3
>> 5) & 0x3;
1391 data
->vddc_phase_shed_control
= ((tmp3
<< 1) | (tmp3
>> 1)) & 0x3;
1394 data
->fast_watermark_threshold
= 100;
1395 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1396 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
))
1397 data
->voltage_control
= SMU7_VOLTAGE_CONTROL_BY_SVID2
;
1399 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1400 PHM_PlatformCaps_ControlVDDGFX
)) {
1401 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1402 VOLTAGE_TYPE_VDDGFX
, VOLTAGE_OBJ_SVID2
)) {
1403 data
->vdd_gfx_control
= SMU7_VOLTAGE_CONTROL_BY_SVID2
;
1407 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1408 PHM_PlatformCaps_EnableMVDDControl
)) {
1409 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1410 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
))
1411 data
->mvdd_control
= SMU7_VOLTAGE_CONTROL_BY_GPIO
;
1412 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1413 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_SVID2
))
1414 data
->mvdd_control
= SMU7_VOLTAGE_CONTROL_BY_SVID2
;
1417 if (SMU7_VOLTAGE_CONTROL_NONE
== data
->vdd_gfx_control
) {
1418 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
1419 PHM_PlatformCaps_ControlVDDGFX
);
1422 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1423 PHM_PlatformCaps_ControlVDDCI
)) {
1424 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1425 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
1426 data
->vddci_control
= SMU7_VOLTAGE_CONTROL_BY_GPIO
;
1427 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
1428 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_SVID2
))
1429 data
->vddci_control
= SMU7_VOLTAGE_CONTROL_BY_SVID2
;
1432 if (data
->mvdd_control
== SMU7_VOLTAGE_CONTROL_NONE
)
1433 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
1434 PHM_PlatformCaps_EnableMVDDControl
);
1436 if (data
->vddci_control
== SMU7_VOLTAGE_CONTROL_NONE
)
1437 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
1438 PHM_PlatformCaps_ControlVDDCI
);
1440 if ((hwmgr
->pp_table_version
!= PP_TABLE_V0
) && (hwmgr
->feature_mask
& PP_CLOCK_STRETCH_MASK
)
1441 && (table_info
->cac_dtp_table
->usClockStretchAmount
!= 0))
1442 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
1443 PHM_PlatformCaps_ClockStretcher
);
1445 data
->pcie_gen_performance
.max
= PP_PCIEGen1
;
1446 data
->pcie_gen_performance
.min
= PP_PCIEGen3
;
1447 data
->pcie_gen_power_saving
.max
= PP_PCIEGen1
;
1448 data
->pcie_gen_power_saving
.min
= PP_PCIEGen3
;
1449 data
->pcie_lane_performance
.max
= 0;
1450 data
->pcie_lane_performance
.min
= 16;
1451 data
->pcie_lane_power_saving
.max
= 0;
1452 data
->pcie_lane_power_saving
.min
= 16;
1454 sys_info
.size
= sizeof(struct cgs_system_info
);
1455 sys_info
.info_id
= CGS_SYSTEM_INFO_PG_FLAGS
;
1456 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
1458 if (sys_info
.value
& AMD_PG_SUPPORT_UVD
)
1459 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
1460 PHM_PlatformCaps_UVDPowerGating
);
1461 if (sys_info
.value
& AMD_PG_SUPPORT_VCE
)
1462 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
1463 PHM_PlatformCaps_VCEPowerGating
);
1468 * Get Leakage VDDC based on leakage ID.
1470 * @param hwmgr the address of the powerplay hardware manager.
1473 static int smu7_get_evv_voltages(struct pp_hwmgr
*hwmgr
)
1475 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1478 uint16_t vddgfx
= 0;
1481 struct phm_ppt_v1_information
*table_info
=
1482 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
1483 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
= NULL
;
1486 for (i
= 0; i
< SMU7_MAX_LEAKAGE_COUNT
; i
++) {
1487 vv_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
1489 if (data
->vdd_gfx_control
== SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
1490 if ((hwmgr
->pp_table_version
== PP_TABLE_V1
)
1491 && !phm_get_sclk_for_voltage_evv(hwmgr
,
1492 table_info
->vddgfx_lookup_table
, vv_id
, &sclk
)) {
1493 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1494 PHM_PlatformCaps_ClockStretcher
)) {
1495 sclk_table
= table_info
->vdd_dep_on_sclk
;
1497 for (j
= 1; j
< sclk_table
->count
; j
++) {
1498 if (sclk_table
->entries
[j
].clk
== sclk
&&
1499 sclk_table
->entries
[j
].cks_enable
== 0) {
1505 if (0 == atomctrl_get_voltage_evv_on_sclk
1506 (hwmgr
, VOLTAGE_TYPE_VDDGFX
, sclk
,
1508 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1509 PP_ASSERT_WITH_CODE((vddgfx
< 2000 && vddgfx
!= 0), "Invalid VDDGFX value!", return -EINVAL
);
1511 /* the voltage should not be zero nor equal to leakage ID */
1512 if (vddgfx
!= 0 && vddgfx
!= vv_id
) {
1513 data
->vddcgfx_leakage
.actual_voltage
[data
->vddcgfx_leakage
.count
] = vddgfx
;
1514 data
->vddcgfx_leakage
.leakage_id
[data
->vddcgfx_leakage
.count
] = vv_id
;
1515 data
->vddcgfx_leakage
.count
++;
1518 pr_info("Error retrieving EVV voltage value!\n");
1522 if ((hwmgr
->pp_table_version
== PP_TABLE_V0
)
1523 || !phm_get_sclk_for_voltage_evv(hwmgr
,
1524 table_info
->vddc_lookup_table
, vv_id
, &sclk
)) {
1525 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1526 PHM_PlatformCaps_ClockStretcher
)) {
1527 if (table_info
== NULL
)
1529 sclk_table
= table_info
->vdd_dep_on_sclk
;
1531 for (j
= 1; j
< sclk_table
->count
; j
++) {
1532 if (sclk_table
->entries
[j
].clk
== sclk
&&
1533 sclk_table
->entries
[j
].cks_enable
== 0) {
1540 if (phm_get_voltage_evv_on_sclk(hwmgr
,
1542 sclk
, vv_id
, &vddc
) == 0) {
1543 if (vddc
>= 2000 || vddc
== 0)
1546 pr_warn("failed to retrieving EVV voltage!\n");
1550 /* the voltage should not be zero nor equal to leakage ID */
1551 if (vddc
!= 0 && vddc
!= vv_id
) {
1552 data
->vddc_leakage
.actual_voltage
[data
->vddc_leakage
.count
] = (uint16_t)(vddc
);
1553 data
->vddc_leakage
.leakage_id
[data
->vddc_leakage
.count
] = vv_id
;
1554 data
->vddc_leakage
.count
++;
1564 * Change virtual leakage voltage to actual value.
1566 * @param hwmgr the address of the powerplay hardware manager.
1567 * @param pointer to changing voltage
1568 * @param pointer to leakage table
1570 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
1571 uint16_t *voltage
, struct smu7_leakage_voltage
*leakage_table
)
1575 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1576 for (index
= 0; index
< leakage_table
->count
; index
++) {
1577 /* if this voltage matches a leakage voltage ID */
1578 /* patch with actual leakage voltage */
1579 if (leakage_table
->leakage_id
[index
] == *voltage
) {
1580 *voltage
= leakage_table
->actual_voltage
[index
];
1585 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
1586 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1590 * Patch voltage lookup table by EVV leakages.
1592 * @param hwmgr the address of the powerplay hardware manager.
1593 * @param pointer to voltage lookup table
1594 * @param pointer to leakage table
1597 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr
*hwmgr
,
1598 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
1599 struct smu7_leakage_voltage
*leakage_table
)
1603 for (i
= 0; i
< lookup_table
->count
; i
++)
1604 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr
,
1605 &lookup_table
->entries
[i
].us_vdd
, leakage_table
);
1610 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1611 struct pp_hwmgr
*hwmgr
, struct smu7_leakage_voltage
*leakage_table
,
1614 struct phm_ppt_v1_information
*table_info
=
1615 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1616 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr
, (uint16_t *)vddc
, leakage_table
);
1617 hwmgr
->dyn_state
.max_clock_voltage_on_dc
.vddc
=
1618 table_info
->max_clock_voltage_on_dc
.vddc
;
1622 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1623 struct pp_hwmgr
*hwmgr
)
1627 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1628 struct phm_ppt_v1_information
*table_info
=
1629 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1631 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
1632 table_info
->vdd_dep_on_sclk
;
1633 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
=
1634 table_info
->vdd_dep_on_mclk
;
1635 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
1636 table_info
->mm_dep_table
;
1638 if (data
->vdd_gfx_control
== SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
1639 for (entry_id
= 0; entry_id
< sclk_table
->count
; ++entry_id
) {
1640 voltage_id
= sclk_table
->entries
[entry_id
].vddInd
;
1641 sclk_table
->entries
[entry_id
].vddgfx
=
1642 table_info
->vddgfx_lookup_table
->entries
[voltage_id
].us_vdd
;
1645 for (entry_id
= 0; entry_id
< sclk_table
->count
; ++entry_id
) {
1646 voltage_id
= sclk_table
->entries
[entry_id
].vddInd
;
1647 sclk_table
->entries
[entry_id
].vddc
=
1648 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
1652 for (entry_id
= 0; entry_id
< mclk_table
->count
; ++entry_id
) {
1653 voltage_id
= mclk_table
->entries
[entry_id
].vddInd
;
1654 mclk_table
->entries
[entry_id
].vddc
=
1655 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
1658 for (entry_id
= 0; entry_id
< mm_table
->count
; ++entry_id
) {
1659 voltage_id
= mm_table
->entries
[entry_id
].vddcInd
;
1660 mm_table
->entries
[entry_id
].vddc
=
1661 table_info
->vddc_lookup_table
->entries
[voltage_id
].us_vdd
;
1668 static int phm_add_voltage(struct pp_hwmgr
*hwmgr
,
1669 phm_ppt_v1_voltage_lookup_table
*look_up_table
,
1670 phm_ppt_v1_voltage_lookup_record
*record
)
1674 PP_ASSERT_WITH_CODE((NULL
!= look_up_table
),
1675 "Lookup Table empty.", return -EINVAL
);
1676 PP_ASSERT_WITH_CODE((0 != look_up_table
->count
),
1677 "Lookup Table empty.", return -EINVAL
);
1679 i
= smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_VDDGFX
);
1680 PP_ASSERT_WITH_CODE((i
>= look_up_table
->count
),
1681 "Lookup Table is full.", return -EINVAL
);
1683 /* This is to avoid entering duplicate calculated records. */
1684 for (i
= 0; i
< look_up_table
->count
; i
++) {
1685 if (look_up_table
->entries
[i
].us_vdd
== record
->us_vdd
) {
1686 if (look_up_table
->entries
[i
].us_calculated
== 1)
1692 look_up_table
->entries
[i
].us_calculated
= 1;
1693 look_up_table
->entries
[i
].us_vdd
= record
->us_vdd
;
1694 look_up_table
->entries
[i
].us_cac_low
= record
->us_cac_low
;
1695 look_up_table
->entries
[i
].us_cac_mid
= record
->us_cac_mid
;
1696 look_up_table
->entries
[i
].us_cac_high
= record
->us_cac_high
;
1697 /* Only increment the count when we're appending, not replacing duplicate entry. */
1698 if (i
== look_up_table
->count
)
1699 look_up_table
->count
++;
1705 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr
*hwmgr
)
1708 struct phm_ppt_v1_voltage_lookup_record v_record
;
1709 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1710 struct phm_ppt_v1_information
*pptable_info
= (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1712 phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
= pptable_info
->vdd_dep_on_sclk
;
1713 phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
= pptable_info
->vdd_dep_on_mclk
;
1715 if (data
->vdd_gfx_control
== SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
1716 for (entry_id
= 0; entry_id
< sclk_table
->count
; ++entry_id
) {
1717 if (sclk_table
->entries
[entry_id
].vdd_offset
& (1 << 15))
1718 v_record
.us_vdd
= sclk_table
->entries
[entry_id
].vddgfx
+
1719 sclk_table
->entries
[entry_id
].vdd_offset
- 0xFFFF;
1721 v_record
.us_vdd
= sclk_table
->entries
[entry_id
].vddgfx
+
1722 sclk_table
->entries
[entry_id
].vdd_offset
;
1724 sclk_table
->entries
[entry_id
].vddc
=
1725 v_record
.us_cac_low
= v_record
.us_cac_mid
=
1726 v_record
.us_cac_high
= v_record
.us_vdd
;
1728 phm_add_voltage(hwmgr
, pptable_info
->vddc_lookup_table
, &v_record
);
1731 for (entry_id
= 0; entry_id
< mclk_table
->count
; ++entry_id
) {
1732 if (mclk_table
->entries
[entry_id
].vdd_offset
& (1 << 15))
1733 v_record
.us_vdd
= mclk_table
->entries
[entry_id
].vddc
+
1734 mclk_table
->entries
[entry_id
].vdd_offset
- 0xFFFF;
1736 v_record
.us_vdd
= mclk_table
->entries
[entry_id
].vddc
+
1737 mclk_table
->entries
[entry_id
].vdd_offset
;
1739 mclk_table
->entries
[entry_id
].vddgfx
= v_record
.us_cac_low
=
1740 v_record
.us_cac_mid
= v_record
.us_cac_high
= v_record
.us_vdd
;
1741 phm_add_voltage(hwmgr
, pptable_info
->vddgfx_lookup_table
, &v_record
);
1747 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr
*hwmgr
)
1750 struct phm_ppt_v1_voltage_lookup_record v_record
;
1751 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1752 struct phm_ppt_v1_information
*pptable_info
= (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1753 phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
= pptable_info
->mm_dep_table
;
1755 if (data
->vdd_gfx_control
== SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
1756 for (entry_id
= 0; entry_id
< mm_table
->count
; entry_id
++) {
1757 if (mm_table
->entries
[entry_id
].vddgfx_offset
& (1 << 15))
1758 v_record
.us_vdd
= mm_table
->entries
[entry_id
].vddc
+
1759 mm_table
->entries
[entry_id
].vddgfx_offset
- 0xFFFF;
1761 v_record
.us_vdd
= mm_table
->entries
[entry_id
].vddc
+
1762 mm_table
->entries
[entry_id
].vddgfx_offset
;
1764 /* Add the calculated VDDGFX to the VDDGFX lookup table */
1765 mm_table
->entries
[entry_id
].vddgfx
= v_record
.us_cac_low
=
1766 v_record
.us_cac_mid
= v_record
.us_cac_high
= v_record
.us_vdd
;
1767 phm_add_voltage(hwmgr
, pptable_info
->vddgfx_lookup_table
, &v_record
);
1773 static int smu7_sort_lookup_table(struct pp_hwmgr
*hwmgr
,
1774 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
)
1776 uint32_t table_size
, i
, j
;
1777 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record
;
1778 table_size
= lookup_table
->count
;
1780 PP_ASSERT_WITH_CODE(0 != lookup_table
->count
,
1781 "Lookup table is empty", return -EINVAL
);
1783 /* Sorting voltages */
1784 for (i
= 0; i
< table_size
- 1; i
++) {
1785 for (j
= i
+ 1; j
> 0; j
--) {
1786 if (lookup_table
->entries
[j
].us_vdd
<
1787 lookup_table
->entries
[j
- 1].us_vdd
) {
1788 tmp_voltage_lookup_record
= lookup_table
->entries
[j
- 1];
1789 lookup_table
->entries
[j
- 1] = lookup_table
->entries
[j
];
1790 lookup_table
->entries
[j
] = tmp_voltage_lookup_record
;
1798 static int smu7_complete_dependency_tables(struct pp_hwmgr
*hwmgr
)
1802 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
1803 struct phm_ppt_v1_information
*table_info
=
1804 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1806 if (data
->vdd_gfx_control
== SMU7_VOLTAGE_CONTROL_BY_SVID2
) {
1807 tmp_result
= smu7_patch_lookup_table_with_leakage(hwmgr
,
1808 table_info
->vddgfx_lookup_table
, &(data
->vddcgfx_leakage
));
1809 if (tmp_result
!= 0)
1810 result
= tmp_result
;
1812 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr
,
1813 &table_info
->max_clock_voltage_on_dc
.vddgfx
, &(data
->vddcgfx_leakage
));
1816 tmp_result
= smu7_patch_lookup_table_with_leakage(hwmgr
,
1817 table_info
->vddc_lookup_table
, &(data
->vddc_leakage
));
1819 result
= tmp_result
;
1821 tmp_result
= smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr
,
1822 &(data
->vddc_leakage
), &table_info
->max_clock_voltage_on_dc
.vddc
);
1824 result
= tmp_result
;
1827 tmp_result
= smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr
);
1829 result
= tmp_result
;
1831 tmp_result
= smu7_calc_voltage_dependency_tables(hwmgr
);
1833 result
= tmp_result
;
1835 tmp_result
= smu7_calc_mm_voltage_dependency_table(hwmgr
);
1837 result
= tmp_result
;
1839 tmp_result
= smu7_sort_lookup_table(hwmgr
, table_info
->vddgfx_lookup_table
);
1841 result
= tmp_result
;
1843 tmp_result
= smu7_sort_lookup_table(hwmgr
, table_info
->vddc_lookup_table
);
1845 result
= tmp_result
;
1850 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr
*hwmgr
)
1852 struct phm_ppt_v1_information
*table_info
=
1853 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1855 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_sclk_vdd_table
=
1856 table_info
->vdd_dep_on_sclk
;
1857 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_mclk_vdd_table
=
1858 table_info
->vdd_dep_on_mclk
;
1860 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
!= NULL
,
1861 "VDD dependency on SCLK table is missing.",
1863 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
->count
>= 1,
1864 "VDD dependency on SCLK table has to have is missing.",
1867 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
!= NULL
,
1868 "VDD dependency on MCLK table is missing",
1870 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
->count
>= 1,
1871 "VDD dependency on MCLK table has to have is missing.",
1874 table_info
->max_clock_voltage_on_ac
.sclk
=
1875 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].clk
;
1876 table_info
->max_clock_voltage_on_ac
.mclk
=
1877 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].clk
;
1878 table_info
->max_clock_voltage_on_ac
.vddc
=
1879 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
1880 table_info
->max_clock_voltage_on_ac
.vddci
=
1881 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].vddci
;
1883 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
= table_info
->max_clock_voltage_on_ac
.sclk
;
1884 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
= table_info
->max_clock_voltage_on_ac
.mclk
;
1885 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
= table_info
->max_clock_voltage_on_ac
.vddc
;
1886 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
= table_info
->max_clock_voltage_on_ac
.vddci
;
1891 static int smu7_patch_voltage_workaround(struct pp_hwmgr
*hwmgr
)
1893 struct phm_ppt_v1_information
*table_info
=
1894 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1895 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
;
1896 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
;
1898 uint32_t hw_revision
, sub_vendor_id
, sub_sys_id
;
1899 struct cgs_system_info sys_info
= {0};
1901 if (table_info
!= NULL
) {
1902 dep_mclk_table
= table_info
->vdd_dep_on_mclk
;
1903 lookup_table
= table_info
->vddc_lookup_table
;
1907 sys_info
.size
= sizeof(struct cgs_system_info
);
1909 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_REV
;
1910 cgs_query_system_info(hwmgr
->device
, &sys_info
);
1911 hw_revision
= (uint32_t)sys_info
.value
;
1913 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID
;
1914 cgs_query_system_info(hwmgr
->device
, &sys_info
);
1915 sub_sys_id
= (uint32_t)sys_info
.value
;
1917 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID
;
1918 cgs_query_system_info(hwmgr
->device
, &sys_info
);
1919 sub_vendor_id
= (uint32_t)sys_info
.value
;
1921 if (hwmgr
->chip_id
== CHIP_POLARIS10
&& hw_revision
== 0xC7 &&
1922 ((sub_sys_id
== 0xb37 && sub_vendor_id
== 0x1002) ||
1923 (sub_sys_id
== 0x4a8 && sub_vendor_id
== 0x1043) ||
1924 (sub_sys_id
== 0x9480 && sub_vendor_id
== 0x1682))) {
1925 if (lookup_table
->entries
[dep_mclk_table
->entries
[dep_mclk_table
->count
-1].vddInd
].us_vdd
>= 1000)
1928 for (i
= 0; i
< lookup_table
->count
; i
++) {
1929 if (lookup_table
->entries
[i
].us_vdd
< 0xff01 && lookup_table
->entries
[i
].us_vdd
>= 1000) {
1930 dep_mclk_table
->entries
[dep_mclk_table
->count
-1].vddInd
= (uint8_t) i
;
1938 static int smu7_thermal_parameter_init(struct pp_hwmgr
*hwmgr
)
1940 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment
;
1942 struct phm_ppt_v1_information
*table_info
=
1943 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1946 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_PCC_GPIO_PINID
, &gpio_pin_assignment
)) {
1947 temp_reg
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCNB_PWRMGT_CNTL
);
1948 switch (gpio_pin_assignment
.uc_gpio_pin_bit_shift
) {
1950 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x1);
1953 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x2);
1956 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, GNB_SLOW
, 0x1);
1959 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, FORCE_NB_PS1
, 0x1);
1962 temp_reg
= PHM_SET_FIELD(temp_reg
, CNB_PWRMGT_CNTL
, DPM_ENABLED
, 0x1);
1967 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCNB_PWRMGT_CNTL
, temp_reg
);
1970 if (table_info
== NULL
)
1973 if (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
!= 0 &&
1974 hwmgr
->thermal_controller
.advanceFanControlParameters
.ucFanControlMode
) {
1975 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMMinLimit
=
1976 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.ucMinimumPWMLimit
;
1978 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMMaxLimit
=
1979 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanPWM
;
1981 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanPWMStep
= 1;
1983 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMMaxLimit
= 100;
1985 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMMinLimit
=
1986 (uint16_t)hwmgr
->thermal_controller
.advanceFanControlParameters
.ucMinimumPWMLimit
;
1988 hwmgr
->thermal_controller
.advanceFanControlParameters
.usFanRPMStep
= 1;
1990 table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
= (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
>= 50) ?
1991 (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
- 50) : 0;
1993 table_info
->cac_dtp_table
->usOperatingTempMaxLimit
= table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
;
1994 table_info
->cac_dtp_table
->usOperatingTempStep
= 1;
1995 table_info
->cac_dtp_table
->usOperatingTempHyst
= 1;
1997 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanPWM
=
1998 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanPWM
;
2000 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanRPM
=
2001 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanRPM
;
2003 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMinLimit
=
2004 table_info
->cac_dtp_table
->usOperatingTempMinLimit
;
2006 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMaxLimit
=
2007 table_info
->cac_dtp_table
->usOperatingTempMaxLimit
;
2009 hwmgr
->dyn_state
.cac_dtp_table
->usDefaultTargetOperatingTemp
=
2010 table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
;
2012 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempStep
=
2013 table_info
->cac_dtp_table
->usOperatingTempStep
;
2015 hwmgr
->dyn_state
.cac_dtp_table
->usTargetOperatingTemp
=
2016 table_info
->cac_dtp_table
->usTargetOperatingTemp
;
2017 if (hwmgr
->feature_mask
& PP_OD_FUZZY_FAN_CONTROL_MASK
)
2018 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2019 PHM_PlatformCaps_ODFuzzyFanControlSupport
);
2026 * Change virtual leakage voltage to actual value.
2028 * @param hwmgr the address of the powerplay hardware manager.
2029 * @param pointer to changing voltage
2030 * @param pointer to leakage table
2032 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
2033 uint32_t *voltage
, struct smu7_leakage_voltage
*leakage_table
)
2037 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2038 for (index
= 0; index
< leakage_table
->count
; index
++) {
2039 /* if this voltage matches a leakage voltage ID */
2040 /* patch with actual leakage voltage */
2041 if (leakage_table
->leakage_id
[index
] == *voltage
) {
2042 *voltage
= leakage_table
->actual_voltage
[index
];
2047 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
2048 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2052 static int smu7_patch_vddc(struct pp_hwmgr
*hwmgr
,
2053 struct phm_clock_voltage_dependency_table
*tab
)
2056 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2059 for (i
= 0; i
< tab
->count
; i
++)
2060 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2061 &data
->vddc_leakage
);
2066 static int smu7_patch_vddci(struct pp_hwmgr
*hwmgr
,
2067 struct phm_clock_voltage_dependency_table
*tab
)
2070 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2073 for (i
= 0; i
< tab
->count
; i
++)
2074 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2075 &data
->vddci_leakage
);
2080 static int smu7_patch_vce_vddc(struct pp_hwmgr
*hwmgr
,
2081 struct phm_vce_clock_voltage_dependency_table
*tab
)
2084 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2087 for (i
= 0; i
< tab
->count
; i
++)
2088 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2089 &data
->vddc_leakage
);
2095 static int smu7_patch_uvd_vddc(struct pp_hwmgr
*hwmgr
,
2096 struct phm_uvd_clock_voltage_dependency_table
*tab
)
2099 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2102 for (i
= 0; i
< tab
->count
; i
++)
2103 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2104 &data
->vddc_leakage
);
2109 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr
*hwmgr
,
2110 struct phm_phase_shedding_limits_table
*tab
)
2113 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2116 for (i
= 0; i
< tab
->count
; i
++)
2117 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].Voltage
,
2118 &data
->vddc_leakage
);
2123 static int smu7_patch_samu_vddc(struct pp_hwmgr
*hwmgr
,
2124 struct phm_samu_clock_voltage_dependency_table
*tab
)
2127 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2130 for (i
= 0; i
< tab
->count
; i
++)
2131 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2132 &data
->vddc_leakage
);
2137 static int smu7_patch_acp_vddc(struct pp_hwmgr
*hwmgr
,
2138 struct phm_acp_clock_voltage_dependency_table
*tab
)
2141 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2144 for (i
= 0; i
< tab
->count
; i
++)
2145 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &tab
->entries
[i
].v
,
2146 &data
->vddc_leakage
);
2151 static int smu7_patch_limits_vddc(struct pp_hwmgr
*hwmgr
,
2152 struct phm_clock_and_voltage_limits
*tab
)
2154 uint32_t vddc
, vddci
;
2155 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2159 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &vddc
,
2160 &data
->vddc_leakage
);
2163 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &vddci
,
2164 &data
->vddci_leakage
);
2171 static int smu7_patch_cac_vddc(struct pp_hwmgr
*hwmgr
, struct phm_cac_leakage_table
*tab
)
2175 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2178 for (i
= 0; i
< tab
->count
; i
++) {
2179 vddc
= (uint32_t)(tab
->entries
[i
].Vddc
);
2180 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr
, &vddc
, &data
->vddc_leakage
);
2181 tab
->entries
[i
].Vddc
= (uint16_t)vddc
;
2188 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr
*hwmgr
)
2192 tmp
= smu7_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dependency_on_sclk
);
2196 tmp
= smu7_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dependency_on_mclk
);
2200 tmp
= smu7_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
);
2204 tmp
= smu7_patch_vddci(hwmgr
, hwmgr
->dyn_state
.vddci_dependency_on_mclk
);
2208 tmp
= smu7_patch_vce_vddc(hwmgr
, hwmgr
->dyn_state
.vce_clock_voltage_dependency_table
);
2212 tmp
= smu7_patch_uvd_vddc(hwmgr
, hwmgr
->dyn_state
.uvd_clock_voltage_dependency_table
);
2216 tmp
= smu7_patch_samu_vddc(hwmgr
, hwmgr
->dyn_state
.samu_clock_voltage_dependency_table
);
2220 tmp
= smu7_patch_acp_vddc(hwmgr
, hwmgr
->dyn_state
.acp_clock_voltage_dependency_table
);
2224 tmp
= smu7_patch_vddc_shed_limit(hwmgr
, hwmgr
->dyn_state
.vddc_phase_shed_limits_table
);
2228 tmp
= smu7_patch_limits_vddc(hwmgr
, &hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
2232 tmp
= smu7_patch_limits_vddc(hwmgr
, &hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
2236 tmp
= smu7_patch_cac_vddc(hwmgr
, hwmgr
->dyn_state
.cac_leakage_table
);
2244 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr
*hwmgr
)
2246 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2248 struct phm_clock_voltage_dependency_table
*allowed_sclk_vddc_table
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
;
2249 struct phm_clock_voltage_dependency_table
*allowed_mclk_vddc_table
= hwmgr
->dyn_state
.vddc_dependency_on_mclk
;
2250 struct phm_clock_voltage_dependency_table
*allowed_mclk_vddci_table
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
2252 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table
!= NULL
,
2253 "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL
);
2254 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table
->count
>= 1,
2255 "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL
);
2257 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table
!= NULL
,
2258 "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL
);
2259 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table
->count
>= 1,
2260 "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL
);
2262 data
->min_vddc_in_pptable
= (uint16_t)allowed_sclk_vddc_table
->entries
[0].v
;
2263 data
->max_vddc_in_pptable
= (uint16_t)allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
2265 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
=
2266 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].clk
;
2267 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
=
2268 allowed_mclk_vddc_table
->entries
[allowed_mclk_vddc_table
->count
- 1].clk
;
2269 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
=
2270 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
2272 if (allowed_mclk_vddci_table
!= NULL
&& allowed_mclk_vddci_table
->count
>= 1) {
2273 data
->min_vddci_in_pptable
= (uint16_t)allowed_mclk_vddci_table
->entries
[0].v
;
2274 data
->max_vddci_in_pptable
= (uint16_t)allowed_mclk_vddci_table
->entries
[allowed_mclk_vddci_table
->count
- 1].v
;
2277 if (hwmgr
->dyn_state
.vddci_dependency_on_mclk
!= NULL
&& hwmgr
->dyn_state
.vddci_dependency_on_mclk
->count
> 1)
2278 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
->entries
[hwmgr
->dyn_state
.vddci_dependency_on_mclk
->count
- 1].v
;
2283 static int smu7_hwmgr_backend_fini(struct pp_hwmgr
*hwmgr
)
2285 if (NULL
!= hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
) {
2286 kfree(hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
);
2287 hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
= NULL
;
2289 pp_smu7_thermal_fini(hwmgr
);
2290 if (NULL
!= hwmgr
->backend
) {
2291 kfree(hwmgr
->backend
);
2292 hwmgr
->backend
= NULL
;
2298 static int smu7_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
2300 struct smu7_hwmgr
*data
;
2303 data
= kzalloc(sizeof(struct smu7_hwmgr
), GFP_KERNEL
);
2307 hwmgr
->backend
= data
;
2308 pp_smu7_thermal_initialize(hwmgr
);
2310 smu7_patch_voltage_workaround(hwmgr
);
2311 smu7_init_dpm_defaults(hwmgr
);
2313 /* Get leakage voltage based on leakage ID. */
2314 result
= smu7_get_evv_voltages(hwmgr
);
2317 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
2321 if (hwmgr
->pp_table_version
== PP_TABLE_V1
) {
2322 smu7_complete_dependency_tables(hwmgr
);
2323 smu7_set_private_data_based_on_pptable_v1(hwmgr
);
2324 } else if (hwmgr
->pp_table_version
== PP_TABLE_V0
) {
2325 smu7_patch_dependency_tables_with_leakage(hwmgr
);
2326 smu7_set_private_data_based_on_pptable_v0(hwmgr
);
2329 /* Initalize Dynamic State Adjustment Rule Settings */
2330 result
= phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr
);
2333 struct cgs_system_info sys_info
= {0};
2335 data
->is_tlu_enabled
= false;
2337 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
2338 SMU7_MAX_HARDWARE_POWERLEVELS
;
2339 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
2340 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
2342 sys_info
.size
= sizeof(struct cgs_system_info
);
2343 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_GEN_INFO
;
2344 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
2346 data
->pcie_gen_cap
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
2348 data
->pcie_gen_cap
= (uint32_t)sys_info
.value
;
2349 if (data
->pcie_gen_cap
& CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)
2350 data
->pcie_spc_cap
= 20;
2351 sys_info
.size
= sizeof(struct cgs_system_info
);
2352 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_MLW
;
2353 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
2355 data
->pcie_lane_cap
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
2357 data
->pcie_lane_cap
= (uint32_t)sys_info
.value
;
2359 hwmgr
->platform_descriptor
.vbiosInterruptId
= 0x20000400; /* IRQ_SOURCE1_SW_INT */
2360 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2361 hwmgr
->platform_descriptor
.clockStep
.engineClock
= 500;
2362 hwmgr
->platform_descriptor
.clockStep
.memoryClock
= 500;
2363 smu7_thermal_parameter_init(hwmgr
);
2365 /* Ignore return value in here, we are cleaning up a mess. */
2366 smu7_hwmgr_backend_fini(hwmgr
);
2372 static int smu7_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
2374 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2375 uint32_t level
, tmp
;
2377 if (!data
->pcie_dpm_key_disabled
) {
2378 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
2380 tmp
= data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
2385 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2386 PPSMC_MSG_PCIeDPM_ForceLevel
, level
);
2390 if (!data
->sclk_dpm_key_disabled
) {
2391 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
2393 tmp
= data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
2398 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2399 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
2404 if (!data
->mclk_dpm_key_disabled
) {
2405 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
2407 tmp
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
2412 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2413 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
2421 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
)
2423 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2425 if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
2426 phm_apply_dal_min_voltage_request(hwmgr
);
2427 /* TO DO for v0 iceland and Ci*/
2429 if (!data
->sclk_dpm_key_disabled
) {
2430 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
)
2431 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2432 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
2433 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
2436 if (!data
->mclk_dpm_key_disabled
) {
2437 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
)
2438 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2439 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
2440 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
2446 static int smu7_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
2448 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2450 if (!smum_is_dpm_running(hwmgr
))
2453 if (!data
->pcie_dpm_key_disabled
) {
2454 smum_send_msg_to_smc(hwmgr
->smumgr
,
2455 PPSMC_MSG_PCIeDPM_UnForceLevel
);
2458 return smu7_upload_dpm_level_enable_mask(hwmgr
);
2461 static int smu7_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
2463 struct smu7_hwmgr
*data
=
2464 (struct smu7_hwmgr
*)(hwmgr
->backend
);
2467 if (!data
->sclk_dpm_key_disabled
)
2468 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
2469 level
= phm_get_lowest_enabled_level(hwmgr
,
2470 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
2471 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2472 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
2477 if (!data
->mclk_dpm_key_disabled
) {
2478 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
2479 level
= phm_get_lowest_enabled_level(hwmgr
,
2480 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
2481 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2482 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
2487 if (!data
->pcie_dpm_key_disabled
) {
2488 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
2489 level
= phm_get_lowest_enabled_level(hwmgr
,
2490 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
2491 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
2492 PPSMC_MSG_PCIeDPM_ForceLevel
,
2500 static int smu7_get_profiling_clk(struct pp_hwmgr
*hwmgr
, enum amd_dpm_forced_level level
,
2501 uint32_t *sclk_mask
, uint32_t *mclk_mask
, uint32_t *pcie_mask
)
2503 uint32_t percentage
;
2504 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2505 struct smu7_dpm_table
*golden_dpm_table
= &data
->golden_dpm_table
;
2510 if (golden_dpm_table
->mclk_table
.count
< 1)
2513 percentage
= 100 * golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
- 1].value
/
2514 golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
- 1].value
;
2516 if (golden_dpm_table
->mclk_table
.count
== 1) {
2518 tmp_mclk
= golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
- 1].value
;
2519 *mclk_mask
= golden_dpm_table
->mclk_table
.count
- 1;
2521 tmp_mclk
= golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
- 2].value
;
2522 *mclk_mask
= golden_dpm_table
->mclk_table
.count
- 2;
2525 tmp_sclk
= tmp_mclk
* percentage
/ 100;
2527 if (hwmgr
->pp_table_version
== PP_TABLE_V0
) {
2528 for (count
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
-1;
2529 count
>= 0; count
--) {
2530 if (tmp_sclk
>= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[count
].clk
) {
2531 tmp_sclk
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[count
].clk
;
2536 if (count
< 0 || level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
)
2539 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
2540 *sclk_mask
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
-1;
2541 } else if (hwmgr
->pp_table_version
== PP_TABLE_V1
) {
2542 struct phm_ppt_v1_information
*table_info
=
2543 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2545 for (count
= table_info
->vdd_dep_on_sclk
->count
-1; count
>= 0; count
--) {
2546 if (tmp_sclk
>= table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
2547 tmp_sclk
= table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
2552 if (count
< 0 || level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
)
2555 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
2556 *sclk_mask
= table_info
->vdd_dep_on_sclk
->count
- 1;
2559 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
)
2561 else if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
2562 *mclk_mask
= golden_dpm_table
->mclk_table
.count
- 1;
2564 *pcie_mask
= data
->dpm_table
.pcie_speed_table
.count
- 1;
2568 static int smu7_force_dpm_level(struct pp_hwmgr
*hwmgr
,
2569 enum amd_dpm_forced_level level
)
2572 uint32_t sclk_mask
= 0;
2573 uint32_t mclk_mask
= 0;
2574 uint32_t pcie_mask
= 0;
2575 uint32_t profile_mode_mask
= AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
|
2576 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
|
2577 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
|
2578 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
;
2580 if (level
== hwmgr
->dpm_level
)
2583 if (!(hwmgr
->dpm_level
& profile_mode_mask
)) {
2584 /* enter profile mode, save current level, disable gfx cg*/
2585 if (level
& profile_mode_mask
) {
2586 hwmgr
->saved_dpm_level
= hwmgr
->dpm_level
;
2587 cgs_set_clockgating_state(hwmgr
->device
,
2588 AMD_IP_BLOCK_TYPE_GFX
,
2589 AMD_CG_STATE_UNGATE
);
2592 /* exit profile mode, restore level, enable gfx cg*/
2593 if (!(level
& profile_mode_mask
)) {
2594 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
)
2595 level
= hwmgr
->saved_dpm_level
;
2596 cgs_set_clockgating_state(hwmgr
->device
,
2597 AMD_IP_BLOCK_TYPE_GFX
,
2603 case AMD_DPM_FORCED_LEVEL_HIGH
:
2604 ret
= smu7_force_dpm_highest(hwmgr
);
2607 hwmgr
->dpm_level
= level
;
2609 case AMD_DPM_FORCED_LEVEL_LOW
:
2610 ret
= smu7_force_dpm_lowest(hwmgr
);
2613 hwmgr
->dpm_level
= level
;
2615 case AMD_DPM_FORCED_LEVEL_AUTO
:
2616 ret
= smu7_unforce_dpm_levels(hwmgr
);
2619 hwmgr
->dpm_level
= level
;
2621 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
:
2622 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
:
2623 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
:
2624 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
:
2625 ret
= smu7_get_profiling_clk(hwmgr
, level
, &sclk_mask
, &mclk_mask
, &pcie_mask
);
2628 hwmgr
->dpm_level
= level
;
2629 smu7_force_clock_level(hwmgr
, PP_SCLK
, 1<<sclk_mask
);
2630 smu7_force_clock_level(hwmgr
, PP_MCLK
, 1<<mclk_mask
);
2631 smu7_force_clock_level(hwmgr
, PP_PCIE
, 1<<pcie_mask
);
2634 case AMD_DPM_FORCED_LEVEL_MANUAL
:
2635 hwmgr
->dpm_level
= level
;
2637 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
:
2642 if (level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
&& hwmgr
->saved_dpm_level
!= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
2643 smu7_fan_ctrl_set_fan_speed_percent(hwmgr
, 100);
2644 else if (level
!= AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
&& hwmgr
->saved_dpm_level
== AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
)
2645 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr
);
2650 static int smu7_get_power_state_size(struct pp_hwmgr
*hwmgr
)
2652 return sizeof(struct smu7_power_state
);
2655 static int smu7_vblank_too_short(struct pp_hwmgr
*hwmgr
,
2656 uint32_t vblank_time_us
)
2658 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2659 uint32_t switch_limit_us
;
2661 switch (hwmgr
->chip_id
) {
2662 case CHIP_POLARIS10
:
2663 case CHIP_POLARIS11
:
2664 case CHIP_POLARIS12
:
2665 switch_limit_us
= data
->is_memory_gddr5
? 190 : 150;
2668 switch_limit_us
= data
->is_memory_gddr5
? 450 : 150;
2672 if (vblank_time_us
< switch_limit_us
)
2678 static int smu7_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
2679 struct pp_power_state
*request_ps
,
2680 const struct pp_power_state
*current_ps
)
2683 struct smu7_power_state
*smu7_ps
=
2684 cast_phw_smu7_power_state(&request_ps
->hardware
);
2687 struct PP_Clocks minimum_clocks
= {0};
2688 bool disable_mclk_switching
;
2689 bool disable_mclk_switching_for_frame_lock
;
2690 struct cgs_display_info info
= {0};
2691 struct cgs_mode_info mode_info
= {0};
2692 const struct phm_clock_and_voltage_limits
*max_limits
;
2694 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2695 struct phm_ppt_v1_information
*table_info
=
2696 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2698 int32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
2700 info
.mode_info
= &mode_info
;
2701 data
->battery_state
= (PP_StateUILabel_Battery
==
2702 request_ps
->classification
.ui_label
);
2704 PP_ASSERT_WITH_CODE(smu7_ps
->performance_level_count
== 2,
2705 "VI should always have 2 performance levels",
2708 max_limits
= (PP_PowerSource_AC
== hwmgr
->power_source
) ?
2709 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
2710 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
2712 /* Cap clock DPM tables at DC MAX if it is in DC. */
2713 if (PP_PowerSource_DC
== hwmgr
->power_source
) {
2714 for (i
= 0; i
< smu7_ps
->performance_level_count
; i
++) {
2715 if (smu7_ps
->performance_levels
[i
].memory_clock
> max_limits
->mclk
)
2716 smu7_ps
->performance_levels
[i
].memory_clock
= max_limits
->mclk
;
2717 if (smu7_ps
->performance_levels
[i
].engine_clock
> max_limits
->sclk
)
2718 smu7_ps
->performance_levels
[i
].engine_clock
= max_limits
->sclk
;
2722 smu7_ps
->vce_clks
.evclk
= hwmgr
->vce_arbiter
.evclk
;
2723 smu7_ps
->vce_clks
.ecclk
= hwmgr
->vce_arbiter
.ecclk
;
2725 cgs_get_active_displays_info(hwmgr
->device
, &info
);
2727 minimum_clocks
.engineClock
= hwmgr
->display_config
.min_core_set_clock
;
2728 minimum_clocks
.memoryClock
= hwmgr
->display_config
.min_mem_set_clock
;
2730 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2731 PHM_PlatformCaps_StablePState
)) {
2732 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
2733 stable_pstate_sclk
= (max_limits
->sclk
* 75) / 100;
2735 for (count
= table_info
->vdd_dep_on_sclk
->count
- 1;
2736 count
>= 0; count
--) {
2737 if (stable_pstate_sclk
>=
2738 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
2739 stable_pstate_sclk
=
2740 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
2746 stable_pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[0].clk
;
2748 stable_pstate_mclk
= max_limits
->mclk
;
2750 minimum_clocks
.engineClock
= stable_pstate_sclk
;
2751 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
2754 if (minimum_clocks
.engineClock
< hwmgr
->gfx_arbiter
.sclk
)
2755 minimum_clocks
.engineClock
= hwmgr
->gfx_arbiter
.sclk
;
2757 if (minimum_clocks
.memoryClock
< hwmgr
->gfx_arbiter
.mclk
)
2758 minimum_clocks
.memoryClock
= hwmgr
->gfx_arbiter
.mclk
;
2760 smu7_ps
->sclk_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
2762 if (0 != hwmgr
->gfx_arbiter
.sclk_over_drive
) {
2763 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.sclk_over_drive
<=
2764 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
),
2765 "Overdrive sclk exceeds limit",
2766 hwmgr
->gfx_arbiter
.sclk_over_drive
=
2767 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
2769 if (hwmgr
->gfx_arbiter
.sclk_over_drive
>= hwmgr
->gfx_arbiter
.sclk
)
2770 smu7_ps
->performance_levels
[1].engine_clock
=
2771 hwmgr
->gfx_arbiter
.sclk_over_drive
;
2774 if (0 != hwmgr
->gfx_arbiter
.mclk_over_drive
) {
2775 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.mclk_over_drive
<=
2776 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
),
2777 "Overdrive mclk exceeds limit",
2778 hwmgr
->gfx_arbiter
.mclk_over_drive
=
2779 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
2781 if (hwmgr
->gfx_arbiter
.mclk_over_drive
>= hwmgr
->gfx_arbiter
.mclk
)
2782 smu7_ps
->performance_levels
[1].memory_clock
=
2783 hwmgr
->gfx_arbiter
.mclk_over_drive
;
2786 disable_mclk_switching_for_frame_lock
= phm_cap_enabled(
2787 hwmgr
->platform_descriptor
.platformCaps
,
2788 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
2791 disable_mclk_switching
= ((1 < info
.display_count
) ||
2792 disable_mclk_switching_for_frame_lock
||
2793 smu7_vblank_too_short(hwmgr
, mode_info
.vblank_time_us
) ||
2794 (mode_info
.refresh_rate
> 120));
2796 sclk
= smu7_ps
->performance_levels
[0].engine_clock
;
2797 mclk
= smu7_ps
->performance_levels
[0].memory_clock
;
2799 if (disable_mclk_switching
)
2800 mclk
= smu7_ps
->performance_levels
2801 [smu7_ps
->performance_level_count
- 1].memory_clock
;
2803 if (sclk
< minimum_clocks
.engineClock
)
2804 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ?
2805 max_limits
->sclk
: minimum_clocks
.engineClock
;
2807 if (mclk
< minimum_clocks
.memoryClock
)
2808 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ?
2809 max_limits
->mclk
: minimum_clocks
.memoryClock
;
2811 smu7_ps
->performance_levels
[0].engine_clock
= sclk
;
2812 smu7_ps
->performance_levels
[0].memory_clock
= mclk
;
2814 smu7_ps
->performance_levels
[1].engine_clock
=
2815 (smu7_ps
->performance_levels
[1].engine_clock
>=
2816 smu7_ps
->performance_levels
[0].engine_clock
) ?
2817 smu7_ps
->performance_levels
[1].engine_clock
:
2818 smu7_ps
->performance_levels
[0].engine_clock
;
2820 if (disable_mclk_switching
) {
2821 if (mclk
< smu7_ps
->performance_levels
[1].memory_clock
)
2822 mclk
= smu7_ps
->performance_levels
[1].memory_clock
;
2824 smu7_ps
->performance_levels
[0].memory_clock
= mclk
;
2825 smu7_ps
->performance_levels
[1].memory_clock
= mclk
;
2827 if (smu7_ps
->performance_levels
[1].memory_clock
<
2828 smu7_ps
->performance_levels
[0].memory_clock
)
2829 smu7_ps
->performance_levels
[1].memory_clock
=
2830 smu7_ps
->performance_levels
[0].memory_clock
;
2833 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2834 PHM_PlatformCaps_StablePState
)) {
2835 for (i
= 0; i
< smu7_ps
->performance_level_count
; i
++) {
2836 smu7_ps
->performance_levels
[i
].engine_clock
= stable_pstate_sclk
;
2837 smu7_ps
->performance_levels
[i
].memory_clock
= stable_pstate_mclk
;
2838 smu7_ps
->performance_levels
[i
].pcie_gen
= data
->pcie_gen_performance
.max
;
2839 smu7_ps
->performance_levels
[i
].pcie_lane
= data
->pcie_gen_performance
.max
;
2846 static int smu7_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
2848 struct pp_power_state
*ps
;
2849 struct smu7_power_state
*smu7_ps
;
2854 ps
= hwmgr
->request_ps
;
2859 smu7_ps
= cast_phw_smu7_power_state(&ps
->hardware
);
2862 return smu7_ps
->performance_levels
[0].memory_clock
;
2864 return smu7_ps
->performance_levels
2865 [smu7_ps
->performance_level_count
-1].memory_clock
;
2868 static int smu7_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
2870 struct pp_power_state
*ps
;
2871 struct smu7_power_state
*smu7_ps
;
2876 ps
= hwmgr
->request_ps
;
2881 smu7_ps
= cast_phw_smu7_power_state(&ps
->hardware
);
2884 return smu7_ps
->performance_levels
[0].engine_clock
;
2886 return smu7_ps
->performance_levels
2887 [smu7_ps
->performance_level_count
-1].engine_clock
;
2890 static int smu7_dpm_patch_boot_state(struct pp_hwmgr
*hwmgr
,
2891 struct pp_hw_power_state
*hw_ps
)
2893 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2894 struct smu7_power_state
*ps
= (struct smu7_power_state
*)hw_ps
;
2895 ATOM_FIRMWARE_INFO_V2_2
*fw_info
;
2898 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2900 /* First retrieve the Boot clocks and VDDC from the firmware info table.
2901 * We assume here that fw_info is unchanged if this call fails.
2903 fw_info
= (ATOM_FIRMWARE_INFO_V2_2
*)cgs_atom_get_data_table(
2904 hwmgr
->device
, index
,
2905 &size
, &frev
, &crev
);
2907 /* During a test, there is no firmware info table. */
2910 /* Patch the state. */
2911 data
->vbios_boot_state
.sclk_bootup_value
=
2912 le32_to_cpu(fw_info
->ulDefaultEngineClock
);
2913 data
->vbios_boot_state
.mclk_bootup_value
=
2914 le32_to_cpu(fw_info
->ulDefaultMemoryClock
);
2915 data
->vbios_boot_state
.mvdd_bootup_value
=
2916 le16_to_cpu(fw_info
->usBootUpMVDDCVoltage
);
2917 data
->vbios_boot_state
.vddc_bootup_value
=
2918 le16_to_cpu(fw_info
->usBootUpVDDCVoltage
);
2919 data
->vbios_boot_state
.vddci_bootup_value
=
2920 le16_to_cpu(fw_info
->usBootUpVDDCIVoltage
);
2921 data
->vbios_boot_state
.pcie_gen_bootup_value
=
2922 smu7_get_current_pcie_speed(hwmgr
);
2924 data
->vbios_boot_state
.pcie_lane_bootup_value
=
2925 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr
);
2927 /* set boot power state */
2928 ps
->performance_levels
[0].memory_clock
= data
->vbios_boot_state
.mclk_bootup_value
;
2929 ps
->performance_levels
[0].engine_clock
= data
->vbios_boot_state
.sclk_bootup_value
;
2930 ps
->performance_levels
[0].pcie_gen
= data
->vbios_boot_state
.pcie_gen_bootup_value
;
2931 ps
->performance_levels
[0].pcie_lane
= data
->vbios_boot_state
.pcie_lane_bootup_value
;
2936 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr
*hwmgr
)
2939 unsigned long ret
= 0;
2941 if (hwmgr
->pp_table_version
== PP_TABLE_V0
) {
2942 result
= pp_tables_get_num_of_entries(hwmgr
, &ret
);
2943 return result
? 0 : ret
;
2944 } else if (hwmgr
->pp_table_version
== PP_TABLE_V1
) {
2945 result
= get_number_of_powerplay_table_entries_v1_0(hwmgr
);
2951 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr
*hwmgr
,
2952 void *state
, struct pp_power_state
*power_state
,
2953 void *pp_table
, uint32_t classification_flag
)
2955 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
2956 struct smu7_power_state
*smu7_power_state
=
2957 (struct smu7_power_state
*)(&(power_state
->hardware
));
2958 struct smu7_performance_level
*performance_level
;
2959 ATOM_Tonga_State
*state_entry
= (ATOM_Tonga_State
*)state
;
2960 ATOM_Tonga_POWERPLAYTABLE
*powerplay_table
=
2961 (ATOM_Tonga_POWERPLAYTABLE
*)pp_table
;
2962 PPTable_Generic_SubTable_Header
*sclk_dep_table
=
2963 (PPTable_Generic_SubTable_Header
*)
2964 (((unsigned long)powerplay_table
) +
2965 le16_to_cpu(powerplay_table
->usSclkDependencyTableOffset
));
2967 ATOM_Tonga_MCLK_Dependency_Table
*mclk_dep_table
=
2968 (ATOM_Tonga_MCLK_Dependency_Table
*)
2969 (((unsigned long)powerplay_table
) +
2970 le16_to_cpu(powerplay_table
->usMclkDependencyTableOffset
));
2972 /* The following fields are not initialized here: id orderedList allStatesList */
2973 power_state
->classification
.ui_label
=
2974 (le16_to_cpu(state_entry
->usClassification
) &
2975 ATOM_PPLIB_CLASSIFICATION_UI_MASK
) >>
2976 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
;
2977 power_state
->classification
.flags
= classification_flag
;
2978 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
2980 power_state
->classification
.temporary_state
= false;
2981 power_state
->classification
.to_be_deleted
= false;
2983 power_state
->validation
.disallowOnDC
=
2984 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
2985 ATOM_Tonga_DISALLOW_ON_DC
));
2987 power_state
->pcie
.lanes
= 0;
2989 power_state
->display
.disableFrameModulation
= false;
2990 power_state
->display
.limitRefreshrate
= false;
2991 power_state
->display
.enableVariBright
=
2992 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
2993 ATOM_Tonga_ENABLE_VARIBRIGHT
));
2995 power_state
->validation
.supportedPowerLevels
= 0;
2996 power_state
->uvd_clocks
.VCLK
= 0;
2997 power_state
->uvd_clocks
.DCLK
= 0;
2998 power_state
->temperatures
.min
= 0;
2999 power_state
->temperatures
.max
= 0;
3001 performance_level
= &(smu7_power_state
->performance_levels
3002 [smu7_power_state
->performance_level_count
++]);
3004 PP_ASSERT_WITH_CODE(
3005 (smu7_power_state
->performance_level_count
< smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_GRAPHICS
)),
3006 "Performance levels exceeds SMC limit!",
3009 PP_ASSERT_WITH_CODE(
3010 (smu7_power_state
->performance_level_count
<=
3011 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
3012 "Performance levels exceeds Driver limit!",
3015 /* Performance levels are arranged from low to high. */
3016 performance_level
->memory_clock
= mclk_dep_table
->entries
3017 [state_entry
->ucMemoryClockIndexLow
].ulMclk
;
3018 if (sclk_dep_table
->ucRevId
== 0)
3019 performance_level
->engine_clock
= ((ATOM_Tonga_SCLK_Dependency_Table
*)sclk_dep_table
)->entries
3020 [state_entry
->ucEngineClockIndexLow
].ulSclk
;
3021 else if (sclk_dep_table
->ucRevId
== 1)
3022 performance_level
->engine_clock
= ((ATOM_Polaris_SCLK_Dependency_Table
*)sclk_dep_table
)->entries
3023 [state_entry
->ucEngineClockIndexLow
].ulSclk
;
3024 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3025 state_entry
->ucPCIEGenLow
);
3026 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3027 state_entry
->ucPCIELaneHigh
);
3029 performance_level
= &(smu7_power_state
->performance_levels
3030 [smu7_power_state
->performance_level_count
++]);
3031 performance_level
->memory_clock
= mclk_dep_table
->entries
3032 [state_entry
->ucMemoryClockIndexHigh
].ulMclk
;
3034 if (sclk_dep_table
->ucRevId
== 0)
3035 performance_level
->engine_clock
= ((ATOM_Tonga_SCLK_Dependency_Table
*)sclk_dep_table
)->entries
3036 [state_entry
->ucEngineClockIndexHigh
].ulSclk
;
3037 else if (sclk_dep_table
->ucRevId
== 1)
3038 performance_level
->engine_clock
= ((ATOM_Polaris_SCLK_Dependency_Table
*)sclk_dep_table
)->entries
3039 [state_entry
->ucEngineClockIndexHigh
].ulSclk
;
3041 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3042 state_entry
->ucPCIEGenHigh
);
3043 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3044 state_entry
->ucPCIELaneHigh
);
3049 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr
*hwmgr
,
3050 unsigned long entry_index
, struct pp_power_state
*state
)
3053 struct smu7_power_state
*ps
;
3054 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3055 struct phm_ppt_v1_information
*table_info
=
3056 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3057 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
3058 table_info
->vdd_dep_on_mclk
;
3060 state
->hardware
.magic
= PHM_VIslands_Magic
;
3062 ps
= (struct smu7_power_state
*)(&state
->hardware
);
3064 result
= get_powerplay_table_entry_v1_0(hwmgr
, entry_index
, state
,
3065 smu7_get_pp_table_entry_callback_func_v1
);
3067 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3068 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3069 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3071 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
3072 if (dep_mclk_table
->entries
[0].clk
!=
3073 data
->vbios_boot_state
.mclk_bootup_value
)
3074 pr_err("Single MCLK entry VDDCI/MCLK dependency table "
3075 "does not match VBIOS boot MCLK level");
3076 if (dep_mclk_table
->entries
[0].vddci
!=
3077 data
->vbios_boot_state
.vddci_bootup_value
)
3078 pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
3079 "does not match VBIOS boot VDDCI level");
3082 /* set DC compatible flag if this state supports DC */
3083 if (!state
->validation
.disallowOnDC
)
3084 ps
->dc_compatible
= true;
3086 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
3087 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
3089 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3090 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3095 switch (state
->classification
.ui_label
) {
3096 case PP_StateUILabel_Performance
:
3097 data
->use_pcie_performance_levels
= true;
3098 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3099 if (data
->pcie_gen_performance
.max
<
3100 ps
->performance_levels
[i
].pcie_gen
)
3101 data
->pcie_gen_performance
.max
=
3102 ps
->performance_levels
[i
].pcie_gen
;
3104 if (data
->pcie_gen_performance
.min
>
3105 ps
->performance_levels
[i
].pcie_gen
)
3106 data
->pcie_gen_performance
.min
=
3107 ps
->performance_levels
[i
].pcie_gen
;
3109 if (data
->pcie_lane_performance
.max
<
3110 ps
->performance_levels
[i
].pcie_lane
)
3111 data
->pcie_lane_performance
.max
=
3112 ps
->performance_levels
[i
].pcie_lane
;
3113 if (data
->pcie_lane_performance
.min
>
3114 ps
->performance_levels
[i
].pcie_lane
)
3115 data
->pcie_lane_performance
.min
=
3116 ps
->performance_levels
[i
].pcie_lane
;
3119 case PP_StateUILabel_Battery
:
3120 data
->use_pcie_power_saving_levels
= true;
3122 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3123 if (data
->pcie_gen_power_saving
.max
<
3124 ps
->performance_levels
[i
].pcie_gen
)
3125 data
->pcie_gen_power_saving
.max
=
3126 ps
->performance_levels
[i
].pcie_gen
;
3128 if (data
->pcie_gen_power_saving
.min
>
3129 ps
->performance_levels
[i
].pcie_gen
)
3130 data
->pcie_gen_power_saving
.min
=
3131 ps
->performance_levels
[i
].pcie_gen
;
3133 if (data
->pcie_lane_power_saving
.max
<
3134 ps
->performance_levels
[i
].pcie_lane
)
3135 data
->pcie_lane_power_saving
.max
=
3136 ps
->performance_levels
[i
].pcie_lane
;
3138 if (data
->pcie_lane_power_saving
.min
>
3139 ps
->performance_levels
[i
].pcie_lane
)
3140 data
->pcie_lane_power_saving
.min
=
3141 ps
->performance_levels
[i
].pcie_lane
;
3151 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr
*hwmgr
,
3152 struct pp_hw_power_state
*power_state
,
3153 unsigned int index
, const void *clock_info
)
3155 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3156 struct smu7_power_state
*ps
= cast_phw_smu7_power_state(power_state
);
3157 const ATOM_PPLIB_CI_CLOCK_INFO
*visland_clk_info
= clock_info
;
3158 struct smu7_performance_level
*performance_level
;
3159 uint32_t engine_clock
, memory_clock
;
3160 uint16_t pcie_gen_from_bios
;
3162 engine_clock
= visland_clk_info
->ucEngineClockHigh
<< 16 | visland_clk_info
->usEngineClockLow
;
3163 memory_clock
= visland_clk_info
->ucMemoryClockHigh
<< 16 | visland_clk_info
->usMemoryClockLow
;
3165 if (!(data
->mc_micro_code_feature
& DISABLE_MC_LOADMICROCODE
) && memory_clock
> data
->highest_mclk
)
3166 data
->highest_mclk
= memory_clock
;
3168 PP_ASSERT_WITH_CODE(
3169 (ps
->performance_level_count
< smum_get_mac_definition(hwmgr
->smumgr
, SMU_MAX_LEVELS_GRAPHICS
)),
3170 "Performance levels exceeds SMC limit!",
3173 PP_ASSERT_WITH_CODE(
3174 (ps
->performance_level_count
<
3175 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
3176 "Performance levels exceeds Driver limit, Skip!",
3179 performance_level
= &(ps
->performance_levels
3180 [ps
->performance_level_count
++]);
3182 /* Performance levels are arranged from low to high. */
3183 performance_level
->memory_clock
= memory_clock
;
3184 performance_level
->engine_clock
= engine_clock
;
3186 pcie_gen_from_bios
= visland_clk_info
->ucPCIEGen
;
3188 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
, pcie_gen_from_bios
);
3189 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
, visland_clk_info
->usPCIELane
);
3194 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr
*hwmgr
,
3195 unsigned long entry_index
, struct pp_power_state
*state
)
3198 struct smu7_power_state
*ps
;
3199 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3200 struct phm_clock_voltage_dependency_table
*dep_mclk_table
=
3201 hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
3203 memset(&state
->hardware
, 0x00, sizeof(struct pp_hw_power_state
));
3205 state
->hardware
.magic
= PHM_VIslands_Magic
;
3207 ps
= (struct smu7_power_state
*)(&state
->hardware
);
3209 result
= pp_tables_get_entry(hwmgr
, entry_index
, state
,
3210 smu7_get_pp_table_entry_callback_func_v0
);
3213 * This is the earliest time we have all the dependency table
3214 * and the VBIOS boot state as
3215 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3216 * state if there is only one VDDCI/MCLK level, check if it's
3217 * the same as VBIOS boot state
3219 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
3220 if (dep_mclk_table
->entries
[0].clk
!=
3221 data
->vbios_boot_state
.mclk_bootup_value
)
3222 pr_err("Single MCLK entry VDDCI/MCLK dependency table "
3223 "does not match VBIOS boot MCLK level");
3224 if (dep_mclk_table
->entries
[0].v
!=
3225 data
->vbios_boot_state
.vddci_bootup_value
)
3226 pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
3227 "does not match VBIOS boot VDDCI level");
3230 /* set DC compatible flag if this state supports DC */
3231 if (!state
->validation
.disallowOnDC
)
3232 ps
->dc_compatible
= true;
3234 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
3235 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
3237 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3238 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3243 switch (state
->classification
.ui_label
) {
3244 case PP_StateUILabel_Performance
:
3245 data
->use_pcie_performance_levels
= true;
3247 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3248 if (data
->pcie_gen_performance
.max
<
3249 ps
->performance_levels
[i
].pcie_gen
)
3250 data
->pcie_gen_performance
.max
=
3251 ps
->performance_levels
[i
].pcie_gen
;
3253 if (data
->pcie_gen_performance
.min
>
3254 ps
->performance_levels
[i
].pcie_gen
)
3255 data
->pcie_gen_performance
.min
=
3256 ps
->performance_levels
[i
].pcie_gen
;
3258 if (data
->pcie_lane_performance
.max
<
3259 ps
->performance_levels
[i
].pcie_lane
)
3260 data
->pcie_lane_performance
.max
=
3261 ps
->performance_levels
[i
].pcie_lane
;
3263 if (data
->pcie_lane_performance
.min
>
3264 ps
->performance_levels
[i
].pcie_lane
)
3265 data
->pcie_lane_performance
.min
=
3266 ps
->performance_levels
[i
].pcie_lane
;
3269 case PP_StateUILabel_Battery
:
3270 data
->use_pcie_power_saving_levels
= true;
3272 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3273 if (data
->pcie_gen_power_saving
.max
<
3274 ps
->performance_levels
[i
].pcie_gen
)
3275 data
->pcie_gen_power_saving
.max
=
3276 ps
->performance_levels
[i
].pcie_gen
;
3278 if (data
->pcie_gen_power_saving
.min
>
3279 ps
->performance_levels
[i
].pcie_gen
)
3280 data
->pcie_gen_power_saving
.min
=
3281 ps
->performance_levels
[i
].pcie_gen
;
3283 if (data
->pcie_lane_power_saving
.max
<
3284 ps
->performance_levels
[i
].pcie_lane
)
3285 data
->pcie_lane_power_saving
.max
=
3286 ps
->performance_levels
[i
].pcie_lane
;
3288 if (data
->pcie_lane_power_saving
.min
>
3289 ps
->performance_levels
[i
].pcie_lane
)
3290 data
->pcie_lane_power_saving
.min
=
3291 ps
->performance_levels
[i
].pcie_lane
;
3301 static int smu7_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
3302 unsigned long entry_index
, struct pp_power_state
*state
)
3304 if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
3305 return smu7_get_pp_table_entry_v0(hwmgr
, entry_index
, state
);
3306 else if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
3307 return smu7_get_pp_table_entry_v1(hwmgr
, entry_index
, state
);
3312 static int smu7_get_gpu_power(struct pp_hwmgr
*hwmgr
,
3313 struct pp_gpu_power
*query
)
3315 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr
->smumgr
,
3316 PPSMC_MSG_PmStatusLogStart
),
3317 "Failed to start pm status log!",
3320 msleep_interruptible(20);
3322 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr
->smumgr
,
3323 PPSMC_MSG_PmStatusLogSample
),
3324 "Failed to sample pm status log!",
3327 query
->vddc_power
= cgs_read_ind_register(hwmgr
->device
,
3329 ixSMU_PM_STATUS_40
);
3330 query
->vddci_power
= cgs_read_ind_register(hwmgr
->device
,
3332 ixSMU_PM_STATUS_49
);
3333 query
->max_gpu_power
= cgs_read_ind_register(hwmgr
->device
,
3335 ixSMU_PM_STATUS_94
);
3336 query
->average_gpu_power
= cgs_read_ind_register(hwmgr
->device
,
3338 ixSMU_PM_STATUS_95
);
3343 static int smu7_read_sensor(struct pp_hwmgr
*hwmgr
, int idx
,
3344 void *value
, int *size
)
3346 uint32_t sclk
, mclk
, activity_percent
;
3348 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3350 /* size must be at least 4 bytes for all sensors */
3355 case AMDGPU_PP_SENSOR_GFX_SCLK
:
3356 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
3357 sclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
3358 *((uint32_t *)value
) = sclk
;
3361 case AMDGPU_PP_SENSOR_GFX_MCLK
:
3362 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
3363 mclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
3364 *((uint32_t *)value
) = mclk
;
3367 case AMDGPU_PP_SENSOR_GPU_LOAD
:
3368 offset
= data
->soft_regs_start
+ smum_get_offsetof(hwmgr
->smumgr
,
3370 AverageGraphicsActivity
);
3372 activity_percent
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, offset
);
3373 activity_percent
+= 0x80;
3374 activity_percent
>>= 8;
3375 *((uint32_t *)value
) = activity_percent
> 100 ? 100 : activity_percent
;
3378 case AMDGPU_PP_SENSOR_GPU_TEMP
:
3379 *((uint32_t *)value
) = smu7_thermal_get_temperature(hwmgr
);
3382 case AMDGPU_PP_SENSOR_UVD_POWER
:
3383 *((uint32_t *)value
) = data
->uvd_power_gated
? 0 : 1;
3386 case AMDGPU_PP_SENSOR_VCE_POWER
:
3387 *((uint32_t *)value
) = data
->vce_power_gated
? 0 : 1;
3390 case AMDGPU_PP_SENSOR_GPU_POWER
:
3391 if (*size
< sizeof(struct pp_gpu_power
))
3393 *size
= sizeof(struct pp_gpu_power
);
3394 return smu7_get_gpu_power(hwmgr
, (struct pp_gpu_power
*)value
);
3400 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
3402 const struct phm_set_power_state_input
*states
=
3403 (const struct phm_set_power_state_input
*)input
;
3404 const struct smu7_power_state
*smu7_ps
=
3405 cast_const_phw_smu7_power_state(states
->pnew_state
);
3406 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3407 struct smu7_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
3408 uint32_t sclk
= smu7_ps
->performance_levels
3409 [smu7_ps
->performance_level_count
- 1].engine_clock
;
3410 struct smu7_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
3411 uint32_t mclk
= smu7_ps
->performance_levels
3412 [smu7_ps
->performance_level_count
- 1].memory_clock
;
3413 struct PP_Clocks min_clocks
= {0};
3415 struct cgs_display_info info
= {0};
3417 data
->need_update_smu7_dpm_table
= 0;
3419 for (i
= 0; i
< sclk_table
->count
; i
++) {
3420 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
3424 if (i
>= sclk_table
->count
)
3425 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
3427 /* TODO: Check SCLK in DAL's minimum clocks
3428 * in case DeepSleep divider update is required.
3430 if (data
->display_timing
.min_clock_in_sr
!= min_clocks
.engineClockInSR
&&
3431 (min_clocks
.engineClockInSR
>= SMU7_MINIMUM_ENGINE_CLOCK
||
3432 data
->display_timing
.min_clock_in_sr
>= SMU7_MINIMUM_ENGINE_CLOCK
))
3433 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
3436 for (i
= 0; i
< mclk_table
->count
; i
++) {
3437 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
3441 if (i
>= mclk_table
->count
)
3442 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
3444 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3446 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
3447 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
3452 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr
*hwmgr
,
3453 const struct smu7_power_state
*smu7_ps
)
3456 uint32_t sclk
, max_sclk
= 0;
3457 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3458 struct smu7_dpm_table
*dpm_table
= &data
->dpm_table
;
3460 for (i
= 0; i
< smu7_ps
->performance_level_count
; i
++) {
3461 sclk
= smu7_ps
->performance_levels
[i
].engine_clock
;
3462 if (max_sclk
< sclk
)
3466 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
3467 if (dpm_table
->sclk_table
.dpm_levels
[i
].value
== max_sclk
)
3468 return (uint16_t) ((i
>= dpm_table
->pcie_speed_table
.count
) ?
3469 dpm_table
->pcie_speed_table
.dpm_levels
3470 [dpm_table
->pcie_speed_table
.count
- 1].value
:
3471 dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
);
3477 static int smu7_request_link_speed_change_before_state_change(
3478 struct pp_hwmgr
*hwmgr
, const void *input
)
3480 const struct phm_set_power_state_input
*states
=
3481 (const struct phm_set_power_state_input
*)input
;
3482 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3483 const struct smu7_power_state
*smu7_nps
=
3484 cast_const_phw_smu7_power_state(states
->pnew_state
);
3485 const struct smu7_power_state
*polaris10_cps
=
3486 cast_const_phw_smu7_power_state(states
->pcurrent_state
);
3488 uint16_t target_link_speed
= smu7_get_maximum_link_speed(hwmgr
, smu7_nps
);
3489 uint16_t current_link_speed
;
3491 if (data
->force_pcie_gen
== PP_PCIEGenInvalid
)
3492 current_link_speed
= smu7_get_maximum_link_speed(hwmgr
, polaris10_cps
);
3494 current_link_speed
= data
->force_pcie_gen
;
3496 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
3497 data
->pspp_notify_required
= false;
3499 if (target_link_speed
> current_link_speed
) {
3500 switch (target_link_speed
) {
3502 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN3
, false))
3504 data
->force_pcie_gen
= PP_PCIEGen2
;
3505 if (current_link_speed
== PP_PCIEGen2
)
3508 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN2
, false))
3511 data
->force_pcie_gen
= smu7_get_current_pcie_speed(hwmgr
);
3515 if (target_link_speed
< current_link_speed
)
3516 data
->pspp_notify_required
= true;
3522 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
3524 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3526 if (0 == data
->need_update_smu7_dpm_table
)
3529 if ((0 == data
->sclk_dpm_key_disabled
) &&
3530 (data
->need_update_smu7_dpm_table
&
3531 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
3532 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
3533 "Trying to freeze SCLK DPM when DPM is disabled",
3535 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3536 PPSMC_MSG_SCLKDPM_FreezeLevel
),
3537 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3541 if ((0 == data
->mclk_dpm_key_disabled
) &&
3542 (data
->need_update_smu7_dpm_table
&
3543 DPMTABLE_OD_UPDATE_MCLK
)) {
3544 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
3545 "Trying to freeze MCLK DPM when DPM is disabled",
3547 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3548 PPSMC_MSG_MCLKDPM_FreezeLevel
),
3549 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3556 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3557 struct pp_hwmgr
*hwmgr
, const void *input
)
3560 const struct phm_set_power_state_input
*states
=
3561 (const struct phm_set_power_state_input
*)input
;
3562 const struct smu7_power_state
*smu7_ps
=
3563 cast_const_phw_smu7_power_state(states
->pnew_state
);
3564 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3565 uint32_t sclk
= smu7_ps
->performance_levels
3566 [smu7_ps
->performance_level_count
- 1].engine_clock
;
3567 uint32_t mclk
= smu7_ps
->performance_levels
3568 [smu7_ps
->performance_level_count
- 1].memory_clock
;
3569 struct smu7_dpm_table
*dpm_table
= &data
->dpm_table
;
3571 struct smu7_dpm_table
*golden_dpm_table
= &data
->golden_dpm_table
;
3572 uint32_t dpm_count
, clock_percent
;
3575 if (0 == data
->need_update_smu7_dpm_table
)
3578 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
3579 dpm_table
->sclk_table
.dpm_levels
3580 [dpm_table
->sclk_table
.count
- 1].value
= sclk
;
3582 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
3583 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
3584 /* Need to do calculation based on the golden DPM table
3585 * as the Heatmap GPU Clock axis is also based on the default values
3587 PP_ASSERT_WITH_CODE(
3588 (golden_dpm_table
->sclk_table
.dpm_levels
3589 [golden_dpm_table
->sclk_table
.count
- 1].value
!= 0),
3592 dpm_count
= dpm_table
->sclk_table
.count
< 2 ? 0 : dpm_table
->sclk_table
.count
- 2;
3594 for (i
= dpm_count
; i
> 1; i
--) {
3595 if (sclk
> golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
) {
3598 - golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
3600 / golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
;
3602 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3603 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
+
3604 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
3607 } else if (golden_dpm_table
->sclk_table
.dpm_levels
[dpm_table
->sclk_table
.count
-1].value
> sclk
) {
3609 ((golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
- 1].value
3611 / golden_dpm_table
->sclk_table
.dpm_levels
[golden_dpm_table
->sclk_table
.count
-1].value
;
3613 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3614 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
-
3615 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
3616 clock_percent
) / 100;
3618 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
3619 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
;
3624 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
3625 dpm_table
->mclk_table
.dpm_levels
3626 [dpm_table
->mclk_table
.count
- 1].value
= mclk
;
3628 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
3629 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
3631 PP_ASSERT_WITH_CODE(
3632 (golden_dpm_table
->mclk_table
.dpm_levels
3633 [golden_dpm_table
->mclk_table
.count
-1].value
!= 0),
3636 dpm_count
= dpm_table
->mclk_table
.count
< 2 ? 0 : dpm_table
->mclk_table
.count
- 2;
3637 for (i
= dpm_count
; i
> 1; i
--) {
3638 if (golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
< mclk
) {
3639 clock_percent
= ((mclk
-
3640 golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
) * 100)
3641 / golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
;
3643 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3644 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
+
3645 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
3646 clock_percent
) / 100;
3648 } else if (golden_dpm_table
->mclk_table
.dpm_levels
[dpm_table
->mclk_table
.count
-1].value
> mclk
) {
3650 (golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
- mclk
)
3652 / golden_dpm_table
->mclk_table
.dpm_levels
[golden_dpm_table
->mclk_table
.count
-1].value
;
3654 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3655 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
-
3656 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
3657 clock_percent
) / 100;
3659 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
3660 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
;
3665 if (data
->need_update_smu7_dpm_table
&
3666 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
)) {
3667 result
= smum_populate_all_graphic_levels(hwmgr
);
3668 PP_ASSERT_WITH_CODE((0 == result
),
3669 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3673 if (data
->need_update_smu7_dpm_table
&
3674 (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
3675 /*populate MCLK dpm table to SMU7 */
3676 result
= smum_populate_all_memory_levels(hwmgr
);
3677 PP_ASSERT_WITH_CODE((0 == result
),
3678 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3685 static int smu7_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
3686 struct smu7_single_dpm_table
*dpm_table
,
3687 uint32_t low_limit
, uint32_t high_limit
)
3691 for (i
= 0; i
< dpm_table
->count
; i
++) {
3692 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
)
3693 || (dpm_table
->dpm_levels
[i
].value
> high_limit
))
3694 dpm_table
->dpm_levels
[i
].enabled
= false;
3696 dpm_table
->dpm_levels
[i
].enabled
= true;
3702 static int smu7_trim_dpm_states(struct pp_hwmgr
*hwmgr
,
3703 const struct smu7_power_state
*smu7_ps
)
3705 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3706 uint32_t high_limit_count
;
3708 PP_ASSERT_WITH_CODE((smu7_ps
->performance_level_count
>= 1),
3709 "power state did not have any performance level",
3712 high_limit_count
= (1 == smu7_ps
->performance_level_count
) ? 0 : 1;
3714 smu7_trim_single_dpm_states(hwmgr
,
3715 &(data
->dpm_table
.sclk_table
),
3716 smu7_ps
->performance_levels
[0].engine_clock
,
3717 smu7_ps
->performance_levels
[high_limit_count
].engine_clock
);
3719 smu7_trim_single_dpm_states(hwmgr
,
3720 &(data
->dpm_table
.mclk_table
),
3721 smu7_ps
->performance_levels
[0].memory_clock
,
3722 smu7_ps
->performance_levels
[high_limit_count
].memory_clock
);
3727 static int smu7_generate_dpm_level_enable_mask(
3728 struct pp_hwmgr
*hwmgr
, const void *input
)
3731 const struct phm_set_power_state_input
*states
=
3732 (const struct phm_set_power_state_input
*)input
;
3733 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3734 const struct smu7_power_state
*smu7_ps
=
3735 cast_const_phw_smu7_power_state(states
->pnew_state
);
3737 result
= smu7_trim_dpm_states(hwmgr
, smu7_ps
);
3741 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
3742 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.sclk_table
);
3743 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
3744 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.mclk_table
);
3745 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
3746 phm_get_dpm_level_enable_mask_value(&data
->dpm_table
.pcie_speed_table
);
3751 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
3753 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3755 if (0 == data
->need_update_smu7_dpm_table
)
3758 if ((0 == data
->sclk_dpm_key_disabled
) &&
3759 (data
->need_update_smu7_dpm_table
&
3760 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
3762 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
3763 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3765 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3766 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
3767 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3771 if ((0 == data
->mclk_dpm_key_disabled
) &&
3772 (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
3774 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr
),
3775 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3777 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3778 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
3779 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3783 data
->need_update_smu7_dpm_table
= 0;
3788 static int smu7_notify_link_speed_change_after_state_change(
3789 struct pp_hwmgr
*hwmgr
, const void *input
)
3791 const struct phm_set_power_state_input
*states
=
3792 (const struct phm_set_power_state_input
*)input
;
3793 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3794 const struct smu7_power_state
*smu7_ps
=
3795 cast_const_phw_smu7_power_state(states
->pnew_state
);
3796 uint16_t target_link_speed
= smu7_get_maximum_link_speed(hwmgr
, smu7_ps
);
3799 if (data
->pspp_notify_required
) {
3800 if (target_link_speed
== PP_PCIEGen3
)
3801 request
= PCIE_PERF_REQ_GEN3
;
3802 else if (target_link_speed
== PP_PCIEGen2
)
3803 request
= PCIE_PERF_REQ_GEN2
;
3805 request
= PCIE_PERF_REQ_GEN1
;
3807 if (request
== PCIE_PERF_REQ_GEN1
&&
3808 smu7_get_current_pcie_speed(hwmgr
) > 0)
3811 if (acpi_pcie_perf_request(hwmgr
->device
, request
, false)) {
3812 if (PP_PCIEGen2
== target_link_speed
)
3813 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3815 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3822 static int smu7_notify_smc_display(struct pp_hwmgr
*hwmgr
)
3824 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3826 if (hwmgr
->feature_mask
& PP_VBI_TIME_SUPPORT_MASK
)
3827 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3828 (PPSMC_Msg
)PPSMC_MSG_SetVBITimeout
, data
->frame_time_x2
);
3829 return (smum_send_msg_to_smc(hwmgr
->smumgr
, (PPSMC_Msg
)PPSMC_HasDisplay
) == 0) ? 0 : -EINVAL
;
3832 static int smu7_set_power_state_tasks(struct pp_hwmgr
*hwmgr
, const void *input
)
3834 int tmp_result
, result
= 0;
3835 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3837 tmp_result
= smu7_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
3838 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3839 "Failed to find DPM states clocks in DPM table!",
3840 result
= tmp_result
);
3842 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3843 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
3845 smu7_request_link_speed_change_before_state_change(hwmgr
, input
);
3846 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3847 "Failed to request link speed change before state change!",
3848 result
= tmp_result
);
3851 tmp_result
= smu7_freeze_sclk_mclk_dpm(hwmgr
);
3852 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3853 "Failed to freeze SCLK MCLK DPM!", result
= tmp_result
);
3855 tmp_result
= smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
3856 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3857 "Failed to populate and upload SCLK MCLK DPM levels!",
3858 result
= tmp_result
);
3860 tmp_result
= smu7_generate_dpm_level_enable_mask(hwmgr
, input
);
3861 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3862 "Failed to generate DPM level enabled mask!",
3863 result
= tmp_result
);
3865 tmp_result
= smum_update_sclk_threshold(hwmgr
);
3866 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3867 "Failed to update SCLK threshold!",
3868 result
= tmp_result
);
3870 tmp_result
= smu7_notify_smc_display(hwmgr
);
3871 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3872 "Failed to notify smc display settings!",
3873 result
= tmp_result
);
3875 tmp_result
= smu7_unfreeze_sclk_mclk_dpm(hwmgr
);
3876 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3877 "Failed to unfreeze SCLK MCLK DPM!",
3878 result
= tmp_result
);
3880 tmp_result
= smu7_upload_dpm_level_enable_mask(hwmgr
);
3881 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3882 "Failed to upload DPM level enabled mask!",
3883 result
= tmp_result
);
3885 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3886 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
3888 smu7_notify_link_speed_change_after_state_change(hwmgr
, input
);
3889 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3890 "Failed to notify link speed change after state change!",
3891 result
= tmp_result
);
3893 data
->apply_optimized_settings
= false;
3897 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
)
3899 hwmgr
->thermal_controller
.
3900 advanceFanControlParameters
.usMaxFanPWM
= us_max_fan_pwm
;
3902 if (phm_is_hw_access_blocked(hwmgr
))
3905 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3906 PPSMC_MSG_SetFanPwmMax
, us_max_fan_pwm
);
3910 smu7_notify_smc_display_change(struct pp_hwmgr
*hwmgr
, bool has_display
)
3912 PPSMC_Msg msg
= has_display
? (PPSMC_Msg
)PPSMC_HasDisplay
: (PPSMC_Msg
)PPSMC_NoDisplay
;
3914 return (smum_send_msg_to_smc(hwmgr
->smumgr
, msg
) == 0) ? 0 : -1;
3918 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
*hwmgr
)
3920 uint32_t num_active_displays
= 0;
3921 struct cgs_display_info info
= {0};
3923 info
.mode_info
= NULL
;
3924 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3926 num_active_displays
= info
.display_count
;
3928 if (num_active_displays
> 1 && hwmgr
->display_config
.multi_monitor_in_sync
!= true)
3929 smu7_notify_smc_display_change(hwmgr
, false);
3935 * Programs the display gap
3937 * @param hwmgr the address of the powerplay hardware manager.
3940 static int smu7_program_display_gap(struct pp_hwmgr
*hwmgr
)
3942 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
3943 uint32_t num_active_displays
= 0;
3944 uint32_t display_gap
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
);
3945 uint32_t display_gap2
;
3946 uint32_t pre_vbi_time_in_us
;
3947 uint32_t frame_time_in_us
;
3949 uint32_t refresh_rate
= 0;
3950 struct cgs_display_info info
= {0};
3951 struct cgs_mode_info mode_info
;
3953 info
.mode_info
= &mode_info
;
3955 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3956 num_active_displays
= info
.display_count
;
3958 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
, DISP_GAP
, (num_active_displays
> 0) ? DISPLAY_GAP_VBLANK_OR_WM
: DISPLAY_GAP_IGNORE
);
3959 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
, display_gap
);
3961 ref_clock
= mode_info
.ref_clock
;
3962 refresh_rate
= mode_info
.refresh_rate
;
3964 if (0 == refresh_rate
)
3967 frame_time_in_us
= 1000000 / refresh_rate
;
3969 pre_vbi_time_in_us
= frame_time_in_us
- 200 - mode_info
.vblank_time_us
;
3970 data
->frame_time_x2
= frame_time_in_us
* 2 / 100;
3972 display_gap2
= pre_vbi_time_in_us
* (ref_clock
/ 100);
3974 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL2
, display_gap2
);
3976 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3977 data
->soft_regs_start
+ smum_get_offsetof(hwmgr
->smumgr
,
3979 PreVBlankGap
), 0x64);
3981 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3982 data
->soft_regs_start
+ smum_get_offsetof(hwmgr
->smumgr
,
3985 (frame_time_in_us
- pre_vbi_time_in_us
));
3990 static int smu7_display_configuration_changed_task(struct pp_hwmgr
*hwmgr
)
3992 return smu7_program_display_gap(hwmgr
);
3996 * Set maximum target operating fan output RPM
3998 * @param hwmgr: the address of the powerplay hardware manager.
3999 * @param usMaxFanRpm: max operating fan RPM value.
4000 * @return The response that came from the SMC.
4002 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_rpm
)
4004 hwmgr
->thermal_controller
.
4005 advanceFanControlParameters
.usMaxFanRPM
= us_max_fan_rpm
;
4007 if (phm_is_hw_access_blocked(hwmgr
))
4010 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4011 PPSMC_MSG_SetFanRpmMax
, us_max_fan_rpm
);
4014 static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr
*hwmgr
,
4015 const void *thermal_interrupt_info
)
4021 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr
*hwmgr
)
4023 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4024 bool is_update_required
= false;
4025 struct cgs_display_info info
= {0, 0, NULL
};
4027 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4029 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
4030 is_update_required
= true;
4032 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_SclkDeepSleep
)) {
4033 if (data
->display_timing
.min_clock_in_sr
!= hwmgr
->display_config
.min_core_set_clock_in_sr
&&
4034 (data
->display_timing
.min_clock_in_sr
>= SMU7_MINIMUM_ENGINE_CLOCK
||
4035 hwmgr
->display_config
.min_core_set_clock_in_sr
>= SMU7_MINIMUM_ENGINE_CLOCK
))
4036 is_update_required
= true;
4038 return is_update_required
;
4041 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level
*pl1
,
4042 const struct smu7_performance_level
*pl2
)
4044 return ((pl1
->memory_clock
== pl2
->memory_clock
) &&
4045 (pl1
->engine_clock
== pl2
->engine_clock
) &&
4046 (pl1
->pcie_gen
== pl2
->pcie_gen
) &&
4047 (pl1
->pcie_lane
== pl2
->pcie_lane
));
4050 static int smu7_check_states_equal(struct pp_hwmgr
*hwmgr
,
4051 const struct pp_hw_power_state
*pstate1
,
4052 const struct pp_hw_power_state
*pstate2
, bool *equal
)
4054 const struct smu7_power_state
*psa
;
4055 const struct smu7_power_state
*psb
;
4058 if (pstate1
== NULL
|| pstate2
== NULL
|| equal
== NULL
)
4061 psa
= cast_const_phw_smu7_power_state(pstate1
);
4062 psb
= cast_const_phw_smu7_power_state(pstate2
);
4063 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4064 if (psa
->performance_level_count
!= psb
->performance_level_count
) {
4069 for (i
= 0; i
< psa
->performance_level_count
; i
++) {
4070 if (!smu7_are_power_levels_equal(&(psa
->performance_levels
[i
]), &(psb
->performance_levels
[i
]))) {
4071 /* If we have found even one performance level pair that is different the states are different. */
4077 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4078 *equal
= ((psa
->uvd_clks
.vclk
== psb
->uvd_clks
.vclk
) && (psa
->uvd_clks
.dclk
== psb
->uvd_clks
.dclk
));
4079 *equal
&= ((psa
->vce_clks
.evclk
== psb
->vce_clks
.evclk
) && (psa
->vce_clks
.ecclk
== psb
->vce_clks
.ecclk
));
4080 *equal
&= (psa
->sclk_threshold
== psb
->sclk_threshold
);
4085 static int smu7_upload_mc_firmware(struct pp_hwmgr
*hwmgr
)
4087 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4089 uint32_t vbios_version
;
4092 /* Read MC indirect register offset 0x9F bits [3:0] to see
4093 * if VBIOS has already loaded a full version of MC ucode
4097 smu7_get_mc_microcode_version(hwmgr
);
4098 vbios_version
= hwmgr
->microcode_version_info
.MC
& 0xf;
4100 data
->need_long_memory_training
= false;
4102 cgs_write_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_INDEX
,
4103 ixMC_IO_DEBUG_UP_13
);
4104 tmp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_DATA
);
4106 if (tmp
& (1 << 23)) {
4107 data
->mem_latency_high
= MEM_LATENCY_HIGH
;
4108 data
->mem_latency_low
= MEM_LATENCY_LOW
;
4110 data
->mem_latency_high
= 330;
4111 data
->mem_latency_low
= 330;
4117 static int smu7_read_clock_registers(struct pp_hwmgr
*hwmgr
)
4119 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4121 data
->clock_registers
.vCG_SPLL_FUNC_CNTL
=
4122 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL
);
4123 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
=
4124 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_2
);
4125 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
=
4126 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_3
);
4127 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
=
4128 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_4
);
4129 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
=
4130 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_SPREAD_SPECTRUM
);
4131 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
=
4132 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_SPREAD_SPECTRUM_2
);
4133 data
->clock_registers
.vDLL_CNTL
=
4134 cgs_read_register(hwmgr
->device
, mmDLL_CNTL
);
4135 data
->clock_registers
.vMCLK_PWRMGT_CNTL
=
4136 cgs_read_register(hwmgr
->device
, mmMCLK_PWRMGT_CNTL
);
4137 data
->clock_registers
.vMPLL_AD_FUNC_CNTL
=
4138 cgs_read_register(hwmgr
->device
, mmMPLL_AD_FUNC_CNTL
);
4139 data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
=
4140 cgs_read_register(hwmgr
->device
, mmMPLL_DQ_FUNC_CNTL
);
4141 data
->clock_registers
.vMPLL_FUNC_CNTL
=
4142 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL
);
4143 data
->clock_registers
.vMPLL_FUNC_CNTL_1
=
4144 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL_1
);
4145 data
->clock_registers
.vMPLL_FUNC_CNTL_2
=
4146 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL_2
);
4147 data
->clock_registers
.vMPLL_SS1
=
4148 cgs_read_register(hwmgr
->device
, mmMPLL_SS1
);
4149 data
->clock_registers
.vMPLL_SS2
=
4150 cgs_read_register(hwmgr
->device
, mmMPLL_SS2
);
4156 * Find out if memory is GDDR5.
4158 * @param hwmgr the address of the powerplay hardware manager.
4161 static int smu7_get_memory_type(struct pp_hwmgr
*hwmgr
)
4163 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4166 temp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC0
);
4168 data
->is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
==
4169 ((temp
& MC_SEQ_MISC0_GDDR5_MASK
) >>
4170 MC_SEQ_MISC0_GDDR5_SHIFT
));
4176 * Enables Dynamic Power Management by SMC
4178 * @param hwmgr the address of the powerplay hardware manager.
4181 static int smu7_enable_acpi_power_management(struct pp_hwmgr
*hwmgr
)
4183 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
4184 GENERAL_PWRMGT
, STATIC_PM_EN
, 1);
4190 * Initialize PowerGating States for different engines
4192 * @param hwmgr the address of the powerplay hardware manager.
4195 static int smu7_init_power_gate_state(struct pp_hwmgr
*hwmgr
)
4197 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4199 data
->uvd_power_gated
= false;
4200 data
->vce_power_gated
= false;
4201 data
->samu_power_gated
= false;
4206 static int smu7_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4208 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4210 data
->low_sclk_interrupt_threshold
= 0;
4214 static int smu7_setup_asic_task(struct pp_hwmgr
*hwmgr
)
4216 int tmp_result
, result
= 0;
4218 smu7_upload_mc_firmware(hwmgr
);
4220 tmp_result
= smu7_read_clock_registers(hwmgr
);
4221 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4222 "Failed to read clock registers!", result
= tmp_result
);
4224 tmp_result
= smu7_get_memory_type(hwmgr
);
4225 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4226 "Failed to get memory type!", result
= tmp_result
);
4228 tmp_result
= smu7_enable_acpi_power_management(hwmgr
);
4229 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4230 "Failed to enable ACPI power management!", result
= tmp_result
);
4232 tmp_result
= smu7_init_power_gate_state(hwmgr
);
4233 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4234 "Failed to init power gate state!", result
= tmp_result
);
4236 tmp_result
= smu7_get_mc_microcode_version(hwmgr
);
4237 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4238 "Failed to get MC microcode version!", result
= tmp_result
);
4240 tmp_result
= smu7_init_sclk_threshold(hwmgr
);
4241 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4242 "Failed to init sclk threshold!", result
= tmp_result
);
4247 static int smu7_force_clock_level(struct pp_hwmgr
*hwmgr
,
4248 enum pp_clock_type type
, uint32_t mask
)
4250 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4252 if (hwmgr
->dpm_level
& (AMD_DPM_FORCED_LEVEL_AUTO
|
4253 AMD_DPM_FORCED_LEVEL_LOW
|
4254 AMD_DPM_FORCED_LEVEL_HIGH
))
4259 if (!data
->sclk_dpm_key_disabled
)
4260 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4261 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4262 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
& mask
);
4265 if (!data
->mclk_dpm_key_disabled
)
4266 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4267 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4268 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& mask
);
4272 uint32_t tmp
= mask
& data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
4278 if (!data
->pcie_dpm_key_disabled
)
4279 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4280 PPSMC_MSG_PCIeDPM_ForceLevel
,
4291 static int smu7_print_clock_levels(struct pp_hwmgr
*hwmgr
,
4292 enum pp_clock_type type
, char *buf
)
4294 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4295 struct smu7_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
4296 struct smu7_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
4297 struct smu7_single_dpm_table
*pcie_table
= &(data
->dpm_table
.pcie_speed_table
);
4298 int i
, now
, size
= 0;
4299 uint32_t clock
, pcie_speed
;
4303 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
4304 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4306 for (i
= 0; i
< sclk_table
->count
; i
++) {
4307 if (clock
> sclk_table
->dpm_levels
[i
].value
)
4313 for (i
= 0; i
< sclk_table
->count
; i
++)
4314 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4315 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
4316 (i
== now
) ? "*" : "");
4319 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
4320 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4322 for (i
= 0; i
< mclk_table
->count
; i
++) {
4323 if (clock
> mclk_table
->dpm_levels
[i
].value
)
4329 for (i
= 0; i
< mclk_table
->count
; i
++)
4330 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
4331 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
4332 (i
== now
) ? "*" : "");
4335 pcie_speed
= smu7_get_current_pcie_speed(hwmgr
);
4336 for (i
= 0; i
< pcie_table
->count
; i
++) {
4337 if (pcie_speed
!= pcie_table
->dpm_levels
[i
].value
)
4343 for (i
= 0; i
< pcie_table
->count
; i
++)
4344 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
4345 (pcie_table
->dpm_levels
[i
].value
== 0) ? "2.5GB, x8" :
4346 (pcie_table
->dpm_levels
[i
].value
== 1) ? "5.0GB, x16" :
4347 (pcie_table
->dpm_levels
[i
].value
== 2) ? "8.0GB, x16" : "",
4348 (i
== now
) ? "*" : "");
4356 static int smu7_set_fan_control_mode(struct pp_hwmgr
*hwmgr
, uint32_t mode
)
4361 case AMD_FAN_CTRL_NONE
:
4362 result
= smu7_fan_ctrl_set_fan_speed_percent(hwmgr
, 100);
4364 case AMD_FAN_CTRL_MANUAL
:
4365 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4366 PHM_PlatformCaps_MicrocodeFanControl
))
4367 result
= smu7_fan_ctrl_stop_smc_fan_control(hwmgr
);
4369 case AMD_FAN_CTRL_AUTO
:
4370 result
= smu7_fan_ctrl_set_static_mode(hwmgr
, mode
);
4372 result
= smu7_fan_ctrl_start_smc_fan_control(hwmgr
);
4380 static int smu7_get_fan_control_mode(struct pp_hwmgr
*hwmgr
)
4382 return hwmgr
->fan_ctrl_enabled
? AMD_FAN_CTRL_AUTO
: AMD_FAN_CTRL_MANUAL
;
4385 static int smu7_get_sclk_od(struct pp_hwmgr
*hwmgr
)
4387 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4388 struct smu7_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
4389 struct smu7_single_dpm_table
*golden_sclk_table
=
4390 &(data
->golden_dpm_table
.sclk_table
);
4393 value
= (sclk_table
->dpm_levels
[sclk_table
->count
- 1].value
-
4394 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
) *
4396 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
4401 static int smu7_set_sclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
4403 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4404 struct smu7_single_dpm_table
*golden_sclk_table
=
4405 &(data
->golden_dpm_table
.sclk_table
);
4406 struct pp_power_state
*ps
;
4407 struct smu7_power_state
*smu7_ps
;
4412 ps
= hwmgr
->request_ps
;
4417 smu7_ps
= cast_phw_smu7_power_state(&ps
->hardware
);
4419 smu7_ps
->performance_levels
[smu7_ps
->performance_level_count
- 1].engine_clock
=
4420 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
*
4422 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
4427 static int smu7_get_mclk_od(struct pp_hwmgr
*hwmgr
)
4429 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4430 struct smu7_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
4431 struct smu7_single_dpm_table
*golden_mclk_table
=
4432 &(data
->golden_dpm_table
.mclk_table
);
4435 value
= (mclk_table
->dpm_levels
[mclk_table
->count
- 1].value
-
4436 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
) *
4438 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
4443 static int smu7_set_mclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
4445 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4446 struct smu7_single_dpm_table
*golden_mclk_table
=
4447 &(data
->golden_dpm_table
.mclk_table
);
4448 struct pp_power_state
*ps
;
4449 struct smu7_power_state
*smu7_ps
;
4454 ps
= hwmgr
->request_ps
;
4459 smu7_ps
= cast_phw_smu7_power_state(&ps
->hardware
);
4461 smu7_ps
->performance_levels
[smu7_ps
->performance_level_count
- 1].memory_clock
=
4462 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
*
4464 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
4470 static int smu7_get_sclks(struct pp_hwmgr
*hwmgr
, struct amd_pp_clocks
*clocks
)
4472 struct phm_ppt_v1_information
*table_info
=
4473 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
4474 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_sclk_table
= NULL
;
4475 struct phm_clock_voltage_dependency_table
*sclk_table
;
4478 if (hwmgr
->pp_table_version
== PP_TABLE_V1
) {
4479 if (table_info
== NULL
|| table_info
->vdd_dep_on_sclk
== NULL
)
4481 dep_sclk_table
= table_info
->vdd_dep_on_sclk
;
4482 for (i
= 0; i
< dep_sclk_table
->count
; i
++)
4483 clocks
->clock
[i
] = dep_sclk_table
->entries
[i
].clk
;
4484 clocks
->count
= dep_sclk_table
->count
;
4485 } else if (hwmgr
->pp_table_version
== PP_TABLE_V0
) {
4486 sclk_table
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
;
4487 for (i
= 0; i
< sclk_table
->count
; i
++)
4488 clocks
->clock
[i
] = sclk_table
->entries
[i
].clk
;
4489 clocks
->count
= sclk_table
->count
;
4495 static uint32_t smu7_get_mem_latency(struct pp_hwmgr
*hwmgr
, uint32_t clk
)
4497 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4499 if (clk
>= MEM_FREQ_LOW_LATENCY
&& clk
< MEM_FREQ_HIGH_LATENCY
)
4500 return data
->mem_latency_high
;
4501 else if (clk
>= MEM_FREQ_HIGH_LATENCY
)
4502 return data
->mem_latency_low
;
4504 return MEM_LATENCY_ERR
;
4507 static int smu7_get_mclks(struct pp_hwmgr
*hwmgr
, struct amd_pp_clocks
*clocks
)
4509 struct phm_ppt_v1_information
*table_info
=
4510 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
4511 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
;
4513 struct phm_clock_voltage_dependency_table
*mclk_table
;
4515 if (hwmgr
->pp_table_version
== PP_TABLE_V1
) {
4516 if (table_info
== NULL
)
4518 dep_mclk_table
= table_info
->vdd_dep_on_mclk
;
4519 for (i
= 0; i
< dep_mclk_table
->count
; i
++) {
4520 clocks
->clock
[i
] = dep_mclk_table
->entries
[i
].clk
;
4521 clocks
->latency
[i
] = smu7_get_mem_latency(hwmgr
,
4522 dep_mclk_table
->entries
[i
].clk
);
4524 clocks
->count
= dep_mclk_table
->count
;
4525 } else if (hwmgr
->pp_table_version
== PP_TABLE_V0
) {
4526 mclk_table
= hwmgr
->dyn_state
.vddc_dependency_on_mclk
;
4527 for (i
= 0; i
< mclk_table
->count
; i
++)
4528 clocks
->clock
[i
] = mclk_table
->entries
[i
].clk
;
4529 clocks
->count
= mclk_table
->count
;
4534 static int smu7_get_clock_by_type(struct pp_hwmgr
*hwmgr
, enum amd_pp_clock_type type
,
4535 struct amd_pp_clocks
*clocks
)
4538 case amd_pp_sys_clock
:
4539 smu7_get_sclks(hwmgr
, clocks
);
4541 case amd_pp_mem_clock
:
4542 smu7_get_mclks(hwmgr
, clocks
);
4551 static void smu7_find_min_clock_masks(struct pp_hwmgr
*hwmgr
,
4552 uint32_t *sclk_mask
, uint32_t *mclk_mask
,
4553 uint32_t min_sclk
, uint32_t min_mclk
)
4555 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4556 struct smu7_dpm_table
*dpm_table
= &(data
->dpm_table
);
4559 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
4560 if (dpm_table
->sclk_table
.dpm_levels
[i
].enabled
&&
4561 dpm_table
->sclk_table
.dpm_levels
[i
].value
>= min_sclk
)
4562 *sclk_mask
|= 1 << i
;
4565 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
4566 if (dpm_table
->mclk_table
.dpm_levels
[i
].enabled
&&
4567 dpm_table
->mclk_table
.dpm_levels
[i
].value
>= min_mclk
)
4568 *mclk_mask
|= 1 << i
;
4572 static int smu7_set_power_profile_state(struct pp_hwmgr
*hwmgr
,
4573 struct amd_pp_profile
*request
)
4575 struct smu7_hwmgr
*data
= (struct smu7_hwmgr
*)(hwmgr
->backend
);
4576 int tmp_result
, result
= 0;
4577 uint32_t sclk_mask
= 0, mclk_mask
= 0;
4579 if (hwmgr
->chip_id
== CHIP_FIJI
) {
4580 if (request
->type
== AMD_PP_GFX_PROFILE
)
4581 smu7_enable_power_containment(hwmgr
);
4582 else if (request
->type
== AMD_PP_COMPUTE_PROFILE
)
4583 smu7_disable_power_containment(hwmgr
);
4586 if (hwmgr
->dpm_level
!= AMD_DPM_FORCED_LEVEL_AUTO
)
4589 tmp_result
= smu7_freeze_sclk_mclk_dpm(hwmgr
);
4590 PP_ASSERT_WITH_CODE(!tmp_result
,
4591 "Failed to freeze SCLK MCLK DPM!",
4592 result
= tmp_result
);
4594 tmp_result
= smum_populate_requested_graphic_levels(hwmgr
, request
);
4595 PP_ASSERT_WITH_CODE(!tmp_result
,
4596 "Failed to populate requested graphic levels!",
4597 result
= tmp_result
);
4599 tmp_result
= smu7_unfreeze_sclk_mclk_dpm(hwmgr
);
4600 PP_ASSERT_WITH_CODE(!tmp_result
,
4601 "Failed to unfreeze SCLK MCLK DPM!",
4602 result
= tmp_result
);
4604 smu7_find_min_clock_masks(hwmgr
, &sclk_mask
, &mclk_mask
,
4605 request
->min_sclk
, request
->min_mclk
);
4608 if (!data
->sclk_dpm_key_disabled
)
4609 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4610 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4611 data
->dpm_level_enable_mask
.
4612 sclk_dpm_enable_mask
&
4617 if (!data
->mclk_dpm_key_disabled
)
4618 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4619 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4620 data
->dpm_level_enable_mask
.
4621 mclk_dpm_enable_mask
&
4628 static int smu7_avfs_control(struct pp_hwmgr
*hwmgr
, bool enable
)
4630 struct pp_smumgr
*smumgr
= (struct pp_smumgr
*)(hwmgr
->smumgr
);
4631 struct smu7_smumgr
*smu_data
= (struct smu7_smumgr
*)(smumgr
->backend
);
4633 if (smu_data
== NULL
)
4636 if (smu_data
->avfs
.avfs_btc_status
== AVFS_BTC_NOTSUPPORTED
)
4640 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
,
4641 CGS_IND_REG__SMC
, FEATURE_STATUS
, AVS_ON
))
4642 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4643 hwmgr
->smumgr
, PPSMC_MSG_EnableAvfs
),
4644 "Failed to enable AVFS!",
4646 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
,
4647 CGS_IND_REG__SMC
, FEATURE_STATUS
, AVS_ON
))
4648 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
4649 hwmgr
->smumgr
, PPSMC_MSG_DisableAvfs
),
4650 "Failed to disable AVFS!",
4656 static const struct pp_hwmgr_func smu7_hwmgr_funcs
= {
4657 .backend_init
= &smu7_hwmgr_backend_init
,
4658 .backend_fini
= &smu7_hwmgr_backend_fini
,
4659 .asic_setup
= &smu7_setup_asic_task
,
4660 .dynamic_state_management_enable
= &smu7_enable_dpm_tasks
,
4661 .apply_state_adjust_rules
= smu7_apply_state_adjust_rules
,
4662 .force_dpm_level
= &smu7_force_dpm_level
,
4663 .power_state_set
= smu7_set_power_state_tasks
,
4664 .get_power_state_size
= smu7_get_power_state_size
,
4665 .get_mclk
= smu7_dpm_get_mclk
,
4666 .get_sclk
= smu7_dpm_get_sclk
,
4667 .patch_boot_state
= smu7_dpm_patch_boot_state
,
4668 .get_pp_table_entry
= smu7_get_pp_table_entry
,
4669 .get_num_of_pp_table_entries
= smu7_get_number_of_powerplay_table_entries
,
4670 .powerdown_uvd
= smu7_powerdown_uvd
,
4671 .powergate_uvd
= smu7_powergate_uvd
,
4672 .powergate_vce
= smu7_powergate_vce
,
4673 .disable_clock_power_gating
= smu7_disable_clock_power_gating
,
4674 .update_clock_gatings
= smu7_update_clock_gatings
,
4675 .notify_smc_display_config_after_ps_adjustment
= smu7_notify_smc_display_config_after_ps_adjustment
,
4676 .display_config_changed
= smu7_display_configuration_changed_task
,
4677 .set_max_fan_pwm_output
= smu7_set_max_fan_pwm_output
,
4678 .set_max_fan_rpm_output
= smu7_set_max_fan_rpm_output
,
4679 .get_temperature
= smu7_thermal_get_temperature
,
4680 .stop_thermal_controller
= smu7_thermal_stop_thermal_controller
,
4681 .get_fan_speed_info
= smu7_fan_ctrl_get_fan_speed_info
,
4682 .get_fan_speed_percent
= smu7_fan_ctrl_get_fan_speed_percent
,
4683 .set_fan_speed_percent
= smu7_fan_ctrl_set_fan_speed_percent
,
4684 .reset_fan_speed_to_default
= smu7_fan_ctrl_reset_fan_speed_to_default
,
4685 .get_fan_speed_rpm
= smu7_fan_ctrl_get_fan_speed_rpm
,
4686 .set_fan_speed_rpm
= smu7_fan_ctrl_set_fan_speed_rpm
,
4687 .uninitialize_thermal_controller
= smu7_thermal_ctrl_uninitialize_thermal_controller
,
4688 .register_internal_thermal_interrupt
= smu7_register_internal_thermal_interrupt
,
4689 .check_smc_update_required_for_display_configuration
= smu7_check_smc_update_required_for_display_configuration
,
4690 .check_states_equal
= smu7_check_states_equal
,
4691 .set_fan_control_mode
= smu7_set_fan_control_mode
,
4692 .get_fan_control_mode
= smu7_get_fan_control_mode
,
4693 .force_clock_level
= smu7_force_clock_level
,
4694 .print_clock_levels
= smu7_print_clock_levels
,
4695 .enable_per_cu_power_gating
= smu7_enable_per_cu_power_gating
,
4696 .get_sclk_od
= smu7_get_sclk_od
,
4697 .set_sclk_od
= smu7_set_sclk_od
,
4698 .get_mclk_od
= smu7_get_mclk_od
,
4699 .set_mclk_od
= smu7_set_mclk_od
,
4700 .get_clock_by_type
= smu7_get_clock_by_type
,
4701 .read_sensor
= smu7_read_sensor
,
4702 .dynamic_state_management_disable
= smu7_disable_dpm_tasks
,
4703 .set_power_profile_state
= smu7_set_power_profile_state
,
4704 .avfs_control
= smu7_avfs_control
,
4705 .disable_smc_firmware_ctf
= smu7_thermal_disable_alert
,
4708 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock
,
4709 uint32_t clock_insr
)
4713 uint32_t min
= max(clock_insr
, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK
);
4715 PP_ASSERT_WITH_CODE((clock
>= min
), "Engine clock can't satisfy stutter requirement!", return 0);
4716 for (i
= SMU7_MAX_DEEPSLEEP_DIVIDER_ID
; ; i
--) {
4719 if (temp
>= min
|| i
== 0)
4725 int smu7_init_function_pointers(struct pp_hwmgr
*hwmgr
)
4729 hwmgr
->hwmgr_func
= &smu7_hwmgr_funcs
;
4730 if (hwmgr
->pp_table_version
== PP_TABLE_V0
)
4731 hwmgr
->pptable_func
= &pptable_funcs
;
4732 else if (hwmgr
->pp_table_version
== PP_TABLE_V1
)
4733 hwmgr
->pptable_func
= &pptable_v1_0_funcs
;