drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26
  27 #include "tonga_processpptables.h"
  28 #include "ppatomctrl.h"
  29 #include "atombios.h"
  30 #include "pp_debug.h"
  31 #include "hwmgr.h"
  32 #include "cgs_common.h"
  33 #include "tonga_pptable.h"
  34
  35 /**
  36  * Private Function used during initialization.
  37  * @param hwmgr Pointer to the hardware manager.
  38  * @param setIt A flag indication if the capability should be set (TRUE) or reset (FALSE).
  39  * @param cap Which capability to set/reset.
  40  */
  41 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
  42 {
  43         if (setIt)
  44                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
  45         else
  46                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
  47 }
  48
  49
  50 /**
  51  * Private Function used during initialization.
  52  * @param hwmgr Pointer to the hardware manager.
  53  * @param powerplay_caps the bit array (from BIOS) of capability bits.
  54  * @exception the current implementation always returns 1.
  55  */
  56 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
  57 {
  58         PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),
  59                 "ATOM_PP_PLATFORM_CAP_ASPM_L1 is not supported!", continue);
  60         PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),
  61                 "ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY is not supported!", continue);
  62         PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),
  63                 "ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL is not supported!", continue);
  64         PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),
  65                 "ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 is not supported!", continue);
  66         PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),
  67                 "ATOM_PP_PLATFORM_CAP_HTLINKCONTROL is not supported!", continue);
  68
  69         set_hw_cap(
  70                         hwmgr,
  71                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY),
  72                         PHM_PlatformCaps_PowerPlaySupport
  73                   );
  74
  75         set_hw_cap(
  76                         hwmgr,
  77                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
  78                         PHM_PlatformCaps_BiosPowerSourceControl
  79                   );
  80
  81         set_hw_cap(
  82                         hwmgr,
  83                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC),
  84                         PHM_PlatformCaps_AutomaticDCTransition
  85                   );
  86
  87         set_hw_cap(
  88                         hwmgr,
  89                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL),
  90                         PHM_PlatformCaps_EnableMVDDControl
  91                   );
  92
  93         set_hw_cap(
  94                         hwmgr,
  95                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL),
  96                         PHM_PlatformCaps_ControlVDDCI
  97                   );
  98
  99         set_hw_cap(
 100                         hwmgr,
 101                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL),
 102                         PHM_PlatformCaps_ControlVDDGFX
 103                   );
 104
 105         set_hw_cap(
 106                         hwmgr,
 107                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_BACO),
 108                         PHM_PlatformCaps_BACO
 109                   );
 110
 111         set_hw_cap(
 112                         hwmgr,
 113                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND),
 114                         PHM_PlatformCaps_DisableVoltageIsland
 115                   );
 116
 117         set_hw_cap(
 118                         hwmgr,
 119                         0 != (powerplay_caps & ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
 120                         PHM_PlatformCaps_CombinePCCWithThermalSignal
 121                   );
 122
 123         set_hw_cap(
 124                         hwmgr,
 125                         0 != (powerplay_caps & ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE),
 126                         PHM_PlatformCaps_LoadPostProductionFirmware
 127                   );
 128
 129         return 0;
 130 }
 131
 132 /**
 133  * Private Function to get the PowerPlay Table Address.
 134  */
 135 const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
 136 {
 137         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 138
 139         u16 size;
 140         u8 frev, crev;
 141         void *table_address = (void *)hwmgr->soft_pp_table;
 142
 143         if (!table_address) {
 144                 table_address = (ATOM_Tonga_POWERPLAYTABLE *)
 145                                 cgs_atom_get_data_table(hwmgr->device,
 146                                                 index, &size, &frev, &crev);
 147                 hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
 148                 hwmgr->soft_pp_table_size = size;
 149         }
 150
 151         return table_address;
 152 }
 153
 154 static int get_vddc_lookup_table(
 155                 struct pp_hwmgr *hwmgr,
 156                 phm_ppt_v1_voltage_lookup_table **lookup_table,
 157                 const ATOM_Tonga_Voltage_Lookup_Table   *vddc_lookup_pp_tables,
 158                 uint32_t        max_levels
 159                 )
 160 {
 161         uint32_t table_size, i;
 162         phm_ppt_v1_voltage_lookup_table *table;
 163
 164         PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
 165                 "Invalid CAC Leakage PowerPlay Table!", return 1);
 166
 167         table_size = sizeof(uint32_t) +
 168                 sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
 169
 170         table = (phm_ppt_v1_voltage_lookup_table *)
 171                 kzalloc(table_size, GFP_KERNEL);
 172
 173         if (NULL == table)
 174                 return -ENOMEM;
 175
 176         memset(table, 0x00, table_size);
 177
 178         table->count = vddc_lookup_pp_tables->ucNumEntries;
 179
 180         for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
 181                 table->entries[i].us_calculated = 0;
 182                 table->entries[i].us_vdd =
 183                         vddc_lookup_pp_tables->entries[i].usVdd;
 184                 table->entries[i].us_cac_low =
 185                         vddc_lookup_pp_tables->entries[i].usCACLow;
 186                 table->entries[i].us_cac_mid =
 187                         vddc_lookup_pp_tables->entries[i].usCACMid;
 188                 table->entries[i].us_cac_high =
 189                         vddc_lookup_pp_tables->entries[i].usCACHigh;
 190         }
 191
 192         *lookup_table = table;
 193
 194         return 0;
 195 }
 196
 197 /**
 198  * Private Function used during initialization.
 199  * Initialize Platform Power Management Parameter table
 200  * @param hwmgr Pointer to the hardware manager.
 201  * @param atom_ppm_table Pointer to PPM table in VBIOS
 202  */
 203 static int get_platform_power_management_table(
 204                 struct pp_hwmgr *hwmgr,
 205                 ATOM_Tonga_PPM_Table *atom_ppm_table)
 206 {
 207         struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL);
 208         struct phm_ppt_v1_information *pp_table_information =
 209                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
 210
 211         if (NULL == ptr)
 212                 return -ENOMEM;
 213
 214         ptr->ppm_design
 215                 = atom_ppm_table->ucPpmDesign;
 216         ptr->cpu_core_number
 217                 = atom_ppm_table->usCpuCoreNumber;
 218         ptr->platform_tdp
 219                 = atom_ppm_table->ulPlatformTDP;
 220         ptr->small_ac_platform_tdp
 221                 = atom_ppm_table->ulSmallACPlatformTDP;
 222         ptr->platform_tdc
 223                 = atom_ppm_table->ulPlatformTDC;
 224         ptr->small_ac_platform_tdc
 225                 = atom_ppm_table->ulSmallACPlatformTDC;
 226         ptr->apu_tdp
 227                 = atom_ppm_table->ulApuTDP;
 228         ptr->dgpu_tdp
 229                 = atom_ppm_table->ulDGpuTDP;
 230         ptr->dgpu_ulv_power
 231                 = atom_ppm_table->ulDGpuUlvPower;
 232         ptr->tj_max
 233                 = atom_ppm_table->ulTjmax;
 234
 235         pp_table_information->ppm_parameter_table = ptr;
 236
 237         return 0;
 238 }
 239
 240 /**
 241  * Private Function used during initialization.
 242  * Initialize TDP limits for DPM2
 243  * @param hwmgr Pointer to the hardware manager.
 244  * @param powerplay_table Pointer to the PowerPlay Table.
 245  */
 246 static int init_dpm_2_parameters(
 247                 struct pp_hwmgr *hwmgr,
 248                 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
 249                 )
 250 {
 251         int result = 0;
 252         struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
 253         ATOM_Tonga_PPM_Table *atom_ppm_table;
 254         uint32_t disable_ppm = 0;
 255         uint32_t disable_power_control = 0;
 256
 257         pp_table_information->us_ulv_voltage_offset =
 258                 le16_to_cpu(powerplay_table->usUlvVoltageOffset);
 259
 260         pp_table_information->ppm_parameter_table = NULL;
 261         pp_table_information->vddc_lookup_table = NULL;
 262         pp_table_information->vddgfx_lookup_table = NULL;
 263         /* TDP limits */
 264         hwmgr->platform_descriptor.TDPODLimit =
 265                 le16_to_cpu(powerplay_table->usPowerControlLimit);
 266         hwmgr->platform_descriptor.TDPAdjustment = 0;
 267         hwmgr->platform_descriptor.VidAdjustment = 0;
 268         hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
 269         hwmgr->platform_descriptor.VidMinLimit = 0;
 270         hwmgr->platform_descriptor.VidMaxLimit = 1500000;
 271         hwmgr->platform_descriptor.VidStep = 6250;
 272
 273         disable_power_control = 0;
 274         if (0 == disable_power_control) {
 275                 /* enable TDP overdrive (PowerControl) feature as well if supported */
 276                 if (hwmgr->platform_descriptor.TDPODLimit != 0)
 277                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 278                         PHM_PlatformCaps_PowerControl);
 279         }
 280
 281         if (0 != powerplay_table->usVddcLookupTableOffset) {
 282                 const ATOM_Tonga_Voltage_Lookup_Table *pVddcCACTable =
 283                         (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
 284                         le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
 285
 286                 result = get_vddc_lookup_table(hwmgr,
 287                         &pp_table_information->vddc_lookup_table, pVddcCACTable, 16);
 288         }
 289
 290         if (0 != powerplay_table->usVddgfxLookupTableOffset) {
 291                 const ATOM_Tonga_Voltage_Lookup_Table *pVddgfxCACTable =
 292                         (ATOM_Tonga_Voltage_Lookup_Table *)(((unsigned long)powerplay_table) +
 293                         le16_to_cpu(powerplay_table->usVddgfxLookupTableOffset));
 294
 295                 result = get_vddc_lookup_table(hwmgr,
 296                         &pp_table_information->vddgfx_lookup_table, pVddgfxCACTable, 16);
 297         }
 298
 299         disable_ppm = 0;
 300         if (0 == disable_ppm) {
 301                 atom_ppm_table = (ATOM_Tonga_PPM_Table *)
 302                         (((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset));
 303
 304                 if (0 != powerplay_table->usPPMTableOffset) {
 305                         if (1 == get_platform_power_management_table(hwmgr, atom_ppm_table)) {
 306                                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 307                                         PHM_PlatformCaps_EnablePlatformPowerManagement);
 308                         }
 309                 }
 310         }
 311
 312         return result;
 313 }
 314
 315 static int get_valid_clk(
 316                 struct pp_hwmgr *hwmgr,
 317                 struct phm_clock_array **clk_table,
 318                 const phm_ppt_v1_clock_voltage_dependency_table  * clk_volt_pp_table
 319                 )
 320 {
 321         uint32_t table_size, i;
 322         struct phm_clock_array *table;
 323
 324         PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
 325                 "Invalid PowerPlay Table!", return -1);
 326
 327         table_size = sizeof(uint32_t) +
 328                 sizeof(uint32_t) * clk_volt_pp_table->count;
 329
 330         table = (struct phm_clock_array *)kzalloc(table_size, GFP_KERNEL);
 331
 332         if (NULL == table)
 333                 return -ENOMEM;
 334
 335         memset(table, 0x00, table_size);
 336
 337         table->count = (uint32_t)clk_volt_pp_table->count;
 338
 339         for (i = 0; i < table->count; i++)
 340                 table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
 341
 342         *clk_table = table;
 343
 344         return 0;
 345 }
 346
 347 static int get_hard_limits(
 348                 struct pp_hwmgr *hwmgr,
 349                 struct phm_clock_and_voltage_limits *limits,
 350                 const ATOM_Tonga_Hard_Limit_Table * limitable
 351                 )
 352 {
 353         PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);
 354
 355         /* currently we always take entries[0] parameters */
 356         limits->sclk = (uint32_t)limitable->entries[0].ulSCLKLimit;
 357         limits->mclk = (uint32_t)limitable->entries[0].ulMCLKLimit;
 358         limits->vddc = (uint16_t)limitable->entries[0].usVddcLimit;
 359         limits->vddci = (uint16_t)limitable->entries[0].usVddciLimit;
 360         limits->vddgfx = (uint16_t)limitable->entries[0].usVddgfxLimit;
 361
 362         return 0;
 363 }
 364
 365 static int get_mclk_voltage_dependency_table(
 366                 struct pp_hwmgr *hwmgr,
 367                 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_mclk_dep_table,
 368                 const ATOM_Tonga_MCLK_Dependency_Table * mclk_dep_table
 369                 )
 370 {
 371         uint32_t table_size, i;
 372         phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
 373
 374         PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
 375                 "Invalid PowerPlay Table!", return -1);
 376
 377         table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
 378                 * mclk_dep_table->ucNumEntries;
 379
 380         mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
 381                 kzalloc(table_size, GFP_KERNEL);
 382
 383         if (NULL == mclk_table)
 384                 return -ENOMEM;
 385
 386         memset(mclk_table, 0x00, table_size);
 387
 388         mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
 389
 390         for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
 391                 mclk_table->entries[i].vddInd =
 392                         mclk_dep_table->entries[i].ucVddcInd;
 393                 mclk_table->entries[i].vdd_offset =
 394                         mclk_dep_table->entries[i].usVddgfxOffset;
 395                 mclk_table->entries[i].vddci =
 396                         mclk_dep_table->entries[i].usVddci;
 397                 mclk_table->entries[i].mvdd =
 398                         mclk_dep_table->entries[i].usMvdd;
 399                 mclk_table->entries[i].clk =
 400                         mclk_dep_table->entries[i].ulMclk;
 401         }
 402
 403         *pp_tonga_mclk_dep_table = mclk_table;
 404
 405         return 0;
 406 }
 407
 408 static int get_sclk_voltage_dependency_table(
 409                 struct pp_hwmgr *hwmgr,
 410                 phm_ppt_v1_clock_voltage_dependency_table **pp_tonga_sclk_dep_table,
 411                 const ATOM_Tonga_SCLK_Dependency_Table * sclk_dep_table
 412                 )
 413 {
 414         uint32_t table_size, i;
 415         phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
 416
 417         PP_ASSERT_WITH_CODE((0 != sclk_dep_table->ucNumEntries),
 418                 "Invalid PowerPlay Table!", return -1);
 419
 420         table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
 421                 * sclk_dep_table->ucNumEntries;
 422
 423         sclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
 424                 kzalloc(table_size, GFP_KERNEL);
 425
 426         if (NULL == sclk_table)
 427                 return -ENOMEM;
 428
 429         memset(sclk_table, 0x00, table_size);
 430
 431         sclk_table->count = (uint32_t)sclk_dep_table->ucNumEntries;
 432
 433         for (i = 0; i < sclk_dep_table->ucNumEntries; i++) {
 434                 sclk_table->entries[i].vddInd =
 435                         sclk_dep_table->entries[i].ucVddInd;
 436                 sclk_table->entries[i].vdd_offset =
 437                         sclk_dep_table->entries[i].usVddcOffset;
 438                 sclk_table->entries[i].clk =
 439                         sclk_dep_table->entries[i].ulSclk;
 440                 sclk_table->entries[i].cks_enable =
 441                         (((sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
 442                 sclk_table->entries[i].cks_voffset =
 443                         (sclk_dep_table->entries[i].ucCKSVOffsetandDisable & 0x7F);
 444         }
 445
 446         *pp_tonga_sclk_dep_table = sclk_table;
 447
 448         return 0;
 449 }
 450
 451 static int get_pcie_table(
 452                 struct pp_hwmgr *hwmgr,
 453                 phm_ppt_v1_pcie_table **pp_tonga_pcie_table,
 454                 const PPTable_Generic_SubTable_Header * pTable
 455                 )
 456 {
 457         uint32_t table_size, i, pcie_count;
 458         phm_ppt_v1_pcie_table *pcie_table;
 459         struct phm_ppt_v1_information *pp_table_information =
 460                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
 461
 462         if (pTable->ucRevId < 1) {
 463                 const ATOM_Tonga_PCIE_Table *atom_pcie_table = (ATOM_Tonga_PCIE_Table *)pTable;
 464                 PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
 465                         "Invalid PowerPlay Table!", return -1);
 466
 467                 table_size = sizeof(uint32_t) +
 468                         sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
 469
 470                 pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
 471
 472                 if (pcie_table == NULL)
 473                         return -ENOMEM;
 474
 475                 memset(pcie_table, 0x00, table_size);
 476
 477                 /*
 478                 * Make sure the number of pcie entries are less than or equal to sclk dpm levels.
 479                 * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
 480                 */
 481                 pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
 482                 if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
 483                         pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
 484                 else
 485                         printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
 486                         Disregarding the excess entries... \n");
 487
 488                 pcie_table->count = pcie_count;
 489
 490                 for (i = 0; i < pcie_count; i++) {
 491                         pcie_table->entries[i].gen_speed =
 492                                 atom_pcie_table->entries[i].ucPCIEGenSpeed;
 493                         pcie_table->entries[i].lane_width =
 494                                 atom_pcie_table->entries[i].usPCIELaneWidth;
 495                 }
 496
 497                 *pp_tonga_pcie_table = pcie_table;
 498         } else {
 499                 /* Polaris10/Polaris11 and newer. */
 500                 const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable;
 501                 PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
 502                         "Invalid PowerPlay Table!", return -1);
 503
 504                 table_size = sizeof(uint32_t) +
 505                         sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
 506
 507                 pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL);
 508
 509                 if (pcie_table == NULL)
 510                         return -ENOMEM;
 511
 512                 memset(pcie_table, 0x00, table_size);
 513
 514                 /*
 515                 * Make sure the number of pcie entries are less than or equal to sclk dpm levels.
 516                 * Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
 517                 */
 518                 pcie_count = (pp_table_information->vdd_dep_on_sclk->count) + 1;
 519                 if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
 520                         pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
 521                 else
 522                         printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
 523                         Disregarding the excess entries... \n");
 524
 525                 pcie_table->count = pcie_count;
 526
 527                 for (i = 0; i < pcie_count; i++) {
 528                         pcie_table->entries[i].gen_speed =
 529                                 atom_pcie_table->entries[i].ucPCIEGenSpeed;
 530                         pcie_table->entries[i].lane_width =
 531                                 atom_pcie_table->entries[i].usPCIELaneWidth;
 532                         pcie_table->entries[i].pcie_sclk =
 533                                 atom_pcie_table->entries[i].ulPCIE_Sclk;
 534                 }
 535
 536                 *pp_tonga_pcie_table = pcie_table;
 537         }
 538
 539         return 0;
 540 }
 541
 542 static int get_cac_tdp_table(
 543                 struct pp_hwmgr *hwmgr,
 544                 struct phm_cac_tdp_table **cac_tdp_table,
 545                 const PPTable_Generic_SubTable_Header * table
 546                 )
 547 {
 548         uint32_t table_size;
 549         struct phm_cac_tdp_table *tdp_table;
 550
 551         table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);
 552         tdp_table = kzalloc(table_size, GFP_KERNEL);
 553
 554         if (NULL == tdp_table)
 555                 return -ENOMEM;
 556
 557         memset(tdp_table, 0x00, table_size);
 558
 559         hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
 560
 561         if (NULL == hwmgr->dyn_state.cac_dtp_table) {
 562                 kfree(tdp_table);
 563                 return -ENOMEM;
 564         }
 565
 566         memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
 567
 568         if (table->ucRevId < 3) {
 569                 const ATOM_Tonga_PowerTune_Table *tonga_table =
 570                         (ATOM_Tonga_PowerTune_Table *)table;
 571                 tdp_table->usTDP = tonga_table->usTDP;
 572                 tdp_table->usConfigurableTDP =
 573                         tonga_table->usConfigurableTDP;
 574                 tdp_table->usTDC = tonga_table->usTDC;
 575                 tdp_table->usBatteryPowerLimit =
 576                         tonga_table->usBatteryPowerLimit;
 577                 tdp_table->usSmallPowerLimit =
 578                         tonga_table->usSmallPowerLimit;
 579                 tdp_table->usLowCACLeakage =
 580                         tonga_table->usLowCACLeakage;
 581                 tdp_table->usHighCACLeakage =
 582                         tonga_table->usHighCACLeakage;
 583                 tdp_table->usMaximumPowerDeliveryLimit =
 584                         tonga_table->usMaximumPowerDeliveryLimit;
 585                 tdp_table->usDefaultTargetOperatingTemp =
 586                         tonga_table->usTjMax;
 587                 tdp_table->usTargetOperatingTemp =
 588                         tonga_table->usTjMax; /*Set the initial temp to the same as default */
 589                 tdp_table->usPowerTuneDataSetID =
 590                         tonga_table->usPowerTuneDataSetID;
 591                 tdp_table->usSoftwareShutdownTemp =
 592                         tonga_table->usSoftwareShutdownTemp;
 593                 tdp_table->usClockStretchAmount =
 594                         tonga_table->usClockStretchAmount;
 595         } else {   /* Fiji and newer */
 596                 const ATOM_Fiji_PowerTune_Table *fijitable =
 597                         (ATOM_Fiji_PowerTune_Table *)table;
 598                 tdp_table->usTDP = fijitable->usTDP;
 599                 tdp_table->usConfigurableTDP = fijitable->usConfigurableTDP;
 600                 tdp_table->usTDC = fijitable->usTDC;
 601                 tdp_table->usBatteryPowerLimit = fijitable->usBatteryPowerLimit;
 602                 tdp_table->usSmallPowerLimit = fijitable->usSmallPowerLimit;
 603                 tdp_table->usLowCACLeakage = fijitable->usLowCACLeakage;
 604                 tdp_table->usHighCACLeakage = fijitable->usHighCACLeakage;
 605                 tdp_table->usMaximumPowerDeliveryLimit =
 606                         fijitable->usMaximumPowerDeliveryLimit;
 607                 tdp_table->usDefaultTargetOperatingTemp =
 608                         fijitable->usTjMax;
 609                 tdp_table->usTargetOperatingTemp =
 610                         fijitable->usTjMax; /*Set the initial temp to the same as default */
 611                 tdp_table->usPowerTuneDataSetID =
 612                         fijitable->usPowerTuneDataSetID;
 613                 tdp_table->usSoftwareShutdownTemp =
 614                         fijitable->usSoftwareShutdownTemp;
 615                 tdp_table->usClockStretchAmount =
 616                         fijitable->usClockStretchAmount;
 617                 tdp_table->usTemperatureLimitHotspot =
 618                         fijitable->usTemperatureLimitHotspot;
 619                 tdp_table->usTemperatureLimitLiquid1 =
 620                         fijitable->usTemperatureLimitLiquid1;
 621                 tdp_table->usTemperatureLimitLiquid2 =
 622                         fijitable->usTemperatureLimitLiquid2;
 623                 tdp_table->usTemperatureLimitVrVddc =
 624                         fijitable->usTemperatureLimitVrVddc;
 625                 tdp_table->usTemperatureLimitVrMvdd =
 626                         fijitable->usTemperatureLimitVrMvdd;
 627                 tdp_table->usTemperatureLimitPlx =
 628                         fijitable->usTemperatureLimitPlx;
 629                 tdp_table->ucLiquid1_I2C_address =
 630                         fijitable->ucLiquid1_I2C_address;
 631                 tdp_table->ucLiquid2_I2C_address =
 632                         fijitable->ucLiquid2_I2C_address;
 633                 tdp_table->ucLiquid_I2C_Line =
 634                         fijitable->ucLiquid_I2C_Line;
 635                 tdp_table->ucVr_I2C_address = fijitable->ucVr_I2C_address;
 636                 tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
 637                 tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
 638                 tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
 639         }
 640
 641         *cac_tdp_table = tdp_table;
 642
 643         return 0;
 644 }
 645
 646 static int get_mm_clock_voltage_table(
 647                 struct pp_hwmgr *hwmgr,
 648                 phm_ppt_v1_mm_clock_voltage_dependency_table **tonga_mm_table,
 649                 const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table
 650                 )
 651 {
 652         uint32_t table_size, i;
 653         const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record;
 654         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
 655
 656         PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),
 657                 "Invalid PowerPlay Table!", return -1);
 658         table_size = sizeof(uint32_t) +
 659                 sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record)
 660                 * mm_dependency_table->ucNumEntries;
 661         mm_table = (phm_ppt_v1_mm_clock_voltage_dependency_table *)
 662                 kzalloc(table_size, GFP_KERNEL);
 663
 664         if (NULL == mm_table)
 665                 return -ENOMEM;
 666
 667         memset(mm_table, 0x00, table_size);
 668
 669         mm_table->count = mm_dependency_table->ucNumEntries;
 670
 671         for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
 672                 mm_dependency_record = &mm_dependency_table->entries[i];
 673                 mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
 674                 mm_table->entries[i].vddgfx_offset = mm_dependency_record->usVddgfxOffset;
 675                 mm_table->entries[i].aclk = mm_dependency_record->ulAClk;
 676                 mm_table->entries[i].samclock = mm_dependency_record->ulSAMUClk;
 677                 mm_table->entries[i].eclk = mm_dependency_record->ulEClk;
 678                 mm_table->entries[i].vclk = mm_dependency_record->ulVClk;
 679                 mm_table->entries[i].dclk = mm_dependency_record->ulDClk;
 680         }
 681
 682         *tonga_mm_table = mm_table;
 683
 684         return 0;
 685 }
 686
 687 /**
 688  * Private Function used during initialization.
 689  * Initialize clock voltage dependency
 690  * @param hwmgr Pointer to the hardware manager.
 691  * @param powerplay_table Pointer to the PowerPlay Table.
 692  */
 693 static int init_clock_voltage_dependency(
 694                 struct pp_hwmgr *hwmgr,
 695                 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
 696                 )
 697 {
 698         int result = 0;
 699         struct phm_ppt_v1_information *pp_table_information =
 700                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
 701
 702         const ATOM_Tonga_MM_Dependency_Table *mm_dependency_table =
 703                 (const ATOM_Tonga_MM_Dependency_Table *)(((unsigned long) powerplay_table) +
 704                 le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
 705         const PPTable_Generic_SubTable_Header *pPowerTuneTable =
 706                 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
 707                 le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
 708         const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
 709                 (const ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
 710                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
 711         const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
 712                 (const ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long) powerplay_table) +
 713                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
 714         const ATOM_Tonga_Hard_Limit_Table *pHardLimits =
 715                 (const ATOM_Tonga_Hard_Limit_Table *)(((unsigned long) powerplay_table) +
 716                 le16_to_cpu(powerplay_table->usHardLimitTableOffset));
 717         const PPTable_Generic_SubTable_Header *pcie_table =
 718                 (const PPTable_Generic_SubTable_Header *)(((unsigned long) powerplay_table) +
 719                 le16_to_cpu(powerplay_table->usPCIETableOffset));
 720
 721         pp_table_information->vdd_dep_on_sclk = NULL;
 722         pp_table_information->vdd_dep_on_mclk = NULL;
 723         pp_table_information->mm_dep_table = NULL;
 724         pp_table_information->pcie_table = NULL;
 725
 726         if (powerplay_table->usMMDependencyTableOffset != 0)
 727                 result = get_mm_clock_voltage_table(hwmgr,
 728                 &pp_table_information->mm_dep_table, mm_dependency_table);
 729
 730         if (result == 0 && powerplay_table->usPowerTuneTableOffset != 0)
 731                 result = get_cac_tdp_table(hwmgr,
 732                 &pp_table_information->cac_dtp_table, pPowerTuneTable);
 733
 734         if (result == 0 && powerplay_table->usSclkDependencyTableOffset != 0)
 735                 result = get_sclk_voltage_dependency_table(hwmgr,
 736                 &pp_table_information->vdd_dep_on_sclk, sclk_dep_table);
 737
 738         if (result == 0 && powerplay_table->usMclkDependencyTableOffset != 0)
 739                 result = get_mclk_voltage_dependency_table(hwmgr,
 740                 &pp_table_information->vdd_dep_on_mclk, mclk_dep_table);
 741
 742         if (result == 0 && powerplay_table->usPCIETableOffset != 0)
 743                 result = get_pcie_table(hwmgr,
 744                 &pp_table_information->pcie_table, pcie_table);
 745
 746         if (result == 0 && powerplay_table->usHardLimitTableOffset != 0)
 747                 result = get_hard_limits(hwmgr,
 748                 &pp_table_information->max_clock_voltage_on_dc, pHardLimits);
 749
 750         hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
 751                 pp_table_information->max_clock_voltage_on_dc.sclk;
 752         hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
 753                 pp_table_information->max_clock_voltage_on_dc.mclk;
 754         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
 755                 pp_table_information->max_clock_voltage_on_dc.vddc;
 756         hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
 757                 pp_table_information->max_clock_voltage_on_dc.vddci;
 758
 759         if (result == 0 && (NULL != pp_table_information->vdd_dep_on_mclk)
 760                 && (0 != pp_table_information->vdd_dep_on_mclk->count))
 761                 result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values,
 762                 pp_table_information->vdd_dep_on_mclk);
 763
 764         if (result == 0 && (NULL != pp_table_information->vdd_dep_on_sclk)
 765                 && (0 != pp_table_information->vdd_dep_on_sclk->count))
 766                 result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
 767                 pp_table_information->vdd_dep_on_sclk);
 768
 769         return result;
 770 }
 771
 772 /** Retrieves the (signed) Overdrive limits from VBIOS.
 773  * The max engine clock, memory clock and max temperature come from the firmware info table.
 774  *
 775  * The information is placed into the platform descriptor.
 776  *
 777  * @param hwmgr source of the VBIOS table and owner of the platform descriptor to be updated.
 778  * @param powerplay_table the address of the PowerPlay table.
 779  *
 780  * @return 1 as long as the firmware info table was present and of a supported version.
 781  */
 782 static int init_over_drive_limits(
 783                 struct pp_hwmgr *hwmgr,
 784                 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
 785 {
 786         hwmgr->platform_descriptor.overdriveLimit.engineClock =
 787                 le16_to_cpu(powerplay_table->ulMaxODEngineClock);
 788         hwmgr->platform_descriptor.overdriveLimit.memoryClock =
 789                 le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
 790
 791         hwmgr->platform_descriptor.minOverdriveVDDC = 0;
 792         hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
 793         hwmgr->platform_descriptor.overdriveVDDCStep = 0;
 794
 795         if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
 796                 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
 797                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 798                         PHM_PlatformCaps_ACOverdriveSupport);
 799         }
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * Private Function used during initialization.
 806  * Inspect the PowerPlay table for obvious signs of corruption.
 807  * @param hwmgr Pointer to the hardware manager.
 808  * @param powerplay_table Pointer to the PowerPlay Table.
 809  * @exception This implementation always returns 1.
 810  */
 811 static int init_thermal_controller(
 812                 struct pp_hwmgr *hwmgr,
 813                 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
 814                 )
 815 {
 816         const PPTable_Generic_SubTable_Header *fan_table;
 817         ATOM_Tonga_Thermal_Controller *thermal_controller;
 818
 819         thermal_controller = (ATOM_Tonga_Thermal_Controller *)
 820                 (((unsigned long)powerplay_table) +
 821                 le16_to_cpu(powerplay_table->usThermalControllerOffset));
 822         PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),
 823                 "Thermal controller table not set!", return -1);
 824
 825         hwmgr->thermal_controller.ucType = thermal_controller->ucType;
 826         hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
 827         hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
 828
 829         hwmgr->thermal_controller.fanInfo.bNoFan =
 830                 (0 != (thermal_controller->ucFanParameters & ATOM_TONGA_PP_FANPARAMETERS_NOFAN));
 831
 832         hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
 833                 thermal_controller->ucFanParameters &
 834                 ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
 835
 836         hwmgr->thermal_controller.fanInfo.ulMinRPM
 837                 = thermal_controller->ucFanMinRPM * 100UL;
 838         hwmgr->thermal_controller.fanInfo.ulMaxRPM
 839                 = thermal_controller->ucFanMaxRPM * 100UL;
 840
 841         set_hw_cap(
 842                         hwmgr,
 843                         ATOM_TONGA_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
 844                         PHM_PlatformCaps_ThermalController
 845                   );
 846
 847         if (0 == powerplay_table->usFanTableOffset)
 848                 return 0;
 849
 850         fan_table = (const PPTable_Generic_SubTable_Header *)
 851                 (((unsigned long)powerplay_table) +
 852                 le16_to_cpu(powerplay_table->usFanTableOffset));
 853
 854         PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),
 855                 "Fan table not set!", return -1);
 856         PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),
 857                 "Unsupported fan table format!", return -1);
 858
 859         hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
 860                 = 100000;
 861         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 862                 PHM_PlatformCaps_MicrocodeFanControl);
 863
 864         if (fan_table->ucRevId < 8) {
 865                 const ATOM_Tonga_Fan_Table *tonga_fan_table =
 866                         (ATOM_Tonga_Fan_Table *)fan_table;
 867                 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
 868                         = tonga_fan_table->ucTHyst;
 869                 hwmgr->thermal_controller.advanceFanControlParameters.usTMin
 870                         = tonga_fan_table->usTMin;
 871                 hwmgr->thermal_controller.advanceFanControlParameters.usTMed
 872                         = tonga_fan_table->usTMed;
 873                 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
 874                         = tonga_fan_table->usTHigh;
 875                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
 876                         = tonga_fan_table->usPWMMin;
 877                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
 878                         = tonga_fan_table->usPWMMed;
 879                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
 880                         = tonga_fan_table->usPWMHigh;
 881                 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
 882                         = 10900;                  /* hard coded */
 883                 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
 884                         = tonga_fan_table->usTMax;
 885                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
 886                         = tonga_fan_table->ucFanControlMode;
 887                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
 888                         = tonga_fan_table->usFanPWMMax;
 889                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
 890                         = 4836;
 891                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
 892                         = tonga_fan_table->usFanOutputSensitivity;
 893                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
 894                         = tonga_fan_table->usFanRPMMax;
 895                 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
 896                         = (tonga_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
 897                 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
 898                         = tonga_fan_table->ucTargetTemperature;
 899                 hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
 900                         = tonga_fan_table->ucMinimumPWMLimit;
 901         } else {
 902                 const ATOM_Fiji_Fan_Table *fiji_fan_table =
 903                         (ATOM_Fiji_Fan_Table *)fan_table;
 904                 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
 905                         = fiji_fan_table->ucTHyst;
 906                 hwmgr->thermal_controller.advanceFanControlParameters.usTMin
 907                         = fiji_fan_table->usTMin;
 908                 hwmgr->thermal_controller.advanceFanControlParameters.usTMed
 909                         = fiji_fan_table->usTMed;
 910                 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
 911                         = fiji_fan_table->usTHigh;
 912                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
 913                         = fiji_fan_table->usPWMMin;
 914                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
 915                         = fiji_fan_table->usPWMMed;
 916                 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
 917                         = fiji_fan_table->usPWMHigh;
 918                 hwmgr->thermal_controller.advanceFanControlParameters.usTMax
 919                         = fiji_fan_table->usTMax;
 920                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
 921                         = fiji_fan_table->ucFanControlMode;
 922                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
 923                         = fiji_fan_table->usFanPWMMax;
 924                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
 925                         = 4836;
 926                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
 927                         = fiji_fan_table->usFanOutputSensitivity;
 928                 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
 929                         = fiji_fan_table->usFanRPMMax;
 930                 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
 931                         = (fiji_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
 932                 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
 933                         = fiji_fan_table->ucTargetTemperature;
 934                 hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
 935                         = fiji_fan_table->ucMinimumPWMLimit;
 936
 937                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
 938                         = fiji_fan_table->usFanGainEdge;
 939                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
 940                         = fiji_fan_table->usFanGainHotspot;
 941                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
 942                         = fiji_fan_table->usFanGainLiquid;
 943                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
 944                         = fiji_fan_table->usFanGainVrVddc;
 945                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
 946                         = fiji_fan_table->usFanGainVrMvdd;
 947                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
 948                         = fiji_fan_table->usFanGainPlx;
 949                 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
 950                         = fiji_fan_table->usFanGainHbm;
 951         }
 952
 953         return 0;
 954 }
 955
 956 /**
 957  * Private Function used during initialization.
 958  * Inspect the PowerPlay table for obvious signs of corruption.
 959  * @param hwmgr Pointer to the hardware manager.
 960  * @param powerplay_table Pointer to the PowerPlay Table.
 961  * @exception 2 if the powerplay table is incorrect.
 962  */
 963 static int check_powerplay_tables(
 964                 struct pp_hwmgr *hwmgr,
 965                 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table
 966                 )
 967 {
 968         const ATOM_Tonga_State_Array *state_arrays;
 969
 970         state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)powerplay_table) +
 971                 le16_to_cpu(powerplay_table->usStateArrayOffset));
 972
 973         PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=
 974                 powerplay_table->sHeader.ucTableFormatRevision),
 975                 "Unsupported PPTable format!", return -1);
 976         PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),
 977                 "State table is not set!", return -1);
 978         PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),
 979                 "Invalid PowerPlay Table!", return -1);
 980         PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
 981                 "Invalid PowerPlay Table!", return -1);
 982
 983         return 0;
 984 }
 985
 986 int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr)
 987 {
 988         int result = 0;
 989         const ATOM_Tonga_POWERPLAYTABLE *powerplay_table;
 990
 991         hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
 992
 993         PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
 994                             "Failed to allocate hwmgr->pptable!", return -ENOMEM);
 995
 996         memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
 997
 998         powerplay_table = get_powerplay_table(hwmgr);
 999
1000         PP_ASSERT_WITH_CODE((NULL != powerplay_table),
1001                 "Missing PowerPlay Table!", return -1);
1002
1003         result = check_powerplay_tables(hwmgr, powerplay_table);
1004
1005         PP_ASSERT_WITH_CODE((result == 0),
1006                             "check_powerplay_tables failed", return result);
1007
1008         result = set_platform_caps(hwmgr,
1009                                    le32_to_cpu(powerplay_table->ulPlatformCaps));
1010
1011         PP_ASSERT_WITH_CODE((result == 0),
1012                             "set_platform_caps failed", return result);
1013
1014         result = init_thermal_controller(hwmgr, powerplay_table);
1015
1016         PP_ASSERT_WITH_CODE((result == 0),
1017                             "init_thermal_controller failed", return result);
1018
1019         result = init_over_drive_limits(hwmgr, powerplay_table);
1020
1021         PP_ASSERT_WITH_CODE((result == 0),
1022                             "init_over_drive_limits failed", return result);
1023
1024         result = init_clock_voltage_dependency(hwmgr, powerplay_table);
1025
1026         PP_ASSERT_WITH_CODE((result == 0),
1027                             "init_clock_voltage_dependency failed", return result);
1028
1029         result = init_dpm_2_parameters(hwmgr, powerplay_table);
1030
1031         PP_ASSERT_WITH_CODE((result == 0),
1032                             "init_dpm_2_parameters failed", return result);
1033
1034         return result;
1035 }
1036
1037 int tonga_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1038 {
1039         int result = 0;
1040         struct phm_ppt_v1_information *pp_table_information =
1041                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1042
1043         if (NULL != hwmgr->soft_pp_table) {
1044                 kfree(hwmgr->soft_pp_table);
1045                 hwmgr->soft_pp_table = NULL;
1046         }
1047
1048         if (NULL != pp_table_information->vdd_dep_on_sclk)
1049                 pp_table_information->vdd_dep_on_sclk = NULL;
1050
1051         if (NULL != pp_table_information->vdd_dep_on_mclk)
1052                 pp_table_information->vdd_dep_on_mclk = NULL;
1053
1054         if (NULL != pp_table_information->valid_mclk_values)
1055                 pp_table_information->valid_mclk_values = NULL;
1056
1057         if (NULL != pp_table_information->valid_sclk_values)
1058                 pp_table_information->valid_sclk_values = NULL;
1059
1060         if (NULL != pp_table_information->vddc_lookup_table)
1061                 pp_table_information->vddc_lookup_table = NULL;
1062
1063         if (NULL != pp_table_information->vddgfx_lookup_table)
1064                 pp_table_information->vddgfx_lookup_table = NULL;
1065
1066         if (NULL != pp_table_information->mm_dep_table)
1067                 pp_table_information->mm_dep_table = NULL;
1068
1069         if (NULL != pp_table_information->cac_dtp_table)
1070                 pp_table_information->cac_dtp_table = NULL;
1071
1072         if (NULL != hwmgr->dyn_state.cac_dtp_table)
1073                 hwmgr->dyn_state.cac_dtp_table = NULL;
1074
1075         if (NULL != pp_table_information->ppm_parameter_table)
1076                 pp_table_information->ppm_parameter_table = NULL;
1077
1078         if (NULL != pp_table_information->pcie_table)
1079                 pp_table_information->pcie_table = NULL;
1080
1081         if (NULL != hwmgr->pptable) {
1082                 kfree(hwmgr->pptable);
1083                 hwmgr->pptable = NULL;
1084         }
1085
1086         return result;
1087 }
1088
1089 const struct pp_table_func tonga_pptable_funcs = {
1090         .pptable_init = tonga_pp_tables_initialize,
1091         .pptable_fini = tonga_pp_tables_uninitialize,
1092 };
1093
1094 int tonga_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1095 {
1096         const ATOM_Tonga_State_Array * state_arrays;
1097         const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1098
1099         PP_ASSERT_WITH_CODE((NULL != pp_table),
1100                         "Missing PowerPlay Table!", return -1);
1101         PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=
1102                         ATOM_Tonga_TABLE_REVISION_TONGA),
1103                         "Incorrect PowerPlay table revision!", return -1);
1104
1105         state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
1106                         le16_to_cpu(pp_table->usStateArrayOffset));
1107
1108         return (uint32_t)(state_arrays->ucNumEntries);
1109 }
1110
1111 /**
1112 * Private function to convert flags stored in the BIOS to software flags in PowerPlay.
1113 */
1114 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1115                 uint16_t classification, uint16_t classification2)
1116 {
1117         uint32_t result = 0;
1118
1119         if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1120                 result |= PP_StateClassificationFlag_Boot;
1121
1122         if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1123                 result |= PP_StateClassificationFlag_Thermal;
1124
1125         if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1126                 result |= PP_StateClassificationFlag_LimitedPowerSource;
1127
1128         if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1129                 result |= PP_StateClassificationFlag_Rest;
1130
1131         if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1132                 result |= PP_StateClassificationFlag_Forced;
1133
1134         if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1135                 result |= PP_StateClassificationFlag_ACPI;
1136
1137         if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1138                 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1139
1140         return result;
1141 }
1142
1143 /**
1144 * Create a Power State out of an entry in the PowerPlay table.
1145 * This function is called by the hardware back-end.
1146 * @param hwmgr Pointer to the hardware manager.
1147 * @param entry_index The index of the entry to be extracted from the table.
1148 * @param power_state The address of the PowerState instance being created.
1149 * @return -1 if the entry cannot be retrieved.
1150 */
1151 int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1152                 uint32_t entry_index, struct pp_power_state *power_state,
1153                 int (*call_back_func)(struct pp_hwmgr *, void *,
1154                                 struct pp_power_state *, void *, uint32_t))
1155 {
1156         int result = 0;
1157         const ATOM_Tonga_State_Array * state_arrays;
1158         const ATOM_Tonga_State *state_entry;
1159         const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1160
1161         PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);
1162         power_state->classification.bios_index = entry_index;
1163
1164         if (pp_table->sHeader.ucTableFormatRevision >=
1165                         ATOM_Tonga_TABLE_REVISION_TONGA) {
1166                 state_arrays = (ATOM_Tonga_State_Array *)(((unsigned long)pp_table) +
1167                                 le16_to_cpu(pp_table->usStateArrayOffset));
1168
1169                 PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),
1170                                 "Invalid PowerPlay Table State Array Offset.", return -1);
1171                 PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
1172                                 "Invalid PowerPlay Table State Array.", return -1);
1173                 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1174                                 "Invalid PowerPlay Table State Array Entry.", return -1);
1175
1176                 state_entry = &(state_arrays->states[entry_index]);
1177
1178                 result = call_back_func(hwmgr, (void *)state_entry, power_state,
1179                                 (void *)pp_table,
1180                                 make_classification_flags(hwmgr,
1181                                         le16_to_cpu(state_entry->usClassification),
1182                                         le16_to_cpu(state_entry->usClassification2)));
1183         }
1184
1185         if (!result && (power_state->classification.flags &
1186                         PP_StateClassificationFlag_Boot))
1187                 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1188
1189         return result;
1190 }