drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef _VEGA10_HWMGR_H_
  25 #define _VEGA10_HWMGR_H_
  26
  27 #include "hwmgr.h"
  28 #include "smu9_driver_if.h"
  29 #include "ppatomctrl.h"
  30 #include "ppatomfwctrl.h"
  31 #include "vega10_ppsmc.h"
  32 #include "vega10_powertune.h"
  33
  34 extern const uint32_t PhwVega10_Magic;
  35 #define VEGA10_MAX_HARDWARE_POWERLEVELS 2
  36
  37 #define WaterMarksExist  1
  38 #define WaterMarksLoaded 2
  39
  40 enum {
  41         GNLD_DPM_PREFETCHER = 0,
  42         GNLD_DPM_GFXCLK,
  43         GNLD_DPM_UCLK,
  44         GNLD_DPM_SOCCLK,
  45         GNLD_DPM_UVD,
  46         GNLD_DPM_VCE,
  47         GNLD_ULV,
  48         GNLD_DPM_MP0CLK,
  49         GNLD_DPM_LINK,
  50         GNLD_DPM_DCEFCLK,
  51         GNLD_AVFS,
  52         GNLD_DS_GFXCLK,
  53         GNLD_DS_SOCCLK,
  54         GNLD_DS_LCLK,
  55         GNLD_PPT,
  56         GNLD_TDC,
  57         GNLD_THERMAL,
  58         GNLD_GFX_PER_CU_CG,
  59         GNLD_RM,
  60         GNLD_DS_DCEFCLK,
  61         GNLD_ACDC,
  62         GNLD_VR0HOT,
  63         GNLD_VR1HOT,
  64         GNLD_FW_CTF,
  65         GNLD_LED_DISPLAY,
  66         GNLD_FAN_CONTROL,
  67         GNLD_VOLTAGE_CONTROLLER,
  68         GNLD_FEATURES_MAX
  69 };
  70
  71 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
  72
  73 #define SMC_DPM_FEATURES    0x30F
  74
  75 struct smu_features {
  76         bool supported;
  77         bool enabled;
  78         uint32_t smu_feature_id;
  79         uint32_t smu_feature_bitmap;
  80 };
  81
  82 struct vega10_performance_level {
  83         uint32_t  soc_clock;
  84         uint32_t  gfx_clock;
  85         uint32_t  mem_clock;
  86 };
  87
  88 struct vega10_bacos {
  89         uint32_t                       baco_flags;
  90         /* struct vega10_performance_level  performance_level; */
  91 };
  92
  93 struct vega10_uvd_clocks {
  94         uint32_t  vclk;
  95         uint32_t  dclk;
  96 };
  97
  98 struct vega10_vce_clocks {
  99         uint32_t  evclk;
 100         uint32_t  ecclk;
 101 };
 102
 103 struct vega10_power_state {
 104         uint32_t                  magic;
 105         struct vega10_uvd_clocks    uvd_clks;
 106         struct vega10_vce_clocks    vce_clks;
 107         uint16_t                  performance_level_count;
 108         bool                      dc_compatible;
 109         uint32_t                  sclk_threshold;
 110         struct vega10_performance_level  performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS];
 111 };
 112
 113 struct vega10_dpm_level {
 114         bool    enabled;
 115         uint32_t        value;
 116         uint32_t        param1;
 117 };
 118
 119 #define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5
 120 #define MAX_REGULAR_DPM_NUMBER 8
 121 #define MAX_PCIE_CONF 2
 122 #define VEGA10_MINIMUM_ENGINE_CLOCK 2500
 123
 124 struct vega10_dpm_state {
 125         uint32_t  soft_min_level;
 126         uint32_t  soft_max_level;
 127         uint32_t  hard_min_level;
 128         uint32_t  hard_max_level;
 129 };
 130
 131 struct vega10_single_dpm_table {
 132         uint32_t                count;
 133         struct vega10_dpm_state dpm_state;
 134         struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
 135 };
 136
 137 struct vega10_pcie_table {
 138         uint16_t count;
 139         uint8_t  pcie_gen[MAX_PCIE_CONF];
 140         uint8_t  pcie_lane[MAX_PCIE_CONF];
 141         uint32_t lclk[MAX_PCIE_CONF];
 142 };
 143
 144 struct vega10_dpm_table {
 145         struct vega10_single_dpm_table  soc_table;
 146         struct vega10_single_dpm_table  gfx_table;
 147         struct vega10_single_dpm_table  mem_table;
 148         struct vega10_single_dpm_table  eclk_table;
 149         struct vega10_single_dpm_table  vclk_table;
 150         struct vega10_single_dpm_table  dclk_table;
 151         struct vega10_single_dpm_table  dcef_table;
 152         struct vega10_single_dpm_table  pixel_table;
 153         struct vega10_single_dpm_table  display_table;
 154         struct vega10_single_dpm_table  phy_table;
 155         struct vega10_pcie_table        pcie_table;
 156 };
 157
 158 #define VEGA10_MAX_LEAKAGE_COUNT  8
 159 struct vega10_leakage_voltage {
 160         uint16_t  count;
 161         uint16_t  leakage_id[VEGA10_MAX_LEAKAGE_COUNT];
 162         uint16_t  actual_voltage[VEGA10_MAX_LEAKAGE_COUNT];
 163 };
 164
 165 struct vega10_display_timing {
 166         uint32_t  min_clock_in_sr;
 167         uint32_t  num_existing_displays;
 168 };
 169
 170 struct vega10_dpmlevel_enable_mask {
 171         uint32_t  uvd_dpm_enable_mask;
 172         uint32_t  vce_dpm_enable_mask;
 173         uint32_t  acp_dpm_enable_mask;
 174         uint32_t  samu_dpm_enable_mask;
 175         uint32_t  sclk_dpm_enable_mask;
 176         uint32_t  mclk_dpm_enable_mask;
 177 };
 178
 179 struct vega10_vbios_boot_state {
 180         bool        bsoc_vddc_lock;
 181         uint16_t    vddc;
 182         uint16_t    vddci;
 183         uint16_t    mvddc;
 184         uint16_t    vdd_gfx;
 185         uint32_t    gfx_clock;
 186         uint32_t    mem_clock;
 187         uint32_t    soc_clock;
 188 };
 189
 190 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 191 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 192 #define DPMTABLE_UPDATE_SCLK        0x00000004
 193 #define DPMTABLE_UPDATE_MCLK        0x00000008
 194 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
 195
 196 struct vega10_smc_state_table {
 197         uint32_t        soc_boot_level;
 198         uint32_t        gfx_boot_level;
 199         uint32_t        dcef_boot_level;
 200         uint32_t        mem_boot_level;
 201         uint32_t        uvd_boot_level;
 202         uint32_t        vce_boot_level;
 203         uint32_t        gfx_max_level;
 204         uint32_t        mem_max_level;
 205         uint8_t         vr_hot_gpio;
 206         uint8_t         ac_dc_gpio;
 207         uint8_t         therm_out_gpio;
 208         uint8_t         therm_out_polarity;
 209         uint8_t         therm_out_mode;
 210         PPTable_t       pp_table;
 211         Watermarks_t    water_marks_table;
 212         AvfsTable_t     avfs_table;
 213 };
 214
 215 struct vega10_mclk_latency_entries {
 216         uint32_t  frequency;
 217         uint32_t  latency;
 218 };
 219
 220 struct vega10_mclk_latency_table {
 221         uint32_t  count;
 222         struct vega10_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
 223 };
 224
 225 struct vega10_registry_data {
 226         uint8_t   ac_dc_switch_gpio_support;
 227         uint8_t   avfs_support;
 228         uint8_t   cac_support;
 229         uint8_t   clock_stretcher_support;
 230         uint8_t   db_ramping_support;
 231         uint8_t   didt_support;
 232         uint8_t   dynamic_state_patching_support;
 233         uint8_t   enable_pkg_pwr_tracking_feature;
 234         uint8_t   enable_tdc_limit_feature;
 235         uint32_t  fast_watermark_threshold;
 236         uint8_t   force_dpm_high;
 237         uint8_t   fuzzy_fan_control_support;
 238         uint8_t   long_idle_baco_support;
 239         uint8_t   mclk_dpm_key_disabled;
 240         uint8_t   od_state_in_dc_support;
 241         uint8_t   pcieLaneOverride;
 242         uint8_t   pcieSpeedOverride;
 243         uint32_t  pcieClockOverride;
 244         uint8_t   pcie_dpm_key_disabled;
 245         uint8_t   dcefclk_dpm_key_disabled;
 246         uint8_t   power_containment_support;
 247         uint8_t   ppt_support;
 248         uint8_t   prefetcher_dpm_key_disabled;
 249         uint8_t   quick_transition_support;
 250         uint8_t   regulator_hot_gpio_support;
 251         uint8_t   sclk_deep_sleep_support;
 252         uint8_t   sclk_dpm_key_disabled;
 253         uint8_t   sclk_from_vbios;
 254         uint8_t   sclk_throttle_low_notification;
 255         uint8_t   show_baco_dbg_info;
 256         uint8_t   skip_baco_hardware;
 257         uint8_t   socclk_dpm_key_disabled;
 258         uint8_t   spll_shutdown_support;
 259         uint8_t   sq_ramping_support;
 260         uint32_t  stable_pstate_sclk_dpm_percentage;
 261         uint8_t   tcp_ramping_support;
 262         uint8_t   tdc_support;
 263         uint8_t   td_ramping_support;
 264         uint8_t   thermal_out_gpio_support;
 265         uint8_t   thermal_support;
 266         uint8_t   fw_ctf_enabled;
 267         uint8_t   fan_control_support;
 268         uint8_t   ulps_support;
 269         uint8_t   ulv_support;
 270         uint32_t  vddc_vddci_delta;
 271         uint8_t   odn_feature_enable;
 272         uint8_t   disable_water_mark;
 273         uint8_t   zrpm_stop_temp;
 274         uint8_t   zrpm_start_temp;
 275         uint8_t   led_dpm_enabled;
 276         uint8_t   vr0hot_enabled;
 277         uint8_t   vr1hot_enabled;
 278 };
 279
 280 struct vega10_odn_clock_voltage_dependency_table {
 281         uint32_t count;
 282         struct phm_ppt_v1_clock_voltage_dependency_record
 283                 entries[MAX_REGULAR_DPM_NUMBER];
 284 };
 285
 286 struct vega10_odn_dpm_table {
 287         struct phm_odn_clock_levels             odn_core_clock_dpm_levels;
 288         struct phm_odn_clock_levels             odn_memory_clock_dpm_levels;
 289         struct vega10_odn_clock_voltage_dependency_table                vdd_dependency_on_sclk;
 290         struct vega10_odn_clock_voltage_dependency_table                vdd_dependency_on_mclk;
 291 };
 292
 293 struct vega10_odn_fan_table {
 294         uint32_t        target_fan_speed;
 295         uint32_t        target_temperature;
 296         uint32_t        min_performance_clock;
 297         uint32_t        min_fan_limit;
 298 };
 299
 300 struct vega10_hwmgr {
 301         struct vega10_dpm_table                 dpm_table;
 302         struct vega10_dpm_table                 golden_dpm_table;
 303         struct vega10_registry_data      registry_data;
 304         struct vega10_vbios_boot_state   vbios_boot_state;
 305         struct vega10_mclk_latency_table mclk_latency_table;
 306
 307         struct vega10_leakage_voltage    vddc_leakage;
 308
 309         uint32_t                           vddc_control;
 310         struct pp_atomfwctrl_voltage_table vddc_voltage_table;
 311         uint32_t                           mvdd_control;
 312         struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
 313         uint32_t                           vddci_control;
 314         struct pp_atomfwctrl_voltage_table vddci_voltage_table;
 315
 316         uint32_t                           active_auto_throttle_sources;
 317         uint32_t                           water_marks_bitmap;
 318         struct vega10_bacos                bacos;
 319
 320         struct vega10_odn_dpm_table       odn_dpm_table;
 321         struct vega10_odn_fan_table       odn_fan_table;
 322
 323         /* ---- General data ---- */
 324         uint8_t                           need_update_dpm_table;
 325
 326         bool                           cac_enabled;
 327         bool                           battery_state;
 328         bool                           is_tlu_enabled;
 329
 330         uint32_t                       low_sclk_interrupt_threshold;
 331
 332         uint32_t                       total_active_cus;
 333
 334         struct vega10_display_timing display_timing;
 335
 336         /* ---- Vega10 Dyn Register Settings ---- */
 337
 338         uint32_t                       debug_settings;
 339         uint32_t                       lowest_uclk_reserved_for_ulv;
 340         uint32_t                       gfxclk_average_alpha;
 341         uint32_t                       socclk_average_alpha;
 342         uint32_t                       uclk_average_alpha;
 343         uint32_t                       gfx_activity_average_alpha;
 344         uint32_t                       display_voltage_mode;
 345         uint32_t                       dcef_clk_quad_eqn_a;
 346         uint32_t                       dcef_clk_quad_eqn_b;
 347         uint32_t                       dcef_clk_quad_eqn_c;
 348         uint32_t                       disp_clk_quad_eqn_a;
 349         uint32_t                       disp_clk_quad_eqn_b;
 350         uint32_t                       disp_clk_quad_eqn_c;
 351         uint32_t                       pixel_clk_quad_eqn_a;
 352         uint32_t                       pixel_clk_quad_eqn_b;
 353         uint32_t                       pixel_clk_quad_eqn_c;
 354         uint32_t                       phy_clk_quad_eqn_a;
 355         uint32_t                       phy_clk_quad_eqn_b;
 356         uint32_t                       phy_clk_quad_eqn_c;
 357
 358         /* ---- Thermal Temperature Setting ---- */
 359         struct vega10_dpmlevel_enable_mask     dpm_level_enable_mask;
 360
 361         /* ---- Power Gating States ---- */
 362         bool                           uvd_power_gated;
 363         bool                           vce_power_gated;
 364         bool                           samu_power_gated;
 365         bool                           need_long_memory_training;
 366
 367         /* Internal settings to apply the application power optimization parameters */
 368         bool                           apply_optimized_settings;
 369         uint32_t                       disable_dpm_mask;
 370
 371         /* ---- Overdrive next setting ---- */
 372         uint32_t                       apply_overdrive_next_settings_mask;
 373
 374         /* ---- Workload Mask ---- */
 375         uint32_t                       workload_mask;
 376
 377         /* ---- SMU9 ---- */
 378         struct smu_features            smu_features[GNLD_FEATURES_MAX];
 379         struct vega10_smc_state_table  smc_state_table;
 380
 381         uint32_t                       config_telemetry;
 382 };
 383
 384 #define VEGA10_DPM2_NEAR_TDP_DEC                      10
 385 #define VEGA10_DPM2_ABOVE_SAFE_INC                    5
 386 #define VEGA10_DPM2_BELOW_SAFE_INC                    20
 387
 388 #define VEGA10_DPM2_LTA_WINDOW_SIZE                   7
 389
 390 #define VEGA10_DPM2_LTS_TRUNCATE                      0
 391
 392 #define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT            80
 393
 394 #define VEGA10_DPM2_MAXPS_PERCENT_M                   90
 395 #define VEGA10_DPM2_MAXPS_PERCENT_H                   90
 396
 397 #define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN         50
 398
 399 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 400 #define VEGA10_DPM2_SQ_RAMP_MIN_POWER                 0x12
 401 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 402 #define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
 403 #define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
 404
 405 #define VEGA10_VOLTAGE_CONTROL_NONE                   0x0
 406 #define VEGA10_VOLTAGE_CONTROL_BY_GPIO                0x1
 407 #define VEGA10_VOLTAGE_CONTROL_BY_SVID2               0x2
 408 #define VEGA10_VOLTAGE_CONTROL_MERGED                 0x3
 409 /* To convert to Q8.8 format for firmware */
 410 #define VEGA10_Q88_FORMAT_CONVERSION_UNIT             256
 411
 412 #define VEGA10_UNUSED_GPIO_PIN       0x7F
 413
 414 #define VEGA10_THERM_OUT_MODE_DISABLE       0x0
 415 #define VEGA10_THERM_OUT_MODE_THERM_ONLY    0x1
 416 #define VEGA10_THERM_OUT_MODE_THERM_VRHOT   0x2
 417
 418 #define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT   0xffffffff
 419 #define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT    0xffffffff
 420
 421 #define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 422 #define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
 423 #define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
 424 #define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
 425
 426 extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 427 extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 428 extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
 429 extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
 430 extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
 431 int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
 432 int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 433 int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 434 int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 435 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
 436
 437 #endif /* _VEGA10_HWMGR_H_ */