2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef _AMD_POWERPLAY_H_
24 #define _AMD_POWERPLAY_H_
26 #include <linux/seq_file.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include "amd_shared.h"
30 #include "cgs_common.h"
33 AMDGPU_PP_SENSOR_GFX_SCLK
= 0,
34 AMDGPU_PP_SENSOR_VDDNB
,
35 AMDGPU_PP_SENSOR_VDDGFX
,
36 AMDGPU_PP_SENSOR_UVD_VCLK
,
37 AMDGPU_PP_SENSOR_UVD_DCLK
,
38 AMDGPU_PP_SENSOR_VCE_ECCLK
,
39 AMDGPU_PP_SENSOR_GPU_LOAD
,
40 AMDGPU_PP_SENSOR_GFX_MCLK
,
41 AMDGPU_PP_SENSOR_GPU_TEMP
,
45 AMD_PP_EVENT_INITIALIZE
= 0,
46 AMD_PP_EVENT_UNINITIALIZE
,
47 AMD_PP_EVENT_POWER_SOURCE_CHANGE
,
50 AMD_PP_EVENT_ENTER_REST_STATE
,
51 AMD_PP_EVENT_EXIT_REST_STATE
,
52 AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE
,
53 AMD_PP_EVENT_THERMAL_NOTIFICATION
,
54 AMD_PP_EVENT_VBIOS_NOTIFICATION
,
55 AMD_PP_EVENT_ENTER_THERMAL_STATE
,
56 AMD_PP_EVENT_EXIT_THERMAL_STATE
,
57 AMD_PP_EVENT_ENTER_FORCED_STATE
,
58 AMD_PP_EVENT_EXIT_FORCED_STATE
,
59 AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE
,
60 AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE
,
61 AMD_PP_EVENT_ENTER_SCREEN_SAVER
,
62 AMD_PP_EVENT_EXIT_SCREEN_SAVER
,
63 AMD_PP_EVENT_VPU_RECOVERY_BEGIN
,
64 AMD_PP_EVENT_VPU_RECOVERY_END
,
65 AMD_PP_EVENT_ENABLE_POWER_PLAY
,
66 AMD_PP_EVENT_DISABLE_POWER_PLAY
,
67 AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL
,
68 AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE
,
69 AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE
,
70 AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE
,
71 AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE
,
72 AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST
,
73 AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST
,
74 AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE
,
75 AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE
,
76 AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING
,
77 AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING
,
78 AMD_PP_EVENT_ENABLE_CGPG
,
79 AMD_PP_EVENT_DISABLE_CGPG
,
80 AMD_PP_EVENT_ENTER_TEXT_MODE
,
81 AMD_PP_EVENT_EXIT_TEXT_MODE
,
82 AMD_PP_EVENT_VIDEO_START
,
83 AMD_PP_EVENT_VIDEO_STOP
,
84 AMD_PP_EVENT_ENABLE_USER_STATE
,
85 AMD_PP_EVENT_DISABLE_USER_STATE
,
86 AMD_PP_EVENT_READJUST_POWER_STATE
,
87 AMD_PP_EVENT_START_INACTIVITY
,
88 AMD_PP_EVENT_STOP_INACTIVITY
,
89 AMD_PP_EVENT_LINKED_ADAPTERS_READY
,
90 AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE
,
91 AMD_PP_EVENT_COMPLETE_INIT
,
92 AMD_PP_EVENT_CRITICAL_THERMAL_FAULT
,
93 AMD_PP_EVENT_BACKLIGHT_CHANGED
,
94 AMD_PP_EVENT_ENABLE_VARI_BRIGHT
,
95 AMD_PP_EVENT_DISABLE_VARI_BRIGHT
,
96 AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS
,
97 AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS
,
98 AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL
,
99 AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT
,
100 AMD_PP_EVENT_SCREEN_ON
,
101 AMD_PP_EVENT_SCREEN_OFF
,
102 AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE
,
103 AMD_PP_EVENT_ENTER_ULP_STATE
,
104 AMD_PP_EVENT_EXIT_ULP_STATE
,
105 AMD_PP_EVENT_REGISTER_IP_STATE
,
106 AMD_PP_EVENT_UNREGISTER_IP_STATE
,
107 AMD_PP_EVENT_ENTER_MGPU_MODE
,
108 AMD_PP_EVENT_EXIT_MGPU_MODE
,
109 AMD_PP_EVENT_ENTER_MULTI_GPU_MODE
,
110 AMD_PP_EVENT_PRE_SUSPEND
,
111 AMD_PP_EVENT_PRE_RESUME
,
112 AMD_PP_EVENT_ENTER_BACOS
,
113 AMD_PP_EVENT_EXIT_BACOS
,
114 AMD_PP_EVENT_RESUME_BACO
,
115 AMD_PP_EVENT_RESET_BACO
,
116 AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS
,
117 AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS
,
118 AMD_PP_EVENT_START_COMPUTE_APPLICATION
,
119 AMD_PP_EVENT_STOP_COMPUTE_APPLICATION
,
120 AMD_PP_EVENT_REDUCE_POWER_LIMIT
,
121 AMD_PP_EVENT_ENTER_FRAME_LOCK
,
122 AMD_PP_EVENT_EXIT_FRAME_LOOCK
,
123 AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO
,
124 AMD_PP_EVENT_LONG_IDLE_ENTER_BACO
,
125 AMD_PP_EVENT_LONG_IDLE_EXIT_BACO
,
126 AMD_PP_EVENT_HIBERNATE
,
127 AMD_PP_EVENT_CONNECTED_STANDBY
,
128 AMD_PP_EVENT_ENTER_SELF_REFRESH
,
129 AMD_PP_EVENT_EXIT_SELF_REFRESH
,
130 AMD_PP_EVENT_START_AVFS_BTC
,
134 enum amd_dpm_forced_level
{
135 AMD_DPM_FORCED_LEVEL_AUTO
= 0,
136 AMD_DPM_FORCED_LEVEL_LOW
= 1,
137 AMD_DPM_FORCED_LEVEL_HIGH
= 2,
138 AMD_DPM_FORCED_LEVEL_MANUAL
= 3,
142 struct cgs_device
*device
;
143 uint32_t chip_family
;
147 enum amd_pp_display_config_type
{
148 AMD_PP_DisplayConfigType_None
= 0,
149 AMD_PP_DisplayConfigType_DP54
,
150 AMD_PP_DisplayConfigType_DP432
,
151 AMD_PP_DisplayConfigType_DP324
,
152 AMD_PP_DisplayConfigType_DP27
,
153 AMD_PP_DisplayConfigType_DP243
,
154 AMD_PP_DisplayConfigType_DP216
,
155 AMD_PP_DisplayConfigType_DP162
,
156 AMD_PP_DisplayConfigType_HDMI6G
,
157 AMD_PP_DisplayConfigType_HDMI297
,
158 AMD_PP_DisplayConfigType_HDMI162
,
159 AMD_PP_DisplayConfigType_LVDS
,
160 AMD_PP_DisplayConfigType_DVI
,
161 AMD_PP_DisplayConfigType_WIRELESS
,
162 AMD_PP_DisplayConfigType_VGA
165 struct single_display_configuration
167 uint32_t controller_index
;
168 uint32_t controller_id
;
169 uint32_t signal_type
;
170 uint32_t display_state
;
171 /* phy id for the primary internal transmitter */
172 uint8_t primary_transmitter_phyi_d
;
173 /* bitmap with the active lanes */
174 uint8_t primary_transmitter_active_lanemap
;
175 /* phy id for the secondary internal transmitter (for dual-link dvi) */
176 uint8_t secondary_transmitter_phy_id
;
177 /* bitmap with the active lanes */
178 uint8_t secondary_transmitter_active_lanemap
;
179 /* misc phy settings for SMU. */
180 uint32_t config_flags
;
181 uint32_t display_type
;
182 uint32_t view_resolution_cx
;
183 uint32_t view_resolution_cy
;
184 enum amd_pp_display_config_type displayconfigtype
;
185 uint32_t vertical_refresh
; /* for active display */
188 #define MAX_NUM_DISPLAY 32
190 struct amd_pp_display_configuration
{
191 bool nb_pstate_switch_disable
;/* controls NB PState switch */
192 bool cpu_cc6_disable
; /* controls CPU CState switch ( on or off) */
193 bool cpu_pstate_disable
;
194 uint32_t cpu_pstate_separation_time
;
196 uint32_t num_display
; /* total number of display*/
197 uint32_t num_path_including_non_display
;
198 uint32_t crossfire_display_index
;
199 uint32_t min_mem_set_clock
;
200 uint32_t min_core_set_clock
;
201 /* unit 10KHz x bit*/
202 uint32_t min_bus_bandwidth
;
203 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
204 uint32_t min_core_set_clock_in_sr
;
206 struct single_display_configuration displays
[MAX_NUM_DISPLAY
];
208 uint32_t vrefresh
; /* for active display*/
210 uint32_t min_vblank_time
; /* for active display*/
211 bool multi_monitor_in_sync
;
212 /* Controller Index of primary display - used in MCLK SMC switching hang
215 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
216 uint32_t line_time_in_us
;
217 bool invalid_vblank_time
;
219 uint32_t display_clk
;
221 * for given display configuration if multimonitormnsync == false then
222 * Memory clock DPMS with this latency or below is allowed, DPMS with
223 * higher latency not allowed.
225 uint32_t dce_tolerable_mclk_in_active_latency
;
228 struct amd_pp_simple_clock_info
{
229 uint32_t engine_max_clock
;
230 uint32_t memory_max_clock
;
234 enum PP_DAL_POWERLEVEL
{
235 PP_DAL_POWERLEVEL_INVALID
= 0,
236 PP_DAL_POWERLEVEL_ULTRALOW
,
237 PP_DAL_POWERLEVEL_LOW
,
238 PP_DAL_POWERLEVEL_NOMINAL
,
239 PP_DAL_POWERLEVEL_PERFORMANCE
,
241 PP_DAL_POWERLEVEL_0
= PP_DAL_POWERLEVEL_ULTRALOW
,
242 PP_DAL_POWERLEVEL_1
= PP_DAL_POWERLEVEL_LOW
,
243 PP_DAL_POWERLEVEL_2
= PP_DAL_POWERLEVEL_NOMINAL
,
244 PP_DAL_POWERLEVEL_3
= PP_DAL_POWERLEVEL_PERFORMANCE
,
245 PP_DAL_POWERLEVEL_4
= PP_DAL_POWERLEVEL_3
+1,
246 PP_DAL_POWERLEVEL_5
= PP_DAL_POWERLEVEL_4
+1,
247 PP_DAL_POWERLEVEL_6
= PP_DAL_POWERLEVEL_5
+1,
248 PP_DAL_POWERLEVEL_7
= PP_DAL_POWERLEVEL_6
+1,
251 struct amd_pp_clock_info
{
252 uint32_t min_engine_clock
;
253 uint32_t max_engine_clock
;
254 uint32_t min_memory_clock
;
255 uint32_t max_memory_clock
;
256 uint32_t min_bus_bandwidth
;
257 uint32_t max_bus_bandwidth
;
258 uint32_t max_engine_clock_in_sr
;
259 uint32_t min_engine_clock_in_sr
;
260 enum PP_DAL_POWERLEVEL max_clocks_state
;
263 enum amd_pp_clock_type
{
264 amd_pp_disp_clock
= 1,
269 #define MAX_NUM_CLOCKS 16
271 struct amd_pp_clocks
{
273 uint32_t clock
[MAX_NUM_CLOCKS
];
274 uint32_t latency
[MAX_NUM_CLOCKS
];
279 PP_GROUP_UNKNOWN
= 0,
291 struct pp_states_info
{
296 #define PP_GROUP_MASK 0xF0000000
297 #define PP_GROUP_SHIFT 28
299 #define PP_BLOCK_MASK 0x0FFFFF00
300 #define PP_BLOCK_SHIFT 8
302 #define PP_BLOCK_GFX_CG 0x01
303 #define PP_BLOCK_GFX_MG 0x02
304 #define PP_BLOCK_GFX_3D 0x04
305 #define PP_BLOCK_GFX_RLC 0x08
306 #define PP_BLOCK_GFX_CP 0x10
307 #define PP_BLOCK_SYS_BIF 0x01
308 #define PP_BLOCK_SYS_MC 0x02
309 #define PP_BLOCK_SYS_ROM 0x04
310 #define PP_BLOCK_SYS_DRM 0x08
311 #define PP_BLOCK_SYS_HDP 0x10
312 #define PP_BLOCK_SYS_SDMA 0x20
314 #define PP_STATE_MASK 0x0000000F
315 #define PP_STATE_SHIFT 0
316 #define PP_STATE_SUPPORT_MASK 0x000000F0
317 #define PP_STATE_SUPPORT_SHIFT 0
319 #define PP_STATE_CG 0x01
320 #define PP_STATE_LS 0x02
321 #define PP_STATE_DS 0x04
322 #define PP_STATE_SD 0x08
323 #define PP_STATE_SUPPORT_CG 0x10
324 #define PP_STATE_SUPPORT_LS 0x20
325 #define PP_STATE_SUPPORT_DS 0x40
326 #define PP_STATE_SUPPORT_SD 0x80
328 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
329 block << PP_BLOCK_SHIFT |\
330 support << PP_STATE_SUPPORT_SHIFT |\
331 state << PP_STATE_SHIFT)
333 struct amd_powerplay_funcs
{
334 int (*get_temperature
)(void *handle
);
335 int (*load_firmware
)(void *handle
);
336 int (*wait_for_fw_loading_complete
)(void *handle
);
337 int (*force_performance_level
)(void *handle
, enum amd_dpm_forced_level level
);
338 enum amd_dpm_forced_level (*get_performance_level
)(void *handle
);
339 enum amd_pm_state_type (*get_current_power_state
)(void *handle
);
340 int (*get_sclk
)(void *handle
, bool low
);
341 int (*get_mclk
)(void *handle
, bool low
);
342 int (*powergate_vce
)(void *handle
, bool gate
);
343 int (*powergate_uvd
)(void *handle
, bool gate
);
344 int (*dispatch_tasks
)(void *handle
, enum amd_pp_event event_id
,
345 void *input
, void *output
);
346 void (*print_current_performance_level
)(void *handle
,
348 int (*set_fan_control_mode
)(void *handle
, uint32_t mode
);
349 int (*get_fan_control_mode
)(void *handle
);
350 int (*set_fan_speed_percent
)(void *handle
, uint32_t percent
);
351 int (*get_fan_speed_percent
)(void *handle
, uint32_t *speed
);
352 int (*get_pp_num_states
)(void *handle
, struct pp_states_info
*data
);
353 int (*get_pp_table
)(void *handle
, char **table
);
354 int (*set_pp_table
)(void *handle
, const char *buf
, size_t size
);
355 int (*force_clock_level
)(void *handle
, enum pp_clock_type type
, uint32_t mask
);
356 int (*print_clock_levels
)(void *handle
, enum pp_clock_type type
, char *buf
);
357 int (*get_sclk_od
)(void *handle
);
358 int (*set_sclk_od
)(void *handle
, uint32_t value
);
359 int (*get_mclk_od
)(void *handle
);
360 int (*set_mclk_od
)(void *handle
, uint32_t value
);
361 int (*read_sensor
)(void *handle
, int idx
, int32_t *value
);
364 struct amd_powerplay
{
366 const struct amd_ip_funcs
*ip_funcs
;
367 const struct amd_powerplay_funcs
*pp_funcs
;
370 int amd_powerplay_init(struct amd_pp_init
*pp_init
,
371 struct amd_powerplay
*amd_pp
);
373 int amd_powerplay_fini(void *handle
);
375 int amd_powerplay_reset(void *handle
);
377 int amd_powerplay_display_configuration_change(void *handle
,
378 const struct amd_pp_display_configuration
*input
);
380 int amd_powerplay_get_display_power_level(void *handle
,
381 struct amd_pp_simple_clock_info
*output
);
383 int amd_powerplay_get_current_clocks(void *handle
,
384 struct amd_pp_clock_info
*output
);
386 int amd_powerplay_get_clock_by_type(void *handle
,
387 enum amd_pp_clock_type type
,
388 struct amd_pp_clocks
*clocks
);
390 int amd_powerplay_get_display_mode_validation_clocks(void *handle
,
391 struct amd_pp_simple_clock_info
*output
);
393 #endif /* _AMD_POWERPLAY_H_ */