drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _AMD_POWERPLAY_H_
  24 #define _AMD_POWERPLAY_H_
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include "amd_shared.h"
  30 #include "cgs_common.h"
  31 #include "dm_pp_interface.h"
  32
  33 extern const struct amd_ip_funcs pp_ip_funcs;
  34 extern const struct amd_pm_funcs pp_dpm_funcs;
  35
  36 enum amd_pp_sensors {
  37         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
  38         AMDGPU_PP_SENSOR_VDDNB,
  39         AMDGPU_PP_SENSOR_VDDGFX,
  40         AMDGPU_PP_SENSOR_UVD_VCLK,
  41         AMDGPU_PP_SENSOR_UVD_DCLK,
  42         AMDGPU_PP_SENSOR_VCE_ECCLK,
  43         AMDGPU_PP_SENSOR_GPU_LOAD,
  44         AMDGPU_PP_SENSOR_GFX_MCLK,
  45         AMDGPU_PP_SENSOR_GPU_TEMP,
  46         AMDGPU_PP_SENSOR_VCE_POWER,
  47         AMDGPU_PP_SENSOR_UVD_POWER,
  48         AMDGPU_PP_SENSOR_GPU_POWER,
  49 };
  50
  51 enum amd_pp_task {
  52         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
  53         AMD_PP_TASK_ENABLE_USER_STATE,
  54         AMD_PP_TASK_READJUST_POWER_STATE,
  55         AMD_PP_TASK_COMPLETE_INIT,
  56         AMD_PP_TASK_MAX
  57 };
  58
  59 struct amd_pp_init {
  60         struct cgs_device *device;
  61         uint32_t chip_family;
  62         uint32_t chip_id;
  63         bool pm_en;
  64         uint32_t feature_mask;
  65 };
  66
  67 enum amd_pp_display_config_type{
  68         AMD_PP_DisplayConfigType_None = 0,
  69         AMD_PP_DisplayConfigType_DP54 ,
  70         AMD_PP_DisplayConfigType_DP432 ,
  71         AMD_PP_DisplayConfigType_DP324 ,
  72         AMD_PP_DisplayConfigType_DP27,
  73         AMD_PP_DisplayConfigType_DP243,
  74         AMD_PP_DisplayConfigType_DP216,
  75         AMD_PP_DisplayConfigType_DP162,
  76         AMD_PP_DisplayConfigType_HDMI6G ,
  77         AMD_PP_DisplayConfigType_HDMI297 ,
  78         AMD_PP_DisplayConfigType_HDMI162,
  79         AMD_PP_DisplayConfigType_LVDS,
  80         AMD_PP_DisplayConfigType_DVI,
  81         AMD_PP_DisplayConfigType_WIRELESS,
  82         AMD_PP_DisplayConfigType_VGA
  83 };
  84
  85 struct single_display_configuration
  86 {
  87         uint32_t controller_index;
  88         uint32_t controller_id;
  89         uint32_t signal_type;
  90         uint32_t display_state;
  91         /* phy id for the primary internal transmitter */
  92         uint8_t primary_transmitter_phyi_d;
  93         /* bitmap with the active lanes */
  94         uint8_t primary_transmitter_active_lanemap;
  95         /* phy id for the secondary internal transmitter (for dual-link dvi) */
  96         uint8_t secondary_transmitter_phy_id;
  97         /* bitmap with the active lanes */
  98         uint8_t secondary_transmitter_active_lanemap;
  99         /* misc phy settings for SMU. */
 100         uint32_t config_flags;
 101         uint32_t display_type;
 102         uint32_t view_resolution_cx;
 103         uint32_t view_resolution_cy;
 104         enum amd_pp_display_config_type displayconfigtype;
 105         uint32_t vertical_refresh; /* for active display */
 106 };
 107
 108 #define MAX_NUM_DISPLAY 32
 109
 110 struct amd_pp_display_configuration {
 111         bool nb_pstate_switch_disable;/* controls NB PState switch */
 112         bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 113         bool cpu_pstate_disable;
 114         uint32_t cpu_pstate_separation_time;
 115
 116         uint32_t num_display;  /* total number of display*/
 117         uint32_t num_path_including_non_display;
 118         uint32_t crossfire_display_index;
 119         uint32_t min_mem_set_clock;
 120         uint32_t min_core_set_clock;
 121         /* unit 10KHz x bit*/
 122         uint32_t min_bus_bandwidth;
 123         /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
 124         uint32_t min_core_set_clock_in_sr;
 125
 126         struct single_display_configuration displays[MAX_NUM_DISPLAY];
 127
 128         uint32_t vrefresh; /* for active display*/
 129
 130         uint32_t min_vblank_time; /* for active display*/
 131         bool multi_monitor_in_sync;
 132         /* Controller Index of primary display - used in MCLK SMC switching hang
 133          * SW Workaround*/
 134         uint32_t crtc_index;
 135         /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 136         uint32_t line_time_in_us;
 137         bool invalid_vblank_time;
 138
 139         uint32_t display_clk;
 140         /*
 141          * for given display configuration if multimonitormnsync == false then
 142          * Memory clock DPMS with this latency or below is allowed, DPMS with
 143          * higher latency not allowed.
 144          */
 145         uint32_t dce_tolerable_mclk_in_active_latency;
 146         uint32_t min_dcef_set_clk;
 147         uint32_t min_dcef_deep_sleep_set_clk;
 148 };
 149
 150 struct amd_pp_simple_clock_info {
 151         uint32_t        engine_max_clock;
 152         uint32_t        memory_max_clock;
 153         uint32_t        level;
 154 };
 155
 156 enum PP_DAL_POWERLEVEL {
 157         PP_DAL_POWERLEVEL_INVALID = 0,
 158         PP_DAL_POWERLEVEL_ULTRALOW,
 159         PP_DAL_POWERLEVEL_LOW,
 160         PP_DAL_POWERLEVEL_NOMINAL,
 161         PP_DAL_POWERLEVEL_PERFORMANCE,
 162
 163         PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
 164         PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
 165         PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
 166         PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
 167         PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
 168         PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
 169         PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
 170         PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
 171 };
 172
 173 struct amd_pp_clock_info {
 174         uint32_t min_engine_clock;
 175         uint32_t max_engine_clock;
 176         uint32_t min_memory_clock;
 177         uint32_t max_memory_clock;
 178         uint32_t min_bus_bandwidth;
 179         uint32_t max_bus_bandwidth;
 180         uint32_t max_engine_clock_in_sr;
 181         uint32_t min_engine_clock_in_sr;
 182         enum PP_DAL_POWERLEVEL max_clocks_state;
 183 };
 184
 185 enum amd_pp_clock_type {
 186         amd_pp_disp_clock = 1,
 187         amd_pp_sys_clock,
 188         amd_pp_mem_clock,
 189         amd_pp_dcef_clock,
 190         amd_pp_soc_clock,
 191         amd_pp_pixel_clock,
 192         amd_pp_phy_clock,
 193         amd_pp_dcf_clock,
 194         amd_pp_dpp_clock,
 195         amd_pp_f_clock = amd_pp_dcef_clock,
 196 };
 197
 198 #define MAX_NUM_CLOCKS 16
 199
 200 struct amd_pp_clocks {
 201         uint32_t count;
 202         uint32_t clock[MAX_NUM_CLOCKS];
 203         uint32_t latency[MAX_NUM_CLOCKS];
 204 };
 205
 206
 207 enum {
 208         PP_GROUP_UNKNOWN = 0,
 209         PP_GROUP_GFX = 1,
 210         PP_GROUP_SYS,
 211         PP_GROUP_MAX
 212 };
 213
 214 struct pp_states_info {
 215         uint32_t nums;
 216         uint32_t states[16];
 217 };
 218
 219 struct pp_gpu_power {
 220         uint32_t vddc_power;
 221         uint32_t vddci_power;
 222         uint32_t max_gpu_power;
 223         uint32_t average_gpu_power;
 224 };
 225
 226 struct pp_display_clock_request {
 227         enum amd_pp_clock_type clock_type;
 228         uint32_t clock_freq_in_khz;
 229 };
 230
 231 #define PP_GROUP_MASK        0xF0000000
 232 #define PP_GROUP_SHIFT       28
 233
 234 #define PP_BLOCK_MASK        0x0FFFFF00
 235 #define PP_BLOCK_SHIFT       8
 236
 237 #define PP_BLOCK_GFX_CG         0x01
 238 #define PP_BLOCK_GFX_MG         0x02
 239 #define PP_BLOCK_GFX_3D         0x04
 240 #define PP_BLOCK_GFX_RLC        0x08
 241 #define PP_BLOCK_GFX_CP         0x10
 242 #define PP_BLOCK_SYS_BIF        0x01
 243 #define PP_BLOCK_SYS_MC         0x02
 244 #define PP_BLOCK_SYS_ROM        0x04
 245 #define PP_BLOCK_SYS_DRM        0x08
 246 #define PP_BLOCK_SYS_HDP        0x10
 247 #define PP_BLOCK_SYS_SDMA       0x20
 248
 249 #define PP_STATE_MASK           0x0000000F
 250 #define PP_STATE_SHIFT          0
 251 #define PP_STATE_SUPPORT_MASK   0x000000F0
 252 #define PP_STATE_SUPPORT_SHIFT  0
 253
 254 #define PP_STATE_CG             0x01
 255 #define PP_STATE_LS             0x02
 256 #define PP_STATE_DS             0x04
 257 #define PP_STATE_SD             0x08
 258 #define PP_STATE_SUPPORT_CG     0x10
 259 #define PP_STATE_SUPPORT_LS     0x20
 260 #define PP_STATE_SUPPORT_DS     0x40
 261 #define PP_STATE_SUPPORT_SD     0x80
 262
 263 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
 264                                                                 block << PP_BLOCK_SHIFT |\
 265                                                                 support << PP_STATE_SUPPORT_SHIFT |\
 266                                                                 state << PP_STATE_SHIFT)
 267
 268 struct amd_powerplay {
 269         struct cgs_device *cgs_device;
 270         void *pp_handle;
 271         const struct amd_ip_funcs *ip_funcs;
 272         const struct amd_pm_funcs *pp_funcs;
 273 };
 274
 275 int amd_powerplay_reset(void *handle);
 276
 277 int amd_powerplay_display_configuration_change(void *handle,
 278                 const struct amd_pp_display_configuration *input);
 279
 280 int amd_powerplay_get_display_power_level(void *handle,
 281                 struct amd_pp_simple_clock_info *output);
 282
 283 int amd_powerplay_get_current_clocks(void *handle,
 284                 struct amd_pp_clock_info *output);
 285
 286 int amd_powerplay_get_clock_by_type(void *handle,
 287                 enum amd_pp_clock_type type,
 288                 struct amd_pp_clocks *clocks);
 289
 290 int amd_powerplay_get_clock_by_type_with_latency(void *handle,
 291                 enum amd_pp_clock_type type,
 292                 struct pp_clock_levels_with_latency *clocks);
 293
 294 int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
 295                 enum amd_pp_clock_type type,
 296                 struct pp_clock_levels_with_voltage *clocks);
 297
 298 int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
 299                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 300
 301 int amd_powerplay_display_clock_voltage_request(void *handle,
 302                 struct pp_display_clock_request *clock);
 303
 304 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
 305                 struct amd_pp_simple_clock_info *output);
 306
 307
 308 #endif /* _AMD_POWERPLAY_H_ */