drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HARDWARE_MANAGER_H_
  24 #define _HARDWARE_MANAGER_H_
  25
  26 struct pp_hwmgr;
  27
  28 /* Automatic Power State Throttling */
  29 enum PHM_AutoThrottleSource
  30 {
  31     PHM_AutoThrottleSource_Thermal,
  32     PHM_AutoThrottleSource_External
  33 };
  34
  35 typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
  36
  37 enum phm_platform_caps {
  38         PHM_PlatformCaps_AtomBiosPpV1 = 0,
  39         PHM_PlatformCaps_PowerPlaySupport,
  40         PHM_PlatformCaps_ACOverdriveSupport,
  41         PHM_PlatformCaps_BacklightSupport,
  42         PHM_PlatformCaps_ThermalController,
  43         PHM_PlatformCaps_BiosPowerSourceControl,
  44         PHM_PlatformCaps_DisableVoltageTransition,
  45         PHM_PlatformCaps_DisableEngineTransition,
  46         PHM_PlatformCaps_DisableMemoryTransition,
  47         PHM_PlatformCaps_DynamicPowerManagement,
  48         PHM_PlatformCaps_EnableASPML0s,
  49         PHM_PlatformCaps_EnableASPML1,
  50         PHM_PlatformCaps_OD5inACSupport,
  51         PHM_PlatformCaps_OD5inDCSupport,
  52         PHM_PlatformCaps_SoftStateOD5,
  53         PHM_PlatformCaps_NoOD5Support,
  54         PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
  55         PHM_PlatformCaps_ActivityReporting,
  56         PHM_PlatformCaps_EnableBackbias,
  57         PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
  58         PHM_PlatformCaps_ShowPowerBudgetWarning,
  59         PHM_PlatformCaps_PowerBudgetWaiverAvailable,
  60         PHM_PlatformCaps_GFXClockGatingSupport,
  61         PHM_PlatformCaps_MMClockGatingSupport,
  62         PHM_PlatformCaps_AutomaticDCTransition,
  63         PHM_PlatformCaps_GeminiPrimary,
  64         PHM_PlatformCaps_MemorySpreadSpectrumSupport,
  65         PHM_PlatformCaps_EngineSpreadSpectrumSupport,
  66         PHM_PlatformCaps_StepVddc,
  67         PHM_PlatformCaps_DynamicPCIEGen2Support,
  68         PHM_PlatformCaps_SMC,
  69         PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
  70         PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
  71         PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
  72         PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
  73         PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
  74         PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */
  75         PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
  76         PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
  77         PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
  78         PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
  79         PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
  80         PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
  81         PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
  82         PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
  83         PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
  84         PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
  85         PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
  86         PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
  87         PHM_PlatformCaps_ABM,                                   /* ABM support.*/
  88         PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
  89         PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
  90         PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
  91         PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
  92         PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
  93         PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
  94         PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
  95         PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
  96         PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
  97         PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
  98         PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
  99         PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
 100         PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
 101         PHM_PlatformCaps_AdjustUVDPriorityForSP,
 102         PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
 103         PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
 104         PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
 105         PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
 106         PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
 107         PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
 108         PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
 109         PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
 110         PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
 111         PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
 112         PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
 113         PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
 114         PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
 115         PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
 116         PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
 117         PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
 118         PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
 119         PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
 120         PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
 121         PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
 122         PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
 123         PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
 124         PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
 125         PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
 126         PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
 127         PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
 128         PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
 129         PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
 130         PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
 131         PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
 132         PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
 133         PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
 134         PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
 135         PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
 136         PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
 137         PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
 138         PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
 139         PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
 140         PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
 141         PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
 142         PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
 143         PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
 144         PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
 145         PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
 146         PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
 147         PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
 148         PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
 149         PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
 150         PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
 151         PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
 152         PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
 153         PHM_PlatformCaps_FPS,                                   /* FPS support */
 154         PHM_PlatformCaps_ACP,                                   /* ACP support */
 155         PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
 156         PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
 157         PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
 158         PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
 159         PHM_PlatformCaps_VddNBDirectRequest,
 160         PHM_PlatformCaps_PauseMMSessions,
 161         PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
 162         PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
 163         PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
 164         PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
 165         PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
 166         PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
 167         PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
 168         PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
 169         PHM_PlatformCaps_IOIC3,
 170         PHM_PlatformCaps_ConnectedStandby,
 171         PHM_PlatformCaps_EVV,
 172         PHM_PlatformCaps_EnableLongIdleBACOSupport,
 173         PHM_PlatformCaps_CombinePCCWithThermalSignal,
 174         PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
 175         PHM_PlatformCaps_StablePState,
 176         PHM_PlatformCaps_OD6PlusinACSupport,
 177         PHM_PlatformCaps_OD6PlusinDCSupport,
 178         PHM_PlatformCaps_ODThermalLimitUnlock,
 179         PHM_PlatformCaps_ReducePowerLimit,
 180         PHM_PlatformCaps_ODFuzzyFanControlSupport,
 181         PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
 182         PHM_PlatformCaps_ControlVDDGFX,
 183         PHM_PlatformCaps_BBBSupported,
 184         PHM_PlatformCaps_DisableVoltageIsland,
 185         PHM_PlatformCaps_FanSpeedInTableIsRPM,
 186         PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
 187         PHM_PlatformCaps_IcelandULPSSWWorkAround,
 188         PHM_PlatformCaps_FPSEnhancement,
 189         PHM_PlatformCaps_LoadPostProductionFirmware,
 190         PHM_PlatformCaps_VpuRecoveryInProgress,
 191         PHM_PlatformCaps_Falcon_QuickTransition,
 192         PHM_PlatformCaps_AVFS,
 193         PHM_PlatformCaps_ClockStretcher,
 194         PHM_PlatformCaps_TablelessHardwareInterface,
 195         PHM_PlatformCaps_EnableDriverEVV,
 196         PHM_PlatformCaps_Max
 197 };
 198
 199 #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
 200
 201 /* Number of uint32_t entries used by CAPS table */
 202 #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
 203         ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
 204
 205 struct pp_hw_descriptor {
 206         uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
 207 };
 208
 209 /* Function for setting a platform cap */
 210 static inline void phm_cap_set(uint32_t *caps,
 211                         enum phm_platform_caps c)
 212 {
 213         caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
 214                              (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
 215 }
 216
 217 static inline void phm_cap_unset(uint32_t *caps,
 218                         enum phm_platform_caps c)
 219 {
 220         caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
 221 }
 222
 223 static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
 224 {
 225         return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
 226                   (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
 227 }
 228
 229 enum phm_clock_Type {
 230         PHM_DispClock = 1,
 231         PHM_SClock,
 232         PHM_MemClock
 233 };
 234
 235 #define MAX_NUM_CLOCKS 16
 236
 237 struct PP_Clocks {
 238         uint32_t engineClock;
 239         uint32_t memoryClock;
 240         uint32_t BusBandwidth;
 241         uint32_t engineClockInSR;
 242 };
 243
 244 struct phm_platform_descriptor {
 245         uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
 246         uint32_t vbiosInterruptId;
 247         struct PP_Clocks overdriveLimit;
 248         struct PP_Clocks clockStep;
 249         uint32_t hardwareActivityPerformanceLevels;
 250         uint32_t minimumClocksReductionPercentage;
 251         uint32_t minOverdriveVDDC;
 252         uint32_t maxOverdriveVDDC;
 253         uint32_t overdriveVDDCStep;
 254         uint32_t hardwarePerformanceLevels;
 255         uint16_t powerBudget;
 256         uint32_t TDPLimit;
 257         uint32_t nearTDPLimit;
 258         uint32_t nearTDPLimitAdjusted;
 259         uint32_t SQRampingThreshold;
 260         uint32_t CACLeakage;
 261         uint16_t TDPODLimit;
 262         uint32_t TDPAdjustment;
 263         bool TDPAdjustmentPolarity;
 264         uint16_t LoadLineSlope;
 265         uint32_t  VidMinLimit;
 266         uint32_t  VidMaxLimit;
 267         uint32_t  VidStep;
 268         uint32_t  VidAdjustment;
 269         bool VidAdjustmentPolarity;
 270 };
 271
 272 struct phm_clocks {
 273         uint32_t num_of_entries;
 274         uint32_t clock[MAX_NUM_CLOCKS];
 275 };
 276
 277 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
 278 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
 279 extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
 280 #endif /* _HARDWARE_MANAGER_H_ */