drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32 #include "ppatomctrl.h"
  33 #include "hwmgr_ppt.h"
  34 #include "power_state.h"
  35 #include "cgs_linux.h"
  36
  37 struct pp_instance;
  38 struct pp_hwmgr;
  39 struct phm_fan_speed_info;
  40 struct pp_atomctrl_voltage_table;
  41
  42 #define VOLTAGE_SCALE 4
  43
  44 uint8_t convert_to_vid(uint16_t vddc);
  45
  46 enum DISPLAY_GAP {
  47         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  48         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  49         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  50         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  51 };
  52 typedef enum DISPLAY_GAP DISPLAY_GAP;
  53
  54 struct vi_dpm_level {
  55         bool enabled;
  56         uint32_t value;
  57         uint32_t param1;
  58 };
  59
  60 struct vi_dpm_table {
  61         uint32_t count;
  62         struct vi_dpm_level dpm_level[1];
  63 };
  64
  65 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  66 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  67 #define PCIE_PERF_REQ_GEN1         2
  68 #define PCIE_PERF_REQ_GEN2         3
  69 #define PCIE_PERF_REQ_GEN3         4
  70
  71 enum PP_FEATURE_MASK {
  72         PP_SCLK_DPM_MASK = 0x1,
  73         PP_MCLK_DPM_MASK = 0x2,
  74         PP_PCIE_DPM_MASK = 0x4,
  75         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
  76         PP_POWER_CONTAINMENT_MASK = 0x10,
  77         PP_UVD_HANDSHAKE_MASK = 0x20,
  78         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
  79         PP_VBI_TIME_SUPPORT_MASK = 0x80,
  80         PP_ULV_MASK = 0x100,
  81         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
  82         PP_CLOCK_STRETCH_MASK = 0x400,
  83         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
  84         PP_SOCCLK_DPM_MASK = 0x1000,
  85         PP_DCEFCLK_DPM_MASK = 0x2000,
  86 };
  87
  88 enum PHM_BackEnd_Magic {
  89         PHM_Dummy_Magic       = 0xAA5555AA,
  90         PHM_RV770_Magic       = 0xDCBAABCD,
  91         PHM_Kong_Magic        = 0x239478DF,
  92         PHM_NIslands_Magic    = 0x736C494E,
  93         PHM_Sumo_Magic        = 0x8339FA11,
  94         PHM_SIslands_Magic    = 0x369431AC,
  95         PHM_Trinity_Magic     = 0x96751873,
  96         PHM_CIslands_Magic    = 0x38AC78B0,
  97         PHM_Kv_Magic          = 0xDCBBABC0,
  98         PHM_VIslands_Magic    = 0x20130307,
  99         PHM_Cz_Magic          = 0x67DCBA25,
 100         PHM_Rv_Magic          = 0x20161121
 101 };
 102
 103 struct phm_set_power_state_input {
 104         const struct pp_hw_power_state *pcurrent_state;
 105         const struct pp_hw_power_state *pnew_state;
 106 };
 107
 108 struct phm_acp_arbiter {
 109         uint32_t acpclk;
 110 };
 111
 112 struct phm_uvd_arbiter {
 113         uint32_t vclk;
 114         uint32_t dclk;
 115         uint32_t vclk_ceiling;
 116         uint32_t dclk_ceiling;
 117         uint32_t vclk_soft_min;
 118         uint32_t dclk_soft_min;
 119 };
 120
 121 struct phm_vce_arbiter {
 122         uint32_t   evclk;
 123         uint32_t   ecclk;
 124 };
 125
 126 struct phm_gfx_arbiter {
 127         uint32_t sclk;
 128         uint32_t sclk_hard_min;
 129         uint32_t mclk;
 130         uint32_t sclk_over_drive;
 131         uint32_t mclk_over_drive;
 132         uint32_t sclk_threshold;
 133         uint32_t num_cus;
 134         uint32_t gfxclk;
 135         uint32_t fclk;
 136 };
 137
 138 struct phm_clock_array {
 139         uint32_t count;
 140         uint32_t values[1];
 141 };
 142
 143 struct phm_clock_voltage_dependency_record {
 144         uint32_t clk;
 145         uint32_t v;
 146 };
 147
 148 struct phm_vceclock_voltage_dependency_record {
 149         uint32_t ecclk;
 150         uint32_t evclk;
 151         uint32_t v;
 152 };
 153
 154 struct phm_uvdclock_voltage_dependency_record {
 155         uint32_t vclk;
 156         uint32_t dclk;
 157         uint32_t v;
 158 };
 159
 160 struct phm_samuclock_voltage_dependency_record {
 161         uint32_t samclk;
 162         uint32_t v;
 163 };
 164
 165 struct phm_acpclock_voltage_dependency_record {
 166         uint32_t acpclk;
 167         uint32_t v;
 168 };
 169
 170 struct phm_clock_voltage_dependency_table {
 171         uint32_t count;                                                                         /* Number of entries. */
 172         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 173 };
 174
 175 struct phm_phase_shedding_limits_record {
 176         uint32_t  Voltage;
 177         uint32_t    Sclk;
 178         uint32_t    Mclk;
 179 };
 180
 181 struct phm_uvd_clock_voltage_dependency_record {
 182         uint32_t vclk;
 183         uint32_t dclk;
 184         uint32_t v;
 185 };
 186
 187 struct phm_uvd_clock_voltage_dependency_table {
 188         uint8_t count;
 189         struct phm_uvd_clock_voltage_dependency_record entries[1];
 190 };
 191
 192 struct phm_acp_clock_voltage_dependency_record {
 193         uint32_t acpclk;
 194         uint32_t v;
 195 };
 196
 197 struct phm_acp_clock_voltage_dependency_table {
 198         uint32_t count;
 199         struct phm_acp_clock_voltage_dependency_record entries[1];
 200 };
 201
 202 struct phm_vce_clock_voltage_dependency_record {
 203         uint32_t ecclk;
 204         uint32_t evclk;
 205         uint32_t v;
 206 };
 207
 208 struct phm_phase_shedding_limits_table {
 209         uint32_t                           count;
 210         struct phm_phase_shedding_limits_record  entries[1];
 211 };
 212
 213 struct phm_vceclock_voltage_dependency_table {
 214         uint8_t count;                                    /* Number of entries. */
 215         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 216 };
 217
 218 struct phm_uvdclock_voltage_dependency_table {
 219         uint8_t count;                                    /* Number of entries. */
 220         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 221 };
 222
 223 struct phm_samuclock_voltage_dependency_table {
 224         uint8_t count;                                    /* Number of entries. */
 225         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 226 };
 227
 228 struct phm_acpclock_voltage_dependency_table {
 229         uint32_t count;                                    /* Number of entries. */
 230         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 231 };
 232
 233 struct phm_vce_clock_voltage_dependency_table {
 234         uint8_t count;
 235         struct phm_vce_clock_voltage_dependency_record entries[1];
 236 };
 237
 238 struct pp_smumgr_func {
 239         int (*smu_init)(struct pp_hwmgr  *hwmgr);
 240         int (*smu_fini)(struct pp_hwmgr  *hwmgr);
 241         int (*start_smu)(struct pp_hwmgr  *hwmgr);
 242         int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
 243                                     uint32_t firmware);
 244         int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
 245         int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
 246                                             uint32_t firmware);
 247         int (*get_argument)(struct pp_hwmgr  *hwmgr);
 248         int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
 249         int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
 250                                           uint16_t msg, uint32_t parameter);
 251         int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
 252                                          void **table);
 253         int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
 254         int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
 255         int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
 256         int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
 257         int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
 258         int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
 259         int (*init_smc_table)(struct pp_hwmgr *hwmgr);
 260         int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
 261         int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
 262         int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
 263         uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
 264         uint32_t (*get_mac_definition)(uint32_t value);
 265         bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
 266         int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
 267                         struct amd_pp_profile *request);
 268         bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
 269 };
 270
 271 struct pp_hwmgr_func {
 272         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 273         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 274         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 275         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 276
 277         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 278                                 struct pp_power_state  *prequest_ps,
 279                         const struct pp_power_state *pcurrent_ps);
 280
 281         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 282                                         enum amd_dpm_forced_level level);
 283
 284         int (*dynamic_state_management_enable)(
 285                                                 struct pp_hwmgr *hw_mgr);
 286         int (*dynamic_state_management_disable)(
 287                                                 struct pp_hwmgr *hw_mgr);
 288
 289         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 290                                      struct pp_hw_power_state *hw_ps);
 291
 292         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 293                             unsigned long, struct pp_power_state *);
 294         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 295         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 296         void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 297         void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 298         uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 299         uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 300         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 301                                                 const void *state);
 302         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 303         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 304         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 305         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 306         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 307                                                 const uint32_t *msg_id);
 308         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 309         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 310         int (*get_temperature)(struct pp_hwmgr *hwmgr);
 311         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 312         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 313         void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 314         uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 315         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 316         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 317         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 318         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 319         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 320         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 321         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 322                                         const void *thermal_interrupt_info);
 323         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 324         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 325                                         const struct pp_hw_power_state *pstate1,
 326                                         const struct pp_hw_power_state *pstate2,
 327                                         bool *equal);
 328         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 329         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 330                                 bool cc6_disable, bool pstate_disable,
 331                                 bool pstate_switch_disable);
 332         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 333                         struct amd_pp_simple_clock_info *info);
 334         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 335                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 336         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 337                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 338         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 339         int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
 340                         enum amd_pp_clock_type type,
 341                         struct pp_clock_levels_with_latency *clocks);
 342         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
 343                         enum amd_pp_clock_type type,
 344                         struct pp_clock_levels_with_voltage *clocks);
 345         int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
 346                         struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 347         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
 348                         struct pp_display_clock_request *clock);
 349         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 350         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 351         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 352         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 353         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 354         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 355         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 356         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 357         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 358         int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
 359         int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
 360                         struct amd_pp_profile *request);
 361         int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
 362         int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
 363         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
 364         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
 365         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
 366 };
 367
 368 struct pp_table_func {
 369         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 370         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 371         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 372         int (*pptable_get_vce_state_table_entry)(
 373                                                 struct pp_hwmgr *hwmgr,
 374                                                 unsigned long i,
 375                                                 struct amd_vce_state *vce_state,
 376                                                 void **clock_info,
 377                                                 unsigned long *flag);
 378 };
 379
 380 union phm_cac_leakage_record {
 381         struct {
 382                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 383                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 384         };
 385         struct {
 386                 uint16_t Vddc1;
 387                 uint16_t Vddc2;
 388                 uint16_t Vddc3;
 389         };
 390 };
 391
 392 struct phm_cac_leakage_table {
 393         uint32_t count;
 394         union phm_cac_leakage_record entries[1];
 395 };
 396
 397 struct phm_samu_clock_voltage_dependency_record {
 398         uint32_t samclk;
 399         uint32_t v;
 400 };
 401
 402
 403 struct phm_samu_clock_voltage_dependency_table {
 404         uint8_t count;
 405         struct phm_samu_clock_voltage_dependency_record entries[1];
 406 };
 407
 408 struct phm_cac_tdp_table {
 409         uint16_t usTDP;
 410         uint16_t usConfigurableTDP;
 411         uint16_t usTDC;
 412         uint16_t usBatteryPowerLimit;
 413         uint16_t usSmallPowerLimit;
 414         uint16_t usLowCACLeakage;
 415         uint16_t usHighCACLeakage;
 416         uint16_t usMaximumPowerDeliveryLimit;
 417         uint16_t usEDCLimit;
 418         uint16_t usOperatingTempMinLimit;
 419         uint16_t usOperatingTempMaxLimit;
 420         uint16_t usOperatingTempStep;
 421         uint16_t usOperatingTempHyst;
 422         uint16_t usDefaultTargetOperatingTemp;
 423         uint16_t usTargetOperatingTemp;
 424         uint16_t usPowerTuneDataSetID;
 425         uint16_t usSoftwareShutdownTemp;
 426         uint16_t usClockStretchAmount;
 427         uint16_t usTemperatureLimitHotspot;
 428         uint16_t usTemperatureLimitLiquid1;
 429         uint16_t usTemperatureLimitLiquid2;
 430         uint16_t usTemperatureLimitVrVddc;
 431         uint16_t usTemperatureLimitVrMvdd;
 432         uint16_t usTemperatureLimitPlx;
 433         uint8_t  ucLiquid1_I2C_address;
 434         uint8_t  ucLiquid2_I2C_address;
 435         uint8_t  ucLiquid_I2C_Line;
 436         uint8_t  ucVr_I2C_address;
 437         uint8_t  ucVr_I2C_Line;
 438         uint8_t  ucPlx_I2C_address;
 439         uint8_t  ucPlx_I2C_Line;
 440         uint32_t usBoostPowerLimit;
 441         uint8_t  ucCKS_LDO_REFSEL;
 442 };
 443
 444 struct phm_tdp_table {
 445         uint16_t usTDP;
 446         uint16_t usConfigurableTDP;
 447         uint16_t usTDC;
 448         uint16_t usBatteryPowerLimit;
 449         uint16_t usSmallPowerLimit;
 450         uint16_t usLowCACLeakage;
 451         uint16_t usHighCACLeakage;
 452         uint16_t usMaximumPowerDeliveryLimit;
 453         uint16_t usEDCLimit;
 454         uint16_t usOperatingTempMinLimit;
 455         uint16_t usOperatingTempMaxLimit;
 456         uint16_t usOperatingTempStep;
 457         uint16_t usOperatingTempHyst;
 458         uint16_t usDefaultTargetOperatingTemp;
 459         uint16_t usTargetOperatingTemp;
 460         uint16_t usPowerTuneDataSetID;
 461         uint16_t usSoftwareShutdownTemp;
 462         uint16_t usClockStretchAmount;
 463         uint16_t usTemperatureLimitTedge;
 464         uint16_t usTemperatureLimitHotspot;
 465         uint16_t usTemperatureLimitLiquid1;
 466         uint16_t usTemperatureLimitLiquid2;
 467         uint16_t usTemperatureLimitHBM;
 468         uint16_t usTemperatureLimitVrVddc;
 469         uint16_t usTemperatureLimitVrMvdd;
 470         uint16_t usTemperatureLimitPlx;
 471         uint8_t  ucLiquid1_I2C_address;
 472         uint8_t  ucLiquid2_I2C_address;
 473         uint8_t  ucLiquid_I2C_Line;
 474         uint8_t  ucVr_I2C_address;
 475         uint8_t  ucVr_I2C_Line;
 476         uint8_t  ucPlx_I2C_address;
 477         uint8_t  ucPlx_I2C_Line;
 478         uint8_t  ucLiquid_I2C_LineSDA;
 479         uint8_t  ucVr_I2C_LineSDA;
 480         uint8_t  ucPlx_I2C_LineSDA;
 481         uint32_t usBoostPowerLimit;
 482         uint16_t usBoostStartTemperature;
 483         uint16_t usBoostStopTemperature;
 484         uint32_t  ulBoostClock;
 485 };
 486
 487 struct phm_ppm_table {
 488         uint8_t   ppm_design;
 489         uint16_t  cpu_core_number;
 490         uint32_t  platform_tdp;
 491         uint32_t  small_ac_platform_tdp;
 492         uint32_t  platform_tdc;
 493         uint32_t  small_ac_platform_tdc;
 494         uint32_t  apu_tdp;
 495         uint32_t  dgpu_tdp;
 496         uint32_t  dgpu_ulv_power;
 497         uint32_t  tj_max;
 498 };
 499
 500 struct phm_vq_budgeting_record {
 501         uint32_t ulCUs;
 502         uint32_t ulSustainableSOCPowerLimitLow;
 503         uint32_t ulSustainableSOCPowerLimitHigh;
 504         uint32_t ulMinSclkLow;
 505         uint32_t ulMinSclkHigh;
 506         uint8_t  ucDispConfig;
 507         uint32_t ulDClk;
 508         uint32_t ulEClk;
 509         uint32_t ulSustainableSclk;
 510         uint32_t ulSustainableCUs;
 511 };
 512
 513 struct phm_vq_budgeting_table {
 514         uint8_t numEntries;
 515         struct phm_vq_budgeting_record entries[1];
 516 };
 517
 518 struct phm_clock_and_voltage_limits {
 519         uint32_t sclk;
 520         uint32_t mclk;
 521         uint32_t gfxclk;
 522         uint16_t vddc;
 523         uint16_t vddci;
 524         uint16_t vddgfx;
 525         uint16_t vddmem;
 526 };
 527
 528 /* Structure to hold PPTable information */
 529
 530 struct phm_ppt_v1_information {
 531         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 532         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 533         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 534         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 535         struct phm_clock_array *valid_sclk_values;
 536         struct phm_clock_array *valid_mclk_values;
 537         struct phm_clock_array *valid_socclk_values;
 538         struct phm_clock_array *valid_dcefclk_values;
 539         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 540         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 541         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 542         struct phm_ppm_table *ppm_parameter_table;
 543         struct phm_cac_tdp_table *cac_dtp_table;
 544         struct phm_tdp_table *tdp_table;
 545         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 546         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 547         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 548         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 549         struct phm_ppt_v1_pcie_table *pcie_table;
 550         struct phm_ppt_v1_gpio_table *gpio_table;
 551         uint16_t us_ulv_voltage_offset;
 552         uint16_t us_ulv_smnclk_did;
 553         uint16_t us_ulv_mp1clk_did;
 554         uint16_t us_ulv_gfxclk_bypass;
 555         uint16_t us_gfxclk_slew_rate;
 556         uint16_t us_min_gfxclk_freq_limit;
 557 };
 558
 559 struct phm_ppt_v2_information {
 560         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 561         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 562         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 563         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 564         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
 565         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
 566         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
 567         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 568
 569         struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
 570
 571         struct phm_clock_array *valid_sclk_values;
 572         struct phm_clock_array *valid_mclk_values;
 573         struct phm_clock_array *valid_socclk_values;
 574         struct phm_clock_array *valid_dcefclk_values;
 575
 576         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 577         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 578
 579         struct phm_ppm_table *ppm_parameter_table;
 580         struct phm_cac_tdp_table *cac_dtp_table;
 581         struct phm_tdp_table *tdp_table;
 582
 583         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 584         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 585         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 586         struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
 587
 588         struct phm_ppt_v1_pcie_table *pcie_table;
 589
 590         uint16_t us_ulv_voltage_offset;
 591         uint16_t us_ulv_smnclk_did;
 592         uint16_t us_ulv_mp1clk_did;
 593         uint16_t us_ulv_gfxclk_bypass;
 594         uint16_t us_gfxclk_slew_rate;
 595         uint16_t us_min_gfxclk_freq_limit;
 596
 597         uint8_t  uc_gfx_dpm_voltage_mode;
 598         uint8_t  uc_soc_dpm_voltage_mode;
 599         uint8_t  uc_uclk_dpm_voltage_mode;
 600         uint8_t  uc_uvd_dpm_voltage_mode;
 601         uint8_t  uc_vce_dpm_voltage_mode;
 602         uint8_t  uc_mp0_dpm_voltage_mode;
 603         uint8_t  uc_dcef_dpm_voltage_mode;
 604 };
 605
 606 struct phm_dynamic_state_info {
 607         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 608         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 609         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 610         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 611         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 612         struct phm_clock_array                    *valid_sclk_values;
 613         struct phm_clock_array                    *valid_mclk_values;
 614         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 615         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 616         uint32_t                                  mclk_sclk_ratio;
 617         uint32_t                                  sclk_mclk_delta;
 618         uint32_t                                  vddc_vddci_delta;
 619         uint32_t                                  min_vddc_for_pcie_gen2;
 620         struct phm_cac_leakage_table              *cac_leakage_table;
 621         struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
 622
 623         struct phm_vce_clock_voltage_dependency_table
 624                                             *vce_clock_voltage_dependency_table;
 625         struct phm_uvd_clock_voltage_dependency_table
 626                                             *uvd_clock_voltage_dependency_table;
 627         struct phm_acp_clock_voltage_dependency_table
 628                                             *acp_clock_voltage_dependency_table;
 629         struct phm_samu_clock_voltage_dependency_table
 630                                            *samu_clock_voltage_dependency_table;
 631
 632         struct phm_ppm_table                          *ppm_parameter_table;
 633         struct phm_cac_tdp_table                      *cac_dtp_table;
 634         struct phm_clock_voltage_dependency_table       *vdd_gfx_dependency_on_sclk;
 635         struct phm_vq_budgeting_table                           *vq_budgeting_table;
 636 };
 637
 638 struct pp_fan_info {
 639         bool bNoFan;
 640         uint8_t   ucTachometerPulsesPerRevolution;
 641         uint32_t   ulMinRPM;
 642         uint32_t   ulMaxRPM;
 643 };
 644
 645 struct pp_advance_fan_control_parameters {
 646         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 647         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 648         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 649         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 650         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 651         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 652         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 653         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 654         uint16_t  usTMax;                          /* The max temperature */
 655         uint8_t   ucFanControlMode;
 656         uint16_t  usFanPWMMinLimit;
 657         uint16_t  usFanPWMMaxLimit;
 658         uint16_t  usFanPWMStep;
 659         uint16_t  usDefaultMaxFanPWM;
 660         uint16_t  usFanOutputSensitivity;
 661         uint16_t  usDefaultFanOutputSensitivity;
 662         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 663         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 664         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 665         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 666         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 667         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 668         uint16_t  usFanCurrentLow;                 /* Low current */
 669         uint16_t  usFanCurrentHigh;                /* High current */
 670         uint16_t  usFanRPMLow;                     /* Low RPM */
 671         uint16_t  usFanRPMHigh;                    /* High RPM */
 672         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 673         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 674         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 675         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 676         uint16_t  usFanGainHotspot;
 677         uint16_t  usFanGainLiquid;
 678         uint16_t  usFanGainVrVddc;
 679         uint16_t  usFanGainVrMvdd;
 680         uint16_t  usFanGainPlx;
 681         uint16_t  usFanGainHbm;
 682         uint8_t   ucEnableZeroRPM;
 683         uint8_t   ucFanStopTemperature;
 684         uint8_t   ucFanStartTemperature;
 685         uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
 686         uint32_t  ulTargetGfxClk;
 687         uint16_t  usZeroRPMStartTemperature;
 688         uint16_t  usZeroRPMStopTemperature;
 689 };
 690
 691 struct pp_thermal_controller_info {
 692         uint8_t ucType;
 693         uint8_t ucI2cLine;
 694         uint8_t ucI2cAddress;
 695         struct pp_fan_info fanInfo;
 696         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 697 };
 698
 699 struct phm_microcode_version_info {
 700         uint32_t SMC;
 701         uint32_t DMCU;
 702         uint32_t MC;
 703         uint32_t NB;
 704 };
 705
 706 enum PP_TABLE_VERSION {
 707         PP_TABLE_V0 = 0,
 708         PP_TABLE_V1,
 709         PP_TABLE_V2,
 710         PP_TABLE_MAX
 711 };
 712
 713 /**
 714  * The main hardware manager structure.
 715  */
 716 struct pp_hwmgr {
 717         uint32_t chip_family;
 718         uint32_t chip_id;
 719
 720         uint32_t pp_table_version;
 721         void *device;
 722         struct pp_smumgr *smumgr;
 723         const void *soft_pp_table;
 724         uint32_t soft_pp_table_size;
 725         void *hardcode_pp_table;
 726         bool need_pp_table_upload;
 727
 728         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
 729         uint32_t num_vce_state_tables;
 730
 731         enum amd_dpm_forced_level dpm_level;
 732         enum amd_dpm_forced_level saved_dpm_level;
 733         enum amd_dpm_forced_level request_dpm_level;
 734         struct phm_gfx_arbiter gfx_arbiter;
 735         struct phm_acp_arbiter acp_arbiter;
 736         struct phm_uvd_arbiter uvd_arbiter;
 737         struct phm_vce_arbiter vce_arbiter;
 738         uint32_t usec_timeout;
 739         void *pptable;
 740         struct phm_platform_descriptor platform_descriptor;
 741         void *backend;
 742
 743         void *smu_backend;
 744         const struct pp_smumgr_func *smumgr_funcs;
 745         bool is_kicker;
 746         bool reload_fw;
 747
 748         enum PP_DAL_POWERLEVEL dal_power_level;
 749         struct phm_dynamic_state_info dyn_state;
 750         const struct pp_hwmgr_func *hwmgr_func;
 751         const struct pp_table_func *pptable_func;
 752
 753         struct pp_power_state    *ps;
 754         enum pp_power_source  power_source;
 755         uint32_t num_ps;
 756         struct pp_thermal_controller_info thermal_controller;
 757         bool fan_ctrl_is_in_default_mode;
 758         uint32_t fan_ctrl_default_mode;
 759         bool fan_ctrl_enabled;
 760         uint32_t tmin;
 761         struct phm_microcode_version_info microcode_version_info;
 762         uint32_t ps_size;
 763         struct pp_power_state    *current_ps;
 764         struct pp_power_state    *request_ps;
 765         struct pp_power_state    *boot_ps;
 766         struct pp_power_state    *uvd_ps;
 767         struct amd_pp_display_configuration display_config;
 768         uint32_t feature_mask;
 769
 770         /* UMD Pstate */
 771         struct amd_pp_profile gfx_power_profile;
 772         struct amd_pp_profile compute_power_profile;
 773         struct amd_pp_profile default_gfx_power_profile;
 774         struct amd_pp_profile default_compute_power_profile;
 775         enum amd_pp_profile_type current_power_profile;
 776         bool en_umd_pstate;
 777 };
 778
 779 struct cgs_irq_src_funcs {
 780         cgs_irq_source_set_func_t set;
 781         cgs_irq_handler_func_t handler;
 782 };
 783
 784 extern int hwmgr_early_init(struct pp_instance *handle);
 785 extern int hwmgr_hw_init(struct pp_instance *handle);
 786 extern int hwmgr_hw_fini(struct pp_instance *handle);
 787 extern int hwmgr_hw_suspend(struct pp_instance *handle);
 788 extern int hwmgr_hw_resume(struct pp_instance *handle);
 789 extern int hwmgr_handle_task(struct pp_instance *handle,
 790                                 enum amd_pp_task task_id,
 791                                 void *input, void *output);
 792 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 793                                 uint32_t value, uint32_t mask);
 794
 795 extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 796                                 uint32_t indirect_port,
 797                                 uint32_t index,
 798                                 uint32_t value,
 799                                 uint32_t mask);
 800
 801 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 802                                         uint32_t index,
 803                                         uint32_t value, uint32_t mask);
 804 extern int phm_wait_for_indirect_register_unequal(
 805                                 struct pp_hwmgr *hwmgr,
 806                                 uint32_t indirect_port, uint32_t index,
 807                                 uint32_t value, uint32_t mask);
 808
 809
 810 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 811 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 812 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
 813
 814 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
 815 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 816 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 817 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
 818 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
 819 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
 820 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
 821 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
 822 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
 823                 uint32_t voltage);
 824 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
 825 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
 826 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
 827 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
 828                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
 829 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 830 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
 831 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 832
 833 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
 834 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
 835 extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
 836
 837 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 838                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
 839
 840 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 841
 842 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 843 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 844
 845 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 846         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 847          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 848
 849 #define PHM_GET_FIELD(value, reg, field)        \
 850         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 851          PHM_FIELD_SHIFT(reg, field))
 852
 853
 854 /* Operations on named fields. */
 855
 856 #define PHM_READ_FIELD(device, reg, field)      \
 857         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 858
 859 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 860         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 861                         reg, field)
 862
 863 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 864         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 865                         reg, field)
 866
 867 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 868         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 869                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 870
 871 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 872         cgs_write_ind_register(device, port, ix##reg,   \
 873                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 874                                 reg, field, fieldval))
 875
 876 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 877         cgs_write_ind_register(device, port, ix##reg,   \
 878                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 879                                 reg, field, fieldval))
 880
 881 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
 882        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 883
 884
 885 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
 886        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 887
 888 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 889         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 890                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 891
 892 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 893                 phm_wait_for_indirect_register_unequal(hwmgr,                   \
 894                                 mm##port##_INDEX, index, value, mask)
 895
 896 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)    \
 897                 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 898
 899 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)                          \
 900                 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
 901                                 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
 902                                         PHM_FIELD_MASK(reg, field) )
 903
 904
 905 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,      \
 906                                 port, index, value, mask)               \
 907         phm_wait_for_indirect_register_unequal(hwmgr,                   \
 908                 mm##port##_INDEX_11, index, value, mask)
 909
 910 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)     \
 911                 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 912
 913 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
 914         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,       \
 915                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 916                 PHM_FIELD_MASK(reg, field))
 917
 918
 919 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,              \
 920                                 port, index, value, mask)               \
 921         phm_wait_on_indirect_register(hwmgr,                            \
 922                 mm##port##_INDEX_11, index, value, mask)
 923
 924 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
 925         PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 926
 927 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
 928         PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,               \
 929                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 930                 PHM_FIELD_MASK(reg, field))
 931
 932 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \
 933                                                         index, value, mask) \
 934                 phm_wait_for_register_unequal(hwmgr,            \
 935                                         index, value, mask)
 936
 937 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)              \
 938         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,                    \
 939                                 mm##reg, value, mask)
 940
 941 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)             \
 942         PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,                           \
 943                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 944                 PHM_FIELD_MASK(reg, field))
 945
 946 #endif /* _HWMGR_H_ */