2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "pp_instance.h"
29 #include "hardwaremanager.h"
30 #include "pp_power_source.h"
31 #include "hwmgr_ppt.h"
32 #include "ppatomctrl.h"
33 #include "hwmgr_ppt.h"
37 struct pp_hw_power_state
;
38 struct pp_power_state
;
40 struct phm_fan_speed_info
;
41 struct pp_atomctrl_voltage_table
;
45 DISPLAY_GAP_VBLANK_OR_WM
= 0, /* Wait for vblank or MCHG watermark. */
46 DISPLAY_GAP_VBLANK
= 1, /* Wait for vblank. */
47 DISPLAY_GAP_WATERMARK
= 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
48 DISPLAY_GAP_IGNORE
= 3 /* Do not wait. */
50 typedef enum DISPLAY_GAP DISPLAY_GAP
;
61 struct vi_dpm_level dpm_level
[1];
65 PP_Result_TableImmediateExit
= 0x13,
68 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0
69 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1
70 #define PCIE_PERF_REQ_GEN1 2
71 #define PCIE_PERF_REQ_GEN2 3
72 #define PCIE_PERF_REQ_GEN3 4
74 enum PHM_BackEnd_Magic
{
75 PHM_Dummy_Magic
= 0xAA5555AA,
76 PHM_RV770_Magic
= 0xDCBAABCD,
77 PHM_Kong_Magic
= 0x239478DF,
78 PHM_NIslands_Magic
= 0x736C494E,
79 PHM_Sumo_Magic
= 0x8339FA11,
80 PHM_SIslands_Magic
= 0x369431AC,
81 PHM_Trinity_Magic
= 0x96751873,
82 PHM_CIslands_Magic
= 0x38AC78B0,
83 PHM_Kv_Magic
= 0xDCBBABC0,
84 PHM_VIslands_Magic
= 0x20130307,
85 PHM_Cz_Magic
= 0x67DCBA25
89 #define PHM_PCIE_POWERGATING_TARGET_GFX 0
90 #define PHM_PCIE_POWERGATING_TARGET_DDI 1
91 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
92 #define PHM_PCIE_POWERGATING_TARGET_PHY 3
94 typedef int (*phm_table_function
)(struct pp_hwmgr
*hwmgr
, void *input
,
95 void *output
, void *storage
, int result
);
97 typedef bool (*phm_check_function
)(struct pp_hwmgr
*hwmgr
);
99 struct phm_set_power_state_input
{
100 const struct pp_hw_power_state
*pcurrent_state
;
101 const struct pp_hw_power_state
*pnew_state
;
104 struct phm_acp_arbiter
{
108 struct phm_uvd_arbiter
{
111 uint32_t vclk_ceiling
;
112 uint32_t dclk_ceiling
;
115 struct phm_vce_arbiter
{
120 struct phm_gfx_arbiter
{
123 uint32_t sclk_over_drive
;
124 uint32_t mclk_over_drive
;
125 uint32_t sclk_threshold
;
129 /* Entries in the master tables */
130 struct phm_master_table_item
{
131 phm_check_function isFunctionNeededInRuntimeTable
;
132 phm_table_function tableFunction
;
135 enum phm_master_table_flag
{
136 PHM_MasterTableFlag_None
= 0,
137 PHM_MasterTableFlag_ExitOnError
= 1,
140 /* The header of the master tables */
141 struct phm_master_table_header
{
142 uint32_t storage_size
;
144 const struct phm_master_table_item
*master_list
;
147 struct phm_runtime_table_header
{
148 uint32_t storage_size
;
150 phm_table_function
*function_list
;
153 struct phm_clock_array
{
158 struct phm_clock_voltage_dependency_record
{
163 struct phm_vceclock_voltage_dependency_record
{
169 struct phm_uvdclock_voltage_dependency_record
{
175 struct phm_samuclock_voltage_dependency_record
{
180 struct phm_acpclock_voltage_dependency_record
{
185 struct phm_clock_voltage_dependency_table
{
186 uint32_t count
; /* Number of entries. */
187 struct phm_clock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
190 struct phm_phase_shedding_limits_record
{
197 extern int phm_dispatch_table(struct pp_hwmgr
*hwmgr
,
198 struct phm_runtime_table_header
*rt_table
,
199 void *input
, void *output
);
201 extern int phm_construct_table(struct pp_hwmgr
*hwmgr
,
202 const struct phm_master_table_header
*master_table
,
203 struct phm_runtime_table_header
*rt_table
);
205 extern int phm_destroy_table(struct pp_hwmgr
*hwmgr
,
206 struct phm_runtime_table_header
*rt_table
);
209 struct phm_uvd_clock_voltage_dependency_record
{
215 struct phm_uvd_clock_voltage_dependency_table
{
217 struct phm_uvd_clock_voltage_dependency_record entries
[1];
220 struct phm_acp_clock_voltage_dependency_record
{
225 struct phm_acp_clock_voltage_dependency_table
{
227 struct phm_acp_clock_voltage_dependency_record entries
[1];
230 struct phm_vce_clock_voltage_dependency_record
{
236 struct phm_phase_shedding_limits_table
{
238 struct phm_phase_shedding_limits_record entries
[1];
241 struct phm_vceclock_voltage_dependency_table
{
242 uint8_t count
; /* Number of entries. */
243 struct phm_vceclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
246 struct phm_uvdclock_voltage_dependency_table
{
247 uint8_t count
; /* Number of entries. */
248 struct phm_uvdclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
251 struct phm_samuclock_voltage_dependency_table
{
252 uint8_t count
; /* Number of entries. */
253 struct phm_samuclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
256 struct phm_acpclock_voltage_dependency_table
{
257 uint32_t count
; /* Number of entries. */
258 struct phm_acpclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
261 struct phm_vce_clock_voltage_dependency_table
{
263 struct phm_vce_clock_voltage_dependency_record entries
[1];
266 struct pp_hwmgr_func
{
267 int (*backend_init
)(struct pp_hwmgr
*hw_mgr
);
268 int (*backend_fini
)(struct pp_hwmgr
*hw_mgr
);
269 int (*asic_setup
)(struct pp_hwmgr
*hw_mgr
);
270 int (*get_power_state_size
)(struct pp_hwmgr
*hw_mgr
);
272 int (*apply_state_adjust_rules
)(struct pp_hwmgr
*hwmgr
,
273 struct pp_power_state
*prequest_ps
,
274 const struct pp_power_state
*pcurrent_ps
);
276 int (*force_dpm_level
)(struct pp_hwmgr
*hw_mgr
,
277 enum amd_dpm_forced_level level
);
279 int (*dynamic_state_management_enable
)(
280 struct pp_hwmgr
*hw_mgr
);
282 int (*patch_boot_state
)(struct pp_hwmgr
*hwmgr
,
283 struct pp_hw_power_state
*hw_ps
);
285 int (*get_pp_table_entry
)(struct pp_hwmgr
*hwmgr
,
286 unsigned long, struct pp_power_state
*);
287 int (*get_num_of_pp_table_entries
)(struct pp_hwmgr
*hwmgr
);
288 int (*powerdown_uvd
)(struct pp_hwmgr
*hwmgr
);
289 int (*powergate_vce
)(struct pp_hwmgr
*hwmgr
, bool bgate
);
290 int (*powergate_uvd
)(struct pp_hwmgr
*hwmgr
, bool bgate
);
291 int (*get_mclk
)(struct pp_hwmgr
*hwmgr
, bool low
);
292 int (*get_sclk
)(struct pp_hwmgr
*hwmgr
, bool low
);
293 int (*power_state_set
)(struct pp_hwmgr
*hwmgr
,
295 void (*print_current_perforce_level
)(struct pp_hwmgr
*hwmgr
,
297 int (*enable_clock_power_gating
)(struct pp_hwmgr
*hwmgr
);
298 int (*notify_smc_display_config_after_ps_adjustment
)(struct pp_hwmgr
*hwmgr
);
299 int (*display_config_changed
)(struct pp_hwmgr
*hwmgr
);
300 int (*disable_clock_power_gating
)(struct pp_hwmgr
*hwmgr
);
301 int (*update_clock_gatings
)(struct pp_hwmgr
*hwmgr
,
302 const uint32_t *msg_id
);
303 int (*set_max_fan_rpm_output
)(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
);
304 int (*set_max_fan_pwm_output
)(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
);
305 int (*get_temperature
)(struct pp_hwmgr
*hwmgr
);
306 int (*stop_thermal_controller
)(struct pp_hwmgr
*hwmgr
);
307 int (*get_fan_speed_info
)(struct pp_hwmgr
*hwmgr
, struct phm_fan_speed_info
*fan_speed_info
);
308 int (*set_fan_control_mode
)(struct pp_hwmgr
*hwmgr
, uint32_t mode
);
309 int (*get_fan_control_mode
)(struct pp_hwmgr
*hwmgr
);
310 int (*set_fan_speed_percent
)(struct pp_hwmgr
*hwmgr
, uint32_t percent
);
311 int (*get_fan_speed_percent
)(struct pp_hwmgr
*hwmgr
, uint32_t *speed
);
312 int (*set_fan_speed_rpm
)(struct pp_hwmgr
*hwmgr
, uint32_t percent
);
313 int (*get_fan_speed_rpm
)(struct pp_hwmgr
*hwmgr
, uint32_t *speed
);
314 int (*reset_fan_speed_to_default
)(struct pp_hwmgr
*hwmgr
);
315 int (*uninitialize_thermal_controller
)(struct pp_hwmgr
*hwmgr
);
316 int (*register_internal_thermal_interrupt
)(struct pp_hwmgr
*hwmgr
,
317 const void *thermal_interrupt_info
);
318 bool (*check_smc_update_required_for_display_configuration
)(struct pp_hwmgr
*hwmgr
);
319 int (*check_states_equal
)(struct pp_hwmgr
*hwmgr
,
320 const struct pp_hw_power_state
*pstate1
,
321 const struct pp_hw_power_state
*pstate2
,
323 int (*set_cpu_power_state
)(struct pp_hwmgr
*hwmgr
);
324 int (*store_cc6_data
)(struct pp_hwmgr
*hwmgr
, uint32_t separation_time
,
325 bool cc6_disable
, bool pstate_disable
,
326 bool pstate_switch_disable
);
327 int (*get_dal_power_level
)(struct pp_hwmgr
*hwmgr
,
328 struct amd_pp_simple_clock_info
*info
);
329 int (*get_performance_level
)(struct pp_hwmgr
*, const struct pp_hw_power_state
*,
330 PHM_PerformanceLevelDesignation
, uint32_t, PHM_PerformanceLevel
*);
331 int (*get_current_shallow_sleep_clocks
)(struct pp_hwmgr
*hwmgr
,
332 const struct pp_hw_power_state
*state
, struct pp_clock_info
*clock_info
);
333 int (*get_clock_by_type
)(struct pp_hwmgr
*hwmgr
, enum amd_pp_clock_type type
, struct amd_pp_clocks
*clocks
);
334 int (*get_max_high_clocks
)(struct pp_hwmgr
*hwmgr
, struct amd_pp_simple_clock_info
*clocks
);
335 int (*power_off_asic
)(struct pp_hwmgr
*hwmgr
);
336 int (*get_pp_table
)(struct pp_hwmgr
*hwmgr
, char **table
);
337 int (*set_pp_table
)(struct pp_hwmgr
*hwmgr
, const char *buf
, size_t size
);
338 int (*force_clock_level
)(struct pp_hwmgr
*hwmgr
, enum pp_clock_type type
, uint32_t mask
);
339 int (*print_clock_levels
)(struct pp_hwmgr
*hwmgr
, enum pp_clock_type type
, char *buf
);
340 int (*enable_per_cu_power_gating
)(struct pp_hwmgr
*hwmgr
, bool enable
);
343 struct pp_table_func
{
344 int (*pptable_init
)(struct pp_hwmgr
*hw_mgr
);
345 int (*pptable_fini
)(struct pp_hwmgr
*hw_mgr
);
346 int (*pptable_get_number_of_vce_state_table_entries
)(struct pp_hwmgr
*hw_mgr
);
347 int (*pptable_get_vce_state_table_entry
)(
348 struct pp_hwmgr
*hwmgr
,
350 struct PP_VCEState
*vce_state
,
352 unsigned long *flag
);
355 union phm_cac_leakage_record
{
357 uint16_t Vddc
; /* in CI, we use it for StdVoltageHiSidd */
358 uint32_t Leakage
; /* in CI, we use it for StdVoltageLoSidd */
367 struct phm_cac_leakage_table
{
369 union phm_cac_leakage_record entries
[1];
372 struct phm_samu_clock_voltage_dependency_record
{
378 struct phm_samu_clock_voltage_dependency_table
{
380 struct phm_samu_clock_voltage_dependency_record entries
[1];
383 struct phm_cac_tdp_table
{
385 uint16_t usConfigurableTDP
;
387 uint16_t usBatteryPowerLimit
;
388 uint16_t usSmallPowerLimit
;
389 uint16_t usLowCACLeakage
;
390 uint16_t usHighCACLeakage
;
391 uint16_t usMaximumPowerDeliveryLimit
;
392 uint16_t usOperatingTempMinLimit
;
393 uint16_t usOperatingTempMaxLimit
;
394 uint16_t usOperatingTempStep
;
395 uint16_t usOperatingTempHyst
;
396 uint16_t usDefaultTargetOperatingTemp
;
397 uint16_t usTargetOperatingTemp
;
398 uint16_t usPowerTuneDataSetID
;
399 uint16_t usSoftwareShutdownTemp
;
400 uint16_t usClockStretchAmount
;
401 uint16_t usTemperatureLimitHotspot
;
402 uint16_t usTemperatureLimitLiquid1
;
403 uint16_t usTemperatureLimitLiquid2
;
404 uint16_t usTemperatureLimitVrVddc
;
405 uint16_t usTemperatureLimitVrMvdd
;
406 uint16_t usTemperatureLimitPlx
;
407 uint8_t ucLiquid1_I2C_address
;
408 uint8_t ucLiquid2_I2C_address
;
409 uint8_t ucLiquid_I2C_Line
;
410 uint8_t ucVr_I2C_address
;
411 uint8_t ucVr_I2C_Line
;
412 uint8_t ucPlx_I2C_address
;
413 uint8_t ucPlx_I2C_Line
;
416 struct phm_ppm_table
{
418 uint16_t cpu_core_number
;
419 uint32_t platform_tdp
;
420 uint32_t small_ac_platform_tdp
;
421 uint32_t platform_tdc
;
422 uint32_t small_ac_platform_tdc
;
425 uint32_t dgpu_ulv_power
;
429 struct phm_vq_budgeting_record
{
431 uint32_t ulSustainableSOCPowerLimitLow
;
432 uint32_t ulSustainableSOCPowerLimitHigh
;
433 uint32_t ulMinSclkLow
;
434 uint32_t ulMinSclkHigh
;
435 uint8_t ucDispConfig
;
438 uint32_t ulSustainableSclk
;
439 uint32_t ulSustainableCUs
;
442 struct phm_vq_budgeting_table
{
444 struct phm_vq_budgeting_record entries
[1];
447 struct phm_clock_and_voltage_limits
{
455 /* Structure to hold PPTable information */
457 struct phm_ppt_v1_information
{
458 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_sclk
;
459 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_mclk
;
460 struct phm_clock_array
*valid_sclk_values
;
461 struct phm_clock_array
*valid_mclk_values
;
462 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc
;
463 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac
;
464 struct phm_clock_voltage_dependency_table
*vddc_dep_on_dal_pwrl
;
465 struct phm_ppm_table
*ppm_parameter_table
;
466 struct phm_cac_tdp_table
*cac_dtp_table
;
467 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_dep_table
;
468 struct phm_ppt_v1_voltage_lookup_table
*vddc_lookup_table
;
469 struct phm_ppt_v1_voltage_lookup_table
*vddgfx_lookup_table
;
470 struct phm_ppt_v1_pcie_table
*pcie_table
;
471 uint16_t us_ulv_voltage_offset
;
474 struct phm_dynamic_state_info
{
475 struct phm_clock_voltage_dependency_table
*vddc_dependency_on_sclk
;
476 struct phm_clock_voltage_dependency_table
*vddci_dependency_on_mclk
;
477 struct phm_clock_voltage_dependency_table
*vddc_dependency_on_mclk
;
478 struct phm_clock_voltage_dependency_table
*mvdd_dependency_on_mclk
;
479 struct phm_clock_voltage_dependency_table
*vddc_dep_on_dal_pwrl
;
480 struct phm_clock_array
*valid_sclk_values
;
481 struct phm_clock_array
*valid_mclk_values
;
482 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc
;
483 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac
;
484 uint32_t mclk_sclk_ratio
;
485 uint32_t sclk_mclk_delta
;
486 uint32_t vddc_vddci_delta
;
487 uint32_t min_vddc_for_pcie_gen2
;
488 struct phm_cac_leakage_table
*cac_leakage_table
;
489 struct phm_phase_shedding_limits_table
*vddc_phase_shed_limits_table
;
491 struct phm_vce_clock_voltage_dependency_table
492 *vce_clock_voltage_dependency_table
;
493 struct phm_uvd_clock_voltage_dependency_table
494 *uvd_clock_voltage_dependency_table
;
495 struct phm_acp_clock_voltage_dependency_table
496 *acp_clock_voltage_dependency_table
;
497 struct phm_samu_clock_voltage_dependency_table
498 *samu_clock_voltage_dependency_table
;
500 struct phm_ppm_table
*ppm_parameter_table
;
501 struct phm_cac_tdp_table
*cac_dtp_table
;
502 struct phm_clock_voltage_dependency_table
*vdd_gfx_dependency_on_sclk
;
503 struct phm_vq_budgeting_table
*vq_budgeting_table
;
508 uint8_t ucTachometerPulsesPerRevolution
;
513 struct pp_advance_fan_control_parameters
{
514 uint16_t usTMin
; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
515 uint16_t usTMed
; /* The middle temperature where we change slopes. */
516 uint16_t usTHigh
; /* The high temperature for setting the second slope. */
517 uint16_t usPWMMin
; /* The minimum PWM value in percent (0.01% increments). */
518 uint16_t usPWMMed
; /* The PWM value (in percent) at TMed. */
519 uint16_t usPWMHigh
; /* The PWM value at THigh. */
520 uint8_t ucTHyst
; /* Temperature hysteresis. Integer. */
521 uint32_t ulCycleDelay
; /* The time between two invocations of the fan control routine in microseconds. */
522 uint16_t usTMax
; /* The max temperature */
523 uint8_t ucFanControlMode
;
524 uint16_t usFanPWMMinLimit
;
525 uint16_t usFanPWMMaxLimit
;
526 uint16_t usFanPWMStep
;
527 uint16_t usDefaultMaxFanPWM
;
528 uint16_t usFanOutputSensitivity
;
529 uint16_t usDefaultFanOutputSensitivity
;
530 uint16_t usMaxFanPWM
; /* The max Fan PWM value for Fuzzy Fan Control feature */
531 uint16_t usFanRPMMinLimit
; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
532 uint16_t usFanRPMMaxLimit
; /* Maximum limit range in percentage, usually set to 100% by default */
533 uint16_t usFanRPMStep
; /* Step increments/decerements, in percent */
534 uint16_t usDefaultMaxFanRPM
; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
535 uint16_t usMaxFanRPM
; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
536 uint16_t usFanCurrentLow
; /* Low current */
537 uint16_t usFanCurrentHigh
; /* High current */
538 uint16_t usFanRPMLow
; /* Low RPM */
539 uint16_t usFanRPMHigh
; /* High RPM */
540 uint32_t ulMinFanSCLKAcousticLimit
; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
541 uint8_t ucTargetTemperature
; /* Advanced fan controller target temperature. */
542 uint8_t ucMinimumPWMLimit
; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
543 uint16_t usFanGainEdge
; /* The following is added for Fiji */
544 uint16_t usFanGainHotspot
;
545 uint16_t usFanGainLiquid
;
546 uint16_t usFanGainVrVddc
;
547 uint16_t usFanGainVrMvdd
;
548 uint16_t usFanGainPlx
;
549 uint16_t usFanGainHbm
;
552 struct pp_thermal_controller_info
{
555 uint8_t ucI2cAddress
;
556 struct pp_fan_info fanInfo
;
557 struct pp_advance_fan_control_parameters advanceFanControlParameters
;
560 struct phm_microcode_version_info
{
568 * The main hardware manager structure.
571 uint32_t chip_family
;
573 uint32_t hw_revision
;
575 uint32_t sub_vendor_id
;
578 struct pp_smumgr
*smumgr
;
579 const void *soft_pp_table
;
580 uint32_t soft_pp_table_size
;
581 bool need_pp_table_upload
;
582 enum amd_dpm_forced_level dpm_level
;
583 bool block_hw_access
;
584 struct phm_gfx_arbiter gfx_arbiter
;
585 struct phm_acp_arbiter acp_arbiter
;
586 struct phm_uvd_arbiter uvd_arbiter
;
587 struct phm_vce_arbiter vce_arbiter
;
588 uint32_t usec_timeout
;
590 struct phm_platform_descriptor platform_descriptor
;
592 enum PP_DAL_POWERLEVEL dal_power_level
;
593 struct phm_dynamic_state_info dyn_state
;
594 struct phm_runtime_table_header setup_asic
;
595 struct phm_runtime_table_header power_down_asic
;
596 struct phm_runtime_table_header disable_dynamic_state_management
;
597 struct phm_runtime_table_header enable_dynamic_state_management
;
598 struct phm_runtime_table_header set_power_state
;
599 struct phm_runtime_table_header enable_clock_power_gatings
;
600 struct phm_runtime_table_header display_configuration_changed
;
601 struct phm_runtime_table_header start_thermal_controller
;
602 struct phm_runtime_table_header set_temperature_range
;
603 const struct pp_hwmgr_func
*hwmgr_func
;
604 const struct pp_table_func
*pptable_func
;
605 struct pp_power_state
*ps
;
606 enum pp_power_source power_source
;
608 struct pp_thermal_controller_info thermal_controller
;
609 bool fan_ctrl_is_in_default_mode
;
610 uint32_t fan_ctrl_default_mode
;
612 struct phm_microcode_version_info microcode_version_info
;
614 struct pp_power_state
*current_ps
;
615 struct pp_power_state
*request_ps
;
616 struct pp_power_state
*boot_ps
;
617 struct pp_power_state
*uvd_ps
;
618 struct amd_pp_display_configuration display_config
;
622 extern int hwmgr_init(struct amd_pp_init
*pp_init
,
623 struct pp_instance
*handle
);
625 extern int hwmgr_fini(struct pp_hwmgr
*hwmgr
);
627 extern int hw_init_power_state_table(struct pp_hwmgr
*hwmgr
);
629 extern int phm_wait_on_register(struct pp_hwmgr
*hwmgr
, uint32_t index
,
630 uint32_t value
, uint32_t mask
);
632 extern int phm_wait_for_register_unequal(struct pp_hwmgr
*hwmgr
,
633 uint32_t index
, uint32_t value
, uint32_t mask
);
635 extern uint32_t phm_read_indirect_register(struct pp_hwmgr
*hwmgr
,
636 uint32_t indirect_port
, uint32_t index
);
638 extern void phm_write_indirect_register(struct pp_hwmgr
*hwmgr
,
639 uint32_t indirect_port
,
643 extern void phm_wait_on_indirect_register(struct pp_hwmgr
*hwmgr
,
644 uint32_t indirect_port
,
649 extern void phm_wait_for_indirect_register_unequal(
650 struct pp_hwmgr
*hwmgr
,
651 uint32_t indirect_port
,
656 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr
*hwmgr
);
657 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr
*hwmgr
);
658 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr
*hwmgr
);
660 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
);
661 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_clock_voltage_dependency_table
*dep_table
);
662 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_clock_voltage_dependency_table
*dep_table
);
663 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_voltage_lookup_table
*lookup_table
);
664 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps
, struct pp_atomctrl_voltage_table
*vol_table
);
665 extern int phm_reset_single_dpm_table(void *table
, uint32_t count
, int max
);
666 extern void phm_setup_pcie_table_entry(void *table
, uint32_t index
, uint32_t pcie_gen
, uint32_t pcie_lanes
);
667 extern int32_t phm_get_dpm_level_enable_mask_value(void *table
);
668 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table
*lookup_table
, uint16_t voltage
);
669 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table
*vddci_table
, uint16_t vddci
);
670 extern int phm_find_boot_level(void *table
, uint32_t value
, uint32_t *boot_level
);
671 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr
*hwmgr
, phm_ppt_v1_voltage_lookup_table
*lookup_table
,
672 uint16_t virtual_voltage_id
, int32_t *sclk
);
673 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr
*hwmgr
);
674 extern int phm_hwmgr_backend_fini(struct pp_hwmgr
*hwmgr
);
675 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr
*hwmgr
, uint32_t mask
);
676 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr
*hwmgr
);
678 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
680 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
681 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
683 #define PHM_SET_FIELD(origval, reg, field, fieldval) \
684 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
685 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
687 #define PHM_GET_FIELD(value, reg, field) \
688 (((value) & PHM_FIELD_MASK(reg, field)) >> \
689 PHM_FIELD_SHIFT(reg, field))
692 #define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \
693 phm_wait_on_register(hwmgr, index, value, mask)
695 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \
696 phm_wait_for_register_unequal(hwmgr, index, value, mask)
698 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
699 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
701 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
702 phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
704 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
705 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
707 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
708 phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
710 /* Operations on named registers. */
712 #define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \
713 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
715 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
716 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
718 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
719 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
721 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
722 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
724 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
725 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
727 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
728 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
730 /* Operations on named fields. */
732 #define PHM_READ_FIELD(device, reg, field) \
733 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
735 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
736 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
739 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
740 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
743 #define PHM_WRITE_FIELD(device, reg, field, fieldval) \
744 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
745 cgs_read_register(device, mm##reg), reg, field, fieldval))
747 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
748 cgs_write_ind_register(device, port, ix##reg, \
749 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
750 reg, field, fieldval))
752 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
753 cgs_write_ind_register(device, port, ix##reg, \
754 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
755 reg, field, fieldval))
757 #define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \
758 PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \
759 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
761 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
762 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
763 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
765 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
766 PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
767 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
769 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
770 PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \
771 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
773 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
774 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
775 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
777 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
778 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
779 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
781 /* Operations on arrays of registers & fields. */
783 #define PHM_READ_ARRAY_REGISTER(device, reg, offset) \
784 cgs_read_register(device, mm##reg + (offset))
786 #define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \
787 cgs_write_register(device, mm##reg + (offset), value)
789 #define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \
790 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
792 #define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \
793 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
795 #define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
796 PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
798 #define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
799 PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \
800 PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \
801 reg, field, fieldvalue))
803 #define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
804 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
805 (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
806 PHM_FIELD_MASK(reg, field))
808 #define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \
809 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
810 (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
811 PHM_FIELD_MASK(reg, field))
813 #endif /* _HWMGR_H_ */