2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "pp_instance.h"
29 #include "hardwaremanager.h"
30 #include "pp_power_source.h"
31 #include "hwmgr_ppt.h"
32 #include "ppatomctrl.h"
33 #include "hwmgr_ppt.h"
34 #include "power_state.h"
38 struct phm_fan_speed_info
;
39 struct pp_atomctrl_voltage_table
;
41 #define VOLTAGE_SCALE 4
43 uint8_t convert_to_vid(uint16_t vddc
);
46 DISPLAY_GAP_VBLANK_OR_WM
= 0, /* Wait for vblank or MCHG watermark. */
47 DISPLAY_GAP_VBLANK
= 1, /* Wait for vblank. */
48 DISPLAY_GAP_WATERMARK
= 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
49 DISPLAY_GAP_IGNORE
= 3 /* Do not wait. */
51 typedef enum DISPLAY_GAP DISPLAY_GAP
;
61 struct vi_dpm_level dpm_level
[1];
65 PP_Result_TableImmediateExit
= 0x13,
68 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0
69 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1
70 #define PCIE_PERF_REQ_GEN1 2
71 #define PCIE_PERF_REQ_GEN2 3
72 #define PCIE_PERF_REQ_GEN3 4
74 enum PP_FEATURE_MASK
{
75 PP_SCLK_DPM_MASK
= 0x1,
76 PP_MCLK_DPM_MASK
= 0x2,
77 PP_PCIE_DPM_MASK
= 0x4,
78 PP_SCLK_DEEP_SLEEP_MASK
= 0x8,
79 PP_POWER_CONTAINMENT_MASK
= 0x10,
80 PP_UVD_HANDSHAKE_MASK
= 0x20,
81 PP_SMC_VOLTAGE_CONTROL_MASK
= 0x40,
82 PP_VBI_TIME_SUPPORT_MASK
= 0x80,
84 PP_ENABLE_GFX_CG_THRU_SMU
= 0x200,
85 PP_CLOCK_STRETCH_MASK
= 0x400,
86 PP_OD_FUZZY_FAN_CONTROL_MASK
= 0x800,
87 PP_SOCCLK_DPM_MASK
= 0x1000,
88 PP_DCEFCLK_DPM_MASK
= 0x2000,
91 enum PHM_BackEnd_Magic
{
92 PHM_Dummy_Magic
= 0xAA5555AA,
93 PHM_RV770_Magic
= 0xDCBAABCD,
94 PHM_Kong_Magic
= 0x239478DF,
95 PHM_NIslands_Magic
= 0x736C494E,
96 PHM_Sumo_Magic
= 0x8339FA11,
97 PHM_SIslands_Magic
= 0x369431AC,
98 PHM_Trinity_Magic
= 0x96751873,
99 PHM_CIslands_Magic
= 0x38AC78B0,
100 PHM_Kv_Magic
= 0xDCBBABC0,
101 PHM_VIslands_Magic
= 0x20130307,
102 PHM_Cz_Magic
= 0x67DCBA25
106 #define PHM_PCIE_POWERGATING_TARGET_GFX 0
107 #define PHM_PCIE_POWERGATING_TARGET_DDI 1
108 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
109 #define PHM_PCIE_POWERGATING_TARGET_PHY 3
111 typedef int (*phm_table_function
)(struct pp_hwmgr
*hwmgr
, void *input
,
112 void *output
, void *storage
, int result
);
114 typedef bool (*phm_check_function
)(struct pp_hwmgr
*hwmgr
);
116 struct phm_set_power_state_input
{
117 const struct pp_hw_power_state
*pcurrent_state
;
118 const struct pp_hw_power_state
*pnew_state
;
121 struct phm_acp_arbiter
{
125 struct phm_uvd_arbiter
{
128 uint32_t vclk_ceiling
;
129 uint32_t dclk_ceiling
;
132 struct phm_vce_arbiter
{
137 struct phm_gfx_arbiter
{
140 uint32_t sclk_over_drive
;
141 uint32_t mclk_over_drive
;
142 uint32_t sclk_threshold
;
146 /* Entries in the master tables */
147 struct phm_master_table_item
{
148 phm_check_function isFunctionNeededInRuntimeTable
;
149 phm_table_function tableFunction
;
152 enum phm_master_table_flag
{
153 PHM_MasterTableFlag_None
= 0,
154 PHM_MasterTableFlag_ExitOnError
= 1,
157 /* The header of the master tables */
158 struct phm_master_table_header
{
159 uint32_t storage_size
;
161 const struct phm_master_table_item
*master_list
;
164 struct phm_runtime_table_header
{
165 uint32_t storage_size
;
167 phm_table_function
*function_list
;
170 struct phm_clock_array
{
175 struct phm_clock_voltage_dependency_record
{
180 struct phm_vceclock_voltage_dependency_record
{
186 struct phm_uvdclock_voltage_dependency_record
{
192 struct phm_samuclock_voltage_dependency_record
{
197 struct phm_acpclock_voltage_dependency_record
{
202 struct phm_clock_voltage_dependency_table
{
203 uint32_t count
; /* Number of entries. */
204 struct phm_clock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
207 struct phm_phase_shedding_limits_record
{
214 extern int phm_dispatch_table(struct pp_hwmgr
*hwmgr
,
215 struct phm_runtime_table_header
*rt_table
,
216 void *input
, void *output
);
218 extern int phm_construct_table(struct pp_hwmgr
*hwmgr
,
219 const struct phm_master_table_header
*master_table
,
220 struct phm_runtime_table_header
*rt_table
);
222 extern int phm_destroy_table(struct pp_hwmgr
*hwmgr
,
223 struct phm_runtime_table_header
*rt_table
);
226 struct phm_uvd_clock_voltage_dependency_record
{
232 struct phm_uvd_clock_voltage_dependency_table
{
234 struct phm_uvd_clock_voltage_dependency_record entries
[1];
237 struct phm_acp_clock_voltage_dependency_record
{
242 struct phm_acp_clock_voltage_dependency_table
{
244 struct phm_acp_clock_voltage_dependency_record entries
[1];
247 struct phm_vce_clock_voltage_dependency_record
{
253 struct phm_phase_shedding_limits_table
{
255 struct phm_phase_shedding_limits_record entries
[1];
258 struct phm_vceclock_voltage_dependency_table
{
259 uint8_t count
; /* Number of entries. */
260 struct phm_vceclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
263 struct phm_uvdclock_voltage_dependency_table
{
264 uint8_t count
; /* Number of entries. */
265 struct phm_uvdclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
268 struct phm_samuclock_voltage_dependency_table
{
269 uint8_t count
; /* Number of entries. */
270 struct phm_samuclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
273 struct phm_acpclock_voltage_dependency_table
{
274 uint32_t count
; /* Number of entries. */
275 struct phm_acpclock_voltage_dependency_record entries
[1]; /* Dynamically allocate count entries. */
278 struct phm_vce_clock_voltage_dependency_table
{
280 struct phm_vce_clock_voltage_dependency_record entries
[1];
283 struct pp_hwmgr_func
{
284 int (*backend_init
)(struct pp_hwmgr
*hw_mgr
);
285 int (*backend_fini
)(struct pp_hwmgr
*hw_mgr
);
286 int (*asic_setup
)(struct pp_hwmgr
*hw_mgr
);
287 int (*get_power_state_size
)(struct pp_hwmgr
*hw_mgr
);
289 int (*apply_state_adjust_rules
)(struct pp_hwmgr
*hwmgr
,
290 struct pp_power_state
*prequest_ps
,
291 const struct pp_power_state
*pcurrent_ps
);
293 int (*force_dpm_level
)(struct pp_hwmgr
*hw_mgr
,
294 enum amd_dpm_forced_level level
);
296 int (*dynamic_state_management_enable
)(
297 struct pp_hwmgr
*hw_mgr
);
298 int (*dynamic_state_management_disable
)(
299 struct pp_hwmgr
*hw_mgr
);
301 int (*patch_boot_state
)(struct pp_hwmgr
*hwmgr
,
302 struct pp_hw_power_state
*hw_ps
);
304 int (*get_pp_table_entry
)(struct pp_hwmgr
*hwmgr
,
305 unsigned long, struct pp_power_state
*);
306 int (*get_num_of_pp_table_entries
)(struct pp_hwmgr
*hwmgr
);
307 int (*powerdown_uvd
)(struct pp_hwmgr
*hwmgr
);
308 int (*powergate_vce
)(struct pp_hwmgr
*hwmgr
, bool bgate
);
309 int (*powergate_uvd
)(struct pp_hwmgr
*hwmgr
, bool bgate
);
310 int (*get_mclk
)(struct pp_hwmgr
*hwmgr
, bool low
);
311 int (*get_sclk
)(struct pp_hwmgr
*hwmgr
, bool low
);
312 int (*power_state_set
)(struct pp_hwmgr
*hwmgr
,
314 int (*enable_clock_power_gating
)(struct pp_hwmgr
*hwmgr
);
315 int (*notify_smc_display_config_after_ps_adjustment
)(struct pp_hwmgr
*hwmgr
);
316 int (*display_config_changed
)(struct pp_hwmgr
*hwmgr
);
317 int (*disable_clock_power_gating
)(struct pp_hwmgr
*hwmgr
);
318 int (*update_clock_gatings
)(struct pp_hwmgr
*hwmgr
,
319 const uint32_t *msg_id
);
320 int (*set_max_fan_rpm_output
)(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
);
321 int (*set_max_fan_pwm_output
)(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
);
322 int (*get_temperature
)(struct pp_hwmgr
*hwmgr
);
323 int (*stop_thermal_controller
)(struct pp_hwmgr
*hwmgr
);
324 int (*get_fan_speed_info
)(struct pp_hwmgr
*hwmgr
, struct phm_fan_speed_info
*fan_speed_info
);
325 int (*set_fan_control_mode
)(struct pp_hwmgr
*hwmgr
, uint32_t mode
);
326 int (*get_fan_control_mode
)(struct pp_hwmgr
*hwmgr
);
327 int (*set_fan_speed_percent
)(struct pp_hwmgr
*hwmgr
, uint32_t percent
);
328 int (*get_fan_speed_percent
)(struct pp_hwmgr
*hwmgr
, uint32_t *speed
);
329 int (*set_fan_speed_rpm
)(struct pp_hwmgr
*hwmgr
, uint32_t percent
);
330 int (*get_fan_speed_rpm
)(struct pp_hwmgr
*hwmgr
, uint32_t *speed
);
331 int (*reset_fan_speed_to_default
)(struct pp_hwmgr
*hwmgr
);
332 int (*uninitialize_thermal_controller
)(struct pp_hwmgr
*hwmgr
);
333 int (*register_internal_thermal_interrupt
)(struct pp_hwmgr
*hwmgr
,
334 const void *thermal_interrupt_info
);
335 bool (*check_smc_update_required_for_display_configuration
)(struct pp_hwmgr
*hwmgr
);
336 int (*check_states_equal
)(struct pp_hwmgr
*hwmgr
,
337 const struct pp_hw_power_state
*pstate1
,
338 const struct pp_hw_power_state
*pstate2
,
340 int (*set_cpu_power_state
)(struct pp_hwmgr
*hwmgr
);
341 int (*store_cc6_data
)(struct pp_hwmgr
*hwmgr
, uint32_t separation_time
,
342 bool cc6_disable
, bool pstate_disable
,
343 bool pstate_switch_disable
);
344 int (*get_dal_power_level
)(struct pp_hwmgr
*hwmgr
,
345 struct amd_pp_simple_clock_info
*info
);
346 int (*get_performance_level
)(struct pp_hwmgr
*, const struct pp_hw_power_state
*,
347 PHM_PerformanceLevelDesignation
, uint32_t, PHM_PerformanceLevel
*);
348 int (*get_current_shallow_sleep_clocks
)(struct pp_hwmgr
*hwmgr
,
349 const struct pp_hw_power_state
*state
, struct pp_clock_info
*clock_info
);
350 int (*get_clock_by_type
)(struct pp_hwmgr
*hwmgr
, enum amd_pp_clock_type type
, struct amd_pp_clocks
*clocks
);
351 int (*get_clock_by_type_with_latency
)(struct pp_hwmgr
*hwmgr
,
352 enum amd_pp_clock_type type
,
353 struct pp_clock_levels_with_latency
*clocks
);
354 int (*get_clock_by_type_with_voltage
)(struct pp_hwmgr
*hwmgr
,
355 enum amd_pp_clock_type type
,
356 struct pp_clock_levels_with_voltage
*clocks
);
357 int (*set_watermarks_for_clocks_ranges
)(struct pp_hwmgr
*hwmgr
,
358 struct pp_wm_sets_with_clock_ranges_soc15
*wm_with_clock_ranges
);
359 int (*display_clock_voltage_request
)(struct pp_hwmgr
*hwmgr
,
360 struct pp_display_clock_request
*clock
);
361 int (*get_max_high_clocks
)(struct pp_hwmgr
*hwmgr
, struct amd_pp_simple_clock_info
*clocks
);
362 int (*power_off_asic
)(struct pp_hwmgr
*hwmgr
);
363 int (*force_clock_level
)(struct pp_hwmgr
*hwmgr
, enum pp_clock_type type
, uint32_t mask
);
364 int (*print_clock_levels
)(struct pp_hwmgr
*hwmgr
, enum pp_clock_type type
, char *buf
);
365 int (*enable_per_cu_power_gating
)(struct pp_hwmgr
*hwmgr
, bool enable
);
366 int (*get_sclk_od
)(struct pp_hwmgr
*hwmgr
);
367 int (*set_sclk_od
)(struct pp_hwmgr
*hwmgr
, uint32_t value
);
368 int (*get_mclk_od
)(struct pp_hwmgr
*hwmgr
);
369 int (*set_mclk_od
)(struct pp_hwmgr
*hwmgr
, uint32_t value
);
370 int (*read_sensor
)(struct pp_hwmgr
*hwmgr
, int idx
, void *value
, int *size
);
371 int (*set_power_profile_state
)(struct pp_hwmgr
*hwmgr
,
372 struct amd_pp_profile
*request
);
373 int (*avfs_control
)(struct pp_hwmgr
*hwmgr
, bool enable
);
374 int (*disable_smc_firmware_ctf
)(struct pp_hwmgr
*hwmgr
);
377 struct pp_table_func
{
378 int (*pptable_init
)(struct pp_hwmgr
*hw_mgr
);
379 int (*pptable_fini
)(struct pp_hwmgr
*hw_mgr
);
380 int (*pptable_get_number_of_vce_state_table_entries
)(struct pp_hwmgr
*hw_mgr
);
381 int (*pptable_get_vce_state_table_entry
)(
382 struct pp_hwmgr
*hwmgr
,
384 struct amd_vce_state
*vce_state
,
386 unsigned long *flag
);
389 union phm_cac_leakage_record
{
391 uint16_t Vddc
; /* in CI, we use it for StdVoltageHiSidd */
392 uint32_t Leakage
; /* in CI, we use it for StdVoltageLoSidd */
401 struct phm_cac_leakage_table
{
403 union phm_cac_leakage_record entries
[1];
406 struct phm_samu_clock_voltage_dependency_record
{
412 struct phm_samu_clock_voltage_dependency_table
{
414 struct phm_samu_clock_voltage_dependency_record entries
[1];
417 struct phm_cac_tdp_table
{
419 uint16_t usConfigurableTDP
;
421 uint16_t usBatteryPowerLimit
;
422 uint16_t usSmallPowerLimit
;
423 uint16_t usLowCACLeakage
;
424 uint16_t usHighCACLeakage
;
425 uint16_t usMaximumPowerDeliveryLimit
;
427 uint16_t usOperatingTempMinLimit
;
428 uint16_t usOperatingTempMaxLimit
;
429 uint16_t usOperatingTempStep
;
430 uint16_t usOperatingTempHyst
;
431 uint16_t usDefaultTargetOperatingTemp
;
432 uint16_t usTargetOperatingTemp
;
433 uint16_t usPowerTuneDataSetID
;
434 uint16_t usSoftwareShutdownTemp
;
435 uint16_t usClockStretchAmount
;
436 uint16_t usTemperatureLimitHotspot
;
437 uint16_t usTemperatureLimitLiquid1
;
438 uint16_t usTemperatureLimitLiquid2
;
439 uint16_t usTemperatureLimitVrVddc
;
440 uint16_t usTemperatureLimitVrMvdd
;
441 uint16_t usTemperatureLimitPlx
;
442 uint8_t ucLiquid1_I2C_address
;
443 uint8_t ucLiquid2_I2C_address
;
444 uint8_t ucLiquid_I2C_Line
;
445 uint8_t ucVr_I2C_address
;
446 uint8_t ucVr_I2C_Line
;
447 uint8_t ucPlx_I2C_address
;
448 uint8_t ucPlx_I2C_Line
;
449 uint32_t usBoostPowerLimit
;
450 uint8_t ucCKS_LDO_REFSEL
;
453 struct phm_tdp_table
{
455 uint16_t usConfigurableTDP
;
457 uint16_t usBatteryPowerLimit
;
458 uint16_t usSmallPowerLimit
;
459 uint16_t usLowCACLeakage
;
460 uint16_t usHighCACLeakage
;
461 uint16_t usMaximumPowerDeliveryLimit
;
463 uint16_t usOperatingTempMinLimit
;
464 uint16_t usOperatingTempMaxLimit
;
465 uint16_t usOperatingTempStep
;
466 uint16_t usOperatingTempHyst
;
467 uint16_t usDefaultTargetOperatingTemp
;
468 uint16_t usTargetOperatingTemp
;
469 uint16_t usPowerTuneDataSetID
;
470 uint16_t usSoftwareShutdownTemp
;
471 uint16_t usClockStretchAmount
;
472 uint16_t usTemperatureLimitTedge
;
473 uint16_t usTemperatureLimitHotspot
;
474 uint16_t usTemperatureLimitLiquid1
;
475 uint16_t usTemperatureLimitLiquid2
;
476 uint16_t usTemperatureLimitHBM
;
477 uint16_t usTemperatureLimitVrVddc
;
478 uint16_t usTemperatureLimitVrMvdd
;
479 uint16_t usTemperatureLimitPlx
;
480 uint8_t ucLiquid1_I2C_address
;
481 uint8_t ucLiquid2_I2C_address
;
482 uint8_t ucLiquid_I2C_Line
;
483 uint8_t ucVr_I2C_address
;
484 uint8_t ucVr_I2C_Line
;
485 uint8_t ucPlx_I2C_address
;
486 uint8_t ucPlx_I2C_Line
;
487 uint8_t ucLiquid_I2C_LineSDA
;
488 uint8_t ucVr_I2C_LineSDA
;
489 uint8_t ucPlx_I2C_LineSDA
;
490 uint32_t usBoostPowerLimit
;
491 uint16_t usBoostStartTemperature
;
492 uint16_t usBoostStopTemperature
;
493 uint32_t ulBoostClock
;
496 struct phm_ppm_table
{
498 uint16_t cpu_core_number
;
499 uint32_t platform_tdp
;
500 uint32_t small_ac_platform_tdp
;
501 uint32_t platform_tdc
;
502 uint32_t small_ac_platform_tdc
;
505 uint32_t dgpu_ulv_power
;
509 struct phm_vq_budgeting_record
{
511 uint32_t ulSustainableSOCPowerLimitLow
;
512 uint32_t ulSustainableSOCPowerLimitHigh
;
513 uint32_t ulMinSclkLow
;
514 uint32_t ulMinSclkHigh
;
515 uint8_t ucDispConfig
;
518 uint32_t ulSustainableSclk
;
519 uint32_t ulSustainableCUs
;
522 struct phm_vq_budgeting_table
{
524 struct phm_vq_budgeting_record entries
[1];
527 struct phm_clock_and_voltage_limits
{
537 /* Structure to hold PPTable information */
539 struct phm_ppt_v1_information
{
540 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_sclk
;
541 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_mclk
;
542 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_socclk
;
543 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_dcefclk
;
544 struct phm_clock_array
*valid_sclk_values
;
545 struct phm_clock_array
*valid_mclk_values
;
546 struct phm_clock_array
*valid_socclk_values
;
547 struct phm_clock_array
*valid_dcefclk_values
;
548 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc
;
549 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac
;
550 struct phm_clock_voltage_dependency_table
*vddc_dep_on_dal_pwrl
;
551 struct phm_ppm_table
*ppm_parameter_table
;
552 struct phm_cac_tdp_table
*cac_dtp_table
;
553 struct phm_tdp_table
*tdp_table
;
554 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_dep_table
;
555 struct phm_ppt_v1_voltage_lookup_table
*vddc_lookup_table
;
556 struct phm_ppt_v1_voltage_lookup_table
*vddgfx_lookup_table
;
557 struct phm_ppt_v1_voltage_lookup_table
*vddmem_lookup_table
;
558 struct phm_ppt_v1_pcie_table
*pcie_table
;
559 struct phm_ppt_v1_gpio_table
*gpio_table
;
560 uint16_t us_ulv_voltage_offset
;
561 uint16_t us_ulv_smnclk_did
;
562 uint16_t us_ulv_mp1clk_did
;
563 uint16_t us_ulv_gfxclk_bypass
;
564 uint16_t us_gfxclk_slew_rate
;
565 uint16_t us_min_gfxclk_freq_limit
;
568 struct phm_ppt_v2_information
{
569 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_sclk
;
570 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_mclk
;
571 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_socclk
;
572 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_dcefclk
;
573 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_pixclk
;
574 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_dispclk
;
575 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_phyclk
;
576 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_dep_table
;
578 struct phm_clock_voltage_dependency_table
*vddc_dep_on_dalpwrl
;
580 struct phm_clock_array
*valid_sclk_values
;
581 struct phm_clock_array
*valid_mclk_values
;
582 struct phm_clock_array
*valid_socclk_values
;
583 struct phm_clock_array
*valid_dcefclk_values
;
585 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc
;
586 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac
;
588 struct phm_ppm_table
*ppm_parameter_table
;
589 struct phm_cac_tdp_table
*cac_dtp_table
;
590 struct phm_tdp_table
*tdp_table
;
592 struct phm_ppt_v1_voltage_lookup_table
*vddc_lookup_table
;
593 struct phm_ppt_v1_voltage_lookup_table
*vddgfx_lookup_table
;
594 struct phm_ppt_v1_voltage_lookup_table
*vddmem_lookup_table
;
595 struct phm_ppt_v1_voltage_lookup_table
*vddci_lookup_table
;
597 struct phm_ppt_v1_pcie_table
*pcie_table
;
599 uint16_t us_ulv_voltage_offset
;
600 uint16_t us_ulv_smnclk_did
;
601 uint16_t us_ulv_mp1clk_did
;
602 uint16_t us_ulv_gfxclk_bypass
;
603 uint16_t us_gfxclk_slew_rate
;
604 uint16_t us_min_gfxclk_freq_limit
;
606 uint8_t uc_gfx_dpm_voltage_mode
;
607 uint8_t uc_soc_dpm_voltage_mode
;
608 uint8_t uc_uclk_dpm_voltage_mode
;
609 uint8_t uc_uvd_dpm_voltage_mode
;
610 uint8_t uc_vce_dpm_voltage_mode
;
611 uint8_t uc_mp0_dpm_voltage_mode
;
612 uint8_t uc_dcef_dpm_voltage_mode
;
615 struct phm_ppt_v3_information
{
616 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_sclk
;
617 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_mclk
;
618 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_socclk
;
619 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_dcefclk
;
620 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_pixclk
;
621 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_dispclk
;
622 struct phm_ppt_v1_clock_voltage_dependency_table
*vdd_dep_on_phyclk
;
626 struct phm_dynamic_state_info
{
627 struct phm_clock_voltage_dependency_table
*vddc_dependency_on_sclk
;
628 struct phm_clock_voltage_dependency_table
*vddci_dependency_on_mclk
;
629 struct phm_clock_voltage_dependency_table
*vddc_dependency_on_mclk
;
630 struct phm_clock_voltage_dependency_table
*mvdd_dependency_on_mclk
;
631 struct phm_clock_voltage_dependency_table
*vddc_dep_on_dal_pwrl
;
632 struct phm_clock_array
*valid_sclk_values
;
633 struct phm_clock_array
*valid_mclk_values
;
634 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc
;
635 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac
;
636 uint32_t mclk_sclk_ratio
;
637 uint32_t sclk_mclk_delta
;
638 uint32_t vddc_vddci_delta
;
639 uint32_t min_vddc_for_pcie_gen2
;
640 struct phm_cac_leakage_table
*cac_leakage_table
;
641 struct phm_phase_shedding_limits_table
*vddc_phase_shed_limits_table
;
643 struct phm_vce_clock_voltage_dependency_table
644 *vce_clock_voltage_dependency_table
;
645 struct phm_uvd_clock_voltage_dependency_table
646 *uvd_clock_voltage_dependency_table
;
647 struct phm_acp_clock_voltage_dependency_table
648 *acp_clock_voltage_dependency_table
;
649 struct phm_samu_clock_voltage_dependency_table
650 *samu_clock_voltage_dependency_table
;
652 struct phm_ppm_table
*ppm_parameter_table
;
653 struct phm_cac_tdp_table
*cac_dtp_table
;
654 struct phm_clock_voltage_dependency_table
*vdd_gfx_dependency_on_sclk
;
655 struct phm_vq_budgeting_table
*vq_budgeting_table
;
660 uint8_t ucTachometerPulsesPerRevolution
;
665 struct pp_advance_fan_control_parameters
{
666 uint16_t usTMin
; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
667 uint16_t usTMed
; /* The middle temperature where we change slopes. */
668 uint16_t usTHigh
; /* The high temperature for setting the second slope. */
669 uint16_t usPWMMin
; /* The minimum PWM value in percent (0.01% increments). */
670 uint16_t usPWMMed
; /* The PWM value (in percent) at TMed. */
671 uint16_t usPWMHigh
; /* The PWM value at THigh. */
672 uint8_t ucTHyst
; /* Temperature hysteresis. Integer. */
673 uint32_t ulCycleDelay
; /* The time between two invocations of the fan control routine in microseconds. */
674 uint16_t usTMax
; /* The max temperature */
675 uint8_t ucFanControlMode
;
676 uint16_t usFanPWMMinLimit
;
677 uint16_t usFanPWMMaxLimit
;
678 uint16_t usFanPWMStep
;
679 uint16_t usDefaultMaxFanPWM
;
680 uint16_t usFanOutputSensitivity
;
681 uint16_t usDefaultFanOutputSensitivity
;
682 uint16_t usMaxFanPWM
; /* The max Fan PWM value for Fuzzy Fan Control feature */
683 uint16_t usFanRPMMinLimit
; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
684 uint16_t usFanRPMMaxLimit
; /* Maximum limit range in percentage, usually set to 100% by default */
685 uint16_t usFanRPMStep
; /* Step increments/decerements, in percent */
686 uint16_t usDefaultMaxFanRPM
; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
687 uint16_t usMaxFanRPM
; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
688 uint16_t usFanCurrentLow
; /* Low current */
689 uint16_t usFanCurrentHigh
; /* High current */
690 uint16_t usFanRPMLow
; /* Low RPM */
691 uint16_t usFanRPMHigh
; /* High RPM */
692 uint32_t ulMinFanSCLKAcousticLimit
; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
693 uint8_t ucTargetTemperature
; /* Advanced fan controller target temperature. */
694 uint8_t ucMinimumPWMLimit
; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
695 uint16_t usFanGainEdge
; /* The following is added for Fiji */
696 uint16_t usFanGainHotspot
;
697 uint16_t usFanGainLiquid
;
698 uint16_t usFanGainVrVddc
;
699 uint16_t usFanGainVrMvdd
;
700 uint16_t usFanGainPlx
;
701 uint16_t usFanGainHbm
;
702 uint8_t ucEnableZeroRPM
;
703 uint8_t ucFanStopTemperature
;
704 uint8_t ucFanStartTemperature
;
705 uint32_t ulMaxFanSCLKAcousticLimit
; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
706 uint32_t ulTargetGfxClk
;
707 uint16_t usZeroRPMStartTemperature
;
708 uint16_t usZeroRPMStopTemperature
;
711 struct pp_thermal_controller_info
{
714 uint8_t ucI2cAddress
;
715 struct pp_fan_info fanInfo
;
716 struct pp_advance_fan_control_parameters advanceFanControlParameters
;
719 struct phm_microcode_version_info
{
726 enum PP_TABLE_VERSION
{
734 * The main hardware manager structure.
737 uint32_t chip_family
;
740 uint32_t pp_table_version
;
742 struct pp_smumgr
*smumgr
;
743 const void *soft_pp_table
;
744 uint32_t soft_pp_table_size
;
745 void *hardcode_pp_table
;
746 bool need_pp_table_upload
;
748 struct amd_vce_state vce_states
[AMD_MAX_VCE_LEVELS
];
749 uint32_t num_vce_state_tables
;
751 enum amd_dpm_forced_level dpm_level
;
752 enum amd_dpm_forced_level saved_dpm_level
;
753 bool block_hw_access
;
754 struct phm_gfx_arbiter gfx_arbiter
;
755 struct phm_acp_arbiter acp_arbiter
;
756 struct phm_uvd_arbiter uvd_arbiter
;
757 struct phm_vce_arbiter vce_arbiter
;
758 uint32_t usec_timeout
;
760 struct phm_platform_descriptor platform_descriptor
;
762 enum PP_DAL_POWERLEVEL dal_power_level
;
763 struct phm_dynamic_state_info dyn_state
;
764 struct phm_runtime_table_header setup_asic
;
765 struct phm_runtime_table_header power_down_asic
;
766 struct phm_runtime_table_header disable_dynamic_state_management
;
767 struct phm_runtime_table_header enable_dynamic_state_management
;
768 struct phm_runtime_table_header set_power_state
;
769 struct phm_runtime_table_header enable_clock_power_gatings
;
770 struct phm_runtime_table_header display_configuration_changed
;
771 struct phm_runtime_table_header start_thermal_controller
;
772 struct phm_runtime_table_header set_temperature_range
;
773 const struct pp_hwmgr_func
*hwmgr_func
;
774 const struct pp_table_func
*pptable_func
;
775 struct pp_power_state
*ps
;
776 enum pp_power_source power_source
;
778 struct pp_thermal_controller_info thermal_controller
;
779 bool fan_ctrl_is_in_default_mode
;
780 uint32_t fan_ctrl_default_mode
;
781 bool fan_ctrl_enabled
;
783 struct phm_microcode_version_info microcode_version_info
;
785 struct pp_power_state
*current_ps
;
786 struct pp_power_state
*request_ps
;
787 struct pp_power_state
*boot_ps
;
788 struct pp_power_state
*uvd_ps
;
789 struct amd_pp_display_configuration display_config
;
790 uint32_t feature_mask
;
793 struct amd_pp_profile gfx_power_profile
;
794 struct amd_pp_profile compute_power_profile
;
795 struct amd_pp_profile default_gfx_power_profile
;
796 struct amd_pp_profile default_compute_power_profile
;
797 enum amd_pp_profile_type current_power_profile
;
800 extern int hwmgr_early_init(struct pp_instance
*handle
);
801 extern int hwmgr_hw_init(struct pp_instance
*handle
);
802 extern int hwmgr_hw_fini(struct pp_instance
*handle
);
803 extern int phm_wait_on_register(struct pp_hwmgr
*hwmgr
, uint32_t index
,
804 uint32_t value
, uint32_t mask
);
806 extern void phm_wait_on_indirect_register(struct pp_hwmgr
*hwmgr
,
807 uint32_t indirect_port
,
814 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr
*hwmgr
);
815 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr
*hwmgr
);
816 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr
*hwmgr
);
818 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
);
819 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_clock_voltage_dependency_table
*dep_table
);
820 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_clock_voltage_dependency_table
*dep_table
);
821 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table
*vol_table
, phm_ppt_v1_voltage_lookup_table
*lookup_table
);
822 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps
, struct pp_atomctrl_voltage_table
*vol_table
);
823 extern int phm_reset_single_dpm_table(void *table
, uint32_t count
, int max
);
824 extern void phm_setup_pcie_table_entry(void *table
, uint32_t index
, uint32_t pcie_gen
, uint32_t pcie_lanes
);
825 extern int32_t phm_get_dpm_level_enable_mask_value(void *table
);
826 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table
*voltage_table
,
828 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table
*lookup_table
, uint16_t voltage
);
829 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table
*vddci_table
, uint16_t vddci
);
830 extern int phm_find_boot_level(void *table
, uint32_t value
, uint32_t *boot_level
);
831 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr
*hwmgr
, phm_ppt_v1_voltage_lookup_table
*lookup_table
,
832 uint16_t virtual_voltage_id
, int32_t *sclk
);
833 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr
*hwmgr
);
834 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr
*hwmgr
, uint32_t mask
);
835 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr
*hwmgr
);
837 extern int smu7_init_function_pointers(struct pp_hwmgr
*hwmgr
);
838 extern int vega10_hwmgr_init(struct pp_hwmgr
*hwmgr
);
840 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr
*hwmgr
, uint8_t voltage_type
,
841 uint32_t sclk
, uint16_t id
, uint16_t *voltage
);
843 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
845 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
846 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
848 #define PHM_SET_FIELD(origval, reg, field, fieldval) \
849 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
850 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
852 #define PHM_GET_FIELD(value, reg, field) \
853 (((value) & PHM_FIELD_MASK(reg, field)) >> \
854 PHM_FIELD_SHIFT(reg, field))
857 /* Operations on named fields. */
859 #define PHM_READ_FIELD(device, reg, field) \
860 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
862 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
863 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
866 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
867 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
870 #define PHM_WRITE_FIELD(device, reg, field, fieldval) \
871 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
872 cgs_read_register(device, mm##reg), reg, field, fieldval))
874 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
875 cgs_write_ind_register(device, port, ix##reg, \
876 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
877 reg, field, fieldval))
879 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
880 cgs_write_ind_register(device, port, ix##reg, \
881 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
882 reg, field, fieldval))
884 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
885 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
888 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
889 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
891 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
892 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
893 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
896 #endif /* _HWMGR_H_ */